TABLE 6.

1 FET Bias Configurations Type Configuration

VDD RD RG

Pertinent Equations

Graphical Solution
ID IDSS

JFET Fixed-bias
VGG

VGSQ VGG VDS VDD IDRS

Q-point VP VGG 0 VGS ID IDSS

+
VDD RD RG

JFET Self-bias

VDS
RS VDD

VGS VDD

IDRS ID(RD

RS)

Q-point VP V' 0 GS

I'D VGS

JFET Voltage-divider bias

R1 R2

RD

VG

R2VDD R1 R2
Q-point VP

ID IDSS VG RS 0 ID IDSS VG VGS

RS VDD RD

VDS

VGS VG IDRS VDD ID(RD RS)

JFET Common-gate
RS VSS VDD RD

VDS

VGS VDD

VSS VSS

IDRS ID(RD

RS)

Q-point VP Q-point 0

VSS RS VSS VGS

ID IDSS VGS = 0 V
Q

JFET (VGSQ 0 V)

VGSQ 0 V IDQ IDSS

VP 0

VGS ID IDSS I'D VGS

JFET (RD 0 )
RG

VDD

VGS VD VS VDS

RS

IDRS VDD IDRS VDD ISRS

Q-point VP V'GS 0

Depletion-type MOSFET Fixed-bias

VGG

VDD RD

ID Q-point

RG

VGSQ VGG VDS VDD IDRS

VP VDD

IDSS

0 VGG ID Q-point

VGS

Depletion-type MOSFET Voltage-divider bias

R1 R2

RD

VG

R2VDD R1 R2

VG RS IDSS

RS

VDS
VDD RD

VGS VG ISRS VDD ID(RD RS)

VDD RD

VP ID

VG VGS

Enhancement type MOSFET Feedback configuration

RG

VGS VDS VGS VDD IDRD

ID(on)

Q-point 0 VGS(Th) ID VGS(on) VDD VGS

VDD

Enhancementtype MOSFET Voltage-divider bias

R1 R2

RD

VG VGS

R2VDD R1 R2 VG IDRS

VG RS

Q-point 0 VGS(Th) VG VGS

RS

281

TABLE 8.1 Relative Levels for the Important Parameters of the CE, CB, and CC Transistor Amplifiers Configuration
Fixed-bias: VCC RB RC

Zi
Medium (1 k ) RB re re (RB 10 re) (ro

Zo
Medium (2 k ) RC ro RC 10RC) (ro

Av
High ( 200) (RC ro) re RC re 10RC)

Ai
High (100) RBro RC)(RB

(ro

re)

(ro RB

10RC , 10 re)

Voltage-divider bias: R1

VCC RC

Medium (1 k ) R1 R2 re

Medium (2 k ) RC ro RC

High ( 200) RC ro re RC re (ro 10RC)

High (50) (R1 R2)ro RC)(R1 R2 (R1 R2) R1 R2 re (ro 10RC)

(ro

re)

R2

(ro RE CE

10RC)

Unbypassed emitter bias: RB

VCC RC

High (100 k ) RB Zb Zb (re RE)

Medium (2 k ) RC (any level of ro)

Low ( 5) RC RE RC RE (RE re)

High (50) RB Zb

re

RB

RB RE RE (RE re)

Emitterfollower: RB

VCC

High (100 k ) RB Zb Zb (re RE)

Low (20 RE re re

Low (

1)

High ( 50) RB Zb

RE RE re 1

RB

RE (RE Commonbase: RE VEE RC VCC (RE Collector feedback: RF

RB RE re)

(RE

re)

Low (20 RE re re

Medium (2 k ) RC

High (200) RC re

Low ( 1) 1

re)

VCC RC

Medium (1 k ) re 1 RC RE 10RC)

Medium (2 k ) RC RF (ro 10RC)

High ( 200) RC re (ro RF 10RC) RC)

High (50) RF RF RF RC RC

(ro

8.12 Troubleshooting

383

gm
TABLE 9.1 Zi, Z0, and Av for various FET configurations Configuration
Fixed-bias [JFET or D-MOSFET]
+VDD

Zi

Zo

Av

Vo Vi

D-MOSFET]
RD C1 Vi Zi RG VGG Zo C2 Vo

Medium (2 k ) High (10 M ) RG RD

(rd 10 RD)

Medium ( 10) gm(rd RD)

RD rd

gm RD

(rd

10 RD)

Self-bias bypassed Rs [JFET or D-MOSFET]

+VDD S

Medium (2 k )
C2 Vo

Medium ( 10) gm(rd RD)

-MOSFET]
C1 Vi Zi RG

RD

High (10 M ) RD rd RG
Zo

RD
(rd 10 RD)

gm RD
(rd 10 RD)

RS

CS

Self-bias unbypassed RS [JFET or D-MOSFET] Low ( 2)

+VDD

d RS -MOSFET]
C1 Vi Zi RG

1
C2 Vo

gmRS gmRS

RS RD rd RS rd RD rd 1

RD

High (10 M ) RG
Zo

gmRD gmRs RD

RS rd

RD
RS

rd

10 RD or rd

gmRD 1 gmRS
[rd 10(Rd RS)]

Voltage-divider bias [JFET or D-MOSFET]

vider bias -MOSFET]

R1 C1 Vi Zi

+VDD

Medium (2 k )
RD C2 Vo Zo

Medium ( 10) gm(rd RD)

High (10 M ) R1 R2

RD r

RD
(rd 10 RD)

gm RD
(rd 10 RD)

R2

RS

CS

9.13 Summary Table

437

gm
TABLE 9.1 (Continued) Configuration
Source-follower [JFET or D-MOSFET] Low ( 1)

Zi

Zo

Av

Vo Vi

-MOSFET]
C1 Vi Zi RG

+VDD

Low (100 k ) High (10 M )

C2 Vo

rd RS 1/gm

gm(rd RS) gm(rd RS)

RG

RS

RS 1/gm

(rd

10 RS)

Zo

gmRS gmRS
(rd 10 R S)

Common-gate [JFET or D-MOSFET]

ate -MOSFET]
C1 Vi Q1

+VDD RD

Medium (2 k ) Low (1 k ) RD rd
C2 Vo

RS

rd RD 1 gmrd RD
(rd 10 RD)

Medium ( 10) RD gmRD rd 1 RD rd

Zi

RS RG

CS

Zo

1 RS gm

(rd

10 RD)

gmRD

(rd

10 R S)

Drain-feedback bias E-MOSFET

back bias T
RF C1 Vi Zi

+VDD RD C2 Vo Zo

Medium (1 M ) Medium (2 k ) RF 1 rd RD gm(rd RD) RF rd RD Medium ( 10) gm(RF rd RD)

RF gmRD

RD
(rd 10 RD)

(RF, rd

10 RD)

gmRD
(RF, rd 10 RD)

Voltage-divider bias E-MOSFET

ider bias T

+VDD

Medium (2 k )
RD R1 D Zo S C2 Vo

Medium ( 10) gm(rd RD)

Medium (1 M ) R1 R2

RD rd

C1 Vi Zi

RD
RS

(Rd

10 RD)

gmRD
(rd 10 RD)

R2

438

Chapter 9

FET Small-Signal Analysis

Rs /RL
the equations will reveal that the isolation provided by the JFET between the gate and channel by the SiO2 layer results in a series of less complex equations than those encountered for the BJT configurations. The linkage provided by Ib between input and output circuits of the BJT transistor amplifier adds a touch of complexity to some of the equations.
TABLE 10.1 Summary of Transistor Configurations (Av, Zi, Zo) Configuration Av Vo /Vi
RL RC) re

Zi
RB re

Zo
RC

hfe hie (RL RC) Including ro: (RL RC ro) re (RL RC) re

RB hie

RC

RB re

RC ro

R1 R2 re

RC

hfe hie (RL RC)

R1 R2 hie

RC

Including ro: (RL RC ro) re R1 R2 re RC ro

RE 1

RL RE RE)

Rs RE

Rs R1 R2 Rs re

R1 R2 (re

Rs 1 R1 R2 (hie hfeRE) RE hfe

hie

Including ro: 1 R1 R2 (re RE) RE

Rs

re

(RL RC) re hfb hib (RL RC) Including ro: (RL RC ro) re

RE re RE hib

RC RC

RE re

RC ro

10.10 Summary Table

477

Rs /RL
TABLE 10.1 Summary of Transistor Configurations (Av, Zi, Zo) (Continued) Configuration
VCC

Av

Vo /Vi
RL RC) RE

Zi
R1 R2 (re RE)

Zo
RC

RC R1 Rs Vi Zo RL Zi R2 RE Vo

(RL RC) RE

R1 R2 (hie

hfeRE)

RC

+
Vs

Including ro: (RL RC) RE RL RC RE1

R1 R2 (re

RE)

RC

VCC

RB (re

RE1)

RC

RC RB Rs Vi Zo Vo

(RL RC) RE1

RL

RB (hie

hfeRE1)

RC

+
Vs

Zi

RE1

RE2

CE

Including ro: RL RC RE1 (RL RC) re

RB (re

RE1) RF

RC

VCC RC RF Rs Vi Vo Zo Zi

re

Av

RC

hfe hie (RL RC)

RF hie A v

RC

+
Vs

RL

Including ro: (RL RC ro) re (RL RC) RE

RF re Av RF RE Av RC RF RC RF ro

VCC RC RF Rs Vi Vo Zo RL Zi RL E

(RL RC) RE

RF hfeRE Av RC RF

+
Vs

Including ro: (RL RC) RE RF RE Av RC RF

478

Chapter 10

Systems ApproachEffects of Rs and RL

Rs /RL
TABLE 10.1 (Continued) Configuration
VDD RD Vo Rsig Vi Zo RL Zi RG RS CS

Av

Vo /Vi

Zi

Zo

gm(RD RL)

RG

RD

+
Vs

Including rd: gm(RD RL rd) RG RD rd

VDD RD Vo Rsig Vi Zo RL Zi RG RS

gm(RD RL) 1 gmRS

RG

RD gmRS

Including rd: gm(RD RL) RD RS gmRS rd RD gmRS

+
Vs

RG

VDD RD R1 Rsig Vi Zo RL Zi R2 RS CS Vo

gm(RD RL)

R1 R2

RD

+
Vs

Including rd: gm(RD RL rd) R1 R2 RD rd

VDD

1
RD Rsig Vi

gm(RS RL) gm(RS RL)

RG

RS 1/gm

+
Vs

Zi

RG RS Zo RL

Vo

Including rd: gmrd (RS RL) rd RD gmrd (RS RL)

RG

RS gmrdRS rd RD

Rsig

Vi RD VDD Zo

Vo RS RL

gm(RD RL) Including rd: gm(RD RL) Zi

RS gmRS

RD

+
Vs

Zi

RS gmrdRS rd RD RL

RD rd

10.10 Summary Table

479