Synchronization in Multiple Clock Domain SoC

Ran Ginosar VLSI Systems Research Center TechnionIsrael Institute of Technology Haifa, Israel
ran@ee.technion.ac.il www.ee.technion.ac.il/~ran
2004 Ran Ginosar Synchronization in Multiple Clock Domain SoC Chapter 1: Introduction

What is the Problem?

Large chips have multiple clock domains, because:
chip interfaces with several unrelated clocks chip size grows:
Hard to design a single clock distribution network:
Skew, Jitter, min / max delays, power, area

More economical to break the chip into multi-sync domains

chip employs clock gating and/or dynamic voltage / frequency scaling

Cross-domain communications require (clock and/or data) synchronization

2004 Ran Ginosar Synchronization in Multiple Clock Domain SoC Chapter 1: Introduction

1) Several Unrelated Clocks

Example: A Communication Controller / Hub / Bridge
66 MHz PCI 1 MHz CF 12 Mbps USB 384 Kbps 3G

50 MHz Memory

133 MHz CPU

75 MHz DSP

20 MHz Flash Memory 54 Mbps 802.11 1 Mbps Bluetooth 100 Mbps Etherent

a.k.a. MCD: Multiple Clock Domains a.k.a. GALS: Globally Asynchronous, Locally Synchronous
2004 Ran Ginosar Synchronization in Multiple Clock Domain SoC Chapter 1: Introduction

2) Large Multi-Sync Chips

MCD / GALS again !

Clock
2004 Ran Ginosar Synchronization in Multiple Clock Domain SoC Chapter 1: Introduction

3) Dynamic Voltage / Frequency Scaling

01000111001110101

200MHz 50MHz 1.1V 1.3V

1 0 1 0

01000111001110101

100MHz 1.2V

50MHz 1.1V
2004 Ran Ginosar Synchronization in Multiple Clock Domain SoC Chapter 1: Introduction

1 0 1 0

MCD and GALS

DVS (C-GALS)

Globally Synchronous
Single clock

MultiSynchronous
Each domain separate clock at same frequency

GALS

Async domains: Different frequency Different frequency per domain per domain

Centrally controlled

Autonomous

MCD
2004 Ran Ginosar Synchronization in Multiple Clock Domain SoC Chapter 1: Introduction

The Problem: Signal Transfer

Goal: highest BW data
Slow is easy

If the two clocks are not the same, sampling the data by FF B may fail
2004 Ran Ginosar

FF A

data

FF B

Clock A

Clock B

Synchronization in Multiple Clock Domain SoC Chapter 1: Introduction

Clock Relationship Classes, Synchronization Types

Class
Synchronous Mesochronous Multisynchronous Plesiochronous Periodic Asynchronous
2004 Ran Ginosar Synchronization in Multiple Clock Domain SoC Chapter 1: Introduction

f
0 0 0 fd< fd>

0 c drifts Varies

Synchronizer
None Phase compensation Adaptive phase compensation Adaptive phase compensation Predictive Two-FF
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Synchronous
Same clock Effort invested in limiting skew, jitter of clock net Main problem: min-delay
Clock
2004 Ran Ginosar Synchronization in Multiple Clock Domain SoC Chapter 1: Introduction

FF A

data

FF B

Synchronous Transfer
Example: Data change after clock rising edge Data sampled on (next) rising edge
FF A data FF B

Clock

data clock
2004 Ran Ginosar Synchronization in Multiple Clock Domain SoC Chapter 1: Introduction

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Asynchronous Input
Data not related to clock, not arriving every cycle

E.g. from a domain with UNRELATED clock

Only safe way is the two-FF synchronizer (and variations)
2004 Ran Ginosar Synchronization in Multiple Clock Domain SoC Chapter 1: Introduction

data

FF B

Clock B
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Course Outline
Clock Distribution Networks Async Basics Metastability and Synchronization Failures Syncing Async Domains Syncing Errors Verifying Synchronizers Syncing Multisync Domains Multisync Long Interconnect MCD / GALS Design
2004 Ran Ginosar Synchronization in Multiple Clock Domain SoC Chapter 1: Introduction

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Clock Distribution Networks

Problem Definition: Why it is hard to design a CDN What is predicted for the future: The Technology Roadmap How ASIC design handles the difficulty: Standard clock trees and clock tuning How custom design handles the difficulty Why it pays to break a large CDN into multiple small ones
2004 Ran Ginosar Synchronization in Multiple Clock Domain SoC Chapter 1: Introduction

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Basics of Asynchronous Design

Methods of Async Design are useful for GALS SoC
Handshake Signaling Data encoding Data validity Formal spec of sequential systems Async and mixed-time FIFOs Sync
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Async conversion
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Metastability
What really happens
Different types of problems

How dangerous it is How to simulate it How to measure it

How to avoid it is in the following chapter

2004 Ran Ginosar

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Synchronizing Async Domains

Control synchronizer Data synchronizer: Push, pull, push-pull Timing assumptions FIFO synchronizer Shared latch synchronizer Reset synchronizer

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Common Synchronization Errors

Taken from real chips

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Verifying Synchronizers
Using tools for Formal Verification Using standard analysis tools

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Syncing Multisync Domains

Take advantage of same frequency domains
Achieve low (zero) latency More complex designs

Extended to rational clocks

When the ration Freq1:Freq2 is known
Or when the ratio is fixed for a while

2004 Ran Ginosar

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Long Interconnect
When is it long?
When time-of-flight > clock cycle When signal timing is lost When inter-wire skew & jitter are too high

Synchronize along the way

Pipeline synchronizer Mixed-time synchronizer

Synchronize only at ends

1-of-m delay-insensitive data encoding High speed asynchronous transfer
2004 Ran Ginosar Synchronization in Multiple Clock Domain SoC Chapter 1: Introduction

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GALS SoC Design

Putting it all together Testability Issues CAD Flow RINGO Stoppable Clocks LS Wrappers De-Synchronization

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What do we learn?
The problems The various solutions What to do Who should do it What not to do What will the future bring us

2004 Ran Ginosar

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