Color Television Chassis

BP2.2U, BP2.3U
AA
Service Manual SDI Plasma Panels: 3122 785 14990

F_15400_000.eps
200505

Contents Page Contents Page

1. Technical Specifications, Connections, and Chassis SSB: Viper: Control (B5A) 60 80-89
Overview 2 SSB: Viper: Main Memory (B5B) 61 80-89
2. Safety Instructions, Warnings, and Notes 5 SSB: Viper: A/V & Tunnel Bus (B5C) 62 80-89
3. Directions for Use 7 SSB: Viper: Supply (B5D) 63 80-89
4. Mechanical Instructions 8 SSB: Viper: Display Diversity & Ambilight (B5E) 64 80-89
5. Service Modes, Error Codes, and Fault Finding 13 SSB: Display Interface: MOP (B6) 65 80-89
6. Block Diagrams and Overviews SSB: HDMI (B7A) 66 80-89
Wiring Diagram 33 SSB: HDMI: I/O & Control (B7B) 67 80-89
Block Diagram Video 34 SSB: HDMI: Supply (B7C) 68 80-89
Block Diagram Audio 35 SSB: USB2.0: Host (B8) 69 80-89
Block Diagram Control 36 SSB: Ethernet (Optional) (B9A) 70 80-89
I2C ICs Overview 37 SSB: UART (B9B) 71 80-89
Supply Lines Overview 38 SSB: POD: Out of Band (B10B) 71 80-89
7. Circuit Diagrams and PWB Layouts Drawing PWB SSB: POD: Common Interface (B10A) 72 80-89
Ambi Light Panel (Optional) (AL) 39 40 SSB: POD: Buffering (B10C) 73 80-89
SSB: DC/DC (B1A) 41 80-89 SSB: POD: TS Buffering (B10D) 74 80-89
SSB: DC/DC Connections (B1B) 42 80-89 SSB: Firewire 1394: Main (Optional) (B11A) 75 80-89
SSB: RS232 Interface (B1C) 43 80-89 SSB: Firewire 1394: Buffering (Optional) (B11B) 76 80-89
SSB: Channel Decoder (B2A) 44 80-89 SSB: Miscelaneous (B12) 77 80-89
SSB: Main Tuner & OOB Tuner (B2B) 45 80-89 SRP Overview SSB 78-79 80-89
SSB: MPIF Main: Video Source Selection (B3A) 46 80-89 External I/O Panel: Externals A (BE1) 90 92
SSB: MPIF Main: Supply (B3B) 47 80-89 External I/O Panel: Externals B (BE2) 91 92
SSB: MPIF Main: IF & SAW Filter (B3C) 48 80-89 Audio Amplifier Panel (C) 93 94
SSB: MPIF Main: Audio Source Selection (B3D) 49 80-89 Side I/O Panel (D) 95 96
SSB: MPIF Main: Audio Amplifier (B3E) 50 80-89 Control Board (E) 97 98
SSB: MPIF Main: Connections A (B3F) 51 80-89 LED Panel (J) 99 100
SSB: MPIF Main: Connections B (B3G) 52 80-89 8. Alignments 101
SSB: PNX2015: Audio/Video (B4A) 53 80-89 9. Circuit Descriptions, Abbreviation List, and IC Data
SSB: PNX2015: DV I/O Interface (B4B) 54 80-89 Sheets 106
SSB: PNX2015: Tunnel Bus (B4C) 55 80-89 Abbreviation List 126
SSB: PNX2015: DDR Interface (B4D) 56 80-89 IC Data Sheets 129
SSB: PNX2015: Standby & Control (B4E) 57 80-89 10. Spare Parts List 142
SSB: PNX2015: Supply (B4F) 58 80-89 11. Revision List 151
SSB: PNX2015: Display Interface (B4G) 59 80-89

©
Copyright 2005 Philips Consumer Electronics B.V. Eindhoven, The Netherlands.
All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic,
mechanical, photocopying, or otherwise without the prior permission of Philips.

Published by EL 0566 TV Service Printed in the Netherlands Subject to modification EN 3122 785 15540
 EN 2 1. BP2.2U, BP2.3U Technical Specifications, Connections, and Chassis Overview

1. Technical Specifications, Connections, and Chassis Overview

Index of this chapter: 1.1.4 Miscellaneous
1.1 Technical Specifications
1.2 Connection Overview Power supply:
1.3 Chassis Overview - Mains voltage (VAC) : 100 - 240

Note: Data below can deviate slightly from the actual situation, - Mains frequency (Hz) : 50/60
due to the different set executions.
Ambient conditions:
1.1 Technical Specifications - Temperature range (°C) : +5 to +40
- Maximum humidity : 90% R.H.
1.1.1 Vision

Display type : Plasma

Power consumption (values are indicative)
Screen size : 42” (107 cm), 16:9
- Normal operation (W) : ≈ 400 (42”)
: 50” (127 cm), 16:9
: ≈ 467 (50”)
Resolution (HxV pixels) : 1024(*3)x768p (42”)
- Standby (W) : <2
: 1366(*3)x768p (50”)
Contrast ratio : 3000:1
Light output (cd/m2) : 1000 (BP2.3) Dimensions (WxHxD in cm) : 124x68x10.4 (42”)
: 1100 (BP2.2) : 141x78x10.4 (50”)
Viewing angle (HxV degrees) : 160x160
Tuning system : PLL Weight (kg/lbs) : 42/92.6 (42”)
TV Color systems : ATSC : 60/132.3 (50”)
: NTSC
Video playback : NTSC
Cable : Unscrambled digital
1.2 Connection Overview
cable - QAM
: Digital cable ready - Note: The following connector color abbreviations are used
CableCard (acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy=
Presets/channels : 100 presets Grey, Rd= Red, Wh= White, and Ye= Yellow.
Tuner bands : VHF
: UHF 1.2.1 Side Connections
: S-band
: Hyper-band
Supported video formats : 640x480i-1fH SIDE I/O
: 640x480p-2fH
: 720x576i-1fH(BP2.2)
: 720x576p-2fH(BP2.2) USB
: 1280x720p-3fH
: 1920x1080i-2fH
Supported computer formats : 640x480 @ 60Hz R
: 800x600 @ 60Hz AUDIO
: 1024x768 @ 60Hz L
: 1366x768 @ 60Hz
CVBS
1.1.2 Sound
SVHS

Sound systems : AV Stereo E_14700_064.eps

: BTSC 071004
Maximum power (WRMS) : 2 x 15
Figure 1-1 Side I/O connections
1.1.3 Multimedia
USB1.1 (only for BP2.3)
Supported digital media : Compact Flash I & II
: Memory Stick
: Microdrive (upto 2GB) 1 2 3 4
: SD / mini SD Card E_06532_022.eps
: Multi Media Card 300904
: Smart Media Card
Figure 1-2 USB (type A)
Supported file formats : JPEG
: MP3 1 - +5V k
: MP3-pro 2 - Data (-) jk
: Slideshow (.alb) 3 - Data (+) jk
USB input : USB1.1 (12 Mbps) 4 - Ground Gnd H

Mini Jack: Audio Headphone - Out

Bk - Headphone 32 - 600 ohm / 10 mW ot
 Technical Specifications, Connections, and Chassis Overview BP2.2U, BP2.3U 1. EN 3

Cinch: Video CVBS - In, Audio - In 20 - Ground Gnd H

Ye - Video CVBS 1 VPP / 75 ohm jq
Wh - Audio L 0.5 VRMS / 10 kohm jq Aerial - In
Rd - Audio R 0.5 VRMS / 10 kohm jq - - F-type (US) Coax, 75 ohm D

SVHS (Hosiden): Video Y/C - In 1.2.4 Rear Connections (rest)

1 - Ground Y Gnd H
2 - Ground C Gnd H
3 - Video Y 1 VPP / 75 ohm j
4 - Video C 0.3 VPPP / 75 ohm j

1.2.2 Digital Media Reader with USB2.0 (only for BP2.2)

In some versions, a 6-in-1 card reader unit is available, which

is connected via USB to the Small Signal Board (see also par.
“Technical Specifications” -> “Multimedia”).
This unit also contains two USB2.0 connectors (see figure rear
connections).

1.2.3 Rear Connections (under side)

LAN
POD SLOT IEEE1394 UART HDMI 1 HDMI 2
19 1 19 1
18 2 18 2
ANTENNA
F_15400_003.eps
OPTIONAL 070305

MONITOR OUT
Figure 1-3 Rear connections (under side)
S/PDIF L R CVBS GEM
POD: CableCARD Interface OUT STAR

68p - See diagram B10A jk F_15400_001.eps

250505

IEEE1394 (optional) Figure 1-5 Rear connections (rest)

1 - Data (-) TPB- jk
2 - Data (+) TPB+ jk AV1 Cinch: Video YPbPrHV- In
3 - Data (-) TPA- jk Gn - Video Y 1 VPP / 75 ohm jq
4 - Data (+) TPA+ jk Bu - Video Pb 0.7 VPP / 75 ohm jq
Rd - Video Pr 0.7 VPP / 75 ohm jq
RJ45: LAN (optional) Bk - H-sync 0-5V jq
8p - See diagram B9A jk Bk - V-sync 0-5V jq

Service Connector (UART) AV1 Cinch: Video CVBS - In, Audio - In

1 - UART_TX Transmit k Ye - Video CVBS 1 VPP / 75 ohm jq
2 - Ground Gnd H Wh - Audio L 0.5 VRMS / 10 kohm jq
3 - UART_RX Receive j Rd - Audio R 0.5 VRMS / 10 kohm jq

HDMI 1 & 2: Digital Video, Digital Audio - In DIGITAL AUDIO Cinch: S/PDIF - In
Bk - Coaxial 0.2 - 0.6VPP / 75 ohm jq
19 1
18 2
E_06532_017.eps
AV1 S-Video (Hosiden): Video Y/C - In
250505
1 - Ground Y Gnd H
2 - Ground C Gnd H
Figure 1-4 HDMI (type A) connector 3 - Video Y 1 VPP / 75 ohm j
4 - Video C 0.3 VPPP / 75 ohm j
1 - D2+ Data channel j
2 - Shield Gnd H AV2 S-Video (Hosiden): Video Y/C - In
3 - D2- Data channel j 1 - Ground Y Gnd H
4 - D1+ Data channel j 2 - Ground C Gnd H
5 - Shield Gnd H 3 - Video Y 1 VPP / 75 ohm j
6 - D1- Data channel j 4 - Video C 0.3 VPPP / 75 ohm j
7 - D0+ Data channel j
8 - Shield Gnd H
AV2 Cinch: Video CVBS - In, Audio - In
9 - D0- Data channel j
Ye - Video CVBS 1 VPP / 75 ohm jq
10 - CLK+ Data channel j
Wh - Audio L 0.5 VRMS / 10 kohm jq
11 - Shield Gnd H
Rd - Audio R 0.5 VRMS / 10 kohm jq
12 - CLK- Data channel j
13 - n.c.
14 - n.c. AV3 Cinch: Video YPbPr - In
15 - DDC_SCL DDC clock j Rd - Video Pr 0.7 VPP / 75 ohm jq
16 - DDC_SDA DDC data jk Bu - Video Pb 0.7 VPP / 75 ohm jq
17 - Ground Gnd H Gn - Video Y 1 VPP / 75 ohm jq
18 - +5V j
19 - HPD Hot Plug Detect j
 EN 4 1. BP2.2U, BP2.3U Technical Specifications, Connections, and Chassis Overview

DIGITAL AUDIO Cinch: S/PDIF - Out GEMSTAR Mini Jack: Remote Control - In/Out
Bk - Coaxial 0.4 - 0.6VPP / 75 ohm kq 1 - Ground Gnd H
2 - RXD j
MONITOR OUT Cinch: Video CVBS - Out, Audio - Out 3 - TXD k
Ye - Video CVBS 1 VPP / 75 ohm kq 4 - IR-OUT k
Wh - Audio L 0.5 VRMS /10 kohm kq 5 - RXD k
Rd - Audio R 0.5 VRMS / 10 kohm kq

1.3 Chassis Overview

AMBI LIGHT PANEL AMBI LIGHT PANEL

AL (OPTIONAL) (OPTIONAL) AL

AUDIO AMPLIFIER C

B SMALL SIGNAL PANEL EXTERNAL I/O PANEL BE

LED PANEL J
E CONTROL BOARD

MULTI MEDIA SIDE I/O PANEL D

CARD READER
& USB (OPTIONAL)

F_15400_110.eps
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Figure 1-6 PWB/CBA locations

 Safety Instructions, Warnings, and Notes
2. Safety Instructions, Warnings, and Notes
Index of this chapter:
2.1 Safety Instructions
2.2 Warnings
2.3 Notes
2.1 Safety Instructions
Safety regulations require that during a repair:
• Connect the set to the Mains/AC Power via an isolation
transformer (> 800 VA).
• Replace safety components, indicated by the symbol h,
only by components identical to the original ones. Any
other component substitution (other than original type) may
increase risk of fire or electrical shock hazard.
Safety regulations require that after a repair, the set must be
returned in its original condition. Pay in particular attention to
the following points:
• Route the wire trees correctly and fix them with the
mounted cable clamps.
• Check the insulation of the Mains/AC Power lead for
external damage.
• Check the strain relief of the Mains/AC Power cord for
proper function.
• Check the electrical DC resistance between the Mains/AC
Power plug and the secondary side (only for sets which
have a Mains/AC Power isolated power supply):
1. Unplug the Mains/AC Power cord and connect a wire
between the two pins of the Mains/AC Power plug.
2. Set the Mains/AC Power switch to the "on" position
(keep the Mains/AC Power cord unplugged!).
3. Measure the resistance value between the pins of the
Mains/AC Power plug and the metal shielding of the
tuner or the aerial connection on the set. The reading
should be between 4.5 Mohm and 12 Mohm.
4. Switch "off" the set, and remove the wire between the
two pins of the Mains/AC Power plug.
• Check the cabinet for defects, to avoid touching of any
inner parts by the customer.
2.2 Warnings
• All ICs and many other semiconductors are susceptible to
electrostatic discharges (ESD w). Careless handling
during repair can reduce life drastically. Make sure that,
during repair, you are connected with the same potential as
the mass of the set by a wristband with resistance. Keep
components and tools also at this same potential. Available
ESD protection equipment:
– Complete kit ESD3 (small tablemat, wristband,
connection box, extension cable and earth cable) 4822
310 10671.
– Wristband tester 4822 344 13999.
• Be careful during measurements in the high voltage
section.
• Never replace modules or other components while the unit
is switched "on".
• When you align the set, use plastic rather than metal tools.
This will prevent any short circuits and the danger of a
circuit becoming unstable.
2.3 Notes
2.3.1 General
• Measure the voltages and waveforms with regard to the
chassis (= tuner) ground (H), or hot ground (I), depending
on the tested area of circuitry. The voltages and waveforms
shown in the diagrams are indicative. Measure them in the
BP2.2U, BP2.3U 2. EN 5
Service Default Mode (see chapter 5) with a color bar
signal and stereo sound (L: 3 kHz, R: 1 kHz unless stated
otherwise) and picture carrier at 475.25 MHz for PAL, or
61.25 MHz for NTSC (channel 3).
• Where necessary, measure the waveforms and voltages
with (D) and without (E) aerial signal. Measure the
voltages in the power supply section both in normal
operation (G) and in stand-by (F). These values are
indicated by means of the appropriate symbols.
• The semiconductors indicated in the circuit diagram and in
the parts lists, are interchangeable per position with the
semiconductors in the unit, irrespective of the type
indication on these semiconductors.
• Manufactured under license from Dolby Laboratories.
“Dolby”, “Pro Logic” and the “double-D symbol”, are
trademarks of Dolby Laboratories.
2.3.2 Schematic Notes
• All resistor values are in ohms and the value multiplier is
often used to indicate the decimal point location (e.g. 2K2
indicates 2.2 kohm).
• Resistor values with no multiplier may be indicated with
either an "E" or an "R" (e.g. 220E or 220R indicates 220
ohm).
• All capacitor values are given in micro-farads (µ= x10-6),
nano-farads (n= x10-9), or pico-farads (p= x10-12).
• Capacitor values may also use the value multiplier as the
decimal point indication (e.g. 2p2 indicates 2.2 pF).
• An "asterisk" (*) indicates component usage varies. Refer
to the diversity tables for the correct values.
• The correct component values are listed in the Spare Parts
List. Therefore, always check this list when there is any
doubt.
2.3.3 Rework on BGA (Ball Grid Array) ICs
General
Although (LF)BGA assembly yields are very high, there may
still be a requirement for component rework. By rework, we
mean the process of removing the component from the PWB
and replacing it with a new component. If an (LF)BGA is
removed from a PWB, the solder balls of the component are
deformed drastically so the removed (LF)BGA has to be
discarded.
Device Removal
As is the case with any component that, it is essential when
removing an (LF)BGA, the board, tracks, solder lands, or
surrounding components are not damaged. To remove an
(LF)BGA, the board must be uniformly heated to a temperature
close to the reflow soldering temperature. A uniform
temperature reduces the chance of warping the PWB.
To do this, we recommend that the board is heated until it is
certain that all the joints are molten. Then carefully pull the
component off the board with a vacuum nozzle. For the
appropriate temperature profiles, see the IC data sheet.
Area Preparation
When the component has been removed, the vacant IC area
must be cleaned before replacing the (LF)BGA.
Removing an IC often leaves varying amounts of solder on the
mounting lands. This excessive solder can be removed with
either a solder sucker or solder wick. The remaining flux can be
removed with a brush and cleaning agent.
After the board is properly cleaned and inspected, apply flux on
the solder lands and on the connection balls of the (LF)BGA.
Note: Do not apply solder paste, as this has shown to result in
problems during re-soldering.
 EN 6 2. BP2.2U, BP2.3U Safety Instructions, Warnings, and Notes

Device Replacement
The last step in the repair process is to solder the new
component on the board. Ideally, the (LF)BGA should be
aligned under a microscope or magnifying glass. If this is not
possible, try to align the (LF)BGA with any board markers.
So as not to damage neighboring components, it may be
necessary to reduce some temperatures and times.
More Information
For more information on how to handle BGA devices, visit this
URL: www.atyourservice.ce.philips.com (needs subscription,
not available for all regions). After login, select “Magazine”,
then go to “Workshop Information”. Here you will find
Information on how to deal with BGA-ICs.
2.3.4 Lead Free Solder
Philips CE is producing lead-free sets (PBF) from 1.1.2005
onwards.
avoid mixed regimes. If not to avoid, clean carefully the
solder-joint from old tin and re-solder with new tin.
• Use only original spare-parts listed in the Service-Manuals.
Not listed standard material (commodities) has to be
purchased at external companies.
• Special information for lead-free BGA ICs: these ICs will be
delivered in so-called "dry-packaging" to protect the IC
against moisture. This packaging may only be opened
short before it is used (soldered). Otherwise the body of the
IC gets "wet" inside and during the heating time the
structure of the IC will be destroyed due to high (steam-
)pressure inside the body. If the packaging was opened
before usage, the IC has to be heated up for some hours
(around 90°C) for drying (think of ESD-protection!).
Do not re-use BGAs at all!
• For sets produced before 1.1.2005, containing leaded
soldering tin and components, all needed spare parts will
be available till the end of the service period. For the repair
of such sets nothing changes.

In case of doubt whether the board is lead-free or not (or with

Identification: The bottom line of a type plate gives a 14-digit
serial number. Digits 5 and 6 refer to the production year, digits
7 and 8 refer to production week (in example below it is 1991
week 18).
mixed technologies), you can use the following method:
• Always use the highest temperature to solder, when using
SAC305 (see also instructions below).
• De-solder thoroughly (clean solder joints to avoid mix of
two alloys).

Caution: For BGA-ICs, you must use the correct temperature-

profile, which is coupled to the 12NC. For an overview of these
profiles, visit the website www.atyourservice.ce.philips.com
(needs subscription, but is not available for all regions)
You will find this and more technical information within the
"Magazine", chapter "Workshop information".
For additional questions please contact your local repair help
E_06532_024.eps desk.
230205

2.3.5 Practical Service Precautions

Figure 2-1 Serial number example

Regardless of the special lead-free logo (which is not always • It makes sense to avoid exposure to electrical shock.
indicated), one must treat all sets from this date onwards While some sources are expected to have a possible
according to the rules as described below. dangerous impact, others of quite high potential are of
limited current and are sometimes held in less regard.
• Always respect voltages. While some may not be
dangerous in themselves, they can cause unexpected
P reactions that are best avoided. Before reaching into a

b powered TV set, it is best to test the high voltage insulation.

It is easy to do, and is a good service precaution.

Figure 2-2 Lead-free logo

Due to lead-free technology some rules have to be respected

by the workshop during a repair:
• Use only lead-free soldering tin Philips SAC305 with order
code 0622 149 00106. If lead-free solder paste is required,
please contact the manufacturer of your soldering
equipment. In general, use of solder paste within
workshops should be avoided because paste is not easy to
store and to handle.
• Use only adequate solder tools applicable for lead-free
soldering tin. The solder tool must be able
– To reach at least a solder-tip temperature of 400°C.
– To stabilize the adjusted temperature at the solder-tip.
– To exchange solder-tips for different applications.
• Adjust your solder tool so that a temperature around 360°C
- 380°C is reached and stabilized at the solder joint.
Heating time of the solder-joint should not exceed ~ 4 sec.
Avoid temperatures above 400°C, otherwise wear-out of
tips will rise drastically and flux-fluid will be destroyed. To
avoid wear-out of tips, switch “off” unused equipment or
reduce heat.
• Mix of lead-free soldering tin/parts with leaded soldering
tin/parts is possible but PHILIPS recommends strongly to
 Directions for Use BP2.2U, BP2.3U 3. EN 7

3. Directions for Use

You can download this information from the following websites:
http://www.philips.com/support
http://www.p4c.philips.com

As the software upgrade is a new feature, it is explained below.

 EN 8 4. BP2.2U, BP2.3U Mechanical Instructions

4. Mechanical Instructions
Index of this chapter: Notes:
4.1 Cable Dressing • Figures below can deviate slightly from the actual situation,
4.2 Service Positions due to the different set executions.
4.3 Assy/Panel Removal • Follow the disassemble instructions in described order.
4.4 Set Re-assembly

4.1 Cable Dressing

F_15400_111.eps
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Figure 4-1 Cable dressing (BP2.2U)

4.2 Service Positions By placing a mirror under the TV, you can monitor the screen.

For easy servicing of this set, there are a few possibilities 4.2.2 Aluminium Stands
created:
• The buffers from the packaging.
• Foam bars (created for service).
• Aluminium service stands (created for Service).

4.2.1 Foam Bars

E_06532_019.eps
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Figure 4-3 Aluminium stands (drawing of MkI)

E_06532_018.eps
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Figure 4-2 Foam bars
The foam bars (order code 3122 785 90580 for two pieces) can
be used for all types and sizes of Flat TVs. By laying the TV
face down on the (ESD protective) foam bars, a stable situation
is created to perform measurements and alignments.
The new MkII aluminium stands (not on drawing) with order
code 3122 785 90690, can also be used to do measurements,
alignments, and duration tests. The stands can be
(dis)mounted quick and easy by means of sliding them in/out
the "mushrooms". The new stands are backwards compatible
with the earlier models.
Important: For (older) FTV sets without these "mushrooms", it
is obligatory to use the provided screws, otherwise it is possible
to damage the monitor inside!.
 Mechanical Instructions BP2.2U, BP2.3U 4. EN 9

4.3 Assy/Panel Removal

4.3.1 Metal Rear Cover

Caution: Disconnect the Mains/AC Power cord before you

remove the rear cover!

1. Place the TV set upside down on a table top, using the

foam bars (see part "Foam Bars").
Caution: do not put pressure on the display, but let the
monitor lean on the speakers or the Front cover.
2. Remove all T10 screws around the edges of the metal rear
cover: “parker” screws around the outer rim, “tapping”
screws around the connector plate.
3. Remove the four "mushrooms" from the rear cover.
4. Lift the metal rear cover from the set. Make sure that wires
and flat foils are not damaged.
1
4.3.2 Speaker Compartment Cover

After removing the metal rear cover, you gain access to the
Speaker Compartment covers.
1. Remove all T10 screws [1] around the outer rim of the
cover.
2. Remove the T10 screws [2] on top of the inner rim.
3. For sets with AmbiLight: Remove the T10 screws [3] at
the bottom of the inner rim.
4. After removal of all the screws, slightly push the top of the
cover inwards. This will lift the outer rim slightly up so you
can take the cover out.
F_15400_114.eps
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Figure 4-5 AmbiLight inverter panel connections
4.3.3 AmbiLight Inverter Panel (if present)
After removal of the Speaker Compartment Covers, this panel
is accessible.
1. Disconnect the cable(s) from the panel.
2. Remove the T10 mounting screws [1] that hold the assy.
3. Take out the panel from its bracket [2].

2
3

1
1 2
3

F_15400_117.eps
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F_15400_112.eps
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Figure 4-6 AmbiLight inverter panel removal
Figure 4-4 Speaker compartment cover removal
4.3.4 Control Panel
To release the complete cover (only for models with the
AmbiLight feature, as in figure above):
After removal of the Speaker Compartment Covers, this panel
• Lift the cover up; let it hinge at the top side.
is accessible. Release the clamps and take out the panel
• Now, unplug the cables [1] at the AmbiLight Inverter panel.

4.3.5 Speakers

After removal of the Speaker Compartment Covers, you can

access the speakers.
 EN 10 4. BP2.2U, BP2.3U Mechanical Instructions

4.3.6 Side I/O Panel 4.3.9 LED Panel

After removal of the Speaker Compartment Covers, this panel
is accessible.
1. Disconnect the cable(s) from the panel.
2. Remove the T10 mounting screws [1] that hold the assy.
3. Take out the panel from its bracket [2].
When defective, replace the whole unit.
1. Disconnect the cable(s) from the panel.
2. Remove the T10 mounting screws that hold the panel.
3. Take out the panel.
When defective, replace the whole unit.
4.3.10 Small Signal Board (SSB)

1. Remove all connector fixation screws [1] at the connector

plate (bottom side), and at the shielding plate (rear side).
2. Remove the fixation screws [2] of the connector plate itself.
2 3. Remove all shielding fixing screws [3].
4. Slide the connector plate away from the SSB [4], and lift the
shielding from the SSB.
5. Unplug all cables on the SSB.
6. Remove the mounting screws that hold the SSB, and lift
1 the panel from the set.

3 1

1
F_15400_116.eps
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Figure 4-7 Side I/O panel removal 4

4.3.7 Multimedia Card Reader (if present) 2

F_15400_113.eps
After removal of the Speaker Compartment Covers, this panel 190505
is accessible.
1. Unplug the related USB cable at the top of the SSB.
Figure 4-9 SSB top shielding
2. Remove the two T10 mounting screws [1] that hold the
assy.
When defective, replace the whole unit.

F_15400_118.eps
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Figure 4-8 Multimedia card reader removal

4.3.8 Audio Amplifier Panel

1. Disconnect all cables from the Audio Amplifier panel.

2. Remove the T10 mounting screw from the Audio panel.
3. Release the two plastic fixation pins.
4. Take out the Audio panel (it hinges at the top side).
 Mechanical Instructions BP2.2U, BP2.3U 4. EN 11

4.3.11 Plasma Display Panel / Glass Plate – Cable at LED panel.

1. Remove the T20 display panel mounting screws [1].
2. Remove the T10 screws [2] from the mounting frame.
3. Unplug all cable(s):
– LVDS cable at SSB side (fragile connector!).
– SSB supply cables at the Main Supply board.
– Mains cable at the Main Supply board.
– Side I/O cable at SSB side (fragile connector!).
– Keyboard cable at SSB side.
– Audio Amplifier supply cable at the Main Supply board.
– Loudspeaker cables (incl. ferrites) at the Audio panel.
4. Lift the metal frame (together with all PWBs) from the
display panel (see figure “Frame lift”).
5. After removal of the frame, lift the PDP from the set.

2 2

1 1

2 2

F_15400_121.eps
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Figure 4-10 Display panel removal (photo from LC4.9 chassis)

F_15400_120.eps
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Figure 4-11 Frame lift (photo from LC4.9 chassis)

 EN 12 4. BP2.2U, BP2.3U Mechanical Instructions

4.3.12 PDP Glass Plate

In order to remove/exchange the PDP glass plate:

1. Remove the PDP as described earlier.
2. Remove the T10 screws [1] from the mounting frame.
3. After removal of the frame, you can lift the glass plate from
the set.

F_15400_119.eps
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Figure 4-12 Glass plate removal (photo from LC4.9 chassis)

4.4 Set Re-assembly

To re-assemble the whole set, execute all processes in reverse

order.

Notes:
• While re-assembling, make sure that all cables are placed
and connected in their original position. See figure "Cable
dressing".
• Pay special attention not to damage the EMC foams on the
SSB shields. Ensure that EMC foams are mounted
correctly.
 Service Modes, Error Codes, and Fault Finding BP2.2U, BP2.3U 5. EN 13

5. Service Modes, Error Codes, and Fault Finding

Index of this chapter: frequency to which the set will tune, would be as specified
5.1 Test Points in the channel map and could be different from the one
5.2 Service Modes corresponding to the physical channel 3.
5.3 Stepwise Start-up • All picture settings at 50% (brightness, color, contrast).
5.4 ComPair • All sound settings at 50%, except volume at 25%.
5.5 Error Codes • All service-unfriendly modes (if present) are disabled, like:
5.6 The Blinking LED Procedure – (Sleep) timer.
5.7 Protections – Child/parental lock.
5.8 Fault Finding and Repair Tips – Picture mute (blue mute or black mute).
5.9 Software Upgrading – Automatic volume levelling (AVL).
– Auto switch "off" (when no video signal was received
for 10 minutes).
5.1 Test Points – Skip/blank of non-favorite pre-sets.
– Smart modes.
The chassis is equipped with test points (Fxxx) printed on the – Auto store of personal presets.
circuit board assemblies. As most signals are digital, it will be – Auto user menu time-out.
almost impossible to measure waveforms with a standard
oscilloscope. Therefore, waveforms are not given in this How to Activate SDM
manual. Several key ICs are capable of generating test Use one of the following methods:
patterns, which can be controlled via ComPair. In this way it is • Use the standard RC-transmitter and key in the code
possible to determine which part is defective. “062596”, directly followed by the “MENU” button.
Note: It is possible that, together with the SDM, the main
Perform measurements under the following conditions: menu will appear. To switch it "off", push the “MENU”
• Service Default Mode. button again.
• Video: Color bar signal. • Short for a moment the two solder pads [1] on the SSB,
• Audio: 3 kHz left, 1 kHz right. with the indication “SDM”. They are located outside the
shielding. Activation can be performed in all modes, except
5.2 Service Modes when the set has a problem with the Stand-by Processor.
See figure “SDM service pads”.

Service Default Mode (SDM) and Service Alignment Mode

(SAM) offer several features for the service technician, while
the Customer Service Mode (CSM) is used for communication 1
between a Customer Helpdesk and a customer.

There is also the option of using ComPair, a hardware interface

between a computer (see requirements below) and the TV
chassis. It offers the ability of structured troubleshooting, test
pattern generation, error code reading, software version
readout, and software upgrading.

Minimum requirements for ComPair: a Pentium processor,

Windows 95/98, and a CD-ROM drive (see also paragraph
“ComPair”).

5.2.1 Service Default Mode (SDM) F_15400_103.eps

110505

Purpose Figure 5-1 SDM service pads

• To create a pre-defined setting, to get the same
measurement results as given in this manual. After activating this mode, “SDM” will appear in the upper right
• To override SW protections (only applicable for protections corner of the screen (if you have picture).
detected by stand-by processor) and make the TV start up
to the step just before protection (a sort of automatic
How to Navigate
stepwise start up). See paragraph “Stepwise Start Up”.
When you press the “MENU” button on the RC transmitter, the
• To start the blinking LED procedure (not valid in protection
set will toggle between the SDM and the normal user menu
mode).
(with the SDM mode still active in the background).

Specifications
How to Exit SDM
Use one of the following methods:
Table 5-1 SDM default settings • Switch the set to STAND-BY via the RC-transmitter.
• Via a standard customer RC-transmitter: key in “00”-
Default sequence.
Region Freq. (MHz) system
Europe, AP-PAL/Multi 475.25 PAL B/G 5.2.2 Service Alignment Mode (SAM)
NAFTA, AP-NTSC, LATAM 61.25 (ch. 3) NTSC M
Purpose
• To perform (software) alignments.
• Tuning frequency 61.25 MHz for NTSC: The TV shall tune
• To change option settings.
to physical channel 3 only if channel 3 is an analog channel
• To easily identify the used software version.
or if there is no channel 3 installed in the channel map. If
• To view operation hours.
there is a digital channel installed in channel 3, then the
EN 14 5. BP2.2U, BP2.3U Service Modes, Error Codes, and Fault Finding

• To display (or clear) the error code buffer. Table 5-2 Display option code overview

How to Activate SAM Display HEX Display Type Size Vertical

Option Resolution
Via a standard RC transmitter: key in the code “062596”
000 00 PDP SDI HD V3 42” 768p
directly followed by the “INFO” button. After activating SAM
001 01 PDP SDI HD V3 50” 768p
with this method a service warning will appear on the screen,
002 02 PDP FHP ALIS 1024i 42” 1024i
you can continue by pressing the red button on the RC.
003 03 LPL 30” 768p
004 04 LPL: 37” 768p
Contents of SAM:
005 05 LPL 42” 768p
• Hardware Info.
006 06 SHARP 32” 768p
– A. VIPER SW Version. Displays the software version
007 07 PDP SDI SD V3 42” 480p
of the VIPER software (main software) (example:
008 08 PDP FHP ALIS 1024i 37” 1024i
BX23U-1.2.3.4_12345 = AAAAB_X.Y.W.Z_NNNNN).
009 09 LCOS XION - 720p
• AAAA= the chassis name.
010 0A LCD AUO 30” 768p
• B= the region: A= AP, E= EU, L= Latam, U = US.
011 0B LCD LPL 32” 768p
• X.Y.W.Z= the software version, where X is the
012 0C LCD AUO 32” 768p
main version number (different numbers are not
013 0D LCD SHARP 37” 768p
compatible with one another) and Y is the sub
014 0E LCD LPL HD 42” 1080p
version number (a higher number is always
015 0F PDP SDI SD 37” 480p
compatible with a lower number). The last two
016 10 PDP FHP ALIS 1080i 37” 1080i
digits are used for development reasons only, so
017 11 PDP FHP ALIS 580i 42” 1080i
they will always be zero in official releases.
018 12 PDP FHP 55” 768p
• NNNNN= last five digits of 12nc code of the
019 13 LCOS VENUS - 720p
software.
020 14 LCOS VENUS - 1080p
– B. SBY PROC Version. Displays the software version
021 15 LCD LPL 26” 768p
of the stand-by processor.
022 16 LCD LPL scanning BL. 32” 768p
– C. Production Code. Displays the production code of
023 17 LG SD 42” 480p
the TV, this is the serial number as printed on the back
024 18 PDP SDI SD V4 42” 480p
of the TV set. Note that if an NVM is replaced or is
025 19 PDP SDI HD V4 42” 768p
initialized after corruption, this production code has to
026 1A PDP FHP HD A2 42” 1024i
be re-written to NVM. ComPair will foresee in a
027 1B PDP SDI HD V4 50” 768p
possibility to do this.
028 1C LCD Sharp full HD 37” 1080p
• Operation Hours. Displays the accumulated total of
operation hours (not the stand-by hours). Every time the
TV is switched "on/off", 0.5 hours is added to this number. • Store. All options and alignments are stored when
• Errors. (Followed by maximal 10 errors). The most recent pressing “cursor right” and then the “OK”-button
error is displayed at the upper left (for an error explanation • SW Maintenance.
see paragraph “Error Codes”). – SW Events. Not useful for service purposes. In case of
• Defective Module. Here the module that generates the specific software problems, the development
error is displayed. If there are multiple errors in the buffer, department can ask for this info.
which are not all generated by a single module, there is – HW Events. Not functional at the moment this manual
probably another defect. It will then display the message is released, description will be published in an update
“UNKNOWN” here. manual if the function becomes available.
• Reset Error Buffer. When you press “cursor right” and
then the “OK” button, the error buffer is reset. How to Navigate
• Alignments. This will activate the “ALIGNMENTS” sub- • In SAM, you can select the menu items with the “CURSOR
menu. UP/DOWN” key on the RC-transmitter. The selected item
• Dealer Options. Extra features for the dealers. will be highlighted. When not all menu items fit on the
• Options. Extra features for Service. screen, move the “CURSOR UP/DOWN” key to display the
• Initialise NVM. When an NVM was corrupted (or replaced) next/previous menu items.
in the former EMG based chassis, the microprocessor • With the “CURSOR LEFT/RIGHT” keys, it is possible to:
replaces the content with default data (to assure that the – (De) activate the selected menu item.
set can operate). However, all preferences and alignment – (De) activate the selected submenu.
values are gone now, and option numbers are not correct.
Therefore, this was a very drastic way. In this chassis, the How to Exit SAM
procedure is implemented in another way: The moment the Use one of the following methods:
processor recognizes a corrupted NVM, the “initialize • Press the “MENU” button on the RC-transmitter.
NVM” line will be highlighted. Now, you can do two things • Switch the set to STAND-BY via the RC-transmitter.
(dependent of the service instructions at that moment):
– Save the content of the NVM via ComPair for Note: As long as SAM is activated, it is not possible to change
development analysis, before initializing. This will give a channel. This could hamper the White Point alignments
the Service department an extra possibility for because you cannot choose your channel/frequency any more.
diagnosis (e.g. when Development asks for this). Workaround: after you have sent the RC code “062596 INFO”
– Initialize the NVM (same as in the past, however now it you will see the service-warning screen, and in this stage it is
happens conscious). still possible to change the channel (so before pressing the
“OK” button).
Note: When you have a corrupted NVM, or you have replaced
the NVM, there is a high possibility that you will not have picture
any more because your display option is not correct. So, before
you can initialize your NVM via the SAM, you need to have a
picture and therefore you need the correct display option. To
adapt this option, use ComPair. The correct HEX values for the
options can be found in the table below.
 Service Modes, Error Codes, and Fault Finding
5.2.3 Customer Service Mode (CSM)
Purpose
When a customer is having problems with his TV-set, he can
call his dealer or the Customer Helpdesk. The service
technician can then ask the customer to activate the CSM, in
order to identify the status of the set. Now, the service
technician can judge the severity of the complaint. In many
cases, he can advise the customer how to solve the problem,
or he can decide if it is necessary to visit the customer.
The CSM is a read only mode; therefore, modifications in this
mode are not possible.
How to Activate CSM
Key in the code “123654” via the standard RC transmitter.
Note: Activation of the CSM is only possible if there is no (user)
menu on the screen!
How to Navigate
By means of the “CURSOR-DOWN/UP” knob on the RC-
transmitter, you can navigate through the menus.
Contents of CSM
• SW Version (example: BX23U-1.2.3.4_12345). Displays
the built-in main software version. In case of field problems
related to software, software can be upgraded. As this
software is consumer upgradeable, it will also be published
on the Internet.
• SBY Processor Version. Displays the built-in stand-by
processor software version. Upgrading this software will be
possible via a PC and a ComPair interface (see chapter
Software upgrade).
• Set Type. This information is very helpful for a helpdesk/
workshop as reference for further diagnosis. In this way, it
is not necessary for the customer to look at the rear of the
TV-set. Note that if an NVM is replaced or is initialized after
corruption, this set type has to be re-written to NVM.
ComPair will foresee a possibility to do this.
• Production Code. Displays the production code (the serial
number) of the TV. Note that if an NVM is replaced or is
initialized after corruption, this production code has to be
re-written to NVM. ComPair will foresee a possibility to do
this.
• Code 1. Gives the latest five errors of the error buffer. As
soon as the built-in diagnose software has detected an
error the buffer is adapted. The last occurred error is
displayed on the leftmost position. Each error code is
displayed as a 2-digit number. When less than 10 errors
occur, the rest of the buffer is empty (00). See also
paragraph Error Codes for a description.
• Code 2. Gives the first five errors of the error buffer. See
also paragraph Error Codes for a description.
• Headphone Volume. Gives the last status of the
headphone volume, as set by the customer. The value can
vary from 0 (volume is minimum) to 100 (volume is
maximum). Change via”MENU”, “TV”, “SOUND”,
“HEADPHONE VOLUME”.
• Dolby. Indicates whether the received transmitter
transmits Dolby sound (“ON”) or not (“OFF”). Attention: The
presence of Dolby can only be tested by the software on
the Dolby Signaling bit. If a Dolby transmission is received
without a Dolby Signaling bit, this indicator will show “OFF”
even though a Dolby transmission is received.
• Sound Mode. Indicates the by the customer selected
sound mode (or automatically chosen mode). Possible
values are “STEREO” and “VIRTUAL DOLBY
SURROUND”. Change via “MENU”, “TV”, “SOUND”,
“SOUND MODE”. It can also have been selected
automatically by signaling bits (internal software).
• Tuner Frequency. Not applicable for US sets.
• Digital Processing. Indicates the selected digital mode.
Possible values are “STANDARD” and “PIXEL PLUS”.
BP2.2U, BP2.3U 5. EN 15
Change via “MENU”, “TV”, “PICTURE”, “DIGITAL
PROCESSING”.
• TV System. Gives information about the video system of
the selected transmitter.
– M: NTSC M signal received
– ATSC: ATSC signal received
• Center Mode. Not applicable.
• DNR. Gives the selected DNR setting (Dynamic Noise
Reduction), “OFF”, “MINIMUM”, “MEDIUM”, or
“MAXIMUM”. Change via “MENU”, “TV”, “PICTURE”,
“DNR”
• Noise Figure. Gives the noise ratio for the selected
transmitter. This value can vary from 0 (good signal) to 127
(average signal) and to 255 (bad signal). For some
software versions, the noise figure will only be valid when
“Active Control” is set to “medium” or “maximum” before
activating CSM.
• Source. Indicates which source is used and the video/
audio signal quality of the selected source. (Example:
Tuner, Video/NICAM) Source: “TUNER”, “AV1”, “AV2”,
“AV3”, “HDMI 1”, “SIDE”. Video signal quality: “VIDEO”, “S-
VIDEO”, “RGB 1FH”, “YPBPR 1FH 480P”, “YPBPR 1FH
576P”, “YPBPR 1FH 1080I”, “YPBPR 2FH 480P”, “YPBPR
2FH 576P”, “YPBPR 2FH 1080I”, “RGB 2FH 480P”, “RGB
2FH 576P” or “RGB 2FH 1080I”. Audio signal quality:
“STEREO”, “SPDIF 1”, “SPDIF 2”, or “SPDIF”.
• Audio System. Gives information about the audible audio
system. Possible values are “Stereo”, ”Mono”, “Mono
selected”, “Analog In: No Dig. Audio”, “Dolby Digital 1+1”,
“Dolby Digital 1/0”, “Dolby Digital 2/0”, “Dolby Digital 2/1”,
“Dolby Digital 2/2”, “Dolby Digital 3/0”, “Dolby Digital 3/1”,
“Dolby Digital 3/2”, “Dolby Digital Dual I”, “Dolby Digital
Dual II”, “MPEG 1+1”, “MPEG 1/0”, “MPEG 2/0”. This is the
same info as you will see when pressing the “INFO” button
in normal user mode (item “signal”). In case of ATSC
receiving there will be no info displayed.
• Tuned Bit. Not applicable for US sets.
• Preset Lock. Indicates if the selected preset has a child
lock: “LOCKED” or “UNLOCKED”. Change via “MENU”,
“TV”, “CHANNELS”, “CHANNEL LOCK”.
• Lock After. Indicates at what time the channel lock is set:
“OFF” or e.g. “18:45” (lock time). Change “MENU”, “TV”,
“CHANNELS”, “LOCK AFTER”.
• TV Ratings Lock. Indicates the “TV ratings lock” as set by
the customer. Change via “MENU”, “TV”, “CHANNELS”,
“TV RATINGS LOCK”. Possible values are: “ALL”,
“NONE”, “TV-Y”, “TV-Y7”, “TV-G”, “TV-PG”, “TV-14” and
“TV-MA”.
• Movie Ratings Lock. Indicates the “Movie ratings lock” as
set by the customer. Change via “MENU”, “TV”,
“CHANNELS”, “MOVIE RATINGS LOCK”. Possible values
are: “ALL”, “NR”, “G”, “PG”, “PG-13”, “R”, “NC-17” and “X”.
• V-Chip Tv Status. Indicates the setting of the V-chip as
applied by the selected TV channel. Same values can be
shown as for “TV RATINGS LOCK”.
• V-Chip Movie Status. Indicates the setting of the V-chip
as applied by the selected TV channel. Same values can
be shown as for “MOVIE RATINGS LOCK”.
• Options 1. Gives the option codes of option group 1 as set
in SAM (Service Alignment Mode).
• Options 2. Gives the option codes of option group 2 as set
in SAM (Service Alignment Mode).
• AVL. Indicates the last status of AVL (Automatic Volume
Level): “ON” or “OFF”. Change via “MENU”, “TV”,
“SOUND”, “AVL”. AVL can not be set in case of digital
audio reception (e.g. Dolby Digital or AC3)
• Delta Volume. Indicates the last status of the delta volume
for the selected preset as set by the customer: from “-12”
to “+12”. Change via “MENU”, “TV”, “SOUND”, “DELTA
VOLUME”.
• HDMI key validity. Indicates the security key’s validity.
• IEEE key validity. Indicates the security key’s validity.
• POD key validity. Indicates the security key’s validity.
• Digital Signal Quality. Indicates quality of the received
digital signal (0= low).
 EN 16 5. BP2.2U, BP2.3U Service Modes, Error Codes, and Fault Finding

How to Exit CSM

Press any key on the RC-transmitter (with exception of the
“CHANNEL +/-”, “VOLUME”, “MUTE” and digit (0-9) keys).

5.3 Stepwise Start-up

The stepwise start-up method, as known from FTL/FTP sets is

not valid any more. The situation for this chassis is as follows:
when the TV is in a protection state detected via the Stand-by
Processor (and thus blinking an error) and SDM is activated via
shortcutting the pins on the SSB, the TV starts up until it
reaches the situation just before protection. So, this is a kind of
automatic stepwise start-up. In combination with the start-up
diagrams below, you can see which supplies are present at a
certain moment.
Important to know here is, that if e.g. the 3V3 detection fails
(and thus error 11 is blinking) and the TV is restarted via SDM,
the Stand-by Processor will enable the 3V3, but will not go to
protection now. The TV will stay in this situation until it is reset
(Mains/AC Power supply interrupted).

The abbreviations “SP” and “MP” in the figures stand for:

• SP: protection or error detected by the Stand-by
Processor.
• MP: protection or error detected by the VIPER Main
Processor.

Off

Mains
“off” Mains
“on”

- WakeUp requested WakeUp

- Acquisition needed requested

Stand-by Semi
(Off St-by)
Active
- No data Acquisition required
and no POD present
Stand-by
- St-by requested
- Tact SW pushed - Tact SW pushed

- WakeUp requested
- Acquisition needed

No data Acquisition WakeUp

required and
requested
POD present
- POD Card removed GoToProtection
- Tact SW pushed
GoToProtection

POD
Stand-by
GoToProtection

Protection
On
F_15400_095.eps
300505

Figure 5-2 Transition diagram

 Service Modes, Error Codes, and Fault Finding BP2.2U, BP2.3U 5. EN 17

Off Stand-by or action holder: MIPS

Protection action holder: St-by

Mains is applied

autonomous action
Standby Supply starts running.
+5V2, 1V2Stb, 3V3Stb and +2V5D become present.
In case of PDP 3V3 Vpr to CPU PDP becomes present.

st-by µP resets If the protection state was left by short circuiting the
SDM pins, detection of a protection condition during
startup will stall the startup. Protection conditions in a
playing set will be ignored. The protection mode will
All I/O lines have a “high” default state:
not be entered.
- Assert the Viper reset.
- Sound-Enable and Reset-Audio should remain “high”.
- NVM power line is “high”, no NVM communication possible.

- Switch Sound-Enable and Reset-Audio “high”.

Initialise I/O pins of the st-by µP, start keyboard scanning, RC They are “low” in the standby mode if the
detection, P50 decoding. Wake up reasons are “off”. standby mode lasted longer than 2s.

In case of FHP PDP: Switch PDPGO “low”

CPUGO (inverse of the stby I/O line POD-MODE) and PDPGO
are then both “low” and the PDP is in the “low power” mode.

Switching the POD-MODE and the

“on” mode “low” in an
SDI PDP set
Switching the POD-MODE
Switch “low” the NVM power reset line. Add a 2ms delay makes the PDP supplies go to the
low in an FHP PDP set
before trying to address the NVM to allow correct NVM “on” mode.Within 4 seconds, a
makes the CPUGO go “high”
initialization. valid LVDS must be sent to the
and starts the PDP CPU.
display to prevent protection.
(valid for V3 version)
Switch “on” all supplies by switching LOW the POD-MODE except in an FHP PDP Cold
and the ON-MODE I/O lines. Boot

+5V, +8V6, +12VS, +12VSW and Vsound are switched on
Wait 50ms and then start polling the detect-
5V, detect-8V6 and detect-12V every 40ms.
The availability of the supplies is checked through detect signals (delivered by
dedicated detect-IC's) going to the st-by µP. These signals are available for
+12V, +8V6, +5V, +1V2 and +2V5. A low to high transition of the signals should
occur within a certain time after toggling the standby line. If an observers is
detected before the time-out elapses, of course, the process should continue in
order to minimize start up time.

detect-5V
received within
No FHP PDP Set?
2900 ms after POD-MODE
toggle? No

Switching the PDPGO “high”

will give a visual artefact and Yes
should only be done if really
necessary.
Switch PDPGO high:
PDP should start: 5V, 8V6 and
Yes 12V are activated

detect-5V
received within
activate +5V supply detection algorithm Yes No +5V error
2900 ms after PDPGO
toggle?

SP
detect-12VSW received within
No +12V error
2900 ms after POD-mode
toggle?

Yes

activate +12VSW supply

SP
detection algorithm

No need to wait for the 8V6 detection at this point.

detect-8V6 received
within 6300 ms after POD-mode toggle?
Startup shall not wait for this detection
and continue startup. Yes

No
Enable the +1V2 supply (ENABLE-1V2)

activate +8V6 supply

+8V6 error
detection algorithm

Start polling the detect-1V2 every 40ms

SP return F_15400_096a.eps
To part B To part B 100505

Figure 5-3 “Off” to “Semi Stand-by” flowchart (part 1)

EN 18 5. BP2.2U, BP2.3U Service Modes, Error Codes, and Fault Finding

From part A From part B

action holder: MIPS

action holder: St-by

autonomous action

detect-1V2
received within No +1.2V error
250ms?

Yes
SP
Enable the supply for
+2.5V and +3.3V (ENABLE-3V3)
No separate enable and
detect is present for the +2V5
supply in the Baby Jaguar.
No
Start polling the detect-3V3 every 40ms

detect-3V3
received within No +3.3V error
250 ms?

Yes

Activate supply detection algorithms for

SP
+1V2 and +3V3

SUPPLY-FAULT I/O line

No Supply fault error
is High?

Yes

Enable the supply fault detection

SP
interrupt

Set I²C slave address

of Standby µP to (A0h)

Detect EJTAG debug probe

(pulling pin of the probe interface to
ground by inserting EJTAG probe)

EJTAG probe
Yes
connected ?

No

No Cold boot?

Release viper reset

Yes Feed initializing boot script (3)
disable alive mechanism

Release viper reset Release viper reset

Feed warm boot script(2) Feed cold boot script(1)

Release PNX2015 reset 100ms

after Viper reset is released

Release PNX2015 reset 100ms after

Viper reset is released

Bootscript ready
No
in 1250 ms?

Yes

Set I²C slave address

of Standby µP to (64h)

RPC start (comm. protocol)

Flash to RAM image

No
transfer succeeded
within 30s?
Code = 5
Yes

Viper SW initialization
Switch Viper in reset Code = 53 No
succeeded
within 20s?

To part C To part C To part C To part C

F_15400_096b.eps
260505

Figure 5-4 “Off” to “Semi Stand-by” flowchart (part 2)

 Service Modes, Error Codes, and Fault Finding BP2.2U, BP2.3U 5. EN 19

From part B From part B From part B

action holder: MIPS
Wait 10ms Yes
action holder: St-by
Enable Alive check mechanism
Switch the NVM reset autonomous action
line HIGH.

MIPS reads the wake up reason Wait until Viper starts to

from standby µP. communicate
Disable all supply related protections and
switch off the +2V5, +3V3 DC/DC converter.

Wait 5ms Wait for the +8V6 to be detected if not yet present. (if
it does not come, the standby µP will enter a
protection mode, this is not a dead end here)

switch off the remaining DC/DC

converters

Switch “on” the LVDS output of

Switch POD-MODE and ON-MODE
3-th try? the PNX2015 with a correct PWR-OK-PDP
I/O line “high”.
SDI PDP clock frequency within 4s after received within 10s
Yes No
Set? switching the POD and “on” after POD and “on” mode
mode to prevent PDP display toggle ?
Yes supply protection.
Log display
error and enter
Yes protection mode
Log Code as
error code

Init SDI PDP

These LVDS items are
SDI V3 display only !!
SP
SP No Switch LVDS back off if
end state is not the active
state.

Send STBYEN = 1
FHP PDP PFCON = 1
Yes Switch PDPGO “low”
Set? VCCON = 1
to PDP display (I²C)

Init FHP PDP

No

Start 4 seconds preheating timer in case of

a LPL scanning backlight LCD set.

AVIP needs to be started before the MPIF in order to have a good clock distribution.
AVIP default power-up mode is Standby. The Viper instructs AVIP via I²C to enable all the
PLLs and clocks and hence enter to Full Power mode.

Initialize PNX2015 HD subsystem

MPIFs should be initialized

MPIF should deliver 4 observers:
POR= 0; normal operation
MSUP = 1: Main supply is present
ASUP = 1; audio supply is present
ROK = 1; reference frequency is present (coming from AVIP)

Log appropriate
All observers present with correct state? No
Observer error

Yes

Initialize tuners and HDMI

Initialize source selection

Initialize video processing ICs

- Spider (if available)

Initialize Columbus
Initialize 3D Combfilter
Initialize AutoTV

Do not enter semi-standby state in case of an LPL

scanning backlight LCD set before 4 s preheating timer has
elapsed.

Semi-Stand-by F_15400_096c.eps
260505

Figure 5-5 “Off” to “Semi Stand-by” flowchart (part 3)

EN 20 5. BP2.2U, BP2.3U Service Modes, Error Codes, and Fault Finding

42" / 50" SDI V4

action holder: MIPS
Semi Stand-by
action holder: St-by

autonomous action

RGB video blanking

and audio mute.

Initialize audio and video processing ICs and

functions.

Wait untill QVCP generates a valid LVDS

output clock

Switch “on” LVDS transmitter

(PNX2015) (if not already on).

Switch the SDI Picture Flag “low” to enable picture. 1.5

seconds later, the display will unblank automatically
and show the LVDS content.

Enable anti-aging
(if applicable).

Switch “off” RGB blanking after valid, stable video.

Switch Audio-Reset and sound enable “low” and demute.

Active F_15400_097.eps
260505

Figure 5-6 “Semi Stand-by” to “Active” flowchart

Service Modes, Error Codes, and Fault Finding BP2.2U, BP2.3U 5. EN 21

42" / 50" SDI V4

action holder: MIPS
Active
action holder: St-by

autonomous action

Mute all sound outputs.

Switch RESET_AUDIO and

SOUND_ENABLE lines “high”

Blank PDP display.

Mute all video outputs.

Wait 600ms to prevent image

retention
(display error)

Switch “off” LVDS signal

(PNX2015).

Switch the SDI Picture Flag “high” to prevent

testpattern display in semi-standby mode

Semi Stand-by F_15400_098.eps

260505

Figure 5-7 “Active” to “Semi Stand-by” flowchart

EN 22 5. BP2.2U, BP2.3U Service Modes, Error Codes, and Fault Finding

action holder: MIPS

POD Semi Stand-by
action holder: St-by

autonomous action

Transfer Wake up reasons to the

Stand-by µP.

Images are re-transferred to DDR-RAM from

Flash RAM (verification through checksum).

MIPS image completes the application reload,

stops DDR-RAM access, puts itself in a
sleepmode, and signals the standby µP when
the Stand-by mode can be entered.

DDR-RAM is put in self refresh mode and the images

are kept in the hibernating DDR-RAM.

Wait 5ms

Switch Viper in reset state

Wait 10ms

Switch the NVM reset line “high”.

Disable all supply related protections and switch “off”

the +2V5, +3V3 DC/DC converter.

Wait 5ms

Switch “off” the remaining DC/DC converters

Switch “off” all supplies by switching “high” the POD-

MODE and the ON-MODE I/O lines.
Important remark:
release RESET AUDIO and For PDP this means
SOUND_ENABLE 2 sec after CPUGO becomes low.
entering stand-by to save power

Stand-by F_15400_099.eps
260505

Figure 5-8 “Semi Stand-by” / ”POD” to “Stand-by” flowchart

 Service Modes, Error Codes, and Fault Finding BP2.2U, BP2.3U 5. EN 23

action holder: MIPS

Semi Stand-by

action holder: St-by

This state transition is entered when stand-by is
autonomous action
requested and an authenticated POD is present.

Reboot

Power-down HDMI and 1394 hardware by keeping

POWERDOWN-1394-GPIO- 0 line “high”.

Set Viper HW blocks (TM1, TM2, MBS, VMSP1 and

VMSP2) to powerdown mode.

Hibernate the PNX2015 memory and keep the

PNX2015 in reset state

Disable +8V6 supply detection algorithm

Disable audio protection algorithm

Switch “off” all supplies which are not needed in POD

standby by switching “high” the ON-MODE I/O line.

POD Stand-by F_15400_100.eps

260505

Figure 5-9 “Semi Stand-by” to “POD Stand-by” flowchart

EN 24 5. BP2.2U, BP2.3U Service Modes, Error Codes, and Fault Finding

POD stand by

action holder: MIPS Switch “on” all supplies by switching “low”

the ON-MODE I/O line.
action holder: St-by

autonomous action Full SSB power and the display related supplies
become available

+8V6
detected within
No +8V6 error
200 ms after ON-MODE
toggle?

Yes

activate +8V6 supply SP

detection algorithm

Wait 2000ms to allow main supply to

deliver full power.

Enable audio protection algorithm

Switch “on” the LVDS output

the PNX2015 with a correct
PWR-OK-PDP
SDI PDP clock frequency within 4s after
Yes received within 5s after No
Set? switching the POD and ON-
POD and ONmode
mode to prevent PDP display
toggle ?
supply protection.
Log display error
and enter
Yes protection mode

No Init SDI PDP

These LVDS items are
SDI V3 display only !!
SP
Switch LVDS back “off” if end
state is not the active state.

Power-up HDMI and 1394 hardware by putting

POWERDOWN-1394 GPIO 0 line “low”.

Enable Viper HW blocks (TM1, TM2, MBS, VMSP1 and

VMSP2) which were in powerdown mode.

Release PNX2015 reset

(AVIPs must be started before the MPIFs in order to have a good clock distribution).
AVIP default power-up mode is Stand-by. The Viper instructs AVIP via I2C to enable all the
PLLs and clocks and hence enter to Full Power mode.

initialize PNX2015 HD subsystem

Initialize MPIFs
MPIF should deliver 4 observers:
POR= 0; normal operation
MSUP = 1: Main supply is present
ASUP = 1; audio supply is present
ROK = 1; reference frequency is present (coming from AVIP)

All observers present with correct state? No appropriate Observer error

Yes

Initialize tuners and Hirate

MP

Initialize source selection

Initialize video processing ICs

- Spider (if available)

Initialize Columbus
Initialize 3D Combfilter
Initialize AutoTV

Semi-Stand-by F_15400_101.eps
120505

Figure 5-10 “POD Stand-by” to “Semi Stand-by” flowchart

 Service Modes, Error Codes, and Fault Finding BP2.2U, BP2.3U 5. EN 25

action holder: MIPS

MP SP
action holder: St-by

autonomous action Log the appropriate error and

set stand-by flag in NVM

Redefine wake up reasons for protection

state and transfer to stand-by µP.

Switch “off” LCD lamp supply (for LCD sets)

If needed to speed up this transition, Wait 250ms (min. = 200ms)

this block could be omitted. This is
depending on the outcome of the
safety investigations.
Switch “off” LVDS signal

Switch “off” 12V LCD supply within a time frame of

min. 0.5ms to max. 50ms after LVDS switch “off”. (for LCD sets)

Ask stand-by µP to enter protection state

Switch Viper in reset state

Wait 10ms

Switch the NVM reset line “high”.

Disable all supply related protections and switch “off”

the +2V5, +3V3 DC/DC converter.

Wait 5ms

Switch “off” the remaining DC/DC converters

Switch “off” all supplies by switching “high” the POD-

MODE and the ON-MODE I/O lines.

Flash LED in order to indicate

protection state*.

(*): This can be the standby LED or the ON LED

depending on the availability in the set under
Protection discussion.
F_15400_102.eps
120505

Figure 5-11 “Protection” flowchart

 EN 26 5. BP2.2U, BP2.3U Service Modes, Error Codes, and Fault Finding
5.4 ComPair
5.4.1 Introduction
ComPair (Computer Aided Repair) is a service tool for Philips
Consumer Electronics products. ComPair is a further
development on the European DST (service remote control),
which allows faster and more accurate diagnostics. ComPair
has three big advantages:
• ComPair helps you to quickly get an understanding on how
to repair the chassis in a short time by guiding you
systematically through the repair procedures.
• ComPair allows very detailed diagnostics (on I2C level) and
is therefore capable of accurately indicating problem areas.
You do not have to know anything about I2C commands
yourself because ComPair takes care of this.
• ComPair speeds up the repair time since it can
automatically communicate with the chassis (when the
microprocessor is working) and all repair information is
directly available. When ComPair is installed together with
the Force/SearchMan electronic manual of the defective
chassis, schematics and PWBs are only a mouse click
away.
5.4.2 Specifications
ComPair consists of a Windows based fault finding program
and an interface box between PC and the (defective) product.
The ComPair interface box is connected to the PC via a serial
(or RS-232) cable.
For this chassis, the ComPair interface box and the TV
communicate via a bi-directional service cable via the service
connector(s).
The ComPair fault finding program is able to determine the
problem of the defective television. ComPair can gather
diagnostic information in two ways:
• Automatic (by communication with the television): ComPair
can automatically read out the contents of the entire error
buffer. Diagnosis is done on I2C/UART level. ComPair can
access the I2C/UART bus of the television. ComPair can
send and receive I2C/UART commands to the micro
controller of the television. In this way, it is possible for
ComPair to communicate (read and write) to devices on
the I2C/UART buses of the TV-set.
• Manually (by asking questions to you): Automatic
diagnosis is only possible if the micro controller of the
television is working correctly and only to a certain extend.
When this is not the case, ComPair will guide you through
the fault finding tree by asking you questions (e.g. Does the
screen give a picture? Click on the correct answer: YES /
NO) and showing you examples (e.g. Measure test-point I7
and click on the correct oscillogram you see on the
oscilloscope). You can answer by clicking on a link (e.g.
text or a waveform picture) that will bring you to the next
step in the fault finding process.
By a combination of automatic diagnostics and an interactive
question / answer procedure, ComPair will enable you to find
most problems in a fast and effective way.
5.4.3 How to Connect
This is described in the chassis fault finding database in
ComPair.
Caution: It is compulsory to connect the TV to the PC as
shown in the picture below (with the ComPair interface in
between), as the ComPair interface acts as a level shifter. If
you connect the TV directly to the PC (via UART), the VIPER
or PNX2015 will be blown!
TO TO
UART SERVICE I2C SERVICE
CONNECTOR CONNECTOR
PC VCR Power
9V DC
I2C
E_06532_021.eps
180804
Figure 5-12 ComPair interface connection
5.4.4 How to Order
ComPair order codes (US):
• ComPair Software: ST4191.
• ComPair Interface Box: 4822 727 21631.
• AC Adapter: T405-ND.
• ComPair Quick Start Guide: ST4190.
• ComPair interface extension cable: 3139 131 03791.
• ComPair UART interface cable: 3122 785 90630
Note: If you encounter any problems, contact your local
support desk.
5.5 Error Codes
5.5.1 Introduction
The error code buffer contains all detected errors since the last
time the buffer was erased. The buffer is written from left to
right, new errors are logged at the left side, and all other errors
shift one position to the right.
When an error has occurred, the error is added to the list of
errors, provided the list is not full or the error is a protection
error.
When an error occurs and the error buffer is full, then the new
error is not added, and the error buffer stays intact (history is
maintained), except when the error is a protection error.
To prevent that an occasional error stays in the list forever, the
error is removed from the list after 50+ operation hours.
When multiple errors occur (errors occurred within a short time
span), there is a high probability that there is some relation
between them.
Basically there are three kinds of errors:
• Errors detected by the Stand-by Processor. These
errors will always lead to protection and an automatic start
of the blinking LED for the concerned error (see paragraph
“The Blinking LED Procedure”). In these cases SDM can
be used to start up (see chapter “Stepwise Start-up”).
• Errors detected by VIPER that lead to protection. In this
case the TV will go to protection and the front LED will blink
at 3 Hz. Further diagnosis via service modes is not possible
here (see also paragraph “Error Codes” -> “Error Buffer” -
> “Extra Info”).
• Errors detected by VIPER that do not lead to
protection. In this case the error can be read out via
ComPair, via blinking LED method, or in case you have
picture, via SAM.
5.5.2 How to Read the Error Buffer
Use one of the following methods:
• On screen via the SAM (only if you have a picture). E.g.:
– 00 00 00 00 00: No errors detected
– 06 00 00 00 00: Error code 6 is the last and only
detected error
– 09 06 00 00 00: Error code 6 was first detected and
error code 9 is the last detected error
• Via the blinking LED procedure (when you have no
picture). See next paragraph.
• Via ComPair.
 Service Modes, Error Codes, and Fault Finding BP2.2U, BP2.3U 5. EN 27

5.5.3 How to Clear the Error Buffer content, as this history can give you significant information).
This to ensure that old error codes are no longer present.
Use one of the following methods: If possible, check the entire contents of the error buffer. In
• By activation of the “RESET ERROR BUFFER” command some situations, an error code is only the result of another error
in the SAM menu. code and not the actual cause (e.g., a fault in the protection
• With a normal RC, key in sequence “MUTE” followed by detection circuitry can also lead to a protection).
“062599” and “OK”. There are several mechanisms of error detection:
• If the content of the error buffer has not changed for 50+ • Via error bits in the status registers of ICs.
hours, it resets automatically. • Via polling on I/O pins going to the stand-by processor.
• Via sensing of analogue values on the stand-by processor.
• Via a “not acknowledge” of an I2C communication
5.5.4 Error Buffer

In case of non-intermittent faults, clear the error buffer before
you begin the repair (before clearing the buffer, write down the
Take notice that some errors need more than 90 seconds
before they start blinking. So in case of problems wait 2
minutes from start-up onwards, and then check if the front LED
is blinking.

Table 5-3 Error code overview

Error Description Error/Prot Detected by Device Defective module Result

1 I2C1 P VIPER n.a. I2C1_blocked Protection + 3 Hz blinking
2 I2C2 P VIPER n.a. I2C2_blocked Protection + 3 Hz blinking
3 I2C3 P Stby µP n.a. / Protection + Error blinking
4 I2C4 P VIPER n.a. I2C4_blocked Protection + 3 Hz blinking
5 VIPER does not boot P Stby µP PNX8550 / Protection + Error blinking
6 5V supply P Stby µP n.a. / Protection + Error blinking
7 8V6 supply P Stby µP n.a. / Protection + Error blinking
8 1.2V DC/DC P Stby µP n.a. / Protection + Error blinking
11 3.3V DC/DC P Stby µP n.a. / Protection + Error blinking
12 12V supply P Stby µP n.a. / Protection + Error blinking
14 Supply Class D amplifiers P Stby µP / Protection + Error blinking
14 Supply Audio part SSB P Stby µP / Protection + Error blinking
17 MPIF1 audio supply E VIPER PNX3000 IF I/O Error logged
18 MPIF1 ref freq E VIPER PNX3000 IF I/O Error logged
25 Supply fault P Stby µP / Protection + Error blinking
27 Phoenix E VIPER PNX2015B HD subsystem Error logged
28 MOP E VIPER EP1C6 Output processor Error logged
29 AVIP1 E VIPER PNX2015 AV input processor 1 Error logged
31 AVIP2 E VIPER PNX2015 AV input processor 2 Error logged
32 MPIF1 E VIPER PNX3000 / Error logged
34 Tuner1 E VIPER / Tuner 1 Error logged
37 Channel decoder E VIPER NXT2003 / Error logged
39 POD Interface E VIPER STV701 / Error logged
43 Hi Rate Front End E VIPER TDA9975 HDMI Error logged
44 Main NVM E VIPER M24C64 / Error logged
45 Columbus 1 E VIPER PNX2015 Comb filter Error logged
53 VIPER P Stby µP PNX8550 / Protection + Error blinking
63 PDP Display P VIPER / Display Protection + 3 Hz blinking
EN 28 5. BP2.2U, BP2.3U Service Modes, Error Codes, and Fault Finding
Extra Info
• Error 1 (I2C bus 1 blocked). When this error occurs, the
TV will go to protection and the front LED will blink at 3 Hz.
Now you can partially restart the TV via the SDM shortcut
pins on the SSB. Depending on the software version it is
possible that no further diagnose (error code read-out) is
possible. With the knowledge that only errors 1, 2, 4, and
63 result in a 3 Hz blinking LED, the range of possible
defects is limited.
• Error 2 (I2C bus 2 blocked). When this error occurs, the
TV will go to protection and the front LED will blink at 3 Hz.
Now you can partially restart the TV via the SDM shortcut
pins on the SSB. Due to hardware restriction (I2C bus 2 is
the fast I2C bus) it will be impossible to start up the VIPER
and therefore it is also impossible to read out the error
codes via ComPair or via the blinking LED method. With
the knowledge that only errors 1, 2, 4, and 63 result in a 3
Hz blinking LED, the range of possible defects is limited.
When you have restarted the TV via the SDM shortcut pins,
and then pressed "CH+" on your remote control, the TV will
go to protection again, and the front LED blink at 3 Hz
again. This could be an indication that the problem is
related to error 2.
• Error 3 (I2C bus 3 blocked). There are only three devices
on I2C bus 3: VIPER, Stand-by Processor, and NVM. The
Stand-by Processor is the detection device of this error, so
this error will only occur if the VIPER or the NVM is blocking
the bus. This error will also be logged when the NVM gives
no acknowledge on the I2C bus (see error 44). Note that if
the 12 V supply is missing (connector 1M46 on the SSB),
the DC/DC supply on the SSB will not work. Therefore the
VIPER will not get supplies and could block I2C bus 3. So,
a missing 12 V can also lead to an error 3.
• Error 4 (I2C bus 4 blocked). Same remark as with error 1.
• Error 5 (I2C bus 5 blocked). This error will point to a
severe hardware problem around the VIPER (supplies not
OK, VIPER completely dead, I2C link between VIPER and
Stand-by Processor broken, etc...).
• Error 12 (12 V error). Except a physical problem with the
12 V itself, it is also possible that there is something wrong
with the Audio DC Protection: see paragraph "Hardware
Protections" for this.
• Error 14 (Audio supply). This error combines two fault
conditions:
– First detection is done on the “on-board” audio supplies
(SSB). The current through resistor 3A95 (schematic
B3E) is measured. An over-current will lead to
protection and error 14 blinking.
– The second detection is done on the audio board itself.
Here, the absence of one of the audio supplies is
sensed, and will also lead to protection and error 14
blinked. For LCD sets this circuit can be found on
schematic SA3, for PDP sets this can be found on
schematic C.
• Error 17 (MPIF audio supply). This error indicates that the
8V-AUD is missing on pin 98 of the MPIF. The result of this
missing supply will be that there is no sound on external
sources (you will have sound from tuner).
• Error 29 (AVIP1). This error will probably generate extra
errors. You will probably also see errors 32 (MPIF) and
error 31 (AVIP 2). Error 29 and 31 will always be logged
together due to the fact that both AVIPs are inside the
PNX2015 and are on the same I2C bus. In this case start
looking for the cause around AVIP (part of PNX2015).
• Error 31 (AVIP2). See info on error 29.
• Error 34 (Tuner 1). When this error is logged, it is not sure
that there is something wrong with the tuner itself. It is also
possible that there is something wrong with the
communication between channel decoder and tuner. See
schematic B2B.
• Error 37 (Channel decoder). This error will always log
error 34 (tuner) extra. This is due to the fact that the tuner
I2C bus is coming from the channel decoder.
• Error 44 (NVM). This error will never occur because it is
masked by error 3 (I2C bus 3). The detection mechanism
for error 3 checks on an I2C acknowledge of the NVM. If
NVM gives no acknowledge, the stand-by software
assumes that the bus is blocked, the TV goes to protection
and error 3 will be blinking.
• Error 53. This error will indicate that the VIPER has started
to function (by reading his boot script, if this would have
failed, error 5 would blink) but initialization was never
completed because of hardware peripheral problems
(NAND flash, ...) or software initialization problems.
Possible cause could be that there is no valid software
loaded (try to upgrade to the latest main software version).
• Error 63 (PDP display). Same remark as with error 1.
5.6 The Blinking LED Procedure
5.6.1 Introduction
The blinking LED procedure can be split up into two situations:
• Blinking LED procedure in case of a protection detected by
the stand-by processor. In this case the error is
automatically blinked. This will be only one error, namely
the one that is causing the protection. Therefore, you do
not have to do anything special, just read out the blinks. A
long blink indicates the decimal digit, a short blink indicates
the units.
• Blinking LED procedure in the “on” state. Via this
procedure, you can make the contents of the error buffer
visible via the front LED. This is especially useful for fault
finding, when there is no picture.
When the blinking LED procedure is activated in the “on” state,
the front LED will show (blink) the contents of the error-buffer.
Error-codes > 10 are shown as follows:
1. “n” long blinks (where “n” = 1 - 9) indicating decimal digit,
2. A pause of 1.5 s,
3. “n” short blinks (where “n”= 1 - 9),
4. A pause of approx. 3 s.
5. When all the error-codes are displayed, the sequence
finishes with a LED blink of 3 s,
6. The sequence starts again.
Example: Error 12 9 6 0 0.
After activation of the SDM, the front LED will show:
1. 1 long blink of 750 ms (which is an indication of the decimal
digit) followed by a pause of 1.5 s,
2. 2 short blinks of 250 ms followed by a pause of 3 s,
3. 9 short blinks followed by a pause of 3 s,
4. 6 short blinks followed by a pause of 3 s,
5. 1 long blink of 3 s to finish the sequence,
6. The sequence starts again.
5.6.2 How to Activate
Use one of the following methods:
• Activate the SDM. The blinking front LED will show the
entire contents of the error buffer (this works in “normal
operation” mode).
• Transmit the commands “MUTE” - “062500” - “OK”
with a normal RC. The complete error buffer is shown.
Take notice that it takes some seconds before the blinking
LED starts.
• Transmit the commands “MUTE” - “06250x” - “OK”
with a normal RC (where “x” is a number between 1 and
5). When x= 1 the last detected error is shown, x= 2 the
second last error, etc.... Take notice that it takes some
seconds before the blinking LED starts.
 Service Modes, Error Codes, and Fault Finding
5.7 Protections 5.8
5.7.1 Software Protections
Most of the protections and errors use either the stand-by 5.8.1
microprocessor or the VIPER controller as detection device.
Since in these cases, checking of observers, polling of ADCs,
filtering of input values are all heavily software based, these
protections are referred to as software protections.
There are several types of software related protections, solving
a variety of fault conditions:
• Protections related to supplies: check of the 12V, +5V, 5.8.2
+8V6, +1.2V, +2.5V and +3.3V.
• Protections related to breakdown of the safety check
mechanism. E.g. since a lot of protection detections are
done by means of the VIPER, failing of the VIPER
communication will have to initiate a protection mode since
safety cannot be guaranteed anymore.
Remark on the Supply Errors 5.8.3
The detection of a supply dip or supply loss during the normal
playing of the set does not lead to a protection, but to a cold
reboot of the set.
Protections during Start-up
During TV start-up, some voltages and IC observers are
actively monitored to be able to optimize the start-up speed,
and to assure good operation of all components. If these
monitors do not respond in a defined way, this indicates a
malfunction of the system and leads to a protection. As the
observers are only used during start-up, they are described in
the start-up flow in detail (see paragraph “Stepwise Start-up").
5.7.2 Hardware Protections
There is one hardware protection in this chassis: “Audio DC
Protection”. This protection occurs when there is a DC voltage
on the speakers. In that case the main supply is switched "off",
but the stand-by supply is still working.
For the Samsung V4 PDP displays, all internal supplies, except
the 5V2, are switched "off" and the LED on the display’s Main
Supply blinks eleven times, which means there is an over-
voltage protection.
In case of LCD supplies, the 12V supply will drop. This will be
detected by the stand-by processor, which will start blinking the
12 V error (error 12).
Repair Tips
• If there is an audio DC protection (DC voltage on your
speakers), you will probably see error 12 blink. To be sure
there is an audio DC protection, disconnect the cable
between the SSB and the Audio PWB and also the cable
between the Main Supply and the Audio PWB. If the TV
starts up, it is very likely that there is DC voltage on the
speakers. Check, and replace if necessary, the audio
amplifiers.
• It is also possible that you have an audio DC protection
because of an interruption in one or both speakers (the DC
voltage that is still on the circuit cannot disappear through
the speakers).
BP2.2U, BP2.3U 5. EN 29
Fault Finding and Repair Tips
Read also paragraph "Error Codes" - "Extra Info".
MPIF
Important things to make the MPIF work:
• Supply.
• Clock signal from the AVIP.
• I2C from the VIPER.
AVIP
Important things to make the AVIP work:
• Supplies.
• Clock signal from the VIPER.
• I2C from the VIPER (error 29 and 31).
DC/DC Converter
Introduction
• The best way to find a failure in the DC/DC converters is to
check their starting-up sequence at power "on" via the
Mains/AC Power cord, presuming that the Stand-by
Processor is operational.
• If the input voltage of the DC/DC converters is around 12 V
(measured on the decoupling capacitors 2U17/2U25/
2U45) and the ENABLE signals are "low" (active), then the
output voltages should have their normal values.
• First, the Stand-by Processor activates the +1V2 supply
(via ENABLE-1V2).
• Then, after this voltage becomes present and is detected
OK (about 100 ms), the other two voltages (+2V5 and
+3V3) will be activated (via ENABLE-3V3).
• The current consumption of controller IC 7U00 is around 20
mA (that means around 200 mV drop voltage across
resistor 3U22).
• The current capability of DC/DC converters is quite high
(short-circuit current is 7 to 10 A), therefore if there is a
linear integrated stabilizer that, for example delivers 1.8V
from +3V3 with its output overloaded, the +3V3 stays
usually at its normal value even though the consumption
from +3V3 increases significantly.
• The +2V5 supply voltage is obtained via a linear stabilizer
made with discrete components that can deliver a lot of
current. Therefore, in case +2V5 (or +2V5D) is short-
circuited to GND, the +3V3 will not have the normal value
but much less. The +2V5D voltage is available in standby
mode via a low power linear stabilizer that can deliver up to
30 mA. In normal operation mode, the value of this supply
voltage will be close to +2V5 (20 - 30 mV difference).
• The supply voltages +5V and +8V6 are available on
connector 1M46; they are not protected by fuses. +12VSW
is protected for over-currents by fuse 1U04.
Fault Finding
• Symptom: +1V2, +2V5, and +3V3 not present (even for a
short while ~10ms).
1. Check 12V availability (fuse 1U01, resistor 3U22,
power MOS-FETs) and enable signal ENABLE-1V2
(active low).
2. Check the voltage on pin 9 (1.5 V).
3. Check for +1V2 output voltage short-circuit to GND that
can generate pulsed over-currents 7-10 A through coil
5U03.
4. Check the over-current detection circuit (2U12 or 3U97
interrupted).
• Symptom: +1V2 present for about 100 ms. Supplies +2V5
and +3V3 not rising.
1. Check the ENABLE-3V3 signal (active "low").
2. Check the voltage on pin 8 (1.5 V).
 EN 30 5. BP2.2U, BP2.3U Service Modes, Error Codes, and Fault Finding
3. Check the under-voltage detection circuit (the voltage
on collector of transistor 7U10-1 should be less than
0.8 V).
4. Check for output voltages short-circuits to GND (+3V3,
+2V5 and +2V5D) that generate pulsed over-currents
of 7-10 A through coil 5U00.
5. Check the over-current detection circuit (2U18 or 3U83
interrupted).
• Symptom: +1V2 OK, but +2V5 and +3V3 present for about
100 ms. Cause: The SUPPLY-FAULT line stays "low"
even though the +3V3 and +1V2 is available. The Stand-by
Processor is detecting that and switches all supply
voltages "off".
1. Check the value of +2V5 and the drop voltage across
resistor 3U22 (they could be too high)
2. Check if the +1V2 or +3V3 are higher than their normal
values. This can be due to defective DC feedback of
the respective DC/DC converter (3U18 or 3UA7).
• Symptom: +1V2, +2V5, and +3V3 look okay, except the
ripple voltage is increased (audible noise can come from
the filtering coils 5U00 or 5U03).
Cause: Instability of the frequency and/or duty cycle of one
or both DC/DC converters.
– Check resistor 3U06, the decoupling capacitors, the
AC feedback circuits (2U20 + 2U21 + 3U14 + 3U15 for
+1V2 or 2U19 + 2U85 + 3U12 + 3U13 for +3V3), the
compensation capacitors 2U09, 2U10, 2U23 and
2U73, and IC 7U00.
Note 1: If fuse 1U01 is broken, this usually means a pair of
defective power MOSFETs (7U01 or 7U03). Item 7U00 should
be replaced as well in this case.
Note 2: The 12V switch and 8V6 switch (see "DC/DC
CONNECTIONS" schematic) are not present on board: they
are bypassed by jumpers.
5.9 Software Upgrading
5.9.1 Introduction
The set software and security keys are stored in a NAND-Flash
(item 7P80), which is connected to the VIPER via the PCI bus.
It is possible for the user to upgrade the main software via the
USB port. This allows replacement of a software image in a
standalone set, without the need of an E-JTAG debugger. A
description on how to upgrade the software can be found in
chapter 3 "Directions For Use".
Important: When the NAND-Flash must be replaced, a new
SSB must be ordered, due to the presence of the security
keys!!! See table “SSB service kits” for the order codes.
Perform the following actions after SSB replacement:
1. Set the correct option codes (see sticker inside the TV).
2. Update the TV software (see chapter 3 for instructions).
3. Perform the alignments as described in chapter 8.
4. Check in CSM menu 5 if the HDMI and POD keys are valid.
Table 5-4 SSB service kits
Model Number New SSB order code
42PF9830A/37 3104 328 42601
50PF9630A/37 3104 328 42611
42PF9630A/37
32PF9630A/37 3104 328 42621
50PF7320A/37 3104 328 42631
42PF7320A/37
37PF7320A/37 3104 328 42641
32PF7320A/37 3104 328 42651
50PF9830A/37 3104 328 42661
42PF9730A/37 3104 328 42671
5.9.2 Procedure
The software image resides in the NAND-Flash, and is
formatted in the following way:
Partition 1
Trimedia2 image
USB CUSTOMER
Trimedia1 image
MIPS image
Partition 0
USB Download Application USB SERVICE
uBTM (boot block) EJTAG
E_14700_082.eps
120505
Figure 5-13 NAND-Flash format
Executables are stored as files in a file system. The boot loader
(uBTM) will load the USB Download Application in partition 0
(USB drivers, bootscript, etc). This application makes it then
possible to upgrade the main software via USB.
Software can be upgraded in two ways:
• Via the USB port.
• Via an external EJTAG tool.
Installing "Partition 0" software is possible via an external
EJTAG tool, but also in a special way with the USB stick (see
description in paragraph “Manual Start of Software Upgrade
Application“).
Software Upgrade via USB
To do a software upgrade (partition 1) via USB, the set must be
operational, and the "Partition 0" files for the VIPER must be
installed in the NAND-Flash!
The new software can be uploaded to the TV by using a
portable memory device or USB storage compliant devices
(e.g. USB memory stick). You can download the new software
from the Philips website to your PC.
Partition 0
To upgrade the USB download application (partition 0 except
the bootblock), insert an USB stick with the correct software,
but press the “red” button on the remote control (in ”TV” mode)
when it is asked via the on screen text.
Caution:
• The USB download application will now erase both
partitions (except the boot block), so you need to reload the
main SW after upgrading the USB download application.
As long as this is not done, the USB download application
will start when the set is switched “on”.
• When something goes wrong during the progress of this
method (e.g. voltage dip or corrupted software file), the set
will not start up, and can only be recovered via the EJTAG
tool!
Software Upgrade via EJTAG
If the "Partition 0" software is corrupted, the "Partition 0"
software needs to be installed.
This is only possible in dedicated workshops with special tools
like the EJTAG probe with software, or via the procedure
described below.
 Service Modes, Error Codes, and Fault Finding BP2.2U, BP2.3U 5. EN 31

5.9.3 Manual Start of the Main Software Upgrade Application

Normally, the software upgrading procedure will start

automatically, when a memory device with the correct software
is inserted, but in case this does not work, it is possible to force
the TV into the software upgrade application. To do so: 2
• Disconnect the TV from the Mains/AC Power.
• Press the “OK” button on a Philips DVD RC-6 remote
control (it is also possible to use the TV remote in "DVD"
mode).
• Keep the “OK” button pressed while connecting the TV to
the Mains/AC Power.
• The software upgrade application will start.
• When a memory device with upgrade software is
connected, the upgrade process will start.

5.9.4 Stand-by Software Upgrade

It will be possible to upgrade the Stand-by software via a PC

and the ComPair interface. Check paragraph "ComPair" on
how to connect the interface. To upgrade the Stand-by F_15400_104.eps
software, use the following steps: 110505

1. Disconnect the TV from the Mains/AC Power.

2. Short circuit the SPI pins [2] on the SSB. They are located Figure 5-14 SPI service pads
outside the shielding (see figure “SPI service pads).
3. Keep the SPI pins shorted while connecting the TV to the
Mains/AC Power.
4. Release the short circuit after approx. two seconds.
5. Start up HyperTerminal (can be found in every Windows
application via Programs -> Accessories ->
Communications -> HyperTerminal. Use the following
settings:
– COM1
– Bits per second = 19200
– Data bits = 8
– Parity = none
– Stop bits = 1
– Flow control = Xon / Xoff.
6. Press “Shift U” on your PC keyboard. You should now see
the following info:
– PNX2015 Loader V1.0
– 19-09-2003
– DEVID=0x05
– Erasing
– MCSUM=0x0000
– =
7. If you do not see the above info, restart the above
procedure, and check your HyperTerminal settings and the
connections between PC and TV.
8. Via “Transfer” -> “Send text file ...”, you can send the
proper upgrade file to the TV. This file will be distributed via
the Service Organization.
9. After successful programming, you must see the following
info:
– DCSUM=0xECB3
– :Ok
– MCSUM=0xECB3
– Programming
– PCSUM=0xECB3
– Finished
10. If you do not see this info, restart the complete procedure.
11. Close HyperTerminal.
12. Disconnect and connect Mains/AC Power again.
EN 32 5. BP2.2U, BP2.3U Service Modes, Error Codes, and Fault Finding

Personal Notes:

E_06532_012.eps
131004
 Block Diagrams and Overviews BP2.3U AA 6. EN 33

6. Block Diagrams and Overviews

Wiring Diagram
WIRING 42” & 50” PLASMA
8108

8148
8735

4P 3P 4P 3P C AUDIO AMPLIFIER 4P 3P 4P 3P
1M49 1M48 1M08 1M10

1M02
1M49 1M48 1M08 1M10

1735
7P

2P3
8102
AMBI LIGHT
AL (OPTIONAL) AL AMBI LIGHT
(OPTIONAL)

8149

1M52

1736
2P3
9P
8736
PLASMA PANEL
1M12 1M11 1M12
1M11

8110
3P 11P 3P
11P

9P

CN8003
9P10
CN8005

8152
5P
PDP
POWER SUPPLY
RIGHT PDP PDP LEFT

CN1M10
SPEAKER

4P
INVERTER INVERTER SPEAKER

CN1M02
7P
CN5003

CN4004
9P12

11P
AMBI LIGHT

AMBI LIGHT
CN1M46 CN1M03 CN8006 CN8001
11P 10P 10P 2P3
8900

8146
8103

CN2021 10P
31P LVDS 8136
CN2026
OR
8150 8120
11P 10P 2P 12P 9P 11P 12P
1M46 1M03 1M63 1D40 1M52 1M36 1M20
4P 31P

1H01
USB 1E40
1M49 1G50
40P
OR
1H07

1E40
40P
1E62
1U03

1M64
8140

20P
14P
3P

4P
8162
EJTAG
Power
E CONTROL BOARD

B SSB D SIDE I/O

8364

1E62
20P
MEMORY

1M36
20P
FILTER
Data

CARD
READER + POD Tuner
1N62
4P

2x USB 2.0 5P EXTERNAL

CONNECTOR 1M15
BE I/O
(OPTIONAL) 3P Compair
AC/Supply
1x
USB
1H01
8195

1M01
1M01
J 3P 12P
3P 1M20
LED PANEL

8101 F_15400_022.eps
310505
 Block Diagrams and Overviews BP2.3U AA 6. EN 34

Block Diagram Video

VIDEO 37” - 50”
B2B MAIN TUNER + OOB TUNER B3 MPIF MAIN: B4 PNX2015: B5 VIPER: B5B VIPER: MAIN MEMORY
7C00
PNX3000HL 7J00 7V00 7V01
PNX2015E PNX8550 K4D551638F
B3C IF
1T04 1C52 B5C B5B
7 107 VIFINP B4C TUNNELBUS
TD1336O
IF-OUT
12 IF-TER2 IF-TER2 2 LPF
SOUND
TRAP
GROUP
DELAY 14 PNX2015
TUNNELBUS DDR INTERFACE
DDR
8 108 VIFINN
OOB
OOB
SUPPLY 28
+5VMPIF
VIPER MM_DATA
SDRAM 1
MAIN HYBRID 7T41 35
1T41 UPC3218GV QSS QSSOUT TUN-VIPER-RX-DATA
TUNER 14 1 7 3 6 99 SIFINP
BPF LPF SCL-DMA-BUS2 North tunnel Tunnel Memory 7V02
IF-1 7C56-1 46 South tunnel
DIGITAL controller K4D551638F
CVBS-TER-OUT EF 3C71
IF-2
15 14 8 2 7 1 2 100 SIFINN BLOCK 40 SDA-DMA-BUS2
in out B3f TUN-VIPER-TX-DATA
SAW 44MHz TO AM INTERNAL MM_A(0-12)
5 13 AGC COTROL
DDR
TUNERAGC-MON

LPF AUDIO SWITCH

7C56-2
FAT-IF-AGC-MAIN

4
EF
5
3C73
120 CVBSOUTIF
B5C DVD
SDRAM 2
AUDIO/VIDEO CSS
B2A CHANNEL B3A CVBS-OUTA 19
N.C.
DECODER SOURCE SELECTION CVBS/Y RIM LPF
CVBS-OUTB 22 B4A AUDIO/VIDEO 2D DE
C LAM P N.C. B3B
7TG0
NXT2003 52 50 C-PRIM 7C32
2-Layer
CVBSOUTIF-MAIN 123 CVBS-IF AG28 DAC-CVBS EF Y-CVBS-MON-OUT
DTV CABLE AND Memory secondary
TERRESTRIAL
53 AUX-IF-AGC-MAIN AV1_CVBS 126 CVBS1 MPIF based scaler
VO-2 video out B3f
DV1F-CLK
RECEIVER N.C. DV1_CLK AD28 Dual SD
9 FAT-ADC-INP-MAIN 1 CVBS2 AF30 DV2A-CLK Temporal AJ30 C-MON-OUT
QAM 8VSB DV2_CLK single HD B3f
ADC 10 FAT-ADC-INN-MAIN AK28 DV3F-CLK noise redux AD27 VSYNC-HIRATE
Demodulator DV3_CLK MPE2 decoder B7A
12 CVBS_DTV
STROBE1N 60 STROBE1N-MAIN R4 AVP1_DLK1SN From AE28 HSYNC-HIRATE
7T43 A 250Mhz BE
POD

DATA LINK 1
FEC UPC3220GR + DATA STROBE1P 61 STROBE1P-MAIN R3 AVP1_DLK1SP MIPS32
1T41 AV2_Y-CVBS 4 CVBS|Y3 LPF D AVIP-1 B6 DISPLAY INTERFACE: MOP

POD-DATA
AGC MIX 7 LINK CPU
B3f
IN OUT 15 1
DATA1N 62 DATA1N-MAIN R2 AVP1_DLK1DN 7G00
119 1 AV2_C 5 C3 1
Micro- I2C TUNER AGC 16 14 B3f Yyuv XC3S200
GPIO 120 8 2FH Scaler and
Controller FRONT_Y-CVBS 8 CVBS|Y4 DATA1P 63 DATA1P-MAIN R1 AVP1_DLK1DP de-interlacer
CATV
35 FS-OUTP 5 OUT OF BAND B3f MUX
FS-OUTN FRONT_C 9 C4 DV1_DATA(0-9) DV1F-DATA 0 TO 7 DV-ROUT
36 6 TUNER B3f STROBE3N 50 STROBE3N-MAIN N4 AVP1_DLK3SN 1SD+1HD
AMP AMP LPF

DATA LINK 3
YUV
28 FDC-ADC-INP 10 OUT IN 12 AV7_Y-CVBS 15 Y_COMB A STROBE3P 51 STROBE3P-MAIN N3 AVP1_DLK3SP COLUMBUS 5 Layer
QPSK
ADC 29 FDC-ADC-INN 9 IF 13
B2f C LAM P
D
DATA
LINK 3D Comb
DV2_DATA(0-9)
Video
TS
Video in
primary MOP
Demodulator AV7_C 16 C_COMB DATA3N 52 DATA3N-MAIN N2 AVP1_DLK3DN filter and DV2A-DATA 0 TO 7 video out DV-GOUT PICTURE ENHANCEMENT
B3f 3 router
2nd noice HD/VGA/
Dual
SIF DATA3P 53 DATA3P-MAIN N1 AVP1_DLK3DP reduction 656
AV1-AV5-AV6_R-PR 25 R|PR|V_1 con
CVBS SEC A/D
MPEG_DATA
B7a Yyuv acces
YUV DV3_DATA(0-9) DV3F-DATA 0 TO 7 DV-BOUT
63 64 AV1-AV5-AV6_G-Y 26 G|Y|Y_1 RGB 2Fh
B7a Yyuv A STROBE2N 55 STROBE2N-MAIN P4 AVP1_DLK2SN
LEVEL
B10B 7P13

DATA LINK 2
AV1-AV5-AV6_B-PB 27 B|PB|U_1 D
B7a ADAPT U U,V DATA STROBE2P 56 STROBE2P-MAIN P3 AVP1_DLK2SP AVIP-2
MUX CLAMP INV.
AV2-AV4_R-PR 30 R|PR|V_2 A LINK
B3f PAL V DATA2N 57 DATA2N-MAIN P2 AVP1_DLK2DN For sets without MOP
2
AV2-AV4_G-Y 31 G|Y|Y_2 D This connection is
B10A POD 7P03 B10C BUFFERING B3f DATA2P 123 DATA2P-MAIN P1 AVP1_DLK2DP made with jumpers
STV0701 MONO SEC. 9G10 to 9G26
AV2-AV4_B-PB 32 B|PB|U_2
B3f CLP PRIM 46 HV-PRM-MAIN M3
AVP1_HVINFO1 MP-OUT-HS
FE-DATA CLP SEC
TIMING RGB_HSYNC J29 MP-HS 59
CIRCUIT 40 CLK-MPIF M4 J28 MP-OUT-VS MP-VS 60
CLP yuv MPIF_CLK RGB_VSYNC
MP-CLKOUT MP-CLK
COMMON AV2_FBL LE Video MPEG VO-1 RGB_CLK_IN J30 55
CRX-POD-A(8) B3f AVP2_HSYNCFBL2 J27 MP-OUT-FFIELD MP-FF 57
INTERFACE AV6_VSYNC G2 decoder RGB_UD
DRX-POD-(9) AVP2_VSYNC2 MP-OUT-DE MP-DE
HARDWARE
7P76 B3f RGB_DE K26 56
CONTROLLER
7P77 B7A HDMI B7B HDMI: I/O + CONTROL
B4B DV I/O INTERFACE
11 7B11 RIN (0-9) MP-ROUT MP-R
BUFFER POD-DATA TDA9975
12
1B01
1P01

To GIN (0-9) MP-GOUT MP-G

1 ARX2+ 1B33 PARX2+
DV1of VIPER RX2+A
POD DATA 3 ARX2- PARX2-
B5C RX2-A DV4_DATA_0 T0 9
4 ARX1+ 1B32 PARX1+
RX1+A HDMI DV4-DATA
VIP
BIN (0-9) MP-BOUT MP-B
6 ARX1- PARX1- Termination
Video
1

RX1-A
2

7 resistance (Optional)
ARX0+ 1B31 PARX0+ output
RX0+A control
9 ARX0- PARX0- formatter
RX0-A DV5-DATA
DV5_DATA_0 T0 9
B4G PNX2015: DISPLAY INTERFACE
10 ARXC+ 1B30 PARXC+
RXC+A
12 ARXC- PARXC- D1 DV4-CLK AK8
RXC-1
18

15
19

ARX-DCC-SCL
LVDS_TX 1G50
16 ARX-DCC-SDA
B26 TXPNXA- 5J50 12
HDMI 19 ARX-HOTPLUG 7B30 LVDS_AN
C26 TXPNXA- 13
CONNECTOR LVDS_AP
VSYNC-HIRATE
1B02 B5A A25 TXPNXB- 5J52 15
LVDS_BN
1 BRX2+ PBRX2+ VHREF DV-HREF AH9 B25 TXPNXB+ 16
1B33 A2 LVDS_BP
RX2+B timing DV-HREF
3 BRX2- PBRX2- Upsample A1 DV-VREF AJ9 DV-VREF
RX2-B generator
4 BRX1+ 1B32 PBRX1+ C2 DV-FREF AK9 D25 TXPNXC- 5J54 18
RX1+B Termination Derepeater DV-FREF LVDS_CN LVDS
6 BRX1- PBRX1- E25 TXPNXC+ 19 CONNECTOR
1

RX2-B resistance LVDS_CP

2

7 BRX0+ 1B31 PBRX0+ TO SCREEN

RX0+B control
9 BRX0- PBRX0- HDMI C23 TXPNXCLK- 5J56 21
RX0-B HDCP LVDS_CLKN
10 BRXC+ receiver D23 TXPNXCLK+ 22
1B30 PBRXC+
RXC+B L16 SDA-MM-BUS1 LVDS_CLKP
12 BRXC- PBRXC- I2C slave
RXC-B L15 SCL-MM-BUS1
18

15 interface TXPNXD- 24
19

BRX-DCC-SCL BRX-DCC-SCL LVDS_DN B24 5J58

HSCL B
16 BRX-DCC-SDA BRX-DCC-SDA C24 TXPNXD+ 25
HSDA B LVDS_DP
HDMI 19 BRX-HOTPLUG 7B31 M135-CLK Line time
E24 TXPNXE- 5J60 27
CONNECTOR VSYNC-HIRATE measuremebt LVDS_EN
F24 TXPNXE+ 28
B5A LVDS_EP
B4E
7LA7 STANDBY 7L50 1
AV1-AV6_FBL-HSYNC Activity M25P05 K4D261638F VDISP
HSYNC detection & Sync 2
B3f
AV6_VSYNC seperator B4D 3
B3f VSYNC sync selec. PMX-MA(0-12)
AV2-AV4_G-Y DDR INTERFACE PMX-MA 4
B3f AV1-AV5-AV6_G-Y SOG Slicers 512K 5 SPI-SDO
STANDBY
Clocks PROCESSOR
B3f
AV2-AV4_R-PR generator FLASH 6 SPI-CLK DDR
B3f Memory

B3f
AV1-AV5-AV6_R-PR R/PR 1 SPI-CSB
See
controller PNX-MDATA PNX-MDATA SDRAM
AV2-AV4_G-Y ADC 3 SPI-WP (0-15)
B3f AV1-AV5-AV6_G-Y G/Y
Block digram
PNX-MCLK-P
16Mx16
Control A17 45
B3f MCLK_P
AV2-AV4_B-PB A16 PNX-MCLK-N 46
B3f MCLK_N
AV1-AV5-AV6_B-PB B/PB
B3f

B3F MPIF MAIN: CONNECTION A BE2 EXTERNALS B D SIDE I/O BE1 EXTERNALS A
1002
1M36 1M36 1020
7A20 1E40 1E40
FRONT_Y-CVBS 2 2 Y MONITOR Y-CVBS-MON-OUT
AV2-AV4_R-PR 7A21 EF 1 1 AV2-AV4_R-PR AV7_Y-CVBS
B3a,B7b OUT BE2
BE1 FRONT_C 4 4 C BE2
B3a,B7b AV2-AV4_G-Y EF 2 2 AV2-AV4_G-Y
3 3 AV2-AV4_B_PB BE1 1060
B3a,B7b AV2-AV4_B_PB EF AV6_VSYNC
1060 EXT 1
4 4 N.C. BE1 BE2
B4a AV2-FBL
AV1-AV6_FBL-HSYNC AV2_Y-CVBS
Y/CVBS BE2
B3a AV2_C 6 6 AV2_C BE2
BE1
B3a AV2_Y-CVBS 7 7 AV2_Y-CVBS
BE1 EXT 2
B3b Y-CVBS-MON-OUT 9 9 Y-CVBS-MON-OUT
BE1 1080
B5c C-MON-OUT 10 10 N.C. 1080 1070 1
11 11 N.C. 1 1 3
B4e AV2-STATUS 3 3 AV2_C
5
N.C REGIMBEAU-AV6-VSYNC C 5 AV7_C BE2
5 4
12 12 4 BE2 2
B4A,B7a AV6_VSYNC AV6_VSYNC BE1
4
2
2
N.C AV1_CVBS-AV7-Y-CVBS SVHS
SVHS SVHS
B3a AV7_Y-CVBS 22 22 AV7_Y-CVBS BE1
N.C AV1-STATUS-AV7-C +8V +8V
AV7_C 23 23 AV7_C
B3a BE1

25 25 1030 1050
B3a CVBS-TER-OUT N.C.
B3a FRONT_Y-CVBS 33 33 FRONT_Y-CVBS 7012 7000
34 34 AV1-AV5-AV6_G-Y AV2-AV4_G-Y
B3a FRONT_C FRONT_C
BE2 BE2
7011 EXT 3 7001
EXT 1
AV1-AV5-AV6_B-PB AV2-AV4_B_PB
B3G MPIF MAIN: CONNECTIONS B 1E62 1E62 BE2 7002
BE2
7A01 7010
B3a,B7b AV1-AV5-AV6_R-PR 7A02 EF 1 1 AV1-AV5-AV6_R-PR AV2-AV4_R-PR
BE1 AV1-AV5-AV6_R-PR
2 BE2 BE2
B3a,B7b AV1-AV5-AV6_G-Y EF 2 AV1-AV5-AV6_G-Y BE1
B3a,B7b AV1-AV5-AV6_B-PB EF 3 3 AV1-AV5-AV6_B-PB BE1
AV1-AV6_FBL-HSYNC 5 5 AV1-AV6_FBL-HSYNC
B7b BE1
B7b AV6_VSYNC 6 6 N.C.
F_15400_123.eps
250505
 Block Diagrams and Overviews BP2.3U AA 6. EN 35

Block Diagram Audio

AUDIO
B2B MAIN TUNER + OOB TUNER B3D MPIF MAIN: AUDIO SOURCE SELECTION B4 PNX2015 B3G MPIF MAIN:CONNECTIONS B C AUDIO AMPLIFIER
1T04 7C00 7J00
TD1336O PNX3000HL PNX2015E

MAIN
HYBRID TUNER
1C52
7 107 VIFINP
IF PNX2015 +19-16V
12 2
8 108 VIFINN 7701
SEE ALSO TDA8925ST 5,13
B2A 7TG0 BLOCKDIAGRAM 7700-2 1M52 1M52 7700-2
NXT2003 VIDEO Driver 1736
99 SIFINP AH1 AUDIO-L 1 1 AUDIO-L 1 Control High 7 5700 1
DATA LINK 1 ADAC1 and
DTV CATV FOR MORE MORE DETAILS Driver
4 Handshake 2
CABLE AND OUT OF BAND SEE ALSO BLOCK DIAGRAM DEM DEC Low 3704
100 SIFINN AUDIO 3

DATA LINK
TERRESTRIAL TUNER VIDEO AND CONTROL
PROCESSING 7700-2 3 Temperature Sensor
RECEIVER I2D
DATA LINK 2 Current Protection Speaker L
AG1 AUDIO-R 3 3 AUDIO-R 7700-1 15W/8Ω
1735
B10A POD 7P03 B10C BUFFERING MPIF ADAC2
6 6 17
Control
and
Driver
High
11 5702 1
STV0701
B7A PROT-AUDIO-SUPPLY 7 7
14 Handshake Driver 2
7P76 DATA LINK 3 Low
COMMON 7P77 B6A SOUND-ENABLE 8 8
3716 3
FE-DATA INTERFACE POR 9 9 8,10
To B7A Speaker R
HARDWARE DV1of VIPER
BUFFER POD-DATA AUDIO SWITCH 15W/8Ω
CONTROLLER -19-16v 1M02
B5C
POD DATA A DLINK1 1
LPF -19-16V
DLINK2 2
D
72 DSNDR2 AC3 ADCAC12 3 TO 1M02
73 DSNDL2 4 A

DSND
AUDIO AD3 ADCAC11
BE1 EXTERNALS A BE2 EXTERNALS B B3G CONNECTIONS B AMPS +19-16V PDP
AM SOUND 74 DSNDR1 AE3 ADCAC10 7706:7713 5 SUPPLY
75 DSNDL1 AF3 SOUND-ENABLE DC 6
ADCAC19 SOUND
1E62 1E62 POR ENABLE DCPROT 7
DIGITAL 1001 AUDIO SWITCH AUDIO SWITCH
SPI-OUT 10 10 SPI-OUT (DIGITAL OUT) (ANALOG OUT)
AUDIO 7715-7717
OUT
B3e AVIP 3752 6705 -19-16V
SPI-1 8 8 SPI-1 PROT-AUDIO-SUPPLY AUDIO
B3e SUPPLY 3742 6704 +19-16V
PROT, CIRCUIT
1040
B3F CONNECTIONS A AUDIO-IN1-R 85 R1 40 CLK-MPIF M4
EXT 1 B3f AUDIO-IN1-L 86 L1
1E40 1E40 B3f
AUDIO-IN2-R 83
AUDIO IN AUDIO-IN1-R 28 28 AUDIO-IN1-R B3f R2
B3d AUDIO-IN2-L 84 L2
L+R+DIG B3f AUDIO-IN5-L 128 L5
AUDIO-IN1-L 27 27 AUDIO-IN1-L B3f
AUDIO-IN5-R 127 R5
B3d B3E AUDIO AMPLIFIER B3F CONNECTIONS A BE2 EXTERNALS B D SIDE I/O
B3f

1060 3A55
7A04-1

LINE / SCART L/R

EXT 2 31 31
AUDIO-IN2-R AUDIO-IN2-R
B3d AB1 ADAC7 7A09
AUDIO IN AUDIO-OUT1-R 70 ADAC7
B3f
L+R AUDIO-IN2-L 30 30 AUDIO-IN2-L AUDIO-OUT1-L 69
B3d B3f 1E40 1E40 1M36 1M36 1010
AUDIO-HDPH-L-AP 19 19 AUDIO-HDPH-L 10 10 SOUND L-HEADPHONE-OUT 2
7A04-2 3A66

1002 AA1 ADAC8 7A11 AUDIO-HDPH-R-AP 20 20 AUDIO-HDPH-R 11 11 SOUND R-HEADPHONE-OUT 3

ADAC8
AUDIO-OUT1-R 13 13 AUDIO-OUT1-R N.C. 7 7 DETECT 5 Headphone
B3d Out 3.5mm
AUDIO OUT
L+R AUDIO-OUT1-L 14 14 AUDIO-OUT1-L
B3d
B3E AUDIO AMPLIFIER B5 AUDIO VIDEO I/O
A-PLOP CONTROL
7V00
PNX8550EH

B5C V3
7A13 2 I2S-WS-MAIN
3 I2S_IN1_WS T29 I2S
I2S-BCLK-MAIN V2 OUT
SPI-1 1 4 SPDIF-IN1 AC30 SPDIF-IN1 I2S_IN1_SCK T30
D SIDE I/O B3g
1

1002
VIPER T28 I2S-MCH-LR U2
1M36 1M36 I2S_OUT2_SD0
6 36 36 SPI-OUT 11 12 SPI-OUT AB29 SPDIF-OUT1 T27 U3
L 6 AUDIO-IN5-L AUDIO-IN5-L B3g I2S-MCH-CSW
13 I2S_OUT2_SD1
B3d U4 I2S
AUDIO IN R30 I2S-MCH-SLR
I2S_OUT2_SD2 IN
L+R R 8 8 AUDIO-IN5-R 37 37 10 V5
AUDIO-IN5-R U27 I2S-SUB-D
B3d I2S_OUT1_SD0
I2S-MAIN-D V4
I2S_OUT2_SD3 R29

B5B VIPER: MAIN MEMORY

7V02
7V01
INTERFACE

MT46V32M16P MM_DATA
DDR

2X DDR AA27 SPDIF-HDMI

SDRAM
8Mx16 MM_A(0-12)

B7A HDMI B7B HDMI: I/O + CONTROL

7B11
TDA9975
1B01
HDMI PANELLINK
RECEIVER
1
2

1B02 A7 SPDIF-HDMI
RX2+
RX2-

PARX2+
1

RX1+
2

RX1- Termination
Resistance
Control Audio DV4-DATA
RX0+
Formatter
18

RX0- DV
PBRX2+
19

INPUT
AUDIO RXC+ Audio PLL Audio FIFO
MULTIPLEXED RXC- DV5-DATA
HDMI
18

WITH VIDEO
19

CONNECTOR HDMI Packet

SEE ALSO HDCP
BLOCKDIAGRAM receiver extraction
HDMI VIDEO
CONNECTOR
F_15400_124.eps
240505
 Block Diagrams and Overviews BP2.3U AA 6. EN 36

Block Diagram Control

CONTROL
B5A VIPER: CONTROL B8 USB 2.0: HOST B5 VIPER: A/V + TUNNELBUS AL AMBI LIGHT

7001 7018 1M11

7N00 7V00
PNX8550EH P87LPC760 7009 7015 5014 RED
ISP1561BM 11
1M49
1 7 14
3H14 SCL
PCI-CLK-USB20 PCI-CLK-USB20 PLL-OUT TO 1M49
1H01 1M46 1N62
B5E 2 MICRO
1 1 1
For Bx2.1 and Bx2.2 sets RESET-ETHERNET B25 VIPER CONTROLLER 7019
1 2 2 2 USB20-DM1 B9A 3 6 7010 7016 5015 BLUE
To Memory Card Reader
3 2
RESET-USB20 E26 See also SDA 6
3 3 3 USB20-DP1 PCI B8
Plus 2x USB 2.0 RESET-FE-MAIN F1 block diagram 12
Connector at the side 4 4 4 HOST B2A I2C
4 8
RXD
4

CONTROLLER SOUND-ENABLE-VPR C27

B3G 1M48
RESET-POD-CI AE29
B10A 1 7020
USB 5016 GREEN
TO 2nd 7011 7017 1
CONNECTOR
No USB Supply! AMBI LIGHT 2 13
PWB 1M12
(Optional) 3 1

2
B9A ETHERNET B10D POD: TS BUFFERING D SIDE I/O
7O00
7P81 7P80 VIPER 3
DP83816AVNG
TC58DVM92F1T (Optional)
1O10 1005 1H01 1H01
1 46 PCI-AD(25-31) BUFFERING 1 1 1

1
2 45 2 2 2 AJ28
EEPROM

3 2
3 +3V3ET-ANA
MAC 3 3 3 AH27
32Mx16
4 PHYTER II 4 4 4

4
Only on
1 8 5 54
Bx2.1 Sets
STBY-WP-NAND-FLASH NAND B3G MPIF MAIN: CONNECTIONS B BE2 EXTERNALS B
6 53
B4A FLASH
7 USB
N.C. CONNECTOR
8 XIO-A(16-23)
ETHERNET No USB Supply!
CONNECTOR 1E62 1E62
For Bx2.3 sets B26 GLINK-RXD 13 13 GLINK-RXD
1x USB 1.1
PCI-AD(0-31) 7106
Connector 7H02 1010
7107
2
D26 EF GLINK-IR-OUT 11 11 GLINK-IR-OUT 4
B10A POD: COMMON INTERFACE B10C POD: BUFFERING B11B FIREWIRE 1394: BUFFERING
3
E24 GLINK-TXD 12 12 GLINK-TXD 1
DV1F-DATA(0-7)
7Z10
7P31 G-LINK
7Z11

1P01 7P32 7Z12

XIO-A(0-23) PCI-AD(0-31)
POD-A(0-13)
BUFFERING BUFFERING
B4 PNX2015: DV I/O INTERFACE
7P34
DV1F-CLK
DV1F-DATA9_SOP 7J00
DV1F-VALID PNX2015E

POD-D(0-7) BUFFERING PCI-AD(24-31)

DATOE
DATDIR 7P76
68P PCI-AD(0-31)
7P03
7P77
STV0701

POD-DATA(0-7) PNX2015
MDOA(0-7)

POD-CLK BUFFERING DV1F-DATA(0-7) DV1F-DATA(0-7)

POD-SOP
DV1F-CLK DV1F-CLK
MDIA(0-7) POD-VALID
DV1F-DATA9_SOP DV1F-DATA9_SOP
COMMON DV1F-VALID DV1F-VALID

RDY_IRQA INTERFACE B2A CHANNEL DECODER E TOP CONTROL B3B MPIF MAIN: SUPPLY
WAITA
RSTA
HARDWARE 1M01 DETECT-1V2 AF16
CD1 CONTROLLER 7TG0 ON / OFF
KEYBOARD 2 DETECT-3V3 AH17 STANDBY &
CD2 B4E DETECT-5V AG17 CONTROL
NXT2003
CE1 CHANNEL + DETECT-8V6 AK18
CE2 CHANNEL - DETECT-12V AJ18
MICLKA
VOLUME + AG22 STBY-WP-NAND- B10D
MISTRTA DTV AV1-STATUS AK24 FLASH
VOLUME - B3G
MIVALA CABLE AND AV2-STATUS AJ24
B3G
OE TERRESTRIAL MENU
FE-DATA(0-7) RXD-UP AK19 AK16 ENABLE-3V3
WE RECEIVER B10D
VS1 J LED SWITCH PANEL P50 AJ13 AH15 ENABLE-1V2 B1A
FE-CLK 1M01 B3G
VSE P50-HDMI AG13
FE-SOP 2 B7A
IORD PROT-AUDIOSUPPLY
FE-VALID AG18
IOWR B3E B3G B5E
SUPPLY-FAULT AG13
B1A B10A AJ21 RESET-SYSTEM
BE2 EXTERNALS B B3F B5A
AH21 RESET-AUDIO
B4A
AH16 COM-SND
B3G
1M20 1M20 1E40 1E40
KEYBOARD 1 1 39 39 KEYBOARD
AK23
3061 6060 7061 7LA3
+5v2-STBY 3
LED1 LED1 3 38 38 LED1 EF LED1-3V3 AK21
BLUE/GREEN
AJ16 LAMP-ON
B6

7 P00 1040 AJ19 TXD-UP

B10D
TPS2211AIDB 3040 4 4 40 40
RC RC AK13
+5v2-STBY
VPPEN IR
POWER SENSOR
VCCEN B3G
INTERFACE
SWITCH
7070
1E62 1E62 9C48
6070 AH20 SDM
LIGHT-SENSOR 5 5 19 19 LIGHT-SENSOR AH23
LIGHT 9C45 SDM
SENSOR
3051 6051 AH26 SCL-UP-VIP
7051 7LA3
+5v2-STBY EF AJ26 SDA-UP-VIP
LED2 LED2 9 9 18 18 LED2 LED2-3V3 AG20
RED F_15400_125.eps
300505
 Block Diagrams and Overviews BP2.3U AA 6. EN 37

I2C ICs Overview

IIC
B5A VIPER: CONTROL B7A HDMI B7B HDMI: I/O + CONTROL B10A POD: COMMON INTERFACE B6 DISPLAY INTERFACE:MOP B5E VIPER: DEBUG AL AMBI LIGHT

+3V3

3H23
3H22
A25 3Q11 SDA-MM SDA-MM-BUS1
I2C1-SDA
C25 3Q10 SCL-MM SCL-MM-BUS1
I2C1-SCL

3G22

3G24
3B61

3B60

3P13

3P12
F26 ERR
7V00-5 TXD-VIPER 01 1B01 L16 L15 16 10
7B00-7B01 47 46
PNX8550 16 ARX-DDC-SDA PARX-DDC-SDA K16 +5V
E27 RXD-VIPER

1
2
VIPER 15 ARX-DDC-SCL PARX-DDC-SCL K15 7B11-2 7P03 5 JTAG-TRST 7G00
TDA9975EL STV0701 XC3S200

3Q30
3Q29
1M49 1M49
1B02 7B04-7B05 3G61 SDA-MOP 3Q73
B27 EJTAG-TDI HDMI COM. INTERFACE 51 7Q05-2 3 3 SDA
16 BRX-DDC-SDA PBRX-DDC-SDA J16 MOP
CONTROL HW CONTROLLER

18
D25 EJTAG-TDO

19
ERR ERR 15 BRX-DDC-SCL PBRX-DDC-SCL J15 3G62 SCL-MOP 3Q72
05 53 EJTAG-TMS 50 7Q05-1 1 1 SCL
A29
ERR ERR ERR

3B08

3B07

3B20

3B19
A28 EJTAG-TCK

3002

3001
43 39 28
2x HDMI
CONNECTOR JTAG-TRST L14 L14 JTAG-TRST
C2 JTAG-TRST +3V3
5 6 5 6 6 7
AD4 RESET-SYSTEM 7B02 7B03
M24C02 M24C02
B1C 7001
P87LPC760BDH 1M48
EEPROM EEPROM 1
(Optional) (Optional)
MICRO TO SECOND
B3B MPIF MAIN: SUPPLY B4E PNX2015: STANDBY & CONTROL B2A MAIN TUNER + OOB TUNER B2B MAIN TUNER + AMBI LIGHT PWB
+3V3 OOB TUNER CONTROLLER 3
+5V

3T10
3T11
3H05
3H04

AF29 3Q13 SDA-DMA SDA-DMA-BUS2 I2C-SDA-TUNER-MAINNXT

I2C2-SDA
AD26 3Q12 SCL-DMA SCL-DMA-BUS2 I2C-SCL-TUNER-MAINNXT
I2C2-SCL (Optional)

3LH4

3LH3
3LG9

3LH1

3LH0
3C40

3C39

3LF8
B9B UART
ERR
02 8
43 44 AG9 AF9 G5 G4 B27 C27 119 120 9
AG11 JTAG-TRST
+3V3-MAIN
7C00-3 7J00-6 7TG0 1T04
AF12 EJTAG-DETECT
PNX3000HL PNX2015E 7T10 NXT2003 TD1336
PCA9515ADP O/FGHP

3TJ7
3TJ6
AJ21 RESET-SYSTEM 1M15
MPIF CONTROL DTV 3O15
3Q15 MAIN TXD 1
COLUMBUS AVIP HD 7L50 2 6 58 RECEIVER
K4D261638F DIG TUNER 2
ERR ERR
18 ERR ERR ERR ERR 3Q14 ERR ERR UART SERVICE
17 DDR
45 29 31 27 3 7 59 37 34
RXD 3O16 3 CONNECTOR
ERR SDRAM
32 16Mx16

B12 MISCELLANEOUS
SDA-DMA-BUS1 9M05 SDA-DMA-BUS1-ATSC

SCL-DMA-BUS1 9M04 SCL-DMA-BUS1-ATSC

B10D POD: TS BUFFERING B4E PNX2015: STANDBY & CONTROL B10D POD: TS BUFFERING B1C VTUN GENERATOR

+3V3-STANDBY 7P15
74HC4066PW
3LE3
3LE4

TXD-VIPER 10 8
AE27 3Q15 SDA-UP-VIP B5A 1U03
I2C3-SDA 3U79
TXD-UP 9 11 TXD 1
AG29 3Q14 SCL-UP-VIP
I2C3-SCL B4E UART
3U81 CONNECTOR

3LE2
3LF0

RXD-UP 2 1 RXD 3 RES

B5B VIPER: MAIN MEMORY ERR
B4E
03 5 6 AG26 AH26
7V01 3L91 RXD-VIPER 3 4
TXD-UP AJ19
K4D551638F B5A
7P14 7J00-5 7P16
3L90 UART-SWITCHn 5
DDR M24C64 RXD-UP AK19 PNX2015E 3LM7
AG16 UART-SWITCH 12
SDRAM 1
EEPROM B10D PNX2015
(8Kx8) 7LA7 STANDBY +3V3-STANDBY
7V02

3LC6
3LC7
M25P05-AVMN6P 7P17 6 1H07
K4D551638F
3LH8
ERR DDR AF14 13 JTAG-TRST 1
DDR 44
SDRAM 3LH9
SDRAM 2 16Mx16 AG14 EJTAG-DETECT 2

EJTAG-TDI 3
B4G PNX2015: DISPLAY INTERFACE EJTAG
EJTAG-TDO 5 CONNECTOR
(FACTORY USE
+3V3 ONLY)
EJTAG-TMS 7

9
3Q03

EJTAG-TCK
3Q04

1G50
A3 3H99 SDA-I2C4 9J16 SDA-I2C4-DISP 31 9U07
I2C4-SDA TYPE 9J16 9J17 7J04 RESET-SYSTEM 11
TO 50PF9830A/37 X X - B5A
B4 3H98 SCL-I2C4 9J17 SCL-I2C4-DISP 30 DISPLAY RES
I2C4-SCL 50PF9630A/37 X X -
42PF9630A/37 X X -
50PF7320A/37 X X -
ERR ERR 42PF7320A/37 X X -
USB 04 7J04 63
CONNECTOR PCA9515DP
1
3 2
4

RES
SEE ALSO
BLOCK DIAGRAM F_15400_126.eps
CONTROL (OPTIONAL DEPENDING ON SCREEN) 310505
 Block Diagrams and Overviews BP2.3U AA 6. EN 38

Supply Lines Overview

SUPLY LINE OVERVIEW
MAIN TUNER + OOB TUNER PNX 2015: TUNNELBUS VIPER: DISPLAY DIVERSITY + AMBILIGHT B10B POD: OUT OF BAND
B1B DC/DC CONNECTIONS B2B B4C B5E
+8V6-SW +8V6-SW +2V5 +2V5 +5V +5V +3V3 +3V3
B1a B1a
B1b B1b
CN1M46 1M46 7T00
7U08 3U47 +8V6-SW +5VTUN 5L01 3L38 VREF-PNX +3V3 +3V3 1M53 TO
1 1 IN OUT
B2b,B7a B1a B4d 1 MEMORY POD: BUFFERING
B3b,e,f,g
COM
CARD B10C
2 2 +12VSW +3V3 READER
+5V +5V B1a +3V3 +3V3
PNX 2015: DDR INTERFACE B1a
3 3 5U04 +8V6
B1b B4D 1M03
PDP 4 4 5U05 +12VS
B1a
5T50 5T51 +5V-OOB VREF-PNX VREF-PNX CN1M03
5 +5V-CON

5U06 +5V B4c PSU +5V2-STBY_9V-STBY POD: TS BUFFERING

POWER SUPPLY 5

6
5

6
B2b,B3b,e,g
B5a,e,B6,B7c B1a
+1V2 +1V2
9 +5V2-STBY_9V-STBY
B1b B10D
B1a +3V3 +3V3
+5V2-STBY B10d
7 7 5U07 MPIF MAIN: VIDEO SOURCE SELECTION +2V5 +2V5
B1a,c,B3e,f, B3A B1a
DISPLAY INTERFACE: MOP +3V3-STANDBY +3V3-STANDBY
8 8
+5V2-STBY_
B4a,e,g,B7c, B6 B12
B10d,B12 +5VMPIF-MAIN +5VMPIF-MAIN 5L52 +2V5-DDRPNX
9 9 5M08 9V-STBY B3a,c
B1b +3V3 +3V3 +5V2-STANDBY +5V2-STANDBY
B5e B1b
11 11 5U12 5L51 B1a
5G01 +3V3M

CN1M03 B3B MPIF MAIN: SUPPLY 7G02 B11A FIREWIRE 1394: MAIN
+2V5M
5 B4E PNX 2015: STANDBY & CONTROL IN OUT
+5V +5V COM +3V3 +3V3
B1a
TO 1M03 B1b +1V2 +1V2
B1a
9 B5E 1C33 +5VMPIF-MAIN 7G03 5Z02 +3V3-VCCA
VIPER +1V2M
+1V2-STANDBY +1V2-STANDBY IN OUT
CN1M02 COM
5C35 7C31-1 VREF-AUD-POS B12 5Z00 +3V3-VCCD
1 B4a
+3V3 +3V3 +5V +5V
7C00 B1a B1b
2 VREF-AUD
2
B3e +3V3-STANDBY +3V3-STANDBY +8V6-SW +8V6-SW
B11B FIREWIRE 1394: BUFFERING
TO 1M02 MPIF 7C31-2 VREF-DEFL B12 B1b
C +3V3 +3V3
B1b +5V2-STBY +5V2-STBY
AUDIO B1a
5 AMPLIFIER 20 B7A HDMI
5Z50 +3V3BUFF
6 +8V6-SW +8V6-SW +3V3 +3V3
B4F PNX 2015: SUPPLY
B7a B1a 1B01
3C31 2x HDMI AIN-5V
+8VMPIF-MAIN B1a B3c +1V2 +1V2 1
CN1M10 CONNECTOR B12 MISCELLANEOUS
TO 1M10 1B02
1 AL 5LN1 PLL-1V2 1 BIN-5V +3V3 +3V3
AMBI B1a
LIGHT
+3V3 +3V3 +5V2-STBY +5V-STBY
B3C MPIF MAIN: IF + SAW FILTER B1a B1b
3M73 7M05
5LN3 LVDS-3V3 HDMI: I/O + CONTROL +3V3-STANDBY
B3b +8VMPIF-MAIN +8VMPIF-MAIN B7B IN OUT
B4e,f,g
COM
+3V3 +3V3 B9b,B10d
B1A DC/DC 5C52 +8VaM 5LN0 PLL-3V3
B1a
+12VS +12VS TO DV4-VALID DV4-VALID 3M79 7M06
B1b +5VMPIF-MAIN +5VMPIF-MAIN +3V3-STANDBY +3V3-STANDBY +1V2-STANDBY
B3b B4B IN OUT
B12 B4e
1U04 B4g,B5e PNX2015 COM
+12SW 3C51 3B40 3V3-DIG
+5VbM 5LN2 UP-3V3
B3e
1U01 B3e,B4a,e,f,g
7U29 7U01 5U00 +3V3 5C54 +5VaM
B1a +2V5 +2V5
B5a,c,d,e,B6,
B7a,b,c,B8, B7C HDMI: SUPPLY BE1 EXTERNALS A
12V/3.3V Conversion +2V5-DDRPNX +2V5-DDRPNX
7U00 B9a,B10a,b,c,d,
14 B4f +3V3 +3V3
1 B11a,b,B12 B4d +8V +8V
B3D MPIF MAIN: AUDIO SOURCE SELECTION B1a
7U03 5U03 +1V2 B4a,d,e,f BE2
Control B5,b,d 5B17 +3V3-APLL VREF VREF
+5V-AUD +5V-AUD PNX 2015: DISPLAY INTERFACE
12V/1.2V Conversion
B3e B4G BE2
16 5B11 3V3-PLL
B3e +8V-AUD +8V-AUD +3V3 +3V3
B1a
7U27 BE2 EXTERNALS B
+2V5 B4c,d,f 5B12 3V3-DIG
IN OUT
5J08 VDISP2
COM B5d
+2V5 Stabilizer MPIF MAIN: AUDIO AMPLIFIER 7B12 1E40
B3E +5VDISP +5VDISP
3B52 +1V8 8 +8V6 +8V6
1M20
B5e IN OUT
+3V3 +3V3 COM 6
B1a 3153
5J10 VDISP 5B18 +1V8-PLL 5100 +8V
7U17 TO 1E40 BE1
+5V2-STBY +2V5D +5V +5V
B1b IN OUT B3F
COM B1b +12VSW +12VSW +5V +5V 3154 VREF
B1a B1b
+2V5D Linear Stabilizer +5V2-STBY +5V2-STBY BE1
7B38
B1b 7J06 +3V3-AV 24 +5V2-STBY +5V2-STBY
IN OUT
+12VSW +12VSW COM 10
B1a 3156
5B10 +3V3-AVI +5V
7A07 +8V-AUD
B3d
7A05 +3V3-STANDBY +3V3-STANDBY
B12 USB 2.0: HOST
B8
VREF-AUD VREF-AUD +5V2-STBY +5V2-STBY
DC/DC B3b B1b
B1C +3V3 +3V3
LED SWITCH PANEL
+8V6-SW +8V6-SW B1a J
7U21 B1b
+5V2-STBY +3V3-UART +5V2-STBY +5V2-STBY
B1b +5V-AUD VIPER: CONTROL 1M20
IN OUT
COM
7A06 B3d B5A B1b
6 +8V +8V
3N31 7N10 3N33 3V3-STANDBY
+3V3 +3V3
+3V3 +3V3 B1a
B1a
+5V +5V +3V3-STANDBY-TRANS
B1b
B3F MPIF MAIN: CONNECTIONS A
1E40
B2A CHANNEL DECODER +5V2-CONN +5V2-STBY +5V2-STBY
VIPER: MAIN MEMORY B9A ETHERNET 10
24 B5B
+2V5 +2V5 +5V2-STBY +5V2-STBY VREF-VPR VREF-VPR +3V3 +3V3
B1a B1b B5c B1a
TO 1E40
1U01 5T55 +2V5_ATSC +8V6-SW +8V6-SW BE2 +2V5D +2V5D 5O00 +3V3-ET-DIG AL AMBI LIGHT
B1a
B1b 8
5Y10 5TG0 +2V5A-XTAL-MAIN 5A06 +8V6-CONN 5V01 +2V5D-DDR 5O01 +3V3-ET-ANA TO 1M10
1010 7002
CN1M10 6 +12V_A +5V
IN OUT
5TG1 +2V5A-FAT-MAIN PSU COM
1M08
ETHERNET TO SECOND
5TG2 +2V5A-FDC-MAIN
B3G MPIF MAIN: CONNECTIONS B B5C VIPER: A/V + TUNNELBUS B9B 1 AMBI LIGHT
+5V +5V +3V3 +3V3 +3V3-STANDBY +3V3-STANDBY PWB
B1a B12 (OPTIONAL)
5TG3 +2V5D-PLL-MAIN B1b
+8V6-SW +8V6-SW +2V5-VPR +2V5-VPR
5TG4 +2V5A-MAIN B1b B5d
B10A POD: COMMON INTERFACE C AUDIO AMPLIFIER
3H50 VREF-VPR
1M02
5TG5 +2V5A-PLL-MAIN B5b +3V3 +3V3 1 -19-16V
B4A PNX2015: AUDIO / VIDEO B1a
2 5708 -19-16VS1
5TG6 +2V5-MAIN +1V2 +1V2 5P02 VCC_EXTO
B1a B5D VIPER: SUPPLY
5714 -19-16VS2
+3V3 5TG7 +3V3-MAIN +3V3 +3V3 1V2 1V2 +5V +5V CN1M02
B1a B1a PSU 7702 5701 VDDOPAMP
B1a B1b

3713
+1V2 5TG7 +1V2 +5V2-STBY +5V2-STBY +2V5 +2V5 7P00
B1b B1a
B1a 3 10 POD-VPP 5 +19-16V
7TG1 +1V2_ATSC +12VS +12VS 5Q07 +2V5-VPR 6
Control 5705 +19-16VS1
B1b B5c 9 11 POD-VCC
5TG8 +1V2_MAIN VREF-AUD-POS VREF-AUD-POS +3V3 +3V3 5709 +19-16VS2
B3b B1a

F_15400_127.eps
260505
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 39

7. Circuit Diagrams and PWB Layouts

Ambi Light Panel (Optional)
1004 D1 2001 A2 2010 C6 2040 C7 2070 D7 3007 D7 3016 C2 3026 D2 5007 A8 6004 D6 7002 A3 7017-2 D7 F002 C4 F011 E1 F020 B2 F029 C10 F038 C7 F050 B5 I006 B5
1010 A2 2002 A3 2011 B6 2041 C8 2071 D8 3008 C6 3017 B4 3027 D2 5008 A8 6005 D5 7009 B5 7018 A5 F003 C4 F012 E1 F021 B1 F030 E10 F040 B7 F060 D5 I007 A6
1050 C4 2003 C2 2012 B6 2042 C8 2072 D8 3009 C6 3018 A4 3028 C2 5014 A9 6006 B6 7010 C5 7019 B5 F004 C4 F013 E1 F022 B1 F031 E10 F041 B7 F098 E4 I008 A6
1M08 A1 2004 D2 2020 A7 2050 C7 3001 C1 3010 C7 3019 A4 3029 A4 5015 B9 6007 B6 7011 E5 7020 D5 F005 C2 F014 E1 F023 A2 F032 E9 F042 A7 F099 E4 I009 B6
1M10 B1 2005 D4 2021 A8 2051 C8 3002 D1 3011 B7 3020 A4 3030 B4 5016 C9 6008 C6 7015-1 A7 A001 E10 F006 D2 F015 D1 F024 A2 F033 E9 F043 A7 I001 A2 I010 C6
1M11 B10 2006 D4 2022 A8 2052 C8 3003 D4 3012 B6 3022 E2 3031 C5 6000 A6 6009 C6 7015-2 A7 A002 B1 0 F007 E2 F016 C1 F025 A1 F034 E7 F045 B5 I002 C2 I011 D6
1M12 E10 2007 E6 2030 B7 2060 D7 3004 E6 3013 B6 3023 E2 3042 E8 6001 B6 6010 E6 7016-1 C7 A003 A1 0 F008 E1 F017 C1 F026 A3 F035 D7 F046 C5 I003 D2 I012 D6
1M48 C1 2008 E6 2031 B8 2061 D8 3005 E6 3014 B7 3024 D4 3999 E4 6002 C6 6011 E6 7016-2 C7 A004 A1 0 F009 E1 F018 B2 F027 A10 F036 D7 F047 D5 I004 D5
1M49 E1 2009 C6 2032 B8 2062 D8 3006 D7 3015 A7 3025 C4 5002 A9 6003 C6 7001 C3 7017-1 D7 F001 C4 F010 E1 F019 B2 F028 B10 F037 C7 F048 A5 I005 C5

1 2 3 4 5 6 7 8 9 10

AL AMBI LIGHT AL

22u

22u
22u
(OPTIONAL)

5007

5002
5014

5008
BD21416-00
I007 B11B-XASK-1
3015 F043 F027
11
1 A004
1K0 10

47n

47n

47n
9

7
8
3018

3019

3020
RED 2 13

4K7

4K7

4K7
A 8 A
7002 7018 I008 7015-1

2020

2021

2022
SI4946 A003 7 TO
LD1117DT BC847BW 2 3
6 CCFL
1M08 I001 F048 F042

1
F025 1010 F026 3029 5
3 2 +5V 4 11
TO 2nd AMBI 1 IN OUT 4
2 F024 F 3A 1m0 16V 4K7 6000 3

3
LIGHT PWB

2002

100n

47n

47n

47n
COM 5
3 F023 2001 2
(OPTIONAL) 4 SI4946
4 BAS316 1
7015-2 6 9

2031

2032
2030
F022

1
B4B-PH-K 1M11

5
6
I006 6001 3014 F041
7
A002
F045 1K0

BZX384-C18

BZX384-C18
TO 1M10 TO 1M10 3017 BAS316

3012 470R

3013 560R
2011 6n8

2012 6n8
7009
BC847BW

6006

6007
OR 4K7
1M10
B F021 F028 B
PDP AUDIO 1
SUPPLY STANDBY 2 F020
F019
5015
3 BD21416-00
OR 4 F018 I009 3011 F040

TO SDI SUPPLY B4B-PH-K +5V F050 1

3030 1K0
BLUE

7
8
7019

47n

47n

47n
BC847BW 7016-1 2 13 TO
4K7 I010
2 SI4946 CCFL

2040

2041

2042
3

1
F038
3028

3016

7001
10K

4K7

I005 6002
11

3
P87LPC760BDH 4 11

47n

47n

47n
1M48 VDD F046 4
F045

BAS316 SI4946
3025
C
B3B-PH-K
F017 560R I002 Φ 7010 7016-2 5
C

2051

2052
BC847BW

2050
TO 2nd AMBI MICROCONTROLLER

5
6
1 4K7 6003 3010 F037
9 14 6 9
LIGHT PWB 2 3001 TXD CIN1B F046
2003

8 13
1n0

1K0

BZX384-C18

BZX384-C18
(OPTIONAL) 3 RXD CIN1A BAS316

3008 470R

3009 560R
7 12 7

2009 6n8

2010 6n8
F016 SCL CMPREF F047 F029

3031

6008

6009
10

4K7
F005 T0 CMP1 F004
6 1050
INT0
P0<3:6> DSX840GA
SDA 3003 5016
5 BD21416-00
CLKOUT GND-HV
F060
P1<0:3> X2 220R
560R F006 20M I011 3007 F036 TO
F015 2 4
RST X1 CCFL
3024

7020 1
4K7

3002 I003 P1.5 1K0

7
8
BC847BW
2004

1 P2<0:1>

47n

47n

47n
GREEN
1n0

P1.7
I012 7017-1 2 13
VSS 2 SI4946

2061

2062
2060
D D
2005

2006
3

3
1K0

1K0
3026

3027

15p

15p

1
F035
F047

I004 6004

3
4 11

47n

47n

47n
4 SI4946
BAS316 7017-2 5

2071

2072
2070
5
6
6005 3006 6
1004 F045 F046 F047 9
F014 7011
1K0

BZX384-C18

BZX384-C18
1 BC847BW BAS316 F034

3005 560R
7

3004 470R
F013

2007 6n8

2008 6n8
2 6010

6011
NC 3 F012
4 3022
1M12
5 F030
F011 100R 2V / div DC 2V / div DC 2V / div DC 1 TO
B5B-PH-K
E 1ms / div 1ms / div 2ms / div 2 CCFL E
3042 3
1M49
F010 F031 A001
1M0 F032 B03B-XASK-1
1 F033
TO 1M49 2 F009
F008
3 F007 3023
4 F098 3999 F099
SSB 100R
B4B-PH-K 10K

3104 313 6072.6 WARNING HIGH VOLTAGE F_15400_013.eps

300505
1 2 3 4 5 6 7 8 9 10
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 40

Layout Ambi Light Panel (Top Side) Layout Ambi Light Panel (Bottom Side)
1004 B2 2001 B1 2010 B2 2040 A1 2070 A1 3007 B1 3016 B2 3026 B2 5007 B1 6004 B1 7002 B2 7020 B1
1010 B1 2002 B2 2011 B2 2041 A1 2071 A1 3008 B2 3017 B2 3027 B2 5008 B1 6005 B1 7009 B2
1050 B2 2003 B2 2012 B2 2042 A2 2072 A1 3009 B2 3018 B2 3028 B2 5014 A2 6006 B2 7010 B2
1M08 B1 2004 B2 2020 A2 2050 A2 3001 B2 3010 B2 3019 B2 3029 B2 5015 A1 6007 B2 7011 B1
1M10 B1 2005 B2 2021 A2 2051 A2 3002 B2 3011 B2 3020 B2 3030 B2 5016 A1 6008 B2 7015 B2
1M11 A2 2006 B2 2022 A2 2052 A2 3003 B2 3012 B2 3022 B2 3031 B2 6000 B2 6009 B2 7016 B2
1M12 A1 2007 B1 2030 A2 2060 A1 3004 B1 3013 B2 3023 B2 3042 A1 6001 B2 6010 B1 7017 B1
1M48 B2 2008 B1 2031 A2 2061 A1 3005 B1 3014 B2 3024 B2 3999 B1 6002 B2 6011 B1 7018 B2
1M49 B2 2009 B2 2032 A2 2062 A1 3006 B1 3015 B2 3025 B2 5002 B2 6003 B2 7001 B2 7019 B2

F_15400_014.eps F_15400_015.eps
3104 313 6072.6 260405 3104 313 6072.6 260405
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 41

SSB: DC/DC
1U01 A11 2U17 A5 2U27 B7 2U42 B11 2U85 B8 3U09 D5 3U19 F9 3U29 D4 3U39 G10 3U54 D10 3U69 H9 3U88 A3 3UA4 D13 6U06 E11 7U00 B4 7U11 E5 7U19 H9 FU02 B4 FU19 F12 IU09 C3 IU19 A5 IU29 B6 IU40 D8 IU50 H8 IU60 D7 IU79 B11
1U04 A12 2U18 C6 2U28 B7 2U45 A9 3U00 C2 3U10 C6 3U20 D8 3U30 D5 3U40 B12 3U55 D10 3U70 H8 3U89 B2 3UA5 D13 6U07 G11 7U01-1 A6 7U13-1 B3 7U27 C12 FU03 A7 FU23 A3 IU10 C4 IU20 A2 IU30 B6 IU41 D8 IU51 H8 IU61 G3 IU80 D12
2U09 F2 2U19 B8 2U29 D8 2U46 E13 3U01 C2 3U11 E7 3U21 B7 3U31 D3 3U41 D5 3U56 D10 3U71 H8 3U93 D9 3UA6 F10 6U08 E11 7U01-2 A6 7U13-2 A2 7U28 D11 FU05 F12 IU01 A13 IU11 C2 IU21 B8 IU31 B5 IU42 A10 IU52 H9 IU62 A3 IU81 D12
2U10 G2 2U20 D8 2U30 E8 2U47 H7 3U02 C2 3U12 B8 3U22 A4 3U32 E4 3U42 E5 3U62 H7 3U80 E4 3U94 D10 3UA7 E10 6U11 B14 7U03-1 B6 7U14-1 B13 7U29-1 B10 FU06 C9 IU02 B13 IU12 C2 IU22 B8 IU32 B5 IU43 A12 IU53 H9 IU63 A3 IU83 A15
2U11 E6 2U21 D8 2U31 A6 2U50 A13 3U03 C3 3U13 B8 3U23 A5 3U33 E3 3U43 B13 3U63 H8 3U82 C7 3U95 E10 3UA8 D7 6U12 A14 7U03-2 B6 7U14-2 B14 7U29-2 B9 FU07 E12 IU03 B2 IU13 D5 IU23 A6 IU33 B15 IU44 C6 IU54 B7 IU65 D4 IU86 A7
2U12 C5 2U22 C9 2U32 B6 2U55 E3 3U04 C3 3U14 D8 3U24 A5 3U34 B14 3U44 A13 3U64 H8 3U83 C6 3U96 C6 3UA9 D7 6U17 G11 7U05-1 C2 7U15-1 D10 9U03 H14 FU08 D12 IU04 B4 IU14 C6 IU24 A5 IU34 B14 IU45 C6 IU55 D8 IU66 D4 IU88 F9
2U13 C2 2U23 F2 2U37 F9 2U58 B11 3U05 C3 3U15 E8 3U25 B5 3U35 C14 3U45 D5 3U65 H8 3U84 B12 3U97 C6 5U00 A8 6U18 B12 7U05-2 C4 7U15-2 D10 9U04 A13 FU09 E11 IU05 B4 IU15 C5 IU25 C5 IU35 B13 IU46 B12 IU56 D10 IU67 D6 IUA0 E4
2U14 A2 2U24 B9 2U38 E5 2U71 B15 3U06 C4 3U16 E8 3U26 B6 3U36 H7 3U46 E5 3U66 H9 3U85 A3 3UA1 B10 5U02 A10 6U21 E7 7U07 E7 7U16 B13 9U05 A13 FU13 C7 IU06 B4 IU16 B5 IU26 D7 IU36 B6 IU47 B12 IU57 D10 IU68 E3
2U15 C4 2U25 A10 2U40 G8 2U72 B10 3U07 C6 3U17 E9 3U27 B5 3U37 G1 3U52 B14 3U67 H9 3U86 A3 3UA2 B10 5U03 C8 6U22 D7 7U10-1 D3 7U17 H7 9U06 E12 FU15 C14 IU07 B4 IU17 B5 IU27 E7 IU37 B14 IU48 H8 IU58 D10 IU69 E5
2U16 A4 2U26 D7 2U41 G8 2U73 D12 3U08 C6 3U18 D9 3U28 B6 3U38 G1 3U53 B14 3U68 H9 3U87 A2 3UA3 D11 6U05 E11 6U23 D7 7U10-2 D4 7U18 H8 FU01 A14 FU18 F12 IU08 C4 IU18 A5 IU28 E7 IU38 G7 IU49 H8 IU59 D10 IU78 B10

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

DC / DC
B1A IU86
5U02

10u
IU42

FU01
+12VSW
B1A
2U14

3U85

3U22
100n

10R
10K

T 3A 420
7U01-1

2U17

1U04
22u
IU18 7 8
3U86

2U45

2U25
2 SI4936ADY

IU24
BC847BPN RES

22u

22u
A IU20
7U13-2
IU62 10K 1
12V/3.3V CONVERSION 9U04
9U05
IU01
+12VS A
3U23 IU23 2U31

2U16

1u0
RES

3U44

2U50
1M0

1u0
4R7 3n3 IU43
5U00 6U12
FU03
3U87

3U24
7U01-2

10R
10K

IU63 3U88 FU23 IU83

SUPPLY-FAULT 10u 1U01 BZX384-C12
5 6
0V 100R 3V3 GND-SIG IU19

3U21

2U19

2U85

2U24

3U52
100n
4 SI4936ADY

10R

1K0
3n3

22u
7U13-1 T 3A 420 SI4835BDY
IU03 BC847BPN 7U03-2 IU46
3 3U84 7U16

3UA1
2U72

100n
4

1K0
7U00 IU33

14
3U89

2U58
5 6

IU54
NCP5422ADR2

IU22
10K

1u0
IU29 10R IU02 6U11 0V
Φ

3U25
SI4936ADY

VCC
4 5

2R2
BC857BS BAV99 COL
FU02 3 7U29-1 IU47 6U18
IU31 2U42 3U40 BZX384-C12
3 BC847BS

2U27

3U13

3U53

330R
2U71

100n
4 1

6K8
BC857BS

1n0
BST H1 3U26 IU30 2U32 IU79 7U14-2

3U27

3U43
7U29-2
B B

10R

47K
GATE IU32 IU78 470n 100K
IU04 2 4R7 IU34
L1 3n3

3UA2

100K
IU21
7 7U03-1
1 IU17 7 8 0V3 1V0

IU35
IU05 VFB H2
16 SI4936ADY
12V SWITCH

2U28
10 6

1n0
2 GATE IU16 3U28 2

3U12
15

1K0
IU06 L2 3U34 IU37
8 1 7U14-1 2 +5V
1 2R2 IU36
IU07 5 BC847BS
COMP +1 IU14 3U08 IU44 3U82 47K
9 6 1
2 -1
3U02
2U13

220R

3U35
100n

47K
IU10 IS 3K3 6K8 0V3
3U05

220R

13 12
ROSC +2

2U18

3U83
100n
11

6K8
-2 12V/1.2V CONVERSION

GND
IU11
IU08
2U15

3U06
100n

39K

3U07 FU15
C C
3
6 3 POD-MODE
GND-SIG
3U00 3U03 IU09 IU15 6K8 3U10 IU45 3U96
IU12 2 5 FU13 FU06
7U05-1 7U05-2 VSW
BC847BS BC847BS IU25 +1V2
33K 10K 3K3 6K8
1 4
3U01

3U04
22K

22K

2U12

3U97

2U22
100n

6K8

22u
BAS316 5U03 7U27
TS2431

3UA3
3U54

10R

2K2
3U09 6U23 10u 3U55 IU56 IU80
6 1 K A 3
3UA8 IU60

3U20

2U20

2U21

3U18

1% 220R
100n
10R

3n3
GND-SIG GND-SIG GND-SIG GND-SIG GND-SIG GND-SIG GND-SIG IU13 6K8 10K
+2V5 STABILIZER

IU57
7U15-1 2 R
68R
BC847BS
3UA9

IU55
1

IU40
7U28

2
3U29

3U56
PHD38N02LT
D D
1K0

1K0
IU81
33K 1%
68R 2U73 3UA4 1%
1 4
3U30 2U26
3U41

3U45

2U29

3U14
1M0

6K8
BC857BS BC857BS

1n0
IU26 1n0 1K0

3UA5
7U10-1 2 7U10-2 5

47R
3U31 IU65 2K2 100n 3U93 IU58
1

BAS316
IU66

6U22

IU41
6 3 IU59
10K 10K 3U94 FU08
K

7U15-2 5 +3V3
TS2431

IU67
3U32

7U11

2U30
BC847BS
10K

1n0
3U33 3U11 3K3

2U11

3U15
IU68 2 4

IU27

1K0
1u0
6U06 FU09 6U05
12K 1%

IU28 FU07

3U95
res

2K2
A

10K 220R +2V5

3U46

2U38

100n

STPS2L30A STPS2L30A
2U55

100n

3U42

2U46
7U07

1u0
IU69 6U08
IUA0 BC817-25W res
3U80 10R

3U16

9U06
RES
3U17
E E

4K7

1% 1K0
BZX384-C18
STPS2L30A
10K
BOOSTER

6U21
12V UNDER-VOLTAGE DETECTION GND-SIG GND-SIG
3UA7 1%

1K0 +2V5D
FU05
FU18
ENABLE-3V3
0V

F IU88 3U19 FU19

ENABLE-1V2 F
22K 0V
2U23

100p

2U37

470n
res 3UA6 1%

2U09 1K0
IU61 res 3U39 1%
100p

STPS2L30A
1K0
3U37

1% 560R

3U38

2U10

100n
6K8

6U07
G GND-SIG GND-SIG GND-SIG IU38 2U40 2U41
G
1u0 1u0
+5V2-STBY

BZX384-C3V3
6U17
3U63

150R
3U64

150R
3U65

150R

3U66

150R
3U67

150R
3U68

150R
3U62

1K0

7U17
TS2431 IU51 IU52

3 A K 1 IU48 7U18 7U19 9U03

BC847B BC847B
R
H IU50 GND-SIG
H
2U47

1n0

IU53
2

3U70

3U69
4R7

4R7

RES
3U36 IU49 3U71

1M0 1K0
+2V5D LINEAR STABILIZER F_15400_016.eps
8204 000 8433.6 260405

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 42

SSB: DC/DC Connections

1 2 3 4 5 6 7 8 1M46 D2 6U25 B6
1U10 E2 7U08 B7

B1B DC/DC CONNECTIONS B1B 1U11 E3

1U12 E3
7U09 C7
7U24 B2
1U13 E2 7U26 B4
1U14 E3 9U10 D6
A VTUN GENERATOR A
1U15 F2 9U11 E6
IU73
6U00 3U57 FU21
+VTUN
1U16 F3 9U12 B7
BAS316 100R 2U00 F3 FU04 D3

BZX384-C27
2U01 E3 FU10 D3

5U09

6U01
100n
2U08
+12VSW

47u
RES
9U12 2U02 F3 FU11 D3
VSW
IU74 7U08
3U47
2U03 E4 FU12 D2
3U58 SI4835BDY FU20
+8V6-SW
2U04 F5 FU14 D3
2K2

BZX384-C12
IU75 1R0
B IU70 B 2U05 F5 FU16 D3
3U59

2U35

6U25

3U48

100K
1K0

1u0
3U60

2U34
2U06 F5 FU17 E3

33R

1u0
7U24 BC847BW
7U26
IU76
BSH112
2U36
2U07 F5 FU20 B8
IU82 IU71

2U43

33p
2U08 B3 FU21 A5
100n
3U61

10K

3UA0 2U33 E4 FU22 E3

2U44

3U49
220p

47K
IU77
100K 2U34 B4 FU24 E3
IU89 2U35 B6 FU60 D4
0V3
IU72 3U50
2U36 B7 FU61 D4
7U09 +5V
C BC847BW 1V0
C 2U39 F4 FU62 D4
47K
2U43 B3 FU63 D3

3U51
0V3

47K
+5V-CON
2U44 C3 FU64 E3
3U47 B7 FU65 E4

ON-MODE
5U14
3U48 B6 FU66 E4
+8V6 SWITCH 3U49 C7 IU39 D5
3U50 C7 IU70 B7
5U01
1M46
FU14
5U10
3U51 C7 IU71 B6
D 1 D 3U57 A4 IU72 C7
2 FU16 FU60 IU39
FROM 1M46 3
FU12 5U04 +8V6
4
FU10 5U05 +12VS 3U58 B4 IU73 A4
FU11 FU61 5U06 +5V
5 3U59 B2 IU74 B4
6 FU63 FU62
FU04 5U07
AUDIO STANDBY (LCD)
7
9U10
+5V2-STBY 3U60 B3 IU75 B3
8 FU17 FU64
5U08
9
9U11
3U61 B2 IU76 B2
FU22
OR 10 +5V2-STBY_9V-STBY
11
FU24 FU65 5U11 RES 3UA0 C4 IU77 C4
FROM 1M46 OF B11B-PH-K
FU66
5U01 D4 IU82 B3
5U12
MAIN SUPPLY (PDP) 5U04 D4 IU89 C6
E 5U13 E
1U10

1U11

1U12

5U05 D4
5U06 D4
2U01

2U03

2U33
100p

100p

100p

5U07 D4
1U13

1U14

5U08 E4
2U00

2U02

2U39

2U04

2U05

2U06

2U07
100p

100p

100p

100n

100n

100n

100n

5U09 B3
1U15

1U16

5U10 D4
5U11 E4
F F 5U12 E4
5U13 E4
5U14 D3
6U00 A3
F_15400_017.eps 6U01 B4
8204 000 8433.6 240505

1 2 3 4 5 6 7 8
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 43

SSB: RS232 Interface

1 2 3 4 5 6 7 8 1H07 D1 IU95 C5
1U02 D8 IU96 D5

B1C RS232 INTERFACE

1U03 D8 IU97 D7

B1C 2U60 B3
2U61 B3
IU98 D6
IU99 E4
2U63 C5
+5V2-STBY 2U64 C6
2U65 C6
2U66 D5
A A 3U72 A3
3U73 A4

3U72

150R
3U73

150R
3U74 A2

3U74

1K0
3U75 B3
IU90
3U76 B3
3U77 B3
IU91
7U20 3U79 D7
BC847B
3U81 E7

2U60
3U90 D3

10n
3 1
3U91 D2

NC
B 4 1V3 IU92
3U75 +3V3-UART
B 3U92 E3

REF
TS431AILT
7U21 1K0 3U98 D7

NC
A

10u 10V
3U99 D7

3U76

3U77

2U61
1K0

1K5
5 2
7U20 B3
9U13
7U21 B2
7U22 C5
+3V3-UART
9U01 E5
9U02 E5
FU30 9U07 E2
RES 9U13 B5
7U22
C ST3232C 16 C 9U14 E5
Φ VCC 9U15 D4
+3V3
2U63 IU93 1 RS232 IU84
9U16 E4
C1+ 6 2U65
100n IU94 V- FU30 C6
3
C1- 2 100n 2U64 FOR FU31 D7
2U66 IU95 V+
4
IU85 FU32 E7
C2+ 100n FACTORY
3U91

3U90
10K

10K

100n IU96 5
FU40 D2
1H07 C2- USE ONLY FU41 D2
FU40 JTAG-TRST 1U02 FU42 D2
1 IU00 3U98 FU51
FU41 EJTAG-DETECT GLINK-TXD 9U15 11 14
2
FU42 10 T1 IN OUT
T1 7 1 FU43 D2
EJTAG-TDI
D 3
4 13
T2 T2
12
IU64 100R 3U99 FU52 2
3
D FU44 D2
FU43 EJTAG-TDO IU87 100R 5 4 FU45 D2
5 8 R1 R1 9
FOR FACTORY TXD IN OUT
6 R2 R2 FU46 E2

GND
FU44 EJTAG-TMS B3B-PH-SM4-TBT(LF)
7 IU97 3U79 FU31
USE ONLY 8 RXD 1U03 RES FU47 E2
FU45 EJTAG-TCK 15
9 100R 1 FU48 E2
10 IU98 3U81 FU32 2
FU46 9U07 RESET-SYSTEM FU49 E2
11 3
FU47 100R 5 4 FU50 E2
12 IU99
FU48 FU49
13 FU51 D8
3U92

B3B-PH-SM4-TBT(LF)
10K

FU50
14
FU52 D8
147279-3
9U16
IU00 D7
GLINK-RXD
E +3V3
9U01
E IU64 D7
IU84 C6
9U02 IU85 D6
IU87 D5
9U14
IU90 A3
IU91 B3
IU92 B3
F_15400_018.eps
8204 000 8433.6 260405
IU93 C5
IU94 C5
1 2 3 4 5 6 7 8
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 44

SSB: Channel Decoder

1T55 B6 2T34 D12 2TG3 D2 2TG9 D6 2TJ5 D7 2TK1 H7 2TK7 H7 2TM2 E6 2TN0 G2 3T16 G14 3T19-4 F14 3T21-2 E14 3TG2 E5 3TG9 D13 3TH7 F6 3TJ4 B4 5T55 B5 5TG5 F2 7T11-2 G14 9T10 E14 FTG2 D2 FTG8 H2 IT10 C14 IT18 G13 ITG5 F6 ITH4 B1 ITI4 F5
1TG0 F12 2T55 B5 2TG4 D6 2TJ0 D6 2TJ6 D7 2TK2 H6 2TK8 H6 2TM3 E5 2TN1 H2 3T17 G13 3T20-1 F14 3T21-3 E14 3TG3 D5 3TH0 B3 3TH9 A4 3TJ5 E6 5TG0 C2 5TG6 G2 7TG0 D8 9T11 E14 FTG3 E2 FTG9 F11 IT11 D13 IT19 G13 ITG8 D5 ITH6 F11 ITI5 E14
2T30 F2 2T56 B5 2TG5 D2 2TJ1 D7 2TJ7 E11 2TK3 H6 2TK9 H7 2TM4 F4 2TN3 C14 3T18 G14 3T20-2 F14 3T22 G13 3TG4 E5 3TH3 D7 3TJ0 B2 3TJ6 E13 5TG1 D2 5TG7 G2 7TG1 A4 9TG2 F12 FTG4 F2 FTH0 A4 IT13 G14 ITG1 B6 ITG9 E5 ITI0 B3
2T31 C13 2TG0 D6 2TG6 D6 2TJ2 D7 2TJ8 E11 2TK4 D6 2TL0 B3 2TM5 E4 2TN4 B1 3T19-1 E14 3T20-3 F14 3T23 H13 3TG5 E14 3TH4 C14 3TJ1 B1 3TJ7 E13 5TG2 D2 5TG8 H2 7TG3-1 B2 9TG3 B4 FTG5 F2 FTH1 B4 IT14 D13 ITG2 B5 ITH1 B4 ITI1 C14
2T32 D12 2TG1 C1 2TG7 D5 2TJ3 D7 2TJ9 E11 2TK5 E14 2TL7 F12 2TM7 E6 3T14 G13 3T19-2 F14 3T20-4 E14 3T24 G7 3TG6 E5 3TH5 E7 3TJ2 B2 5T10 C1 5TG3 E2 7T10 D14 7TG3-2 B3 FTG0 C2 FTG6 G2 FTH2 D7 IT16 G14 ITG3 F6 ITH2 B2 ITI2 C2
2T33 G14 2TG2 D6 2TG8 D5 2TJ4 D7 2TK0 H7 2TK6 H7 2TL9 F12 2TM8 E5 3T15 F13 3T19-3 F14 3T21-1 E14 3T26 F4 3TG8 D13 3TH6 F6 3TJ3 B1 5T11 C14 5TG4 E2 7T11-1 G13 7TG4 B4 FTG1 D2 FTG7 G2 FTH3 C13 IT17 G14 ITG4 G7 ITH3 B2 ITI3 E4

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

B2A CHANNEL DECODER B2A

+1V2

A 7TG1
A
SI2306DS

3TH9 FTH0
+1V2_ATSC
2TL0 47K

100n

ITI0 3TH0
ITH1 5T55

+2V5A-XTAL-MAIN
ITG2 ITG1 1T55

+2V5A-FDC-MAIN
+2V5A-FDC-MAIN
+2V5A-FDC-MAIN
+2V5A-FAT-MAIN
+2V5A-FAT-MAIN
+2V5A-FAT-MAIN

+2V5D-PLL-MAIN
+2V5A-PLL-MAIN
ITH2 3TJ0 1K0 +2V5
7TG3-2
B 500mA F
B

100u 4V

+2V5A-MAIN
+2V5A-MAIN
+2V5A-MAIN
2T56

2T55
BC847BPN

1u0
ITH3

+1V2-MAIN
+1V2-MAIN
+1V2-MAIN
+1V2-MAIN
+1V2-MAIN
+1V2-MAIN
+1V2-MAIN
+1V2-MAIN
+1V2-MAIN
+1V2-MAIN

+2V5-MAIN
+2V5-MAIN
+2V5-MAIN

+3V3-MAIN
+3V3-MAIN
+3V3-MAIN
+3V3-MAIN
+3V3-MAIN
+3V3-MAIN
+3V3-MAIN
3TJ1 ITH4 47K RES

9TG3
+3V3 7TG3-1 7TG4
BC847BPN SI2306DS
47K 3TJ2
2TN4
3TJ3

220n
RES
47K

8K2 FTH1
3TJ4
+2V5_ATSC
47K
RES
+12VSW

FTH3 3TH4 ITI1

5T10 ITI2 5TG0 FTG0 AUX-IF-AGC-MAIN

C +2V5_ATSC +2V5A-XTAL-MAIN 1K0 2TN3

100n
C
100u 4V
2TG1

IT10 5T11
+3V3-MAIN

2T31
100n
5TG1 FTG1

8
7T10
+2V5A-FAT-MAIN PCA9515ADP
I2C ADDRESS = 14/16 VCC
2TG3

10n

2T32 3TG8 IT11

6 SDA1 SDA0 3 SCL-DMA-BUS1-ATSC

2TG7 100n

2TG8 100n

2TG9 100n

2TK4 100n

2TG0 100n

2TG2 100n

2TJ0 100n

2TG4 100n

2TG6 100n

2TJ3 100n

2TJ4 100n

2TJ5 100n

2TJ6 100n

2TJ1 100n

2TJ2 100n
D 68p 100R
D
3TG9 IT14
7 SCL1 SCL0 2 SDA-DMA-BUS1-ATSC
5TG2 FTG2
+2V5A-FDC-MAIN 7TG0 2T34 100R

10n

10n

10n
1 EN 5

109
121

105
125
127

117
NXT2003 NC

45

17
32
48
57
62
71
84
98

18
39
85

47
60
69
78
92
40

11
12
13

24
25
26
GND

2
3TH3 68p
2TG5

ITG8 FTH2

AVDD_OSC

AVDD_PLL

DVDD_PLL
3TG3
10n

2TJ7

2TJ8

2TJ9
AVDD

AVDD_FAT

AVDD_FDC

VDD1.2

VDD2.5

VDD3.3
220R 2TM2

4
33K
3TH5
FAT-ADC-INN-MAIN
3TG2 1u0
10n
33K
128
8 BIAS_RES Φ AUX_AGC 53 +3V3-MAIN 3TJ6 9T10 RES
5TG3 FTG3
10 FAT_INCM DTV I2C_SCL 58 1K0
59 3TJ7 9T11 RES
+2V5D-PLL-MAIN 220R 2TM3 9 N
FAT_IN
CABLE AND TERRESTRIAL I2C_SDA
FAT-ADC-INP-MAIN 104 2TK5
E 6
7
P
N
FAT_VREF
RECEIVER I2C_SLAVE_ADDR
0
1 103
50
1K0
3TG5
100n
ITI5 E
P IF_AGC FAT-IF-AGC-MAIN
3TJ5 38 1K0
FDC-AGC FDC_AGC MPEG_CLK 70 3T19-1 FE-CLK
FDC-ADC-INN 2TM5 3TG6 ITG9 1K0 29 93 3T21-3 68R FE-DATA0
ITI3 27 FDC_INCM 0 68R
10n 220R FDC_INN 1 91 3T21-2 FE-DATA1
3TG4 2TM8 2TM7 28 90 3T21-1 68R FE-DATA2
1u0 10n 31 FDC_INP 2 68R
5TG4 220R 88 3T20-4 FE-DATA3
FTG4 2TM4 N
FDC-ADC-INP ITI4 30 FDC_VREF MPEG_DATA 3 87 3T20-3 68R FE-DATA4
+2V5A-MAIN P 4
FS-OUTN 10n 36 83 68R 3T20-2 FE-DATA5
35 N 5 68R
FS-OUTP FS_OUT 77 3T20-1 FE-DATA6
P 6
100u 4V

I2C-SDA-TUNER-MAINNXT 119 75 68R 3T19-4 FE-DATA7

2T30 0 7 68R
I2C-SCL-TUNER-MAINNXT 120 1 SER_DATA
3TH6 118 74 3T19-3 FE-VALID
2 MPEG_DATA_EN 68R
116 68
F +3V3-MAIN
4K7 ITG3
115
113
3
4
MPEG_ERR
MPEG_PKT_SYNC 72
42
ITH6

FTG9 2TL7
3T19-2
68R
FE-SOP F
5TG5 FTG5 IRQ-FE-MAIN 5 OSC_CLK
SEL-POD 3T26 67 43 33p +3V3-MAIN
+2V5A-PLL-MAIN 6 OSC_XTAL_IN 1TG0
100R 65 GPIO 44
3TH7 108 7 OSC_XTAL_OUT
52 9TG2 13M5
+3V3-MAIN ITG5 106 8 PDET_COMP_IN
4K7 9 PDET_REF_OUT 49

3T15
RESET-FE-MAIN 107 64 2TL9

10K
102 10 POD_CRX 63
FM-TRAP 11 POD_DRX 33p

100K
3T18
101 55 IT19
ITG4 12 RF_AGC 7T11-1
99 46 BC847BPN
13
5TG6 79 NC 124 IT17 7T11-2
FTG6 POWER_RESET IT18 3T17
+2V5-MAIN 56 UC_EN BC847BPN

GND_HS
10K 3T16
TUNERAGC-MON
G G
3T24

4K7

100K
1 AGND DGND IT16
5
14
15
16
21
22
23
34
41

4
19
20
33
37
51
54
61
66
73
76
80
81
82
86
89
94
95
96
97
100
110
111
112
114
122
123
126
129
5TG7 FTG7 3T14 2T33
+3V3 +3V3-MAIN
3T22 1K0 100n
IT13
22u 6.3V

CRX-POD
2TN0

68R 3T23
DRX-POD
68R
10n

10n
10n

10n
2TK8 1u0

2TK9 1u0

2TK6 1u0

2TK7 1u0
2TK2

2TK3

2TK0

2TK1

5TG8 FTG8

H +1V2_ATSC +1V2-MAIN
H
22u 6.3V
2TN1

F_15400_019.eps
8204 000 8426.4 260405

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 45

SSB: Main Tuner & OOB Tuner

1T04 A2 2T02 D3 2T07 G7 2T11 D2 2T15 G5 2T19 H7 2T24 B6 2T35 B2 2T51 C8 3T02 D3 3T06 C7 3T10 C2 3T25 H4 5T46 G8 5T50 B5 7T12 B4 AT41 C7 AT46 G8 AT51 C10 FT01 B3 FT05 F6 FT09 C8 IT02 F5 IT06 B3 IT25 B6 IT29 B3
1T41 C6 2T04 C7 2T08 A7 2T12 F7 2T16 H6 2T20 B3 2T25 B6 2T43 B9 2T53 C10 3T03 F5 3T07 C7 3T11 C3 5T42 C5 5T47 F6 5T51 B6 7T41 C8 AT43 C7 AT47 H8 AT52 C10 FT02 F6 FT06 D2 FT41 B8 IT03 G6 IT07 F8 IT26 B4 IT30 G5
1T44 G9 2T05 F5 2T09 B2 2T13 B2 2T17 A5 2T21 H6 2T27 H5 2T45 C8 2T58 B3 3T04 F5 3T08 F5 3T12 B4 5T44 G9 5T48 F7 5T53 C7 7T43 G6 AT44 G10 AT48 H6 AT56 C5 FT03 G7 FT07 A7 IT00 A6 IT04 D2 IT08 F8 IT27 B2
2T01 B2 2T06 F5 2T10 F6 2T14 G6 2T18 A6 2T23 H5 2T28 G7 2T48 C10 2T98 D8 3T05 F5 3T09 B4 3T13 B4 5T45 B3 5T49 B2 7T00 A6 9T04 B8 AT45 H10 AT49 H6 AT57 C5 FT04 D3 FT08 B2 IT01 F5 IT05 D3 IT09 B4 IT28 B2

1 2 3 4 5 6 7 8 9 10 11 12 13

B2B MAIN TUNER + OOB TUNER B2B

7T00

1T04
MAIN DIG TUNER C0 IT00
LD1117DT

3 2 FT07
TD1316O/FGHP +8V6-SW IN OUT +5VTUN
TUNER
A 18 17
COM
A

10u 10V
2T17

2T18

2T08
100n

100n
DC_PWR
1

IF_AGC
IF_OUT
+5VTUN

RF_GC
19 16

VTUN
FM-T
OOB

DNU

SDA

IF_1
IF_2
SCL
+5V

NC
AS

IT29 10
11
12
13
14
15

3T09
1
2
3
4
5
6
7
8
9

4K7
+5VTUN

2T13 IT28
IT06 5T50 5T51 IT25
IT27 +5V +5V-OOB
2T09

2T20

9T04
330u 6.3V
IT09 3T12 IT26

2T24

2T25
100n
7T12
B BC847BW
B
10n

10n

10n
4K7

FT41
3T13

4K7
FT08 FT01

2T43

1u0
2T01

2T35

2T58
5T49

5T45
100n
100n
100n

AT41 2T45

+5VTUN

1
7T41

3T07 RES
10n UPC3218GV
+5V-OOB

AT56

5T53

2T04

VCC
RES

3K9
1u8

2p2
2T48 AT51
1T41 2 INPUT1 OUTPUT1 7 FAT-ADC-INP-MAIN
+5VTUN
+5VTUN

5T42
C C

RES

1u8
1 7
I O 2T51 10n
14 8
IGND OGND 2T53 AT52
AT43 3 6 FAT-ADC-INN-MAIN
AT57 10n
2 4 INPUT2 OUTPUT2
10n
FT09
3T10

6 9

GND1

GND2
GND GND 3T06
11 13 4 VAGC AGC CONTROL
3T11
4K7

1K0

2T98
X7351P

10n
4K7

44M
IT04 IT05

5
3T02
FT06

FT04
10n
2T11

1K0

D D
2T02

100n
I2C-SDA-TUNER-MAINNXT
I2C-SCL-TUNER-MAINNXT

AUX-IF-AGC-MAIN
FAT-IF-AGC-MAIN
TUNERAGC-MON

FM-TRAP
IF-TER2

E E
FS-OUTN

FS-OUTP

FDC-AGC

FDC-ADC-INP

FDC-ADC-INN
+5V-OOB
3T04

5T47
3T05 10R

10R

F IT01 IT02
+5V-OOB F
2T12

1u0
IT07 IT08
2T10

100n
RES
3T03

2T05

2T06
RES

3T08
10R

10R
82p

82p

FT02
FT05

5T48
FT03
2T07

1u0

7T43
G UPC3220GR G
3

7
8

AT44
VAGC
Φ VCC
CATV
IT30 2T14 OUT OF BAND 2T28 AT46

5T46

RES
1 15

1u8

1u8
1 TUNER 1 5T44
1T44
2T15 10n IT03 AGCIN 10n
2 1 7

RES
2 MIXOUT I O AT45
3T25

14 8
75R

10n 2T16 AT48 2T19 AT47 IGND OGND

5 16
1 2
2 4
2T27 10n AT49 OSCIN 10n
6 10 6 9
2 1 GND GND
11 13
10n 2T21
13
1 AMPOUT
H 2T23 10n
12
2
AMPIN
2
9
X7351P
44M H
10n GND
4
11
14

F_15400_020.eps
8204 000 8426.4 260405

1 2 3 4 5 6 7 8 9 10 11 12 13
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 46

SSB: MPIF Main: Video Source Selection

0T00 A11 2C02 C4 2C04 C4 2C06 D2 2C08 D2 2C11 D2 2C13 E5 2C15 E2 2C17 F3 2C19 F3 2C22 F6 2C27 F4 5C01 F4 7C00-4 C7 FC03 F5 FC06 G5 IC04 F6 IC06 C4 IC08 D5 IC10 C3 IC12 C8
2C01 C4 2C03 C2 2C05 C3 2C07 D3 2C09 D3 2C12 E4 2C14 E3 2C16 E3 2C18 F2 2C20 G2 2C23 F8 2C28 G4 5C03 G4 FC02 C5 FC04 E11 IC02 C4 IC05 E8 IC07 C4 IC09 D5 IC11 C8

1 2 3 4 5 6 7 8 9 10 11 12

B3A MPIF MAIN: VIDEO SOURCE SELECTION B3A

A A
0T00

B B

7C00-4
PNX3000HL/N2

IC10 2C01 FC02

CVBSOUTIF-MAIN 123
CVBS_IF SOURCE SELECT
2C03 IC02
22n 126
AND DATA LINK
AV1_CVBS CVBS1
C 22n
RES
IC06
1
CVBS2 CVBS_OUTA
19
IC11
C
IC07 IC12
12 22
CVBS_DTV CVBS_OUTB
2C05

2C02

2C04
22n

22n

22n
4 60 STROBE1N-MAIN
CVBS|Y3 STROBE1N
5 61 STROBE1P-MAIN
C3 STROBE1P
8 62 DATA1N-MAIN
2C06 CVBS|Y4 DATA1N
AV2_Y-CVBS
9 63 DATA1P-MAIN
22n 2C07 C4 DATA1P
AV2_C
D FRONT_Y-CVBS
2C08 22n
IC09
15
Y_COMB
STROBE3N
50 STROBE3N-MAIN
D
16
22n 2C09 C_COMB 51
FRONT_C STROBE3P STROBE3P-MAIN
IC08 6
2C11 22n GND_VSW 52
AV7_Y-CVBS DATA3N DATA3N-MAIN
22n 25 53
R|PR|V_1 DATA3P DATA3P-MAIN
2C12

2C13
RES

26
22n

RES
22n

G|Y|Y_1 55
STROBE2N STROBE2N-MAIN
27
B|PB|U_1
56 STROBE2P-MAIN
STROBE2P
30
2C14 R|PR|V_2 57
E AV7_C
22n
31
G|Y|Y_2
DATA2N DATA2N-MAIN
E
58 DATA2P-MAIN
DATA2P
32
2C15 B|PB|U_2
AV1-AV5-AV6_R-PR FC04
46 HV-PRM-MAIN
22n 2C16 HV_PRIM
AV1-AV5-AV6_G-Y 49 IC05
VCC_DIG
45
22n HV_SEC
48
GND_DIG
2C17 IC04

2C23
47

22n
AV1-AV5-AV6_B-PB VD2V5
22n 54
FUSE10
2C22

22n

F +5VMPIF-MAIN
5C01 FC03
64
VCC_I2D F
59
GND_I2D
2C18
2C27

100n

AV2-AV4_R-PR
22n 2C19
AV2-AV4_G-Y
2C20 22n
AV2-AV4_B-PB 5C03 FC06
22n +5VMPIF-MAIN
2C28

100n

G G

F_15400_021.eps
8204 000 8427.7 260405

1 2 3 4 5 6 7 8 9 10 11 12
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 47

SSB: MPIF Main: Supply

1 2 3 4 5 6 7 8 9 10
1C33 I7

B3B MPIF MAIN: SUPPLY

2AB5 B5
FC31 5C35
+5VMPIF-MAIN
B3B 2C31 A7
2C32 H2
2C33 H2

2C31

100n
6
2C34 H4
A IC36
2 7C31-1
A 2C35 C4
BC847BS
3V9 2C36 C5
1
IC83 FC32
9C50 VREF-AUD-POS 2C37 H4

res
7C00-3 3V2 2C39 D7

3C30

560R

2C43

100u 4V
PNX3000HL/N2
2C40 D6

2C41

22p
2C41 B5
MPIF-SUPPLY IC37 2C42 C5
E/W & CONTROL
2C43 A7

3C32
2

1K2
VOUTO 2AB5 2C44 E5
2C45 D7
B VAUDS
3 1n0 IC38
VREF-AUD
B 2C46 C5
1V4 3C30 A6

3C34
20 3C31 I7

1K2
VDEFLO
3C32 B6
21 3C33 E4
VDEFLS
IC47 3C45 3C34 B6
13 3
RREF 3C35 H3
47K IC81
IC32 5 7C31-2 3C36 H4
7 BC847BS
BGDEC 3V9 FC41 3C37 H3

2C42
4

22p
VREF-DEFL 3C38 I3
C 3V2 C

2C35

2C36

2C46
33

100n
3C39 E5

1u0

1u0
FUSE9

3C43

1K8
10 3C40 F5
FUSE8
IC82 3C41 F6
23
FUSE7 3C42 I3
1V4 3C43 C6

3C44
11

1K2
GND_FILT 3C44 D6
29 3C45 C5
GND_RGB
3C46 H3
34
GND_VADC 3C47 I4
FC36 5C33 5C33 D7
D VCC_FILT
14 +5VMPIF-MAIN D 5C34 D6

10u 10V
FC37 5C34 5C35 A7

2C45

2C39

100n
28 +5VMPIF-MAIN
VCC_RGB
5C36 D5
FC38 5C36 5C37 G2

2C40

100n
35 +5VMPIF-MAIN
VCC_VADC 7C00-3 A3
18 7C31-1 A6
TESTPIN3

2C44

100n
24 7C31-2 C6
TESTPIN2
7C32-1 H3
36
7C32-2 H3
EWVIN 9C46 G10
E REW
38
IC89 3C33 E 9C47 G10
IC46 820R 9C48 G10
37 EW-DRIVE
EWIOUT
9C49 F6
44 IC44 3C39 9C50 A7
SCL SCL-DMA-BUS2
FC31 A7
IC45 100R 3C40
43 SDA-DMA-BUS2 FC32 A7
SDA
100R IC35 FC36 D6
42 IRQ-MPIF
IRQ
FC40 FC37 D6
40 9C49 CLK-MPIF
XREF FC38 D4
FC40 F7
F ADR
39
+5VMPIF-MAIN F
3C41

10K FC41 C7
41
FUSE6 IC01 H3
RES

IC32 C5
IC33 H2
IC34 H3
+5VMPIF-MAIN

SPI-PROG 9C47 IC35 F7

IC36 A5
SDM 9C48 IC37 B6
IC38 B6
9C46
IC39 H4
G G IC40 I3
IC41 G3
IC44 E4
IC45 F4
5C37 IC41
IC46 E4
+8V6-SW
IC47 C4
10u 10V

IC81 C6
2C32

2C33

3C46

3C35

3C36
100n

33R

1K0

82K

IC82 C6
IC83 A6
IC01
IC89 E4
H 4 IC34
H
BC847BPN
7C32-2 2C34
5 6
IC33 IC39 1u0
Y-CVBS-MON-OUT 3 7C32-1 2
BC847BPN 2C37
1
3C37
IC40 1u0 3C31
330R +8V6-SW +8VMPIF-MAIN
3C38

3C42

330R

3C47
10K

47K

10R

I +5V
1C33
+5VMPIF-MAIN
I
500mA F
DAC-CVBS

F_15400_022.eps
8204 000 8427.7 260405

1 2 3 4 5 6 7 8 9 10
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 48

SSB: MPIF Main: IF & SAW Filter

1C51 A4 1C61 A5 2C50 A5 2C57 B7 2C65 C9 2C72 E2 2C83 C6 3C55 C9 3C59 D3 3C66 D4 3C73 B9 5C52 A1 6C51 C4 7C53 D4 7C57 A9 9C54 C4 9C59 C9 AC03 C6 FC73 D1 IC55 C3 IC59 B7 IC64 C8 IC75 A6 IC79 B9 IC87 B8
1C52 B4 1C62 B5 2C52 A1 2C58 B8 2C67 C6 2C75 B7 3C50 D3 3C56 D2 3C60 D1 3C67 E2 3C74 B10 5C53 A7 6C52 D3 7C54 D3 9C51 A4 9C56 C4 9C61 C7 AC04 C6 IC51 A1 IC56 D2 IC60 B7 IC65 C8 IC76 A9 IC84 C4 IC88 B8
1C53 D4 1C63 C5 2C53 A1 2C60 B1 2C68 C8 2C78 C6 3C51 A6 3C57 D2 3C61 D4 3C70 B9 3C75 B10 5C54 B1 6C59 C9 7C55 E2 9C52 A4 9C57 C4 AC01 B6 AC05 C4 IC52 B1 IC57 D4 IC61 C7 IC72 B7 IC77 A9 IC85 A4
1C54 A10 2AB8 B10 2C55 A7 2C63 B6 2C70 D2 2C79 C8 3C53 B7 3C58 D4 3C65 D3 3C71 A9 3C76 B9 5C57 D2 7C00-2 B7 7C56 B10 9C53 B4 9C58 D2 AC02 C6 FC52 C6 IC54 D3 IC58 E2 IC63 C9 IC74 C4 IC78 B10 IC86 B8

1 2 3 4 5 6 7 8 9 10

B3C MPIF MAIN: IF + SAW FILTER B3C

1C61
X7351P 44M
1 7
I O
14 8
IGND OGND
2 4
6 9
GND GND
11 13

+8VMPIF-MAIN

A 5C52 IC51
+8VaM
1C51
40M4
2C50 +5VMPIF-MAIN
3C51 +5VbM
A
2 7
I O1 2R2
9C51 3 8 3
10u 16V

ISWI O2 10n
2C52

2C53

10n

1 1 7C57
9C52 4 11 BC847BW 1C54
IC85 OFWK9656L 3C71

2C55

100n
5 12 2 1 3 2NDSIFEXTM
I O
6 NC 16
IC76 IC77 1K0
9 17 IC75 2
5C53 GND
10 GND
+5VMPIF-MAIN +5VbM

3C70

100R

3C76

120R
13 SFSKA
IC72 4M5

330u 6.3V
14

2C57
2C75
15

10n
18
5C54

IC88
2C58
IC52 1C62 +5VbM
+5VaM X7351P 44M
10n
1 7
I O
B 14
IGND OGND
8
IC86
3 CVBSOUTIF-MAIN
B
2C60

10n

IC87 3C73 IC79

2 4 1 7C56

109

103

104
7C00-2

112

110
6 9 BC847BW
GND GND PNX3000HL/N2 100R 3C74 3C75
11 13 2

GND1_IF

VCC_IF

DTVIFPLL

DTVIFINP

DTVIFINN
IC59 IC60
2C63 3C53 IC78 180R 180R
111 120
VIFPLL CVBSOUTIF

2AB8

330p
1C52 390R
OFWK3953L 38M9 100n
9C53 AC01 107 116
2
I1 O1
7
VIFINP IF PART DTVOUTP
3 8
I2 O2 AC02 108 117
VIFINN DTVOUTN
1
AC03 99
4 11
SIFINP
5 12 122 +5VaM
AC04 100 VCC1_VSW
IC55 6 NC 16 IC63
9C54 SIFINN 6C59 3C55
9 17 118
VCC_SUP +5VMPIF-MAIN
AC05 10 GND IC61 330R
101 BAS316
IC84 13 125 +5VaM
SIFAGC VCC2_VSW

9C59

2C65
9C56 14

10n
IC64
114
C 15
2NDSIFAGC C

2C78

2C67
105

1u0
18

1u0
9C57 TUNERAGC

2C68

2C79
102

1u0
1u0
FC52 DTVIFAGC

GND_SUP

TESTPIN1
1C63 9C61 113

GND2_IF
2NDSIFEXT IC65 +5V-AUD

FUSE5
X7351P 44M
1 7 2NDSIFEXTM 106
+8VaM I O FUSE4
14 8
IGND OGND

115

121
2C83
2 4

119

124
10n
6C51 IC74
6 9
GND GND
3C56

11 13
6K8

BA591 +8VaM
FC73 IC54
2C70
IF-TER2
1C53
10n +8VaM OFWK3955L 38M
5C57

3C57

3C66

3C58
470n

2 7
2K2

4K7

4K7

I1 O1
BA591
6C52

3 8
I2 O2

D 1
D
3C50

4K7
3C65

4 11
4K7

5 12
3C59 IC57 6 NC 16
7C53 9 17
BC847BW 10 GND
22K
IC56 13
3C60
3C61

9C58 14
47K

SEL-IF-LL2 7C54
BC847BW 15
27K
18
+8VaM
2C72

1n0

3C67

4K7

IC58

VISUAL-CHECK 7C55

E BC847BW
E

F_15400_023.eps
8204 000 8427.7 260405

1 2 3 4 5 6 7 8 9 10
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 49

SSB: MPIF Main: Audio Source Selection

1 2 3 4 5 6 7 8 9 10 11 12
2K40 C4

B3D MPIF MAIN: AUDIO SOURCE SELECTION

2K41 C3

B3D 2K43 C3
2K45 D4
2K46 C3
A A 2K47 C3
2K58 H10
2K60 H10
2K61 I10
2K63 I10
2K64 I3
2K65 H3
2K67 F3
2K68 G3
B B 2K75 G3
2K76 G3
IK94
7C00-1 B4
9C60 C3
7C00-1 IK01 F4

2K46

2K47

2K40

100n
IK03 G4

1u0

1u0
PNX3000HL/N2
IK04 G4
91 AUDIO SOURCE SELECT IK10 H4
VAADCP
IK25 77 IK11 F8
+5V-AUD VCC_AADC
IK23 IK24 IK12 F8
C 9C60 98 C
+8V-AUD VCC1_ASW IK13 G8
88 IK14 G8
VCC2_ASW
2K41

2K43
100n

100n
IK15 H8
92 IK16 H8
MIC2N
93 IK17 I8
MIC2P
IK18 I8
94
MIC1N IK19 H4
95 IK20 H4
MIC1P
IK21 I4
IK93
D 89 D IK22 G4
VAADCREF
90 IK23 C3
VAADCN
2K45

100n
IK24 C4
97
GND1_ASW IK25 C3
96 IK93 D4
FUSE1
78 IK94 B3
FUSE2
76
GND_AADC
71
FUSE3

E 87 E
GND2_ASW

SCART1R

SCART2R
SCART1L

SCART2L
DSNDR1

DSNDR2
DSNDL1

DSNDL2
AMEXT

LINER
LINEL
R1

R2

R3

R4

R5
L1

L2

L3

L4

L5
128
127
86
85

84
83

82
81

80
79

75
74

73
72

68
67

70
69

66
65
17

IK11
AUDIO-OUT2-R

F F

2K67 IK01 IK12

AUDIO-IN1-L AUDIO-OUT2-L
1u0 2K75 IK22
AUDIO-IN1-R
1u0

IK13
AUDIO-OUT1-R
G G
2K68 IK03
AUDIO-IN2-L
1u0
2K76 IK04
AUDIO-IN2-R
IK14
1u0 AUDIO-OUT1-L

IK19

IK20
H IK15 1u0 H
DSNDR2
2K60
2K65 IK10
AUDIO-IN5-L 1u0
IK16
1u0 DSNDL2
2K58
2K64 IK21
AUDIO-IN5-R 1u0
IK17
1u0 DSNDR1
2K63

IK18 1u0
DSNDL1
I 2K61 I

F_15400_024.eps
8204 000 8427.7 260405
1 2 3 4 5 6 7 8 9 10 11 12
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 50

SSB: MPIF Main: Audio Amplifier

2A20 A8 6A00 C8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 2A21 C12 6A01 E11
2A22 G8 6A02 A3
2A23 H9 7A04-1 A7

B3E MPIF MAIN: AUDIO AMPLIFIER B3E

2A24 I12 7A04-2 C9
2A32 B7 7A05-1 F6
2A79 G8 7A05-2 E5
2A81 F7 7A05-3 F2
2A83 E9 7A05-4 H2
+5V2-STBY +5V2-STBY
+5V2-STBY
2A84 B6 7A06 G8
A-PLOP 2A85 D9 7A07 E7
2A86 C9 7A08-1 A4
A A

3A52

100K
7A08-2 2A87 B6 7A08-2 A5
BC847BPN IK30 2A88 B5 7A09 A8

BAS316
3A87

6A02
IK53 IK54 4 +5V-AUD +5V BC857BW
3A53 7A15 2A89 G3 7A10-1 C8
7A08-1 10K IK32
BC847BPN 6 5 2A90 I3 7A10-2 B9
10K 4V6 3A55 2A20 3A60
IK52 2A91 B3 7A11 C11
IK51 3A51

3A31

100K
2 3 7A04-1 2A93 C10 7A12-1 D11
IK68 TS482IST 100K 7A09 16V 100u 33R

8
680K 3 FK00 FK02 2A96 H3 7A12-2 D12
0V6 BC807-25W IK62 2AA0 3A61
1 1 AUDIO-HDPH-L-AP
IK67 2A98 D10 7A13-1 H10

2A91

3A28

3A54
2

47K

10K
1u0
16V 100u IK46 33R 2A99 B7 7A13-2 H12

4
2AA0 B8 7A13-3 I10

RES
3A59

100K

3A62

1K0
IK33 3A88

3A32

100K
2A87
7A16-1 2AA1 D10 7A13-4 I12

1u0

47u 16V
IK64

2A32

3A30

470K
BC847BS
1K0 2AA2 C12 7A13-5 H10
B IK69 2A99
+5V2-STBY
B 2AA3 G9 7A13-6 H11
2A88 RES 33p 2AA4 G9 7A14-1 E3

150R
3A57

3A58

220K
ADAC7 IK63
9A82 3A38 2AA5 E2 7A14-2 E4
100n
220K 2AA6 E3 7A15 A11
5V3

220R
3A33

270K

2A84

3A56
4

1u0
IK65 IK55 3A64 2AB1 G7 7A16-1 B10
2V2 6 BC847BPN
3A22 3A23 7A10-2 5
2AB2 E6 7A16-2 C13
IK96 3A63 10K FK07
7A10-1 2 +5V-AUD 2AB3 E4 7A18-1 F9
15K IK50 27K
BC847BPN
10K
3 2AB7 F8 7A18-2 E8
FK06 0V
1 3A14 F2 9A80 I3
0V 3A65 IK66 3A15 H9 9A81 H3

3A34

100K
+5V
3A66 2A21 3A67 3A16 I13 9A82 B6
220K 0V
C C 3A17 I13 9A83 D9

BAT54 COL
100K 16V 100u 33R
3A20 E9 9A86 D4

6A00
IK86 BC807-25W IK80 2AA2 3A68 FK11
FK09
AUDIO-HDPH-R-AP 3A21 E10 9A88 H10

2A93

100n
7A11 16V 100u IK85 33R 3A22 B6 9A90 F3

3A35

100K
2A86

1u0
3A23 B7 FK00 B7

3A70

100K

3A69
RES

1K0
7A04-2 7A16-2
BC847BS 3A24 I2 FK01 G8

47u 16V
TS482IST
IK81

2AA1
3A25 I3 FK02 B9

3A29

470K
2A85 3A89

8
ADAC8 5 3A26 G2 FK03 E7
7 +5V2-STBY 1K0 3A27 G3 FK06 C7
100n IK87

150R
3A71

3A72

220K
6
IK82 3A28 B3 FK07 C9

3A36

270K

4
3A29 D10 FK09 C10
5V3 3A30 B7 FK11 C12

220R
3A73
4
FK17 IK56
D +12VSW +12VSW 2V2 6
IK05
BC847BPN
7A12-2 5
3A75
D 3A31 A5
3A32 B5
FK17 D11
FK18 G9
IK88 2A98 3A74 10K
+12VSW 7A12-1 2
+12VSW BC847BPN 3
3A33 B5 FK19 I13
33p IK83 0V 10K 3A34 C9 IK02 F8
9A86

RES 1
RES

3A37 3A35 C9 IK05 D11

3A83

9A83
RES
1K2

0V 3A76 IK84

3A95
3A36 D9 IK30 A10

15R
IK31 220K

2A83

1u0
220K 0V 3A37 D10 IK31 D4

BAT54 COL
3A80

470K
RES

RES IK35 3A20 3A21 3A38 B7 IK32 A11

6A01
BC847BPN 3A39 I3 IK33 B11
IK90 11V7 15K IK49 27K
7A14-2 +12VSW 3A40 G3 IK35 E7

3A92
AUDIO-SW +12VSW 3A41 F7 IK36 E8

68R
IK89
3A42 G7 IK46 B9
E 2AB3
E
2AA6

7A05-2
3A81

120K

RES

4
RES

1u0

LM324 3A93 IK36 3A43 G8 IK47 I3

VREF-AUD 4 BC847BPN
1n0 7A18-2 3A44 G8 IK48 G3
RES RES 5 IK77 IK78 7A07 5
3A46 BC817-25W 10K 11V7
IK91 7 3
3A45 G8 IK49 E10
2AA5 IK97
ADAC4 7A14-1 6 1K0 FK03 0V3
3A46 E6 IK50 C6
BC847BPN
220n 3A84 11 +8V-AUD 3A47 E6 IK51 A3

2AB2

3A47

10K
1n0
RES 3V0 PROT-AUDIOSUPPLY 3A48 F7 IK52 A3
RES
3A82

150K

3A94

100K
IK92 1K0 6
3A49 F7 IK53 A4

1u0
2A81
RES
390R

3A50 F7 IK54 A4
3A85

3A48
RES

10K
7A18-1
+8V6-SW 0V BC847BPN 3A51 A3 IK55 B9
1 3A52 A4 IK56 D12
IK79
3A14

RES
33K

3A53 A4 IK57 G9

RES

2AB7
3A96

100n
10K
F F 3A54 B5
3A55 A8
IK58 I12
IK59 H11

3A49

3A50

3A90

3A91
18R

68R
10K

18K
IK95
9A90 +12VSW 3A56 B7 IK60 I12
RES 3A57 B8 IK62 B8
7A05-1
+12VSW IK02
LM324 3A58 B8 IK63 B7
7A05-3 4 3A59 B8 IK64 B8
LM324 3 IK74 IK75
1 3A41 3A60 A9 IK65 B8
IK70 4 7A06
ADAC2 10 3AA1 IK71 2 BC817-25W +3V3 3A61 B9 IK66 C8
1K0 FK01
8 AUDIO-R +5V-AUD 3A62 B9 IK67 B6
11
2AB1

3A42

9
10K
1n0

220R 3A63 C8 IK68 A6

3A64 B9 IK69 B6

3A77
11

2A79

2R2
1u0
3A43
3A65 C8 IK70 G2

10K
G 2A89
IK76
G 3A66 C11
3A67 C12
IK71 G4
IK72 H2
IK98
33p 3A68 C12 IK73 H4
3A26 3A27 3A40 3A69 C12 IK74 F7
FK18

100u 4V
3A78

2AA3

2AA4
3A70 C11 IK75 F7
220K
3A45

2A22

100n
3A44

18K

1u0
18K IK48 47K 1K0 IK57
22K 3A71 D11 IK76 G7
9A81 3A72 D11 IK77 E6
RES 7A13-1 7A13-2 3A73 D10 IK78 E7

14

14
74HCU04PW 74HCU04PW
2A23 IK59 3A86 3A74 D11 IK79 F7
+12VSW SPI-1 1 1 2 3 1 4 SPDIF-IN1
68R
3A75 D12 IK80 C11
1n0

7
3A76 D11 IK81 C11

3A15

3A79
75R

47K
3A77 G9 IK82 D11
H H 3A78 G10 IK83 D10
2A96

100n

3A79 H11 IK84 D12

7A05-4 9A88 3A80 E2 IK85 C12
LM324 RES 3A81 E2 IK86 C9
IK72 4 3A82 F2 IK87 D9
ADAC1 12 3AA2 IK73 7A13-5 7A13-6
3A83 D3 IK88 D9

14

14
14 AUDIO-L 74HCU04PW 74HCU04PW FK19
1 1 2A24 3A16 3A84 E4 IK89 E3
13 220R SPDIF-OUT1 11 10 13 12 SPI-OUT
IK60 IK58 220R
3A85 F3 IK90 E3
11 100n

7
3A86 H12 IK91 E2

120R
3A17
3A87 A10 IK92 F3
3A88 B11 IK95 F2
I 2A90
IK99
7A13-3 7A13-4
I 3A89 D13
3A90 F8
IK96 C8
IK97 E4
33p

14

14
74HCU04PW 74HCU04PW 3A91 F8 IK98 G3
3A24 3A25 3A39 5 1 6 9 1 8 3A92 E7 IK99 I3
18K IK47 47K 1K0 3A93 E8

7
9A80 3A94 F8
RES 3A95 D7
3A96 F8
F_15400_025.eps 3AA1 G3
8204 000 8427.7 260405 3AA2 H3

1 2 3 4 5 6 7 8 9 10 11 12 13 14
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 51

SSB: MPIF Main: Connections A

1 2 3 4 5 6 7 8 9

B3F MPIF MAIN: CONNECTIONS A B3F

0A00 E9
0A01 F9
0A02 E9
9A47 C4
9A52 D4
9A54 D4
9A32
2A41 0A03 F9 9A55 F4
100p 1E40 B9 9A56 F4
9A33 1E41 B1 9A57 F4
2A42 IA15 2A25 A5 9A58 C4
5A08
100p
+8V6-SW 2A29 B8 9A59 D4
9A34 2A25 6 3
A 2A43
100p
100n 7A20-1 2 7A21 7A20-2 5
A 2A31 D7
2A33 C3
9A60 D4
9A61 F4
9A35 AV2_FBL BC847BS BC847BW BC847BS 2A40 D3 9A62 D4
2A44 IA16 1 4 2A41 A3 9A63 D4
100p 3A13 3A18 3A19 3A97 3A98 3A99
AV2-AV4_R-PR
9A36
2A42 A3 9A64 E4
AV2_C 100R IA17 560R 100R IA18 560R 100R IA19 560R
2A45 AV2-AV4_G-Y IA20 2A43 A3 9A65 E4
100p AV2-AV4_B-PB 2A44 A3 9A66 E4
9A37 AV2_Y-CVBS IA21 2A45 A3 9A67 E4
2A46 2A46 B3 9A68 F4

+8V6-CONN
100p AV2_FBL
9A38 AV2_C 3A01
2A47 B3 FA00 B8
Y-CVBS-MON-OUT
1E41 2A47 2A48 B3 FA01 B8
100R
100p 2A49 B3 FA02 B8
1 9A39 C-MON-OUT 5A06 +8V6-CONN 2A50 B3 FA03 B8
B 2
3
2A48
100p
AV2_Y-CVBS
3A02
+8V6-SW
1E40
B 2A51 C3 FA04 C8
4 100R 2A52 C3 FA05 C8

2A29

100n
9A40 AV2-STATUS FA00
5 1 2A53 C3 FA06 C8
2A49 Y-CVBS-MON-OUT FA01
6 2
100p FA02 2A54 C3 FA07 B8
7 3
9A41 REGIMBEAU-AV6-VSYNC FA03 2A55 D3 FA08 C8
8 4
2A50 C-MON-OUT FA07 2A56 D3 FA09 C8
9 100p 5
9A44 AUDIO-OUT1-L FA04
10
2A51 FA05
6 2A57 D3 FA10 C8
11 100p 7 2A58 D3 FA11 C8
AV2-STATUS FA06
12 9A45 8
AUDIO-OUT1-R AV6_VSYNC 9A29 2A59 E3 FA12 C8
13 9
2A52 IA01 FA08 2A60 E3 FA13 C8
FOR 32" 14 100p 10
REGIMBEAU 9A11 FA09 2A61 E3 FA14 C8
15 11
9A46 AUDIO-OUT2-L REGIMBEAU-AV6-VSYNC FA10
FOR 37",42",50"
C TO 1E40
16
17
2A53
100p
AUDIO-OUT1-L FA11
FA12
12
13 C 2A62 E3
2A63 E3
FA15 C8
FA16 D8
18 9A47 14
AUDIO-OUT2-R 2A64 F3 FA17 D8
19 15
2A54 AUDIO-OUT1-R FA13 2A65 F3 FA18 D8
20 9A58 16
21
100p
2A33
AUDIO-HDPH-L-AP FA14
17 TO 1E40 2A66 F3 FA19 D8
22 100p AUDIO-OUT2-L FA15
18 2A67 F3 FA20 D8
EXTERNALS 23 9A59 FA16
19 2A68 F3 FA21 D8
24 +5V2-CONN AUDIO-HDPH-R-AP 20
2A40 3A01 B6 FA22 E8
25
26
100p
9A60
AUDIO-OUT2-R FA17
21
22
EXTERNALS 3A02 B6 FA23 D8
AV1_CVBS-AV7-Y-CVBS +5V2-CONN FA18
27 AUDIO-HDPH-L-AP
5A07 23 3A03 D6 FA24 E8
2A55 9A06
28 100p
FA28
FA31
24 OR 3A04 E6 FA25 E8
29 9A54 25 3A05 E6 FA26 E8
AV1-STATUS-AV7-C +5V2-STBY
D 30
31
2A56 AUDIO-HDPH-R-AP 9A01 FA32
26
27 D 3A06 F6 FA27 E8

2A31
10p

100n
FA19 3A13 A6 FA28 D8
32 28
9A52 CVBS-TER-OUT 3A18 A6 FA29 E8
33 29
2A57 FA20
34 100p 9A62 AV1_CVBS IA02 9A16 FA21
30 3A19 A7 FA30 E8
35 AUDIO-IN1-L 31
2A58 AV7_Y-CVBS IA03 3A03 3A97 A7 FA31 D8
36 9A63 32
100p AUDIO-IN1-R AV1_CVBS-AV7-Y-CVBS 100R FA23 3A98 A7 FA32 D8
37 33
2A59 AV1-STATUS IA05 9A19 FA22 3A99 A8 IA01 C6
38 100p 34
AV7_C IA04 3A04 5A06 B7 IA02 D6
39 9A64 35
AUDIO-IN2-L AV1-STATUS-AV7-C 100R FA25
40
2A60 FA26
36 0A02 5A07 D7 IA03 D6
100p 37 5A08 A5 IA04 E6
40FMN-BMT-A-TFT CVBS-TER-OUT FA27
9A65 38
AUDIO-IN2-R FA24 7A20-1 A6 IA05 E6
39
2A61 AUDIO-IN1-L FA29 7A20-2 A8 IA15 A6
E 100p
9A66
FRONT_Y-CVBS AUDIO-IN1-R
FA30
40
40FMN-BMT-A-TFT
E 7A21 A7 IA16 A5
2A62
9A01 D6 IA17 A6
100p AUDIO-IN2-L 0A00 9A06 D6 IA18 A7
9A67 9A11 C6 IA19 A8
FRONT_C
2A63 AUDIO-IN2-R 9A16 D6 IA20 A6
100p IA22
9A61 3A05 9A19 E6 IA21 B6
AUDIO-IN5-L FRONT_Y-CVBS
2A64
9A29 C6 IA22 E6
3A06 100R
100p FRONT_C 0A01 9A32 A4 IA23 F6
9A68 9A33 A4
AUDIO-IN5-R IA23 100R
2A65 AUDIO-IN5-L 9A34 A4
100p
9A35 A4
9A55 LED1 AUDIO-IN5-R
F 2A66
100p LED1 0A03
F 9A36 A4
9A37 B4
9A56 KEYBOARD 9A38 B4
2A67 KEYBOARD 9A39 B4
100p
9A40 B4
9A57 RC RC
2A68
9A41 B4
100p 9A44 C4
F_15400_026.eps 9A45 C4
8204 000 8427.7 260405 9A46 C4

1 2 3 4 5 6 7 8 9
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 52

SSB: MPIF Main: Connections B

1 2 3 4 5 6 7 8 9 1E62 E1 9A79 D5
1E63 C1 FA33 A4

B3G MPIF MAIN: CONNECTIONS B

1M52 A4 FA34 A4

1M52
FA33
2A34
100p
5A01
100p
2A75
AUDIO-L B3G 2A01 E8
2A34 A5
FA35 A4
FA36 A4
1 2A35 A5 FA37 A4
2A35 2A76
2 FA34 5A02 2A36 A5 FA38 A4
TO 1739 3
2A36
100p 100p
2A77
AUDIO-R
2A37 A5 FA39 D3
A 4
5
FA35
2A37
100p 5A03 100p
IA00
AUDIO-SW A 2A38 A5 FA40 D3
6 FA36 5A04
100p 3V PROT-AUDIOSUPPLY 2A39 A5 FA41 D3
7
AUDIO STANDBY 8 FA37 2A38
100p 5A05 2A69 D3 FA42 D3
10V8 SOUND-ENABLE
9 2A70 D3 FA43 D3
10 11 2A39
FA38
RES 100p 2A71 D3 FA47 D4
2A72 E3 FA48 B6
2A73 E3 FA49 B6
6A10-1 6A10-2
2A74 E3 FA50 B6
+5V 2 1 4 5 +5V 2A75 A7 FA54 C3
2A76 A7 FA55 C6
B BAV99S BAV99S B 2A77 A7 FA56 C6

3
FA48
9A02 COM-SND 2A78 B3 FA57 C6
2A78 2A80 D3 FA58 C6
FA49
100p 9A03 LIGHT-SENSOR
2A82 2A82 B3 FA60 F3
FA50
100p 9A04 LED2 2A92 C3 FA61 F2
2A92
IA10 100p 9A05
2A97 C3 FA62 F2
SDA-MM
2AA8 C3 IA00 A6
IA11
9A07 SCL-MM 2AA9 C3 IA10 C3
IA12 FA58 2AAA C3 IA11 C3
9A08 P50
2A97 2AAB D3 IA12 C3
C 1E63 FA54 1n0
2AA8
9A09 A-PLOP C 2AB6 D3 IA25 E8
20 FA55
19
100p 9A10 GLINK-RXD 3A07 F6 IA26 F6
2AA9 3A08 F6 IA27 F7
18 FA56
100p 9A21 GLINK-TXD
17 3A09 F7 IA28 F8
2AAA
FOR 32" 16
15
100p 9A22
FA57
GLINK-IR-OUT 3A10 F7 IA44 D9
2AB6
14 FA39 3A11 F8 IA45 E9
100p 9A69 SPI-OUT
13
TO 1E62 12 FA40
2A69
10p 9A70
FA47
9A79
3A12 F8 IA46 E9
11 HSYNC-HIRATE 5A01 A6
2A70
10 FA41 5A02 A6
100p 9A71 SPI-1
9
2A71 5A03 A6
D EXTERNALS 8
7 FA42
10p 9A77 AV1-STATUS D 5A04 A6
9A78 AV6_VSYNC
6
5 FA43
2AAB 5A05 A6
100p 9A75 AV1-AV6_FBL-HSYNC
4 5A10 E9
2A80
3 6A10-1 B3
100p
2 IA44
9A72 AV1-AV5-AV6_B-PB 6A10-2 B4
1
2A72
100p 7A01-1 F6
IA45
9A73 AV1-AV5-AV6_G-Y 7A01-2 F8
2A73 7A02 F7
100p
IA46 9A02 B3
9A74 AV1-AV5-AV6_R-PR
2A74 9A03 B3
E 1E62 100p
E 9A04 B3
20
19 IA25 5A10
9A05 C3
18 +8V6-SW 9A07 C3
FOR 37",42",50" 17
6 3 9A08 C3
16

2A01

100n
15 9A09 C3
2 7A01-1 7A02 5 7A01-2
14
BC847BS BC847BW BC847BS 9A10 C3
13
12
1 4 9A21 C3
3A07 3A09 3A11
TO 1E62 11 IA26 IA27 IA28 9A22 C3
10 100R 100R 100R
9A69 D3
9
560R

560R

560R
3A08

3A10

3A12
8 9A70 D3
F EXTERNALS 7
6 F 9A71 D3
9A72 D4
5
4 9A73 E4
FA60
3 9A74 E4
FA61
2
1 9A75 D4
FA62 F_15400_027.eps 9A77 D4
8204 000 8427.7 260405 9A78 D4

1 2 3 4 5 6 7 8 9
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 53

SSB: PNX2015: Audio/Video

1 2 3 4 5 6 7 8 9 0E02 F1 5J01 A6
0E03 F1 5J02 A6

B4A PNX2015: AUDIO / VIDEO 2J03

5J00
+1V2
B4A 2J01 A1
2J03 A6
5J03 A6
5J04 E6
5J13 IJ08 2LT6 2J06 A6 5J05 E6
100n 5J01 +3V3
100n
2J08 A6 5J06 F6
2J06 7J08 2J10 A6 5J07 F6
CY2305SC-1

6
A VREF-AUD-POS
IJ01
100n IJ02 5J02 Φ VDD A 2J13 E6
2J16 E6
5J13 A8
5J15 B7
IJ00
+3V3 ZERO 3
3J02
M27-MOP
2J08 DELAY 1 2J18 F6 5J16 C7

100n
2J01
22R 3J05
7J00-7 5J03
BUFFER 2 M27-POD 2J20 F6 6J07 D9
PNX 2015 100n 2
M27-CLK 1
+1V2 REF CLK 22R 2J22 D1 6J08 D9
Φ
3J06
5 M27-PNX
2J10 3 2J23 D1 7J00-7 A3
Y5
AUDIO / VIDEO 7
22R 3J14
ADAC_CLK 100n 4 M27-HIRATE 2J24 E1 7J01-1 E8
AVP1_DLK_VDDA N5 22R
AH1 M5 8 2J25 E1 7J02-1 F9
ADAC1 ADAC1 AVP1_DLK_VDDD 2J30 5J15 CLKOUT
2LA5
AH2
ADAC1N AVP1_DLK_VSSA P5 +3V3
GND 2J30 B6 7J02-2 E9

4
AH3 AVP1_DLK_VSSD R5 3J60 2J31 B7 7J08 A8
ADAC1P 100n IJ26
AVP1_DLK1DN R2 DATA1N-MAIN
3n3 2J32 C7 7J10-1 B6
ADAC2 AG1 AVP1_DLK1DP R1 DATA1P-MAIN 100K
ADAC2
B 2LA6
AG2
AG3
ADAC2N AVP1_DLK1SN
AVP1_DLK1SP
R4
R3
STROBE1N-MAIN
STROBE1P-MAIN BC857BS
4 IJ27 3J62 IJ25 3J61 B 2J33 C6 7J10-2 B5
ADAC2P
P2 7J10-2 5 1 IJ28 2J34 D7 7J11 C6
3n3 AVP1_DLK2DN DATA2N-MAIN 10K 680R IJ30 3J63 2J31
AF1
ADAC3 AVP1_DLK2DP P1 DATA2P-MAIN BC857BS AV1-AV6_FBL-HSYNC 2J35 D7 7J12-1 D6
AF2 AVP1_DLK2SN P4 STROBE2N-MAIN 3 IJ31 7J10-1 2
ADAC3N 10K 1u0 2LA5 B1 7J12-2 D5
AG4 AVP1_DLK2SP P3 STROBE2P-MAIN
ADAC3P 2LA6 B1 7J13 D6

680K
3J64
AVP1_DLK3DN N2 DATA3N-MAIN 6
3J65
ADAC4 AE1 AVP1_DLK3DP N1 DATA3P-MAIN IJ32 2LA7 C1 9J20 C7
ADAC4

3J66

1K0
AE2 AVP1_DLK3SN N4 STROBE3N-MAIN 220R IJ33 3J67
2LA7
AB5
ADAC4N
N3 7J11
2J32 FJ20 2LA8 C1 9J21 C6
ADAC4P AVP1_DLK3SP STROBE3P-MAIN
3n3 AVP1_DTC_CLVSS T6 BC847BW 10K IJ34
1u0
2LA9 D1 9J22 C4
AD1 AVP1_DTC_VDD3 T3 IJ35 3J68 2LT0 E9 9J24 C5
ADAC5
AD2 AVP1_DTC_VDDA T4
ADAC5N 2LT6 A9 FJ20 C8
AB4 AVP1_DTC_VSSA T5 9J22 IJ03 100K
ADAC5P
C AC1
AVP1_HSYNCFBL1
AVP1_HSYNCFBL2
T1
T2 9J24
9J20
AV2_FBL
C 3J01 E4 FJ42 D7
AC2
ADAC6
M3 HV-PRM-MAIN
3J02 A9 FLA8 E7
ADAC6N AVP1_HVINFO1
AB3
ADAC6P AVP1_VSYNC1 M1 3J03 E4 IJ00 A4
9J21

120R
AVP1_VSYNC2 M2 3J05 A9 IJ01 A4
+12VS +5V2-STBY
ADAC7 AB1 5J16
ADAC7 2J33 3J06 A9 IJ02 A6
AB2 AVP2_DLK_VDDA H5 +3V3
2LA8 ADAC7N
AA4 AVP2_DLK_VDDD G6 3J69 3J07 F4 IJ03 C5
ADAC7P 100n IJ39

3J12
AVP2_DLK_VSSA J5
3n3
AA1 K5
3J08 F4 IJ04 E6
ADAC8 ADAC8 AVP2_DLK_VSSD 100K
2LA9
AA2
ADAC8N AVP2_DLK1DN K2 4 IJ40 3J71 IJ38 3J70 3J09 F4 IJ05 E6

3L05

3L04
10R

2R2
AA3 K1 BC857BS

120R
ADAC8P AVP2_DLK1DP 3J11 F2 IJ06 F6
K4 7J12-2 5 1 IJ41
3n3 AVP2_DLK1SN 10K 680R IJ43 3J72 2J34
DSNDL1 AF3 AVP2_DLK1SP K3 BC857BS AV6_VSYNC 3J12 D4 IJ07 F6
ADAC9 7J12-1
D 2J22
AF4
ADAC9N AVP2_DLK2DN J2 3 IJ44 2
10K 1u0 FJ42
IJ53 IJ54
D 3J13 D4 IJ08 A8
AF5
ADAC9P AVP2_DLK2DP J1 3J13 3J14 A9 IJ09 E9

680K
3J73
AVP2_DLK2SN J4 6
3n3 3J74

BAT54 COL
DSNDR1 AE3 J3 IJ45 3J60 B7 IJ11 E8
AVP2_DLK2SP

BAS316
ADAC10

3J75

6J07

6J08
1K0
AE4 AVP2_DLK3DN H2 220R IJ46 3J76 3J61 B6 IJ25 B6
2J23 ADAC10N 2J35
AE5 AVP2_DLK3DP H1 7J13
ADAC10P BC847BW 3J62 B6 IJ26 B6
AVP2_DLK3SN H4 10K
3n3 IJ47 1u0
DSNDL2 AD3 AVP2_DLK3SP H3 3J77 IJ09 3J63 B7 IJ27 B5
ADAC11
AD4 AVP2_DTC_CLVSS K6
2J24
AD5
ADAC11N
L3
3J64 B7 IJ28 B7
ADAC11P AVP2_DTC_VDD3 100K
3n3 AVP2_DTC_VDDA L4 3J65 B6 IJ30 B7

2LT0
AC3 L5

1u0
DSNDR2 ADAC12 AVP2_DTC_VSSA IJ04 5J04 3J66 C5 IJ31 B5
AC4 AVP2_HSYNCFBL1 L1 3JA2 120R
2J25 ADAC12N +1V2 3J67 C7 IJ32 B6

100K

100K
3L01

3L00
AC5 AVP2_HSYNCFBL2 L2 AV2_FBL
ADAC12P
E

100n
E

2J13
AVP2_HVINFO1 G3 3J68 C7 IJ33 C7
3n3
I2S-MCH-LR U2 AVP2_VSYNC1 G1 3J01 120R
U3
I2S_IN_SD1
G2 IJ55 11V0 3J69 C7 IJ34 C7
I2S-MCH-CSW I2S_IN_SD2 AVP2_VSYNC2 AV6_VSYNC
I2S-MCH-SLR U4
I2S_IN_SD3 5J05
4 3J70 D6 IJ35 C7
IJ05 3L02 10V3
I2S-MAIN-D V4 I2S_OUT_SCK Y2 3J03 68R I2S-BCLK-AVIP 6 BC847BPN
I2S_IN_SD4 7J02-2
3J71 D6 IJ38 D6
I2S-SUB-D V5 I2S_OUT_SD1 W1 IJ11 5
I2S_IN_SD5 FLA8 3L03 10K
3J72 D7 IJ39 D6

100n
2J16
W5 I2S_OUT_SD2 W2 RESET-AUDIO 2 7J01-1
I2S_IN_SD6 BC847BPN
I2S_OUT_SD3 V1 3 3J73 D7 IJ40 D5
470K 1V3
I2S-BCLK-MAIN V2 I2S_OUT_SD4 W3 3J07 68R I2S-MAIN-ND 1 11V1 11V0
I2S_SCK_SYS
W4 3J08 68R 3J74 D6 IJ41 D7
I2S_OUT_SD5 I2S-SUB-ND 5J06
IJ06
I2S-WS-MAIN V3
I2S_WS_SYS I2S_OUT_SD6 Y4
+3V3
6 3J75 D6 IJ43 D7
I2S_OUT_WS Y3 3J09 68R I2S-WS-AVIP A-PLOP 3J76 D7 IJ44 D5

100n
2J18
CLK-MPIF M4 2 7J02-1
MPIF_CLK BC847BPN 3J77 D7 IJ45 D6
0V7
F I2S-BCLK-SUB
I2S-WS-SUB
U1
U5
I2S_SCK_XTRA
1
F 3JA2 E4 IJ46 D7
I2S_WS_XTRA IJ07 5J07 3L00 E9 IJ47 D7
+1V2
3L01 E8 IJ53 D9
0E02 0E03
100n
2J20

3L02 E9 IJ54 D9
3J11 68R 3L03 E8 IJ55 E8
3L04 D9
F_15400_028.eps 3L05 D9
8204 000 8428.7 260405 5J00 A6

1 2 3 4 5 6 7 8 9
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 54

SSB: PNX2015: DV I/O Interface

1 2 3 4 5 6 7 8 9
3LR0 D4
3LR1 C4

B4B PNX 2015: DV I/O INTERFACE B4B 3LR3-1 B4

3LR3-2 B4
3LR3-3 B4
3LR3-4 B4
3LR4-1 B4
3LR4-2 B4
3LR4-3 B4
3LR4-4 B4
3LR5-2 C4
3LR5-3 B4
A A 3LR5-4 B4
3LR6-1 C4
3LR6-2 C4
3LR6-3 C4
7J00-4 3LR6-4 C4
PNX 2015
3LR7-1 C4
Φ 3LR7-2 D4
DV INPUT 3LR7-3 C4
DV4-CLK AK8 DV_CLK DV1_CLK
AD28 9LA7 DV1F-CLK 7J00-2 3LR8-1 C4
DV4-VALID AH8 DV_VALID AD29 33R 3LR4-1 DV1F-VALID PNX 2015 3LR8-2 C4
DV1_VALID

DV4-DATA0_SOP AG8 DV4_DATA_0 AB27 33R 3LR3-4 DV1F-DATA0

Φ 3LR8-3 C4
DV1_DATA0 OUTPUT INTERFACE 3LR8-4 C4
B DV4-DATA1_ERR
DV4-DATA2_0
AK7
AJ7
DV4_DATA_1
DV4_DATA_2
DV1_DATA1
DV1_DATA2
AA30
AA29
33R 3LR3-2
33R 3LR3-1
DV1F-DATA1
DV1F-DATA2
MP-ROUT-0
MP-ROUT-1
A27
A28
RIN0
RIN1 LVDS_AN B26 TXPNXA-
B 3LR9-1 D4
DV4-DATA3_1 AH7 DV4_DATA_3 DV1_DATA3
AA28 33R 3LR3-3 DV1F-DATA3 MP-ROUT-2 A29
RIN2 LVDS_AP C26 TXPNXA+ 3LR9-2 D4
DV4-DATA4_2 AG7 DV4_DATA_4 AB29 33R 3LR4-3 DV1F-DATA4 MP-ROUT-3 A30 3LR9-3 D4
DV1_DATA4 RIN3
DV4-DATA5_3 AF7 DV4_DATA_5 AB28 33R 3LR4-4 DV1F-DATA5 MP-ROUT-4 B28 LVDS_BN A25 TXPNXB-
DV1_DATA5 RIN4 3LR9-4 D4
DV4-DATA6_4 AK6 DV4_DATA_6 AC30 33R 3LR4-2 DV1F-DATA6 MP-ROUT-5 B30 LVDS_BP B25 TXPNXB+
AJ6
DV1_DATA6
AC28 33R 3LR5-4 DV1F-DATA7 C28
RIN5 3LS0-2 E4
DV4-DATA7_5 DV4_DATA_7 DV1_DATA7 MP-ROUT-6 RIN6
DV4-DATA8_6 AH6 DV4_DATA_8 AC27 33R 3LR5-3 DV1F-DATA8_ERR MP-ROUT-7 C29 LVDS_CN D25 TXPNXC- 3LS0-3 D4
DV1_DATA8 RIN7
DV4-DATA9_7 AG6 DV4_DATA_9 DV1_DATA9
AB30 33R 3LR5-2 DV1F-DATA9_SOP MP-ROUT-8 C30
RIN8 LVDS_CP E25 TXPNXC+ 3LS0-4 D4
MP-ROUT-9 D27
RIN9 3LS1-1 D4
DV5-DATA0_SOP AF6 DV5_DATA_0 AF30 33R 3LR1 DV2A-CLK LVDS_DN B24 TXPNXD-
DV2_CLK 3LS1-2 D4
DV5-DATA1_ERR AK5 DV5_DATA_1 AF27 33R 3LR7-1 DV2A-VALID MP-GOUT-0 D28 LVDS_DP C24 TXPNXD+
AH5
DV2_VALID
D29
GIN0 3LS1-3 D4
DV5-DATA2_0 DV5_DATA_2 MP-GOUT-1 GIN1
DV5-DATA3_1 AG5 DV5_DATA_3 AE30 33R 3LR8-2 DV2A-DATA0_SOP MP-GOUT-2 D30 LVDS_EN E24 TXPNXE- 3LS1-4 D4
DV2_DATA0 GIN2
C DV5-DATA4_2
DV5-DATA5_3
AK4
AJ4
DV5_DATA_4
DV5_DATA_5
DV2_DATA1
DV2_DATA2
AF28
AD27
33R 3LR7-3
33R 3LR6-4
DV2A-DATA1_ERR
DV2A-DATA2_0
MP-GOUT-3
MP-GOUT-4
E27
E28
GIN3
GIN4
LVDS_EP F24 TXPNXE+
C 7J00-2 B7
7J00-4 A2
DV5-DATA6_4 AH4 DV5_DATA_6 AD26 33R 3LR6-3 DV2A-DATA3_1 MP-GOUT-5 E30
DV2_DATA3 GIN5 9LA7 B4
DV5-DATA7_5 AK3 DV5_DATA_7 AD30 33R 3LR6-1 DV2A-DATA4_2 MP-GOUT-6 F26 LVDS_CLKN C23 TXPNXCLK-
AJ3
DV2_DATA4
AE26 33R 3LR6-2 DV2A-DATA5_3 F27
GIN6
D23
AJ10 C8
DV5-DATA8_6 DV5_DATA_8 DV2_DATA5 MP-GOUT-7 GIN7 LVDS_CLKP TXPNXCLK+
DV5-DATA9_7 AK2 DV5_DATA_9 AE27 33R 3LR8-1 DV2A-DATA6_4 MP-GOUT-8 F28
DV2_DATA6 GIN8 AJ10
AE28 33R 3LR8-3 DV2A-DATA7_5 MP-GOUT-9 F29 RGB_CLK_IN J30 MP-CLKOUT
DV2_DATA7 GIN9
DV-VREF AJ9 DV_VREF AE29 33R 3LR8-4 DV2A-DATA8_6 RGB_UD J27 MP-OUT-FFIELD
DV2_DATA8
DV-FREF AK9 DV_FREF AG27 33R 3LR7-2 DV2A-DATA9_7 MP-BOUT-0 F30 RGB_HSYNC J29 MP-OUT-HS
DV2_DATA9 BIN0
DV-HREF AH9 DV_HREF MP-BOUT-1 G26 RGB_VSYNC J28 MP-OUT-VS
BIN1
AK28 33R 3LR0 DV3F-CLK MP-BOUT-2 G27 RGB_DE K26 MP-OUT-DE
DV3_CLK BIN2
AK30 33R 3LS1-2 DV3F-VALID MP-BOUT-3 G28
DV3_VALID BIN3
MP-BOUT-4 G29
33R BIN4
AJ30 3LR9-1 DV3F-DATA0_SOP MP-BOUT-5 G30
DV3_DATA0 BIN5
D DV3_DATA1
DV3_DATA2
AH29
AG29
33R 3LR9-3
33R 3LS0-3
DV3F-DATA1_ERR
DV3F-DATA2_0
MP-BOUT-6
MP-BOUT-7
H27
H28
BIN6
BIN7
D
AG30 33R 3LR9-4 DV3F-DATA3_1 MP-BOUT-8 H30
DV3_DATA3 BIN8
AH30 33R 3LS1-4 DV3F-DATA4_2 MP-BOUT-9 J26
DV3_DATA4 BIN9
AG28 33R 3LS0-4 DV3F-DATA5_3
DV3_DATA5
AH27 33R 3LR9-2 DV3F-DATA6_4
DV3_DATA6
AJ28 33R 3LS1-3 DV3F-DATA7_5
DV3_DATA7
AK29 33R 3LS1-1 DV3F-DATA8_6
DV3_DATA8
AH28 33R 3LS0-2 DV3F-DATA9_7
DV3_DATA9

E E

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 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 55

SSB: PNX2015: Tunnel Bus

1 2 3 4 5 6
2L01 E5
2L05 F2

B4C PNX 2015: TUNNELBUS B4C 2L06 F2

2L07 F3
2L08 F3
2L64 E2
3L08 D4
A 7J00-1
A 3L09 B4
PNX 2015 3L10 B4
Φ 3L11 B4
TUNNELBUS 3L12 B4
A1 TUNS_TX_BUSY R28 TUN-VIPER-RX-BUSY 3L13 B4
TUNN_TX_BUSY
D2 TUNS_TX_CLKN M30 3L10 47R TUN-VIPER-RX-CLKN
TUNN_TX_CLKN 3L14 B4
C2 TUNS_TX_CLKP M29 3L09 47R TUN-VIPER-RX-CLKP
TUNN_TX_CLKP
3L15 B4
C4 TUNS_TX_D0 K28 3L11 47R TUN-VIPER-RX-DATA0
TUNN_TX_D0
3L12 47R
3L16 B4
B4 TUNS_TX_D1 K27 TUN-VIPER-RX-DATA1
TUNN_TX_D1
A4 TUNS_TX_D2 L30 3L13 47R TUN-VIPER-RX-DATA2 3L17 B4
TUNN_TX_D2
F3 TUNS_TX_D3 L28 3L14 47R TUN-VIPER-RX-DATA3 3L18 B4
B B3
C3
TUNN_TX_D3
TUNN_TX_D4 TUNS_TX_D4 K29
N26 3L16 47R
3L15 47R TUN-VIPER-RX-DATA4
TUN-VIPER-RX-DATA5
B 3L19 B4
TUNN_TX_D5 TUNS_TX_D5
D3 TUNS_TX_D6 L27 3L17 47R TUN-VIPER-RX-DATA6 3L21 B4
TUNN_TX_D6
E3 TUNS_TX_D7 K30 3L18 47R TUN-VIPER-RX-DATA7
TUNN_TX_D7
47R
3L23 B4
F2 TUNS_TX_D8 M27 3L19 TUN-VIPER-RX-DATA8
TUNN_TX_D8
A3 TUNS_TX_D9 N28 3L21 47R TUN-VIPER-RX-DATA9 3L25 C4
TUNN_TX_D9
F1 TUNS_TX_D10 N27 3L23 47R TUN-VIPER-RX-DATA10 3L27 C4
TUNN_TX_D10
A2 TUNS_TX_D11 P28 3L25 47R TUN-VIPER-RX-DATA11
TUNN_TX_D11 3L29 C4
B1 TUNS_TX_D12 P27 3L27 47R TUN-VIPER-RX-DATA12
TUNN_TX_D12
C1 TUNS_TX_D13 N30 3L29 47R TUN-VIPER-RX-DATA13 3L31 C4
TUNN_TX_D13
D1 TUNS_TX_D14 N29 3L31 47R TUN-VIPER-RX-DATA14
TUNN_TX_D14
3L33 47R
3L33 C4
E1 TUNS_TX_D15 R29 TUN-VIPER-RX-DATA15
TUNN_TX_D15
3L35 D4
D9 TUNS_RX_D0 R27 TUN-VIPER-TX-DATA0 3L38 F3
C C9
A9
TUNN_RX_D0
TUNN_RX_D1 TUNS_RX_D1 P30
T27
TUN-VIPER-TX-DATA1
TUN-VIPER-TX-DATA2
C 3L39 F3
TUNN_RX_D2 TUNS_RX_D2
D8
TUNN_RX_D3 TUNS_RX_D3 R30 TUN-VIPER-TX-DATA3 5L01 E2
B9 TUNS_RX_D4 T28 TUN-VIPER-TX-DATA4
TUNN_RX_D4 7J00-1 A3
D7 TUNS_RX_D5 T29 TUN-VIPER-TX-DATA5
TUNN_RX_D5
C8 TUNS_RX_D6 T30 TUN-VIPER-TX-DATA6 9LA8 D2
TUNN_RX_D6
A8 TUNS_RX_D7 U27 TUN-VIPER-TX-DATA7 9LA9 D2
TUNN_RX_D7
D6 TUNS_RX_D8 V27 TUN-VIPER-TX-DATA8
TUNN_RX_D8 IL03 E3
C6 TUNS_RX_D9 V28 TUN-VIPER-TX-DATA9
TUNN_RX_D9
B6
TUNN_RX_D10 TUNS_RX_D10 V29 TUN-VIPER-TX-DATA10 IL05 F4
A6 TUNS_RX_D11 V30 TUN-VIPER-TX-DATA11
TUNN_RX_D11
D5 TUNS_RX_D12 W26 TUN-VIPER-TX-DATA12
TUNN_RX_D12
C5 TUNS_RX_D13 W27 TUN-VIPER-TX-DATA13
TUNN_RX_D13
A5 TUNS_RX_D14 W28 TUN-VIPER-TX-DATA14
D E4
TUNN_RX_D14
TUNN_RX_D15 TUNS_RX_D15 W29 TUN-VIPER-TX-DATA15 D
D4 TUNS_RX_BUSY W30 3L08 47R TUN-VIPER-TX-BUSY
TUNN_RX_BUSY
9LA8 B7 TUNS_RX_CLKN U30 TUN-VIPER-TX-CLKN
TUNN_RX_CLKN
9LA9 C7 TUNS_RX_CLKP U28 TUN-VIPER-TX-CLKP
+2V5 TUNN_RX_CLKP
100R 3L35
A7 TUNS_REF M28 RES
TUNN_REF VREF-PNX
2L64

100n

2L01

100n

E E

5L01 IL03
+2V5
3L38

2L07

100n
1K0
2L06

100n
RES

IL05
VREF-PNX

F 1V4
F
3L39

2L08

100n
1K0

F_15400_030.eps
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 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 56

SSB: PNX2015: DDR Interface

1 2 3 4 5 6 7 8 9
2L50 A8

B4D PNX 2015: DDR INTERFACE

2L51 A8

B4D 2L52 A8
2L53 A8
2L54 A8
2L55 C6
+2V5-DDRPNX +2V5-DDRPNX 2L56 A6
2L57 A6
7J00-3 2L58 A7
2015 PNX
2L59 C5
Φ 2L60 C5

2L56

100n
2L57

100n
2L58

100n

2L50

100n
2L51

100n
2L52

100n
2L53

100n
2L54

100n

2L61
A A

1n0
PNX-MA-0 33R C12 DDR INTERFACE 2L61 A9
3L41 33R 3L40 D12 MA_0 2L62 E6
PNX-MA-1
33R D11 MA_1
PNX-MA-2
MA_2
2L63 E7
PNX-MA-3 3L43 33R 3L42 C10
MA_3 3L40 A1
PNX-MA-4 33R D21 D14 3L95 33R PNX-MBA0
PNX-MA-5 3L45 33R 3L44 C21 MA_4 MBA_0
C13 PNX-MBA1
3L41 A1
MA_5 MBA_1 7L50 3L42 A1

18

33

15

55

61
PNX-MA-6 33R D20 3L90 3L94 33R

9
3L47 33R 3L46 D19 MA_6 C17 1K0 MT46V16M16D3TG-7L 3L43 A1
PNX-MA-7 MCKE_0 PNX-MCKE
C19 MA_7 A16
PNX-MA-8 33R
MCLK_N PNX-MCLK-N VDD VDDQ 14 3L44 A1
PNX-MA-9
PNX-MA-10 3L49
33R 3L48
33R
D18
D13
MA_8
MA_9 A17 3L51
100R
PNX-MCLK-P
PNX-MA-0
PNX-MA-1
29
30
0 Φ 17
19
3L45 A1
PNX-MA-11 33R 3L91 C18 MA_10 MCLK_P
C14 PNX-MCS-0 PNX-MA-2 31
1 DDR 25
3L46 B1
3L92 33R MA_11 MCS_0 2 SDRAM NC 3L47 B1
PNX-MA-12 D17 PNX-MA-3 32 43
3L93 MA_12 3L52 3
3L48 B1
B PNX-MDATA-0 A11
MD_0
MDQM_0
MDQM_1
B15
D16 22R 3L99
PNX-MDQM-0
PNX-MDQM-1
PNX-MA-4
PNX-MA-5
35
36
4
5 A
16Mx16 50
53 B 3L49 B1
PNX-MDATA-1 B12 22R PNX-MA-6 37 3L50 B8
MD_1 6 3L50
PNX-MDATA-2 C11 A15 PNX-MDQS-0 PNX-MA-7 38 2 PNX-MDATA-0
PNX-MDATA-3 A12 MD_2 MDQS_0
B16 PNX-MDQS-1 PNX-MA-8 39
7 0
4 22R 3L56 PNX-MDATA-1
3L51 B4
MD_3 MDQS_1 8 1 3L52 B4
PNX-MDATA-4 A10 ILN1 PNX-MA-9 40 5 3L57 22R PNX-MDATA-2
MD_4 9 2
PNX-MDATA-5 B13
Mem_DLL0
E21 PNX-MA-10 28
10 3
7 22R 3L58 PNX-MDATA-3 3L56 B9
B10 MD_5 E10 3L59 22R
PNX-MDATA-6
MD_6 Mem_DLL1 VREF-PNX
PNX-MA-11 41
11 4
8 PNX-MDATA-4 3L57 B8

2L60

100n

5L50
PNX-MDATA-7 A13 PNX-MA-12 42 10 22R 3L60 PNX-MDATA-5
MD_7 12 5 3L58 B9
PNX-MDATA-8 A18 C16 AP 11 3L61 22R PNX-MDATA-6
PNX-MDATA-9 B21 MD_8 MM_VREF
PNX-MBA0 26
6
13 22R 3L62 PNX-MDATA-7
3L59 B8
MD_9 3L98 0 D 7 3L60 C9
PNX-MDATA-10 B18 A14 PNX-MRAS PNX-MBA1 27 BA 54 3L63 22R PNX-MDATA-8
MD_10 MRAS 3L97 1 8
3L61 C8

2L59

100n
PNX-MDATA-11 A21 D15 33R PNX-MCAS 56 22R 3L64 PNX-MDATA-9
MD_11 MCAS 9
A19 C15 33R 3L96 3L65 22R

+1V2
PNX-MDATA-12
MD_12 MWE PNX-MWE PNX-MDQM-0 20
L 10
57 PNX-MDATA-10 3L62 C9
C PNX-MDATA-13
PNX-MDATA-14
C20
B19 MD_13
MD_14
33R PNX-MDQM-1
VREF-PNX
47
U
DM
11
12
59
60
22R
3L67
3L66
22R
PNX-MDATA-11
PNX-MDATA-12 C 3L63 C8
3L64 C9
PNX-MDATA-15 A20 49 62 22R 3L68 PNX-MDATA-13
MD_15 2L55 100n VREF 13 3L65 C8
63 3L69 22R PNX-MDATA-14
14
PNX-MCLK-N 46
CK
65 22R 3L70 PNX-MDATA-15 3L66 C9
15
PNX-MCLK-P 45
CK 22R 3L67 C8
PNX-MCKE 44 3L68 C9
CKE 3L89
PNX-MCS-0 24 16 PNX-MDQS-0
PNX-MRAS 23
CS
DQS
L
51 3L71 22R PNX-MDQS-1
3L69 C8
RAS U 3L70 C9
PNX-MCAS 22 22R
CAS
PNX-MWE 21
WE
3L71 D8
VSS VSSQ 3L89 C9
3L90 A4

34

48

66

12

52

58

64
6
3L91 B1
D D 3L92 B1
3L93 B1
3L94 A4
3L95 A4
3L96 C4
IL04 3L97 C4
5L52 +2V5-DDRPNX
+2V5 3L98 C4
3L99 B4
5L51 5L50 C5
5L51 E6
5L52 E6
7J00-3 A3

2L62

2L63

100p
E E

1n0
7L50 A6
IL04 D6
ILN1 B5

F_15400_031.eps
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 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 57

SSB: PNX2015: Standby & Control

1LA0 D7 3LN4 C4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 2LA0 D7 3LN5 C4
2LA1 D7 3LN6 C4
2LA2 D10 3LN7 C4
2LA4 F11 3LQ6 C7

B4E PNX 2015: STANDBY & CONTROL B4E 2LB0 C7

2LB1 E11
2LB3 B1
3LR2 D1
3LS2 D1
3LS3 F2
2LB4 E2 3LS4 G2
2LT1 H11 3LS5 G2
2LT2 I11 3LS6 F3
2LT3 G7 3LS7 F3
2LT4 H7 3LS8 H2
+3V3-STANDBY 7J00-5 2LT5 I7 3LS9 H3
A PNX 2015 +3V3-STANDBY
A 3LA0 A1 3LT0 H3
Φ 3LA1 A1 3LT1 I2
3LA0 10K ON-MODE ON-MODE 3LM0 100R P0.0 AK15
STANDBY PROCESSOR 3LA2 A1 3LT2 I2
P0_0 3LF1 3LE0 3LA3 A1 3LT3 G11
3LA1 10K POD-MODE POD-MODE 3LM1 100R P0.1 AJ15 AJ25 CTRL1-STBY CTRL1-STBY
P0_1 PWM1 3LA4 B1 3LT4 H11
3LA2 10K ENABLE-1V2 ENABLE-1V2 3LM2 100R P0.2 AH15 100R 10K
P0_2 3LE1
3LA3 10K 3LM3 100R P0.3 AG15 AG25 ALE 3LA5 B1 3LT5 H11
P0_3 ALE 3LB7
3LA4 10K ENABLE-3V3 ENABLE-3V3 3LM4 100R P0.4 AK16 ALE 3LA6 B1 3LT6 H12
P0_4 100R 3LH7
3LA5 1K0 LAMP-ON LAMP-ON 3LM5 100R P0.5 AJ16 AF25 EA 10K 3LA7 B1 3LT7 H12
P0_5 EA
3LA6 10K COM-SND COM-SND 3LM6 100R P0.6 AH16 3LA8 E2 3LT8 G10
100R P0.7
P0_6 3LH2 100R 3LB8
3LA7 10K UART-SWITCH UART-SWITCH 3LM7 AG16 AK26 RESET-STBY EA 3LA9 C1 3LT9 I13
P0_7 MC_RESET +3V3-STANDBY
RC 100R 10K 3LB1 E3 3LU0 I12
3LC0 10K RC 3LG3 100R 3LE2
P50 AK13 AH26 SCL-UP-VIP
P1_0 SCL_MC SCL-UP-VIP 3LE3 3LB2 E3 3LU1 I11
2LB3 1n0 P50-HDMI 3LG7 100R AJ13 100R
P1_1
B 3LC2 10K P50-HDMI SUPPLY-FAULT 3LG5 100R AH13
P1_2 SDA_MC
AG26
3LF0
SDA-UP-VIP 4K7 B 3LB3 E3
3LB4 E8
3LU2 I11
3LU3 I10

3LB5
3LC3 10K 3LG6 100R

10K
SUPPLY-FAULT AG13 100R
P1_3 3LE4 3LB5 B9 3LU4 F8
3LC4 10K P50 POWER-OK-DISPLAY +3V3-STANDBY 3LD2 10K AK14 AH10 SPI-CLK SDA-UP-VIP
P1_4 SPI_CLK
3LC5 100K POWER-OK-DISPLAY SCL-UP-SW 3LG8 100R AH14 3LB6 D7 3LU5 G6
P1_5 4K7
3LC6 4K7 SCL-UP-SW SDA-UP-SW 3LH9 100R AG14 AG10 SPI-CSB SPI-SDI 3LB7 A8 3LU6 F6
P1_6 SPI_CSB
3LC7 4K7 SDA-UP-SW 3LH8 100R AF14 3LB8 B8 3LU7 F6
P1_7
ILC3 DETECT-1V2 AJ10 SPI-SDI 3LB9 C8 3LU8 F5
SPI_SDI
3LA9 10K 3LN0 100R P2.0 AF16 3LC0 B1 3LU9 H5
3LN1 P2_0
100R P2.1 AK17 AK10 SPI-SDO 3LC1 E1 3LV0 H6
P2_1 SPI_SDO
DETECT-3V3 3LN2 100R P2.2 AH17
P2_2 FLA0 5LA2 3LC2 B1 3LV1 G7
DETECT-5V 3LN3 100R P2.3 AG17 AK12
3LN4 P2_3 XTAL_MC_VDD 3LC3 B1 3LV2 H7
DETECT-8V6 100R P2.4 AK18
P2_4 +1V2-STANDBY 3LC4 B1 3LV3 G8

2LB0

100n
DETECT-12V 3LN5 100R P2.5 AJ18 AJ12
P2_5 XTALI_MC 3LC5 B1 3LV4 I8
CTRL4-STBY 3LN6 100R P2.6 AH18
P2_6
C 3LG2 10K PROT-AUDIOSUPPLY POWER-OK-PLATFORM-3V3
PROT-AUDIOSUPPLY
9LC7 3LN7 100R P2.7 AG18
P2_7 XTALO_MC
AH12 C 3LC6 B1
3LC7 B1
3LV5 I6
3LV6 I6
3LC9 10K 3LJ0 100R
POWER-OK-PLATFORM-3V3 RXD-UP AK19 AG12 3LC8 E1 3LV7 I6
P3_0 XTAL_MC_VSS
3LD0 10K RESET-MIPS TXD-UP 3LJ1 100R AJ19 3LC9 C1 3LV8 I5
9LC6 P3_1 3LQ6 3LB9
3LD1 10K RESET-PNX2015 3LJ4 100R AH19 AH25 PSEN PSEN 3LD0 C1 5LA1 D11
P3_2 PSEN
ILB9 FLB7 SDM IRQ-POD RES 3LJ5 100R AG19 100R 10K 3LD1 C1 5LA2 C7
P3_3
RESET-MIPS 3V2 3LJ6 100R AK20 AK25 3LD2 B4 5LA3 F10
3LR2 10K P3_4 PWM0
RESET-PNX2015 3V2 3LJ7 100R AH20
P3_5 2LA0 +3V3-STANDBY
3LD3 D1 6L00 I6
SDM 3LJ8 100R AG20
3LD3 10K P3_6 3LD4 D1 6L01 H6
LED2-3V3 LED2-3V3 3LJ9 100R AK21
P3_7 22p 3LD5 D1 6L02 F6

3LB6
RES

1M0
3LD4 10K LED1-3V3 LED1-3V3
FLA5 +1V2

1LA0
3LD6 D1 6L03 I12

8
16M
3LD5 10K RESET-SYSTEM RESET-SYSTEM 3V2 3LK0 100R AJ21 7LA7
P4_0

100R
3LD7 D1 7J00-5 A5

3LF2
3LD6 10K RESET-AUDIO RESET-AUDIO 3LK1 100R AH21 M25P05-AVMN6
P4_1 2LA1
3LD7 10K DEBUG-BREAK DEBUG-BREAK 3LK2 100R AG21 VCC 3LD8 D1 7J00-6 D12
Φ
P4_2 FLA1
D 3LD8 10K EJTAG-DETECT EJTAG-DETECT 3LK3 100R AF21 SPI-SDO 5 2
D 3LD9 D1 7LA2-1 G3

DSX840GA
P4_3 22p D Q
3LD9 10K CTRL3-STBY CTRL3-STBY 3LK4 100R AK22 512K 3LE0 A8 7LA2-2 G3
P4_4 FLA2

5LA1
3LE7 10K 3LK5 100R AJ22 SPI-CLK 6 3LE1 A7 7LA3-1 I2
AH22
P4_5 C FLASH FLB0
ILC2 P4_6 FLA3 M27-PNX 3LE2 B7 7LA3-2 H3
3LE8 10K RESET-MAIN-NVM RESET-MAIN-NVM 3LK6 100R AG22 SPI-CSB 1 3LE3 B8 7LA7 D8
P4_7 S
3LE9 10K STBY-WP-NAND-FLASH STBY-WP-NAND-FLASH 3LK7 100R ILB6 7J00-6
FLA4 3LE4 B8 7LB0 I8

180R
2LA2

3LL8
3LS2 680R KEYBOARD 3LK8 100R AK23 3 PNX 2015

10p
KEYBOARD P5_0 BACKLIGHT-CONTROL SPI-WP W 3LE5 E1 7LB1 G8
2LB4 100n LIGHT-SENSOR ILB3 3LK9 100R AH23
P5_1 Φ 3LE6 E1 7LB2 F8

2LB1

100n
3LC1 10K TEMP-SENSOR TEMP-SENSOR 3LL0 100R AG23 7
3LC8 10K FRONT-DETECT FRONT-DETECT 3LL1 100R AF23
P5_2 HOLD ILB5 CONTROL 3LE7 D1 7LB3 I1 0
P5_3 ILB8
AV1-STATUS 3LL2 100R AK24 VSS 3LE8 D1 7LB4 H10
P5_4

3LF9
3LL3 100R 3LE9 D1 7LB5 H12

10K
AV2-STATUS AJ24 Y29 XTAL_SYS_VDD FLA6
P5_5

120R
3LB4

3LL9
3LE5 10K 3LL4 100R 3LF8 100R 3LF0 B7 9LA0 E10

10K
AH24 AF9 SCL-DMA-BUS2

4
P5_6 SCL_COL
3LE6 10K 3LL7 100R AG24 Y28 XTALI_SYS 3LF1 A7 9LA1 F10
P5_7 FLA7
E 3LH5 10K SPI-PROG SPI-PROG
FJ40
3LL5 100R AK27 Y27 XTALO_SYS
SDA_COL
AG9 3LG9 100R SDA-DMA-BUS2 E 3LF2 D6
3LF8 E13
9LA2 E10
9LA3 F10
P6_4 JTAG-TCK
3LH6 10K SPI-WP SPI-WP 3LL6 100R AJ27
P6_5 3LF9 E6 9LA5 G3
+3V3-STANDBY JTAG-TD-VIPER-PNX2015 Y26 XTAL_SYS_VSS C27 3LH0 100R SCL-DMA-BUS2
+3V3 SCL_HD 3LG2 C1 9LA6 I3
10K RES

RES

10K RES

RES

+3V3-STANDBY
3LG3 B4 9LC6 C3

9LA2
10K 3LJ3 AH11 JTAG_TCK B27 3LH1 100R SDA-DMA-BUS2
SDA_HD 3LG5 B4 9LC7 C3
3LA8

3LB1

3LB2

3LB3

9LA0
10K

10K

AK11 JTAG_TDI
JTAG-TD-DVB-HDMI 9LA1 AJ11 F4 IRQ-HIRATE 3LG6 B4 FJ40 E3
JTAG_TDO HD_EXINT1
JTAG-TMS AG11 F5 3LJ2 10K +3V3 3LG7 B4 FLA0 C7
JTAG_TMS HD_EXINT2
JTAG-TRST AF11 3LG8 B4 FLA1 D8
JTAG_TRSTN
RESET-MIPS 9LA3 C22 IRQ-HD1 3LG9 E13 FLA2 D8
+5V2-STBY +5V2-STBY INT_HD1
RESET-PNX2015 AA27 RESET_IN D22 IRQ-HD2 3LH0 E13 FLA3 D8
INT_HD2
5LA3 ILB7 3LH1 E13 FLA4 D8
AD6 SDAC_VDDD G4 3LH3 100R SCL-DMA-BUS2
+1V2 SCL_AVIP 3LH2 B7 FLA5 D9
F +3V3-STANDBY
+3V3-STANDBY
AE6 SDAC_VSSD F 3LH3 F13 FLA6 E14
330R
3LS3

3LS7

3LH4 100R
10K

G5 SDA-DMA-BUS2
SDA_AVIP 3LH4 F13 FLA7 E14

2LA4

100n
D10 NC_1
3LH5 E1 FLB0 D10
Y1 NC_3 A22 IRQ-AVIP
INT_AVIP1 3LH6 E1 FLB1 H10
IL12 Y30 NC_4 B22 IRQ-AVIP-SUB
INT_AVIP2 3LH7 B7 FLB2 I1 0
3LU6

3LU4
68K

10K
7LB2 AJ1 NC_5
IL11 4 IL20 IL21 NCP303LSN10T1 AJ2 3LH8 B4 FLB3 G8
3LS6 3LU8 3LU7 6L02 NC_6
BC847BPN 2 3LH9 B4 FLB4 H8
IL10 +5V IN FLB3
5 7LA2-2 1 DETECT-5V 3LJ0 C4 FLB5 I8
10K 10R 180K BAS316 RST
6 3 3V4 3LJ1 C4 FLB7 C2
GND
3LU5

3
22K

3LS4 IL13 2LT3 IL22 3LJ2 F13 IL10 G2

LED1-3V3 2 7LA2-1 5 4 3LJ3 E11 IL11 F3
CD NC
BC847BPN
10K 100n 3LJ4 C4 IL12 F4
1
3LJ5 C4 IL13 G2
G +3V3-STANDBY +3V3-STANDBY +1V2 +3V3-STANDBY G 3LJ6 C4 IL14 G2
3LS5 +3V3-STANDBY 3LJ7 D4 IL17 I2
3LJ8 D4 IL20 F6
10K
3LJ9 D4 IL21 F7
3LV1

3LT8
3LK0 D4 IL22 G7

3LT3

10R
68K

10K
IL14 RES

3LV3
9LA5 3LK1 D4 IL23 H6

10K
LED1 7LB1
+8V6-SW IL23 IL24 NCP303LSN10T1 3LK2 D4 IL24 H7
3LU9 3LV0 6L01

100K
3LT7
2 3LK3 D4 IL25 H7
IN FLB4
1 DETECT-8V6 3LK4 D4 IL26 I7
+5V2-STBY +5V2-STBY 47K 330K BAS316 RST

3LT4
3

4K7
GND 3V4 3LK5 D4 IL27 I6
3LV2

22K

2LT4 IL25 7LB4 7LB5

BC847BW 3LK6 D4 IL28 I7
5 4 NCP303LSN10T1 IL30
CD NC IL31 3LK7 D4 IL29 H11
2
100n FLB1 IN
H H 3LK8 D4 IL30 H11
560R
3LS8

3LS9

1
10K

DETECT-1V2 RST
3 3LK9 E4 IL31 H12
3V4 GND

180K
3LT5

3LT6
3LL0 E4 IL32 I12

68K
+3V3-STANDBY IL29 2LT1
IL41 4 5 3LL1 E4 IL33 I11
+3V3-STANDBY NC CD
100n
3LL2 E4 IL34 I11
IL42 4 3LL3 E4 IL40 H2
IL40 3LT0
BC847BPN 3LL4 E4 IL41 H3
3LV6

5 7LA3-2
68K

10K +3V3-STANDBY 3LL5 E4 IL42 H3

+3V3-STANDBY
3LV4

6
10K

7LB0 3LL6 E4 IL43 I2

IL17 IL43 3 IL27 IL26 NCP303LSN10T1
3LT1 3LV8 3LV7 6L00 3LL7 E4 ILB3 D3
LED2-3V3 2 7LA3-1 LED2 +12VSW 2
IN FLB5 3LL8 D10 ILB5 E10

3LU1
BC847BPN 1

68K
10K 10R 560K BAS316 RST DETECT-12V
3LL9 E10 ILB6 D11

3LU3
1 3

10K
GND 3V4 7LB3
3LM0 A4 ILB7 F11
3LV5

NCP303LSN10T1
22K

2LT5 IL28 IL33 6L03 IL32

I 3LT2
5
CD NC
4
DETECT-3V3
FLB2
1
IN
2 3LU0

100K
3LT9

10R
+3V3 I 3LM1 A4
3LM2 A4
ILB8 E8
ILB9 C1
100n RST BAS316
3 3LM3 A4 ILC2 D1
10K 3V4 GND

3LU2

22K
IL34 2LT2 3LM4 B4 ILC3 B1
RES 4 5
NC CD 3LM5 B4
9LA6 3LM6 B4
100n
3LM7 B4
3LN0 C4
3LN1 C4
3LN2 C4
F_15400_032.eps
8204 000 8427.7 260405
3LN3 C4

1 2 3 4 5 6 7 8 9 10 11 12 13 14
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 58

SSB: PNX2015: Supply

1 2 3 4 5 6 7 8
2L80 E1

B4F PNX 2015: SUPPLY B4F

2L81 E1
2L82 E1
2L83 E1
2L84 E1
2L85 E1
2L86 E2
2L87 E2
7J00-9 7J00-8 2L88 E2
PNX 2015 PNX 2015 2L89 E2
+3V3
A Φ +1V2
Φ A 2L90 E2
GND SUPPLY 2L91 E3

47u 4V
2LN2

2LN3

2LN4

2LN5

2LN6

2LN7

2LN8
+3V3

100n

100n

100n

100n

100n

100n
B2 R16
B5
VSS_1 VSS_36
R17 E9
2L92 E3
VSS_2 VSS_37 C1V2_VDD_1 2LN2 A7
B8 R18 E11
VSS_3 VSS_38 C1V2_VDD_2
B11 E12 F25 2LN3 A7
VSS_4 C1V2_VDD_3 P3V3VDD_1
B14
VSS_5 VSS_40
T13 E16
C1V2_VDD_4 P3V3VDD_2
G25 2LN4 A7
B17 T14 E17 H26 2LN5 A8
VSS_6 VSS_41 C1V2_VDD_5 P3V3VDD_3
B20 T15 F9 M6 +1V2
B29
VSS_7 VSS_42
T16 F10
C1V2_VDD_6 P3V3VDD_4
N6
2LN6 A8
VSS_8 VSS_43 C1V2_VDD_7 P3V3VDD_5 2LN7 A8
C25 T17 F12 V6
VSS_9 VSS_44 C1V2_VDD_8 P3V3VDD_6

100u 4V
2LN8 A8

2LP0

2LP2

2LP3

2LP4
100n

100n

100n
D24 T18 F16 W6
VSS_10 VSS_45 C1V2_VDD_9 P3V3VDD_7
D26
VSS_11 VSS_46
J6 F17
C1V2_VDD_10 P3V3VDD_8
AF8 2LP0 B7
E2 U6 AA6 AA26 2LP2 B8
VSS_12 VSS_47 C1V2_VDD_11 P3V3VDD_9
B E23
E26
VSS_13 VSS_48
U13
U14
J25
K25
C1V2_VDD_12
AB26
B 2LP3 B8
VSS_14 VSS_49 C1V2_VDD_13 P3V3VDD_11 2LP4 B8
E29 U15 AB6 AC26
VSS_15 VSS_50 C1V2_VDD_14 P3V3VDD_12
H29 U16 P6 AD25 2LP7 B8
VSS_16 VSS_51 C1V2_VDD_15 P3V3VDD_13 +2V5
L29
VSS_17 VSS_52
U17 R6
C1V2_VDD_16 P3V3VDD_14
AE7 2LP8 B8
N13 U18 AB25 AE13 2LP9 B8
VSS_18 VSS_53 C1V2_VDD_17 P3V3VDD_15

100u 4V

2LR0
2LP7

2LP8

2LP9
100n

100n

100n
N14 U29 F22 AE14
N15
VSS_19 VSS_54
V13 F21
C1V2_VDD_18 P3V3VDD_16
AE24
2LR0 B8
VSS_20 VSS_55 C1V2_VDD_19 P3V3VDD_17 2LR2 C8
N16 V14 AA5 AE25 +1V2-STANDBY
VSS_21 VSS_56 C1V2_VDD_20 P3V3VDD_18
N17 V15 AE10 AF26 2LR4 D8
VSS_22 VSS_57 C1V2_VDD_21 P3V3VDD_19
N18
VSS_23 VSS_58
V16 AE12
C1V2_VDD_22 2LR5 D8
P13 V17 AF10 AE15 5LN0 ILN3 2LR6 D8
VSS_24 VSS_59 C1V2_VDD_23 SB1V2VDD_1
P14 V18 AF12 AE16 PLL-3V3
P15
VSS_25 VSS_60
AC29 AF13
C1V2_VDD_24 SB1V2VDD_2
AE17
+3V3 2LR8 E8
VSS_26 VSS_61 C1V2_VDD_25 SB1V2VDD_3
C P16
VSS_27 VSS_62
AF29 E20
C1V2_VDD_26 SB1V2VDD_4
AE18 C 2LR9 E8

2LR2
2LS5 E6

100n
P17 AJ5 E22 AF15 +3V3-STANDBY
VSS_28 VSS_63 C1V2_VDD_27 SB1V2VDD_5
P18
VSS_29 VSS_64
AJ8 AA25
C1V2_VDD_28 SB1V2VDD_6
AF17 5LN0 C7
U26 AJ14 AF18 5LN1 C7
VSS_30 VSS_65 +2V5-DDRPNX SB1V2VDD_7
U25 AJ17 AE19
P29
VSS_31 VSS_66
AJ20 +2V5 SB3V3VDD_1
AE21
5LN2 D7
VSS_32 VSS_67 SB3V3VDD_2 5LN1 ILN4
R13 AJ23 AE22 5LN3 E7
VSS_33 VSS_68 SB3V3VDD_3 +1V2 PLL-1V2
R14 AJ26 E5 AF19 5LN4 E6
VSS_34 VSS_69 P2V5VDD_1 SB3V3VDD_4
R15
VSS_35 VSS_70
AJ29 E6
P2V5VDD_2 SB3V3VDD_5
AF20 7J00-8 A5

2LR4

100n
E7 7J00-9 A2
P2V5VDD_3
E8 A23
E13
P2V5VDD_4 VDD_LVDS_1
A24
ILN2 E6
P2V5VDD_5 VDD_LVDS_2 LVDS-3V3 ILN3 C8
E14 A26
P2V5VDD_6 VDD_LVDS_3
E15 B23 5LN2 ILN5 ILN4 C8
P2V5VDD_7 VDD_LVDS
D E18
E19
P2V5VDD_8
AE9
+3V3-STANDBY
UP-3V3 D ILN5 D8
P2V5VDD_9 VDDA_SYS_PLL PLL-1V2 ILN6 E8
F6 T25
P2V5VDD_10 VCCA_LVDS_PLL LVDS-3V3

2LR5

2LR6
100n

100n
F7 V25
P2V5VDD_11 VDDA_1_7_MCAB +3V3
F13 P26
P2V5VDD_12 VCCA_U5PLL PLL-3V3
F14
P2V5VDD_13
F15 AF24
P2V5VDD_14 ADC_VSSA
F18 AF22 UP-3V3 5LN3 ILN6
P2V5VDD_15 ADC3V3VDDA
F19 LVDS-3V3
P2V5VDD_16 +3V3
2L87
2L80

2L81

2L82

2L83

2L84

100n
2L85

100n
2L86

100n

100n
2L88

100p
2L89

2L90

2L92

L26 V26
2u2

2u2

2u2

2u2

1n0

1n0

1n0

1n0

2L91 P2V5VDD_17 AVDD_MCAB +1V2

M25 W25
P2V5VDD_18 AVSS_MCAB

2LR8

2LR9
100n

100n
M26 5LN4
P2V5VDD_19 ILN2
N25 AK1
P2V5VDD_20 SDAC_3V3
R26
P2V5VDD_21
E P25
P2V5VDD_22 E

2LS5

100n
T26
P2V5VDD_23
R25 P2V5VDD_24

F_15400_033.eps
8204 000 8427.7 260405

1 2 3 4 5 6 7 8
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 59

SSB: PNX2015: Display Interface

1 2 3 4 5 6 7 8 9 10 11 12 13 1G50 F12
2J37 H4
FJ28 H10
FJ29 H10
2J40 F9 FJ30 H10

B4G PNX 2015: DISPLAY INTERFACE

2J41 F9 FJ31 H10

B4G 2J42 G9
2J43 G9
2J44 G9
FJ32 H10
FJ36 H10
FJ37 H10
2J45 H9 IJ10 B10
2J46 H9 IJ12 C11
A A 2J47 H9
2J48 H9
IJ13 D11
IJ14 B4
(VSYNC)
9J19 CTRL-DISP3
2J49 I9 IJ15 D2

5J08 FJ14
* 2J57 D4
2J60 C10
IJ16 D3
IJ18 G2
+3V3 VDISP2 2J61 D5 IJ19 G2
* I2C-BUFFER *
2J64 H5 IJ20 G2

100n
2J74
5J09
* 2J67 D12
2J68 E12
IJ21 H2
IJ22 H2
* 2J69 H5 IJ23 H2
B IJ14 5J10 B 2J70 H5
2J71 B5
IJ24 H2
IJ61 B12
+5VDISP 5J82 RES 2J75 RES
+5V2-STBY
5J11 * FJ13
VDISP
100n
2J72 I9
2J73 I9
IJ67 C3
IJ68 D4
2J74 B5 IJ69 D4
5J12 * 2J71 5J85 IJ10 IJ61
2J75 B1 1 IJ70 D3
9J18

5J14

9J15
+3V3
2J76 D3 IJ71 I2
* 100n
3J23 G2 IJ72 I2

3J31

3J32
100n
2J60

4K7

4K7
6J06 7J04
IJ67 3J86 6J03
PCA9515DP 3J24 G2 IJ73 C5
7J06 VCC BAV99 COL
1K0 SML-310 3J25 D3 IJ81 H3
SI3441BDV
C +12VSW
RES RES
SDA-I2C4 3 SDA0 SDA1 6
RES
C 3J26 E5
3J28 D4

* IJ73 SCL-I2C4 2 SCL0 SCL1 7

IJ12 3LQ7 FJ15
SCL-I2C4-DISP
3J31 C10
3J32 C11
3J92

47K
* 3J87

1K0
* 0V
ENABLE-5V
5 EN
NC
1
100R 3J42 F4
3J43 F5

100p
2J67
GND

RES
6J01
*
BZX384-C5V6
2J61

1n0
* 3J44 F5
3J45 G2

4
7J07
*
BC847BW 3J46 G2
3J99

47R
* IJ15 2J76

1u0
* IJ70
3J25

47K
* IJ16 3 IJ68 IJ69 6J04 3J47 H2
D 1 3J28
* 3J94
* +3V3 BAV99 COL D 3J48 F2
3J49 F2
10K 10K
2
3J50 H2

100n
2J57
VDISP-SWITCH * 9J16 RES
RES
3LQ8 FJ16
SDA-I2C4-DISP
3J51 H2
3J52 H4
IJ13 100R
9J17 RES 3J53 H2

RES
100p
2J68
3J54 I2
3J26
3J55 I2
+3V3 3J56 I3
10K
*
3J86 C5
E E 3J87 C5
3J88 F5
3J91 G2
+3V3 3J92 C2
3J94 D5
3J99 D2
3LQ7 C12
3LQ8 D12
* * * *
3J42

3J43

3J44

3J88

5J08 A4
47R

47R

47R

47R

5J09 B4
F TXPNXA-
2J40
F 5J10 B5
5J11 B5
10p

1 5J50 4

3
DLW21S
3J49 FJ12 5J12 B5
CTRL1-MOP
47R
* CTRL-DISP1 (IRQ)

1G50 5J14 C2
TXPNXA+

2
3J48 FJ11 (PDWIN) 2J41 5J50 F8
CTRL2-MOP
47R
* CTRL-DISP2
10p 2J42
VDISP 1
2
5J52 G8
3J46 FJ10 (CPU-GO) 3 5J54 G8
CTRL3-MOP
* CTRL-DISP3 TXPNXB- 10p 4 5J56 H8

1 5J52 4

3
DLW21S
47R VDISP2 5
3J45 FJ09 (PDP-GO) 6 5J58 I8
CTRL4-MOP
* CTRL-DISP4
TXPNXB+
CTRL-DISP1
CTRL-DISP2
7 5J60 I8

2
47R 2J43 8
G CTRL-DISP3 G 5J82 B9
CTRL1-VIPER
IJ18 3J91

47R
* 10p 2J44 CTRL-DISP4
9
10
11
5J85 B9
6J01 D2
TXPNXC- FJ23
IJ19 3J24
* 10p 12

1 5J54 4

3
CTRL2-VIPER FJ24 6J03 C11

DLW21S
13
47R 14 6J04 D11
FJ25
LVDS
CTRL4-VIPER
IJ20 3J23
* TXPNXC+ FJ26
15
6J06 C5

2
+3V3-STANDBY 2J45 16
47R
* * * * 17
CONNECTOR 7J04 C9
100p

100p

100p

100p
2J37

2J70

2J69

2J64

FJ27
CTRL1-STBY
IJ21 3J50

47R
* TXPNXCLK-
10p 2J46
FJ28
18
19
7J06 C3
7J07 D4
* 10p 20

1 5J56 4

3
FJ29

DLW21S
7J09 I4
IJ22 3J47
* 21
3J52

FJ30
4K7

CTRL3-STBY
H 47R
TXPNXCLK+ FJ31
22
23 H 9J15 C10
9J16 D10

2
CTRL4-STBY
IJ23 3J51

47R
* 2J47

10p 2J48
FJ32
24
25
26
9J17 E10
IJ81 FJ36 9J18 C2
POD-MODE
IJ24 3J53
* TXPNXD- 10p
FJ37
27
28 9J19 A5
1 5J58 4

3
100K DLW21S 29
IJ71 7J09 SCL-I2C4-DISP FJ09 G5
30
ON-MODE
3J55
* BC847BW SDA-I2C4-DISP 31 FJ10 G5
100K

TXPNXD+ 33

* *
32
2

100K 3J56 2J49 FJ11 F5

IJ72 FI-WE31P-HFE-E1500 FJ12 F5
10p 2J72
MP-OUT-VS
3J54

47R
* TXPNXE-
FJ13 B5
I 10p
I
1 5J60 4

FJ14 A5
DLW21S

FJ15 C12
TXPNXE+ FJ16 D12
2

2J73
FJ23 G10
10p FJ24 G10
FJ25 G10
F_15400_034.eps FJ26 H10
8204 000 8427.7 260405 FJ27 H10

1 2 3 4 5 6 7 8 9 10 11 12 13
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 60

SSB: Viper: Control

0H00 B10 1M00 A10 2Q69 F14 3H08 C3 3H15 F7 3H27 D1 3H72 D7 3H80-3 D8 3H84 E8 3H93 E8 3Q04 B2 3Q16 H10 3Q23 H10 3Q40-1 F7 5H01 H11 6H06-1 H14 7V00-5 A5 9H13 C1 9Q14 E10 AH10 A7 FQ04 H15 FQ22 C1 FQ52 F4 IQ03 G10 IQ16 F12 IQ27 E7 IQ53 G2
0H01 A10 1M64 H13 2Q70 F14 3H09 D1 3H16 C3 3H29 E2 3H73 A7 3H80-4 C8 3H85 E1 3H94 H7 3Q10 A4 3Q17 H11 3Q24 E10 3Q40-2 F7 5H02 G11 6H06-2 H12 9H03 B4 9H14 F4 9Q15 F10 AH11 A2 FQ05 H15 FQ23 C1 FQ53 F4 IQ04 G10 IQ17 F13 IQ28 F7 IQ60 H2
0H02 B11 2H06 H9 3H01 C1 3H10 D1 3H22 B13 3H31 E2 3H74 A7 3H81-1 D8 3H86 E8 3H95 H7 3Q11 A4 3Q18 H11 3Q27 B1 3Q40-3 F7 5H03 F14 6H07-1 G13 9H04 B1 9H15 F4 9Q16 F10 FH12 H7 FQ06 H15 FQ41 B14 FQ54 C4 IQ05 H10 IQ21 F13 IQ30 E1 IQ61 H2
0H04 B10 2H07 H9 3H03 C3 3H11 D1 3H23 B13 3H40 H3 3H75 A2 3H81-2 C8 3H87 E2 3H97 G1 3Q12 B4 3Q19 H11 3Q38-1 F7 3Q40-4 F7 5H04 F14 6H07-2 G12 9H05 F4 9H16 B4 9Q17 H13 FQ00 G15 FQ10 F1 FQ42 B14 IH09 D1 IQ06 H10 IQ22 F7 IQ32 F10
0H05 B10 2H08 A2 3H04 A13 3H12 A9 3H24 F7 3H41 H1 3H79 A7 3H81-3 D8 3H88 E8 3H98 B4 3Q13 B4 3Q20 G10 3Q38-2 F7 3Q48 A4 6H00 H7 7H01 G2 9H06 E4 9H30 E1 9Q18 H13 FQ01 G15 FQ19 C1 FQ43 B14 IH16 F7 IQ13 E12 IQ23 G7 IQ50 B2
1H00 A2 2H09 A1 3H05 A13 3H13 D1 3H25 F7 3H70 E8 3H80-1 D7 3H82 A2 3H89 E11 3H99 B4 3Q14 B4 3Q21 H11 3Q38-3 F7 3Q50 D4 6H01 E1 7H02 H2 9H07 C1 9H40 H2 9Q65 C14 FQ02 H15 FQ20 C1 FQ44 C14 IH17 F7 IQ14 E10 IQ24 G7 IQ51 B2
1H01 G15 2Q67 E13 3H06 A9 3H14 B9 3H26 F7 3H71 C1 3H80-2 C7 3H83 E2 3H90 B1 3Q03 B2 3Q15 B4 3Q22 H11 3Q38-4 F7 3Q52 D4 6H03 F1 7Q01 E12 9H08 C1 9Q13 E10 9Q66 C13 FQ03 E3 FQ21 C1 FQ50 C4 IH18 F7 IQ15 F12 IQ25 G7 IQ52 G2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

B5A VIPER: CONTROL 1M00

EMC HOLE
+3V3 +3V3

B5A

3H05

3H04
1K8

1K8
7V00-5
VIPER REV C SCL-DMA SCL-DMA-BUS1

A 2H08
C4
XTALI PLL_OUT
D28
3H79 AH10
PLL-OUT PLL-OUT
3H06
SDA-DMA SDA-DMA-BUS1 A
27p
CONTROL 22R 22R
3H75
DSX840GA
A2 D29 3H74 M135-CLK PCI-CLK-VPR
XTALO M135_CLK
1H00

3H82
27M

1M0
100R C30 3H73 68R M27-CLK
3Q48 M27_CLK 3H12 0H01
RESET-SYSTEM AD4 22R PLL-OUT
RESET_IN
100R 22R
2H09 AK12
SDA-MM A25 I2C1_SDA PCI_AD0 PCI-AD0
SCL-MM 100R 3Q11 C25 AJ12 PCI-AD1 PCI-CLK-ETHERNET
27p AH11 100R 3Q10 I2C1_SCL PCI_AD1 AH12
PCI_AD2 PCI-AD2 FQ41
+3V3 SDA-DMA AF29 AG12 PCI-AD3 SCL-DMA SCL-DMA-BUS2
100R 3Q13 AD26 I2C2_SDA PCI_AD3 AJ11 3H14
SCL-DMA I2C2_SCL PCI_AD4 PCI-AD4 PLL-OUT FQ42
100R 3Q12 AG11 PCI-AD5 SDA-DMA SDA-DMA-BUS2
3Q03 IQ50 PCI_AD5 22R 0H00 0H04 0H02
SCL-I2C4 SDA-UP-VIP AE27 AK10 PCI-AD6
+3V3 100R 3Q15 AG29 I2C3_SDA PCI_AD6
SCL-UP-VIP AJ10 PCI-AD7 PCI-CLK-USB20
4K7 100R 3Q14 I2C3_SCL PCI_AD7 +3V3 +3V3
3Q27

3H90

AG10
4K7

4K7

PCI_AD8 PCI-AD8
B 3Q04

4K7
IQ51
SDA-I2C4 SDA-I2C4
SCL-I2C4 100R 3H99
A3
B4
I2C4_SDA PCI_AD9
AK9
AJ9
PCI-AD9
PCI-AD10
B
100R 3H98 I2C4_SCL PCI_AD10 AH9
PCI_AD11 PCI-AD11
0H05

3H22

3H23
RES JTAG-TD-VIPER-PNX2015 9H03 AG9

4K7

4K7
JTAG-TD-VIPER-PNX2015 D2 JTAG_TDO PCI_AD12 PCI-AD12
9H04 JTAG-TD-CON-VIPER 9H16 C1 AK8 +3V3
JTAG-TD-CON-VIPER JTAG_TDI PCI_AD13 PCI-AD13
JTAG-TCK E4 AG8 PCI-AD14
JTAG_TCK PCI_AD14 FQ43
JTAG-TMS JTAG-TMS D3 AK7 PCI-AD15 SCL-MM SCL-MM-BUS1
JTAG_TMS PCI_AD15 AJ5
JTAG-TRST C2 JTAG_TRST PCI_AD16 PCI-AD16 FQ44
JTAG-TRST AG5 PCI-AD17 SDA-MM SDA-MM-BUS1
FQ19 PCI_AD17
JTAG-TD-POD-CON 4K7 EJTAG-TDO D25 AJ4 PCI-AD18

4K7

4K7

4K7
FQ20 DBG_TDO PCI_AD18
JTAG-TD-CON-VIPER 4K7 3H16 EJTAG-TDI B27 AH4 PCI-AD19
FQ21 DBG_TDI PCI_AD19
JTAG-TMS 4K7 3H08 EJTAG-TCK A28 AK3 PCI-AD20
FQ22 DBG_TCK PCI_AD20
JTAG-TCK 3H03 EJTAG-TMS A29 AJ3 PCI-AD21
FQ23 DBG_TMS PCI_AD21

9Q66

9Q65
AK2 PCI-AD22

3H80-2

3H80-4

3H81-2
PCI_AD22
C +3V3
3H01 4K7 POWERDOWN-1394
SEL-IF-LL1
B5
E5 GPIO0 PCI_AD23
AJ1
AH2
PCI-AD23
PCI-AD24
C
D4 GPIO1 PCI_AD24 AG2
SEL-IF-LL2 GPIO2 PCI_AD25 PCI-AD25 SDA-I2C4
3H71 B1 AG3 PCI-AD26

4K7

4K7

4K7

4K7
+3V3 IRQ-IEEE1394 FQ50 E7 GPIO3 PCI_AD26 AG4
4K7 IRQ-IEEE1394 PCI-AD27 SCL-I2C4
A5 GPIO4 PCI_AD27 AF1
IRQ-MPIF 9H08 PCI-AD28
FQ54 GPIO5 PCI_AD28
IRQ-FE-MAIN 9H07 IRQ-MAIN IRQ-MAIN A26 AF2 PCI-AD29
GPIO6 PCI_AD29 AF4
IRQ-AVIP 9H13 RESET-ETHERNET B25 PCI-AD30

3H80-1

3H80-3

3H81-1

3H81-3
GPIO7 PCI_AD30 AF5
POWER-OK-PLATFORM-3V3 3Q50 D5 PCI-AD31
GPIO8 PCI_AD31
RESET-USB20 100R E26
3H10 4K7 CTRL4-VIPER GPIO9 AH7
+3V3 CTRL4-VIPER D27 GPIO10 PCI_PAR PCI-PAR
3H09 4K7 REGIMBEAU REGIMBEAU B29 AF7 PCI-PERR
3H11 4K7 GPIO11 PCI_PERR
RES DEBUG-BREAK DEBUG-BREAK 3Q52 B28 AK6 PCI-STOP
IH09 GPIO12 PCI_STOP
RES SOUND-ENABLE-VPR SOUND-ENABLE-VPR 100R C27 AH6 PCI-TRDY
GPIO13 PCI_TRDY
D +3V3 3H13 4K7 IRQ-ETHERNET IRQ-ETHERNET
GLINK-IR-OUT-VIP
E25
D26
GPIO14 PCI_IRDY
AG6
AF6
PCI-IRDY
PCI-FRAME
D
3H27 RES GPIO15 PCI_FRAME
GLINK-IR-OUT-VIP AJ6 PCI-DEVSEL
+3V3 PCI_DEVSEL
F3 AJ2 3H72 100R PCI-AD16
10K SC1_SCCK PCI_IDSEL
G4 AD2 PCI-CLK-VPR
SC1_OFFN PCI_CLK
E2 AH1 PCI-CBE3
SC1_RST PCI_CBE3
G5 AK5 PCI-CBE2
SC1_CMD PCI_CBE2
F4 AJ7 PCI-CBE1 +5V
SC1_DA PCI_CBE1
PCI_CBE0 AG7 PCI-CBE0
3H87 IRQ-USB20 IRQ-USB20 H4 AH10 PCI-SERR
4K7 SC2_SCCK PCI_SERR
3H85 RESET-FE-MAIN RESET-FE-MAIN F1 +3V3
4K7 SC2_OFFN 3H70
3H83 IRQ-POD IRQ-POD G3 AD1 PCI-INTA PCI-INTA 4K7 +3V3
+3V3 SC2_RST INTA

2Q67

100n
4K7 RES IRQ-HD2 9H06 F2 SC2_CMD AE1 IQ13
RESET-TM E1 PCI-REQ PCI-REQ 3H84 4K7
FQ03 SC2_DA PCI_REQ
E AE2 PCI-REQ-A PCI-REQ-A 3H86 4K7 E
BAS316

PCI_REQ_A

3Q24
6H01

3H89
AE4

10K

10K
3H29 PCI_REQ_B PCI-REQ-B PCI-REQ-B 3H88 4K7
+3V3 HSYNC-HIRATE AE28
QVCP2L_DATA_OUT0 AD5 3H93 4K7
4K7 VSYNC-HIRATE AD27 QVCP2L_DATA_OUT1 PCI_GNT PCI-GNT PCI-GNT
9H30 IRQ-SUB IRQ-SUB AF30 AE3 PCI-GNT-A USB20-OC1 9Q13
QVCP2L_DATA_OUT2 PCI_GNT_A

7
RESET-POD-CI AE29 AE5 7Q01
IQ30 3H31 QVCP2L_DATA_OUT3 PCI_GNT_B IQ27 IQ14
IRQ-HIRATE IRQ-HIRATE AD28 USB-OVERCUR 9Q14 LM3526MX-LNOPB
+3V3 QVCP2L_DATA_OUT4
4K7 FQ52 AC27 AA3 3Q38-1 XIO-D8 IQ15 IN
QVCP2L_DATA_OUT5 XIO_D8
IRQ-HD1 9H05 AE30 AA4 100R 3Q38-2 XIO-D9 1 5H03
QVCP2L_DATA_OUT6 XIO_D9 ENA_
FQ53 AD29 AB1 3Q38-3 100R XIO-D10 IQ16 8
9H14 QVCP2L_DATA_OUT7 XIO_D10 OUTA

47u 6.3V
RESET-1394 AD30 AB2 100R 3Q38-4 XIO-D11 2
QVCP2L_DATA_OUT8 XIO_D11 FLGA IQ17

2Q69
IRQ-AVIP-SUB HDMI-COAST 9H15 AB27 AB3 3Q40-1 100R XIO-D12 USB20-PWE1 9Q15
QVCP2L_DATA_OUT9 XIO_D12
AB28 AB4 100R 3Q40-3 XIO-D13 3
QVCP2L_CLK_OUT XIO_D13 FLGB
AC1 3Q40-2 100R XIO-D14 IQ32 5
XIO_D14 OUTB
F SOUND-ENABLE
XIO_D15 AC4
W3
100R 3Q40-4
100R
XIO-D15
XIO-ACK
USB-BUS-PW 9Q16 4
ENB_
5H04
F
XIO_ACK
W4 IQ28 GND
XIO_A25

47u 6.3V
FQ10 AA2 IH16 3H24 100R XIO-SEL0
6H03 XIO_SEL0 IQ21

2Q70
A-PLOP AA1 IH17 3H15 100R XIO-SEL1

6
XIO_SEL1
Y4 IH18 3H26 100R XIO-SEL2
BAS316 XIO_SEL2
Y2 IQ22 3H25 100R XIO-SEL0
XIO_SEL3
3H97

4K7

W2 IQ23
XIO_SEL4
E24 GLINK-TXD +5V
UA1_TX
UA1_RX B26 GLINK-RXD

UA2_TX F26 TXD-VIPER

IQ53 E27 RXD-VIPER
UA2_RX
G IQ52
POWER-OK-PLATFORM-3V3 UA2_RTSN C29
B30
IQ24
6H07-2 6H07-1
G
UA2_CTSN IQ25
POWER-OK-PLATFORM 7H01
PDTC114EU 5H02 BAV99S BAV99S
+3V3 1H01

DLW21S
IQ03 22R
USB1-DM FQ00 1
USB1_DM AJ28 USB1-DM IQ04 3Q20 22R FQ01 2
USB1_DP AH27 USB1-DP 2H07 USB1-DP FQ02 3
3H40

RES
10K

USB2_DM AF26 USB2-DM USB-BUS-PW IQ05 3Q21 22R 4

USB2_DP AK29 USB2-DP 1n0 USB2-DM 5H01 FQ04 5 USB
AJ29 USB-BUS-PW FQ05

DLW21S
IQ61 IQ06 3Q22 22R
GLINK-IR-OUT
USB_BUS_PWR
AG27 USB-OVERCUR
USB-OVERCUR 2H06
USB2-DP FQ06
6 CONNECTOR
USB_OVRCUR 7
IQ60 3Q19

3Q23

3Q16

3Q17

3Q18
FH12 1n0 8
GLINK-IR-OUT-VIP 7H02 AD3 RESET-MIPS 1M64 9 11
PDTC114EU SYS_RSTN_OUT
10 12
RES BAV99S 1 TO 1N62 BAV99S
SML-310

H 2
H
3H41

3H94

1-1470168-1
10R

RES 4K7

+5V 3

15K

15K

15K

15K
6H00

4
6H06-2 6 5 6H06-1
SSB

9Q17

9Q18
9H40
B4B-PH-SM4-TBT(LF)
3H95

330R

+3V3 F_15400_035.eps
8204 000 8430.4 260405

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 61

SSB: Viper: Main Memory

2Q01 B8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 2Q03 B9
2Q21 B13
2Q23 B14

B5B VIPER: MAIN MEMORY B5B

2V00 C7
2V01 C14
2V02 C2
2V03 G8
2V04 G9
2V05 G9
2V16 G10
2V17 G11
A A 2V18 G11
2V19 G11
2V20 G11
2V21 G11
SD RAM1 SD RAM2 2V22 G12
2V23 G12

2Q01

2Q03

2Q21

2Q23
7V00-2

1u0

1u0

1u0

1u0
VIPER REV C +2V5D-DDR 2V24 G12
+2V5D-DDR +2V5D-DDR +2V5D-DDR
2V25 G12
2V26 G12
2V27 G13
DDR INTERFACE *
7V01 *
7V02 2V28 G13

18

33

15

55

61

61

55

15

33

18
MT46V32M16P-5BTR MT46V32M16P-5BTR

1
2V29 G13
B MM_A0 29
0
VDD
Φ
VDDQ 14
17
14
17
VDDQ
Φ
VDD
0
29 MM_A0 B 2V30 G13
MM_A0 B13 D19 MM_DATA_7 MM_A1 30 25 25 30 MM_A1 2V31 G14
MM_A1 D15
MM_ADDR0 MM_DATA0
B19 MM_DATA_3 MM_A2 31
1 DDR NC
43 43
NC DDR 1
31 MM_A2 2V35 G14
MM_A2 MM_ADDR1 MM_DATA1 MM_DATA_5 MM_A3 2 SDRAM SDRAM 2 MM_A3
B14 C19 32 53 53 32 3V00 C9
MM_ADDR2 MM_DATA2 3 3
MM_A3 A15 A21 MM_DATA_4 MM_A4 35 8Mx16 19 19 8Mx16 35 MM_A4
MM_A4 MM_ADDR3 MM_DATA3 MM_DATA_1 MM_A5 4 DNU DNU 4 MM_A5
3V01 C11
C15 D20 36 50 50 36
MM_ADDR4 MM_DATA4 5 A A 5 3V02 C9
MM_A5 B15 D21 MM_DATA_6 MM_A6 37 37 MM_A6
MM_A6 MM_ADDR5 MM_DATA5 MM_DATA_2 MM_A7 6 MM_DATA_0 MM_DATA_16 6 MM_A7 3V03 C11
A16 B21 38 2 3V00 22R 3V01 22R 2 38
MM_A7 MM_ADDR6 MM_DATA6 MM_DATA_0 MM_A8 7 0 MM_DATA_1 MM_DATA_17 0 7 MM_A8
D16
MM_ADDR7 MM_DATA7
C21 39
8 1
4 3V02 22R 3V03 22R 4
1 8
39 3V04 C9
MM_A8 B16 A24 MM_DATA_13 MM_A9 40 5 3V04 22R MM_DATA_2 MM_DATA_18 3V05 22R 5 40 MM_A9 3V05 C11
MM_A9 MM_ADDR8 MM_DATA8 MM_DATA_12 MM_A10 9 2 MM_DATA_3 MM_DATA_19 2 9 MM_A10
C16 B22 28 7 3V06 22R 3V07 22R 7 28
MM_A10 MM_ADDR9 MM_DATA9 MM_DATA_10 MM_A11 10 3 MM_DATA_4 MM_DATA_20 3 10 MM_A11
3V06 C9
D14 A22 41 8 3V08 22R 3V09 22R 8 41
MM_A11 MM_ADDR10 MM_DATA10 MM_DATA_8 MM_A12 11 4 MM_DATA_5 MM_DATA_21 4 11 MM_A12 3V07 C11
C18 D22 42 10 3V10 22R 3V11 22R 10 42
MM_ADDR11 MM_DATA11 12 5 5 12 3V08 C9
C MM_A12

VREF-VPR
B17
MM_ADDR12 MM_DATA12
MM_DATA13
C24
C22
MM_DATA_11
MM_DATA_14 MM_BA0 26
AP
0 D
6
7
11
13 3V14 22R
3V12 22R MM_DATA_6
MM_DATA_7
MM_DATA_22
MM_DATA_23 3V15 22R
3V13 22R 11
13
6
7 D
AP
0
26 MM_BA0 C 3V09 C11
2V02 C12 B24 MM_DATA_15 MM_BA1 27 BA 54 3V16 22R MM_DATA_8 MM_DATA_24 3V17 22R 54 BA 27 MM_BA1 3V10 C9
MM_AVREF MM_DATA14 MM_DATA_9 1 8 MM_DATA_9 MM_DATA_25 8 1
100n MM_DATA15
D23
9
56 3V18 22R 3V19 22R 56
9 3V11 C11
MM_BA0 D13 C6 MM_DATA_21 MM_DQM_0 20 57 3V20 22R MM_DATA_10 MM_DATA_26 3V21 22R 57 20 MM_DQM_2
MM_BA0 MM_DATA16 MM_DATA_17 MM_DQM_1 L 10 MM_DATA_11 MM_DATA_27 10 L MM_DQM_3 3V12 C9
MM_BA1 A13 B6 47 DM 59 3V22 22R 3V23 22R 59 DM 47
MM_BA1 MM_DATA17 MM_DATA_23 2V00 100n U 11 MM_DATA_12 MM_DATA_28 11 U 3V13 C11
D7 60 3V32 22R 3V33 22R 60 2V01 100n
MM_DATA18 MM_DATA_16 12 MM_DATA_13 MM_DATA_29 12
MM_CS0 B12
MM_DATA19
C7 VREF-VPR 49
VREF
62 3V34 22R 3V35 22R 62
VREF
49 VREF-VPR 3V14 C9
MM_CS0 MM_DATA_20 13 MM_DATA_14 MM_DATA_30 13
IH20 D17 B7 63 3V36 22R 3V37 22R 63 3V15 C11
MM_CS1 MM_DATA20 MM_DATA_22 MM_CLK_N 14 MM_DATA_15 MM_DATA_31 14 MM_CLK_N
C9 46 65 3V38 22R 3V39 22R 65 46
MM_DATA21
MM_DATA_19 MM_CLK_P
CK 15 15 CK
MM_CLK_P
3V16 C9
MM_DQM_0 A19 D8 45 45
MM_DQM_0 MM_DATA22 MM_DATA_18 MM_CKE CK CK MM_CKE 3V17 C11
MM_DQM_1 D24 A7 44 44
MM_DQM_1 MM_DATA23 CKE CKE 3V18 C9
MM_DQM_2 D6 A8 MM_DATA_24 MM_CS0 24 16 3V42 22R MM_DQS0 MM_DQS2 3V43 22R 16 24 MM_CS0
B11 MM_DQM_2 MM_DATA24 MM_DATA_26 MM_RAS CS L MM_DQS1 MM_DQS3 L CS MM_RAS
MM_DQM_3
MM_DQM_3 MM_DATA25
B9 23
RAS DQS
U
51 3V40 22R 3V41 22R 51
U
DQS RAS
23 3V19 C11
D MM_DQS0 B20
MM_DQS_0
MM_DATA26
MM_DATA27
D10
A9
MM_DATA_27
MM_DATA_28
MM_CAS
MM_WE
22
21
CAS
WE
CAS
WE
22
21
MM_CAS
MM_WE D 3V20 C9
3V21 C11
MM_DQS1 A23 D9 MM_DATA_30
MM_DQS_1 MM_DATA28 MM_DATA_29 VSS VSSQ VSSQ VSS 3V22 C9
MM_DQS2 A6 C10
MM_DQS_2 MM_DATA29 MM_DATA_31 3V23 C11

34

48

66

12

52

58

64

64

58

52

12

66

48

34
MM_DQS3 B10 A10
MM_DQS_3 MM_DATA30 MM_DATA_25
MM_DATA31
D11 3V32 C9
MM_RAS C13 3V33 C11
MM_CAS A12 MM_RAS
MM_CAS 3V34 C9
MM_WE D12
MM_WE 3V35 C11
MM_CKE D18 3V36 D9
MM_CKE
MM_CLK_N A18
MM_CLK_N
3V37 D11
MM_CLK_P B18 3V38 D9
MM_CLK_P
3V39 D11
E 3V44 E 3V40 D9
3V41 D11
3V78

1K0

100R
3V42 D9
3V43 D11
3V44 E3
3V78 E3
5V01 G9
5V02 G9
7V00-2 A4
7V01 B7
7V02 B13
IH20 D3
F F IH21 G9

5V01 IH21
+2V5D-DDR
+2V5D +2V5D-DDR

5V02
G RES
G

47u 4V
2V16

2V17

2V18

2V19

2V20

2V21

2V22

2V23

2V24

2V25

2V26

2V27

2V28

2V29

2V30

2V31

2V35
100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n
2V03

2V04

2V05
100n

100p
1n0
F_15400_036.eps
8204 000 8430.4 260405

1 2 3 4 5 6 7 8 9 10 11 12 13 14
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 62

SSB: Viper: A/V & Tunnel Bus

2H00 H3
1 2 3 4 5 6 7 8 9 10 11 12 13 2H01 I6
2H02 H3
2H03 H2

B5C VIPER: A/V + TUNNELBUS B5C

2H11 D12
2H12 D12
2H13 D12
2Q25 C12
7V00-1 2Q29 B12
VIPER REV C
2Q31 C12
3H02 C9
DV1F-DATA0 AG13 DV1_DATA0
AUDIO/VIDEO QVCP5L_DATA_OUT0 J28 100R 3Q28-4 DV-BOUT-0 3H07 E8
DV1F-DATA1 100R 3Q28-3
A DV1F-DATA2
AH13
AJ13
DV1_DATA1
DV1_DATA2
QVCP5L_DATA_OUT1
QVCP5L_DATA_OUT2
J27
H30 100R 3Q28-2
100R 3Q28-1
DV-BOUT-1
DV-BOUT-2 A 3H18 C3
3H19 C10
DV1F-DATA3 AK13 H27 DV-BOUT-3
DV1_DATA3 QVCP5L_DATA_OUT3
DV1F-DATA4 AG14 G30 100R 3Q34-4 DV-BOUT-4 3H20 D10
DV1_DATA4 QVCP5L_DATA_OUT4 100R 3Q34-3
+3V3 DV1F-DATA5 AJ14 G29 DV-BOUT-5 3H21 D9
DV1_DATA5 QVCP5L_DATA_OUT5 100R 3Q34-2
DV1F-DATA6 AG15 G28 DV-BOUT-6 3H28 B3
DV1_DATA6 QVCP5L_DATA_OUT6 100R 3Q34-1
DV1F-DATA7 AH15 G27 DV-BOUT-7
DV1F-DATA8_ERR
DV1_DATA7 QVCP5L_DATA_OUT7 100R 3Q26-4 3H32 B3
AJ15 DV1_DATA8 QVCP5L_DATA_OUT8 F30 DV-BOUT-8
DV1F-DATA9_SOP AK15 F29 100R 3Q26-3 DV-BOUT-9 3H48 G9
4K7 DV1_DATA9 QVCP5L_DATA_OUT9
DV1F-VALID DV1F-VALID AG16 M28 100R 3Q25-2 DV-GOUT-0 3H49 F9
DV1_VALID QVCP5L_DATA_OUT10 100R 3Q25-1
3H28 DV1F-CLK AH16 M27 DV-GOUT-1 3H50 H3
DV1_CLK QVCP5L_DATA_OUT11 100R 3Q44-4
QVCP5L_DATA_OUT12 L29 DV-GOUT-2 3H51 H3
DV2A-DATA2_0 AJ16 L27 100R 3Q44-3 DV-GOUT-3
DV2A-DATA3_1 DV2_DATA0 QVCP5L_DATA_OUT13 100R 3Q44-2 3H92 D11
AK16 DV2_DATA1 QVCP5L_DATA_OUT14 K30 DV-GOUT-4
DV2A-DATA4_2 AJ17 K29 100R 3Q44-1 3Q00 C11
B DV2A-DATA5_3
DV2A-DATA6_4
AG17
DV2_DATA2
DV2_DATA3
QVCP5L_DATA_OUT15
QVCP5L_DATA_OUT16 K28
100R 3Q08-3
100R 3Q08-4
DV-GOUT-5
DV-GOUT-6 B 3Q01 D11
AK18
DV2_DATA4 QVCP5L_DATA_OUT17
K27 DV-GOUT-7 3Q02-1 C9
DV2A-DATA7_5 AJ18 J30 100R 3Q08-2 DV-GOUT-8
DV2_DATA5 QVCP5L_DATA_OUT18 5Q05 3Q02-2 C9
DV2A-DATA8_6 AH18 J29 100R 3Q08-1 DV-GOUT-9
DV2A-DATA9_7
DV2_DATA6 QVCP5L_DATA_OUT19 100R 3Q07-4 3Q02-3 C9
AG19 DV2_DATA7 QVCP5L_DATA_OUT20 R28 DV-ROUT-0 1u0
4K7 DV2A-VALID 100R 3Q07-3 3Q02-4 C8
DV2A-VALID AK19 DV2_VALID QVCP5L_DATA_OUT21 R27 DV-ROUT-1 IQ00 IQ01 2Q29 IQ02
DV2A-CLK 100R 3Q07-2 47R 3Q05-1 C9
3H32 AH19 DV2_CLK QVCP5L_DATA_OUT22 P29 DV-ROUT-2 DAC-CVBS
DV2A-DATA1_ERR AJ19 P27 100R 3Q07-1 DV-ROUT-3 3Q05-2 C8
DV2_ERR QVCP5L_DATA_OUT23 3Q00 100p
DV2A-DATA0_SOP AG18 N30 100R 3Q05-4 DV-ROUT-4
DV2_SOP QVCP5L_DATA_OUT24 3Q05-3 C9
N29 100R 3Q05-3 DV-ROUT-5
QVCP5L_DATA_OUT25 3Q05-4 C9

3Q06

2Q25

2Q31
100R 3Q05-2

560p
DV3F-DATA2_0

39R

12p
AK24 DV3_DATA0 QVCP5L_DATA_OUT26 N28 DV-ROUT-6
DV3F-DATA3_1 AJ24 N27 100R 3Q05-1 DV-ROUT-7 3Q06 C11
DV3_DATA1 QVCP5L_DATA_OUT27
DV3F-DATA4_2 AK25 QVCP5L_DATA_OUT28 M30 100R 3Q25-4 DV-ROUT-8 3Q07-1 C8
DV3F-DATA5_3 DV3_DATA2 100R 3Q25-3 3Q07-2 B9
C DV3F-DATA6_4
DV3F-DATA7_5
AG23
AH24
DV3_DATA3
DV3_DATA4
QVCP5L_DATA_OUT29
QVCP5L_CLK_OUT
M29
E30 100R 3H02
100R
DV-ROUT-9
DV-CLKIN C 3Q07-3 B9
AJ25 F28 3Q02-3 DV-OUT-VS
DV3_DATA5 QVCP5L_VSYNC 3Q07-4 B8
DV3F-DATA8_6 AK26 F27 100R 3Q02-4 DV-OUT-HS
DV3_DATA6 QVCP5L_HSYNC 3Q08-1 B9
DV3F-DATA9_7 AG24 G26 100R 3Q02-1 DV-OUT-FFIELD
4K7 DV3_DATA7 QVCP5L_AUX1 5Q06
DV3F-VALID DV3F-VALID AJ26 QVCP5L_AUX2 E29 100R 3Q02-2 DV-OUT-DE 3Q08-2 B9
DV3F-CLK DV3_VALID
3H18 AG25 DV3_CLK 2u2 3Q08-3 B8
DV3F-DATA1_ERR AF24 AH30 IH08 3H19 1K0
DV3_ERR DAC_IRSET IH12 120R IH13 2H11 IH14 3Q08-4 B9
DV3F-DATA0_SOP AH25 AF27 IH07 3H21 39R C-MON-OUT
DV3_SOP DAC_RDUMPY
IH06 3H20 39R
3Q09 E8
AH29 3Q01
DAC_RDUMPC 100p 3Q25-1 B8
I2S-MAIN-ND IH10 AG26 AG28
DV_FREF DAC_CVBS RES
I2S-SUB-ND IH11 AK28 AJ30 3Q25-2 B9
DV_VREF DAC_CHROMA

3H92

2H13

2H12
RES
IH15 3Q25-3 C8

75R

12p

27p
AJ27 DV_HREF
TS_DATA0 AJ22 TS-DATA0 3Q25-4 C9
D I2S-WS-AVIP 9H18 IH01
AA30
AA29
I2S_IN1_SD
I2S_IN1_WS
TS_DATA1
TS_DATA2
AG21
AK22
TS-DATA1
TS-DATA2 D 3Q26-3 B9
3Q26-4 A8
I2S-BCLK-AVIP 9H19 AA28 I2S_IN1_SCK TS_DATA3 AH21 TS-DATA3
IH03 AB30 AJ21 TS-DATA4 3Q28-1 A9
I2S_IN1_OSCLK TS_DATA4
TS_DATA5 AK21 TS-DATA5 3Q28-2 A8
W28 I2S_IN2_SD TS_DATA6 AG20 TS-DATA6 3Q28-3 A9
9H32 W27 AJ20 TS-DATA7
I2S_IN2_WS TS_DATA7 3Q28-4 A9
9H33 Y29 I2S_IN2_SCK TS_VALID AK23 TS-VALID
Y27 AH22 TS-SOP 3Q33 H5
IH00 I2S_IN2_OSCLK TS_SOP
AG22 3Q09 TS-CLK 3Q34-1 A9
TS_CLK
SPDIF-HDMI AA27
SPDIF_IN2
33R 3Q34-2 A9
SPDIF-IN1 AC30 SPDIF_IN1 I2S_OUT1_SD0 U27 I2S-SUB-D 3Q34-3 A8
V30 3H07 22R BACKLIGHT-CONTROL
I2S_OUT1_SD1 3Q34-4 A9
I2S_OUT1_SD2 V29 CTRL1-VIPER
V28 3Q35 H5
I2S_OUT1_SD3
I2S_OUT1_WS V27 E 3Q37 H6
I2S_OUT1_SCK W30 CTRL2-VIPER 3Q39 H5
I2S_OUT1_OSCLK W29 IH04 3Q41 H5
3Q43 H6
I2S_OUT2_SD0 T28 I2S-MCH-LR
T27 I2S-MCH-CSW 3Q44-1 B9
I2S_OUT2_SD1
I2S_OUT2_SD2 R30 I2S-MCH-SLR 3Q44-2 B8
I2S_OUT2_SD3 R29 I2S-MAIN-D 3Q44-3 B9
I2S_OUT2_WS T29 I2S-WS-MAIN 3Q44-4 B9
I2S_OUT2_SCK T30 I2S-BCLK-MAIN
3Q45 H5
I2S_OUT2_OSCLK U29 IH05 3Q47 H5
3Q64 3Q49 H6
SPDIF_OUT AB29 SPDIF-OUT1
3Q51 H5
68R
F 3Q53 H5
3Q55 H6
3Q57 H5
3Q59 I5
3Q61 I6
68R 3H49 I2S-WS-SUB 3Q63 I5
68R 3H48 I2S-BCLK-SUB
3Q64 F8
3Q65 I9
3Q66 I5

9H26
9H27
3Q67 I6
3Q68 I9
9H34
G 9H29 G 5H05 H2
5Q05 B12
5Q06 C12
7V00-4 7V00-1 A6
VIPER REV C
7V00-4 G7
9H18 D3
TUNNELBUS 9H19 D4
TUN-VIPER-TX-DATA0 3Q33 47R N2 G2 TUN-VIPER-RX-DATA0 9H26 G8
N1 TUN_TX_DATA0 TUN_RX_DATA0 G1 TUN-VIPER-RX-DATA1
IQ35 TUN-VIPER-TX-DATA1 3Q35 47R 9H27 G8
5H05 TUN_TX_DATA1 TUN_RX_DATA1 J4
TUN-VIPER-TX-DATA2 3Q37 47R P4 TUN-VIPER-RX-DATA2
+2V5-VPR TUN_TX_DATA2 TUN_RX_DATA2 J3
9H29 G7
TUN-VIPER-TX-DATA3 3Q39 47R P2 TUN-VIPER-RX-DATA3
TUN-VIPER-TX-DATA4 3Q41 47R R1 TUN_TX_DATA3 TUN_RX_DATA3 H1 TUN-VIPER-RX-DATA4 9H32 D3
TUN_TX_DATA4 TUN_RX_DATA4 K4 9H33 D4
2H03

3H50

2H00

R2 TUN-VIPER-RX-DATA5
100n

100n

TUN-VIPER-TX-DATA5 3Q43 47R

10K

H FQ15
TUN-VIPER-TX-DATA6
TUN-VIPER-TX-DATA7
3Q45 47R R3
R4
TUN_TX_DATA5
TUN_TX_DATA6
TUN_RX_DATA5
TUN_RX_DATA6
J2
J1
TUN-VIPER-RX-DATA6
TUN-VIPER-RX-DATA7
H 9H34 G7
3Q47 47R FQ15 H3
T3 TUN_TX_DATA7 TUN_RX_DATA7 K1 TUN-VIPER-RX-DATA8
TUN-VIPER-TX-DATA8 3Q49 47R IH00 E4
1V3 VREF-VPR T4 TUN_TX_DATA8 TUN_RX_DATA8 L4 TUN-VIPER-RX-DATA9
TUN-VIPER-TX-DATA9 3Q51 47R
TUN-VIPER-TX-DATA10 3Q53 47R U2 TUN_TX_DATA9 TUN_RX_DATA9 L2 TUN-VIPER-RX-DATA10 IH01 D4
TUN_TX_DATA10 TUN_RX_DATA10 M4 IH03 D4
3H51

2H02

U4 TUN-VIPER-RX-DATA11
100n

TUN-VIPER-TX-DATA11 3Q55 47R

10K

TUN_TX_DATA11 TUN_RX_DATA11 M3
TUN-VIPER-TX-DATA12 3Q57 47R V1 TUN-VIPER-RX-DATA12 IH04 E8
V2 TUN_TX_DATA12 TUN_RX_DATA12 M2 TUN-VIPER-RX-DATA13
TUN-VIPER-TX-DATA13 3Q59 47R IH05 F8
V3 TUN_TX_DATA13 TUN_RX_DATA13 M1 TUN-VIPER-RX-DATA14
TUN-VIPER-TX-DATA14 3Q61 47R IH06 D9
V4 TUN_TX_DATA14 TUN_RX_DATA14 N4 TUN-VIPER-RX-DATA15
TUN-VIPER-TX-DATA15 3Q63 47R
TUN_TX_DATA15 TUN_RX_DATA15 IH07 D9
TUN-VIPER-TX-CLKP 3Q66 47R T1 K3 RES TUN-VIPER-RX-CLKP IH08 C9
TUN_TX_CLOCKP TUN_RX_CLOCKP
TUN-VIPER-TX-CLKN 3Q67 47R T2 3Q65 100R TUN-VIPER-RX-CLKN IH10 D5
W1 TUN_TX_CLOCKN N3 3Q68 TUN-VIPER-RX-BUSY
TUN-VIPER-TX-BUSY IH11 D5
K2
TUN_TX_BUSY TUN_RX_BUSY
47R
I IH12 C11
VREF-VPR TUN_AVREF IH13 C12
IH14 C13
IH15 D5
2H01

100n

IQ00 B11
IQ01 B12
IQ02 B13
IQ35 H3
F_15400_037.eps
8204 000 8430.4 260405

1 2 3 4 5 6 7 8 9 10 11 12 13
 F
E
D
C
B
A
2Q04 C11
2Q02 C11
2Q00 C10

1
1

7V00-3
V18 VSSC_36

VIPER REV C
V17 VSSC_35
2Q07 C12
2Q06 C12
2Q05 C12

V16 VSSC_34 VDDC_1 M12

+1V2
V15 M13
VSSC_33 VDDC_2
V14 VSSC_32 VDDC_3 M14
V13 M15
VSSC_31 VDDC_4
U18 VSSC_30 VDDC_5 M16

8204 000 8430.4

U17 M17
VSSC_29 VDDC_6
U16 VSSC_28 VDDC_7 M18
2Q10 C13
2Q09 C13
2Q08 C12

U15 M19
VSSC_27 VDDC_8
U14 VSSC_26 VDDC_9 N12
U13 VSSC_25 VDDC_10 N19
T18 VSSC_24 VDDC_11 P12
T17 P19

2
2

VSSC_23 VDDC_12
T16 VSSC_22 VDDC_13 R12
T15 VSSC_21 VDDC_14 R19
SSB: Viper: Supply

T14 VSSC_20 VDDC_15 T12

2Q13 C14
2Q12 C13
2Q11 C13

T13 VSSC_19 VDDC_16 T19

R18 VSSC_18 VDDC_17 U12
R17 VSSC_17 VDDC_18 U19
R16 VSSC_16 VDDC_19 V12
R15 VSSC_15 VDDC_20 V19
R14 VSSC_14 VDDC_21 W12
R13 VSSC_13 VDDC_22 W13
2Q16 C14
2Q15 C14
2Q14 C14

P18 W14
VSSC_12 VDDC_23
P17 VSSC_11 VDDC_24 W15
P16 W16
VSSC_10 VDDC_25
P15 W17

3
3

VSSC_9 VDDC_26
B5D VIPER: SUPPLY

P14 W18
VSSC_8 VDDC_27
P13 VSSC_7 VDDC_28 W19
N18
VSSC_6
N17 VSSC_5
2Q19 C15
2Q18 C15
2Q17 C15

N16
VSSC_4 J26
N15 VSSC_3 VDD_1 L26
+3V3

N14 VSSC_2 VDD_2

N13 N26
VSSC_1 VDD_3 R26
VDD_4 U26
M26 VSS_68 VDD_5
AK30 W26
VSS_67 VDD_6 AA5
2Q24 E11
2Q22 E11
2Q20 E10

AK17 VSS_66 VDD_7

AK11 AA26
VSS_65 VDD_8
AK4 AC5

4
4

VSS_64 VDD_9 AC26

AJ23 VSS_63 VDD_10
AH26 AF9
VSS_62 VDD_11 AF11
AH20 VSS_61 VDD_12
AH14 AF13
VSS_60 VDD_13 AF15
AH8
2Q28 E12
2Q27 E12
2Q26 E12

VSS_59 VDD_14 AF17

AH3
VSS_58 VDD_15 AF19
AG1 VSS_57 VDD_16
AF28 AF21
VSS_56 VDD_17 AF23
AF22 VSS_55 VDD_18
AF20 D1
VSS_54 VDD_19 Y3
AF18 VSS_53 VDD_20
AF16 AC2
VSS_52 VDD_21 AF3
2Q33 E13
2Q32 E13
2Q30 E12
Circuit Diagrams and PWB Layouts

AF14 VSS_51 VDD_22

AF12 AH5

5
5

VSS_50 VDD_23 AH11

AF10 VSS_49 VDD_24
AF8 AH17
VSS_48 VDD_25 AH23
AC29
SUPPLY

VSS_47 VDD_26 AJ8

AC3 VSS_46 VDD_27
AB26 AK1
VSS_45 VDD_28 AK14
AB5
2Q37 E14
2Q35 E14
2Q34 E13

VSS_44 VDD_29 AK20

Y28
VSS_43 VDD_30 AK27
Y26
VSS_42 VDD_31 H29
Y5
VSS_41 VDD_32 L28
Y1
VSS_40 VDD1_33 P30
V26
VSS_39 VDD1_34 U28
V5
VSS_38 VDD1_35 Y30
U30
VSS_37 VDD1_36 AC28
2Q39 E14
2Q38 E14

2Q40 D10

U3

6
6

VSS_36 VDD1_37 AG30

T26
VSS_35 VDD1_38 AH28
T5
BP2.3U AA

VSS_34 VDD1_39 E28

P28
VSS_33 VDD1_40 A4
P26 VSS_32 VDD2_41
P5 A30
VSS_31 VDD2_42 C3
P1 VSS_30 VDD2_43
M5 C26
2Q44 D11
2Q43 D11
2Q42 D11

VSS_29 VDD2_44 E23

L30 VSS_28 VDD2_45
L3 VSS_27
K26 E9
VSS_26 VDD_2V5_1 E11
K5 VSS_25 VDD_2V5_2 E13
+2V5-VPR

H28
7.

VSS_24 VDD_2V5_3 E15

H26 VSS_23 VDD_2V5_4
H5 E17

7
7

VSS_22 VDD_2V5_5 E19

2Q47 D12
2Q46 D12
2Q45 D12

H2 VSS_21 VDD_2V5_6
E22 E21
VSS_20 VDD_2V5_7 J5
E20 VSS_19 VDD_2V5_8
E18 L5
VSS_18 VDD_2V5_9 N5
E16 VSS_17 VDD_2V5_10
E14 R5
VSS_16 VDD_2V5_11 U5
E12 VSS_15 VDD_2V5_12
E10 W5
2Q50 D13
2Q49 D13
2Q48 D12

VSS_14 VDD_2V5_13 H3
EN 63

E8 VSS_13 VDD_2V5_14
E3 L1
VSS_12 VDD_2V5_15 P3
D30 VSS_11 VDD_2V5_16
C28 U1
VSS_10 VDD_2V5_17 A11
C23 VSS_9 VDD_2V5_18
C17 A17
8
8

VSS_8 VDD_2V5_19 B23

C11 VSS_7 VDD_2V5_20 C8
2Q53 D14
2Q52 D13
2Q51 D13

C5
VSS_6 VDD_2V5_21 C14
B8 VSS_5 VDD_2V5_22 2Q63
A27 C20
VSS_4 VDD_2V5_23
A20 VSS_3
IQ09

100n
A14 VSS_2 VDDA_3V3 F5
+3V3

A1 VSS_1 VDDA_1V2 E6
5Q01
VDDA_1_7_MCAB B3
B2 VSSA_1_7_MCAB AE26
IQ10
2Q56 D14
2Q55 D14
2Q54 D14

VDD_DAC 2Q64
AF25 VSS_DAC
+1V2

100n 5Q02
9
9

2Q65
IQ07
+1V2

100n 5Q03
2Q59 D15
2Q58 D15
2Q57 D15

2Q66
IQ08
+3V3

100n 5Q04
2Q62 F11
2Q61 F11
2Q60 F10

+2V5

10
10

2Q20 2Q40 2Q00

2Q65 B9
2Q64 B9
2Q63 B8

2Q60
47u 4V 47u 4V 47u 4V
100n

2Q22 2Q42 2Q02

5Q02 B9
5Q01 B9
2Q66 B9

RES
5Q08
5Q07

47u 4V 47u 4V 47u 4V

2Q43
2Q61
11
11

1u0 16V
1n0
2Q62 2Q24 2Q44 2Q04
5Q03 B9

5Q07 E11
5Q04 B10

IQ11
+1V2
+3V3

100p 100n 100n 100n

+2V5-VPR

2Q26 2Q45 2Q05

100n 100n 100n

2Q46 2Q06
2Q27
IQ07 C9
5Q08 F11

100n 100n
7V00-3 C1

100n
+2V5-VPR

2Q47 2Q07
12
12

2Q28
100n 100n
100n
2Q48 2Q08
IQ10 B9
IQ09 C8
IQ08 C9

2Q30
100n 100n
100n
2Q49 2Q09
2Q32
100n 100n
100n 2Q50 2Q10
IQ11 E11

2Q33 100n 100n

13
13

100n 2Q51 2Q11

2Q34 100n 100n

2Q52 2Q12
100n
100n 100n
2Q35
2Q53 2Q13
100n
100n 100n
2Q37 2Q54 2Q14

100n 100n 100n

14
14

2Q38 2Q55 2Q15

100n 100n 100n

2Q39 2Q56 2Q16

100n 100n 100n

2Q57 2Q17

100n 100n
2Q58 2Q18

100n 100n
15
15

2Q59 2Q19

100n 100n
B5D

260405
F_15400_038.eps
F
E
D
C
B
A
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 64

SSB: Viper: Display Diversity & Ambilight

1D40 A3 2Q71 C7 2Q80 E4 2Q86 C2 2Q92 A9 3Q36 B5 3Q75 D4 3Q89 A4 3Q97 B9 5Q11 C2 6H09 C6 9Q61 C9 FQ11 A3 FQ24 B4 FQ30 E3 FQ36 A3 FQ47 D2 FQ58 E2 IQ41 B9 IQ47 B5
1M03 E2 2Q72 C7 2Q81 E4 2Q87 A4 2Q93 E4 3Q42 B5 3Q76 D4 3Q90 A4 3Q98 C9 5Q12 C2 7Q05-1 B9 9Q62 B9 FQ12 A3 FQ25 B7 FQ31 E3 FQ37 B3 FQ48 D2 FQ59 E2 IQ42 B8 IQ48 A5
1M49 B6 2Q73 D4 2Q82 E4 2Q88 C2 3Q29 C8 3Q46 E6 3Q79 E4 3Q91 A5 3Q99 B8 5Q13 C2 7Q05-2 C9 9Q63 C9 FQ13 A3 FQ26 B7 FQ32 A3 FQ38 B3 FQ49 E2 FQ61 E3 IQ43 B9 IQ49 B5
1M63 D2 2Q74 D4 2Q83 C2 2Q89 B4 3Q30 B8 3Q72 B8 3Q80 E4 3Q92 B5 5Q00 B1 6H04 A8 9Q19 C8 FQ07 B6 FQ14 B3 FQ27 D3 FQ33 A3 FQ39 B3 FQ55 C7 FQ62 E3 IQ44 A5 IQ54 E6
2Q36 B4 2Q75 D4 2Q84 A2 2Q90 B4 3Q31 B9 3Q73 B8 3Q81 E4 3Q93 B5 5Q09 A1 6H05 C8 9Q30 A3 FQ08 A3 FQ16 B3 FQ28 D3 FQ34 A3 FQ40 B4 FQ56 E2 FQ63 E3 IQ45 C9
2Q41 D2 2Q79 E4 2Q85 B1 2Q91 B9 3Q32 B9 3Q74 D4 3Q82 E5 3Q96 B5 5Q10 A1 6H08 C5 9Q60 B9 FQ09 A3 FQ17 B3 FQ29 D3 FQ35 A3 FQ46 D2 FQ57 E3 IQ40 B9 IQ46 C8

1 2 3 4 5 6 7 8 9 10

B5E VIPER: DISPLAY DIVERSITY + AMBILIGHT

3Q90 * IQ48
CTRL4-STBY

2Q87
* 100R
3Q89 * IQ44 I2C AMBILIGHT *
ENABLE-5V
A 5Q10 * 1D40* A
FQ08 100p 47R +5V
FQ32
+12VSW 1
FQ09 FQ33
2
* * FQ11 3 3Q91 * 6H04
2Q84

100n

9Q30 FQ34 CTRL1-STBY

* 4 2Q92
5Q09

FQ12 FQ35 100R

5
FQ13 FQ36
6 470p
FQ14
FQ16
7 FQ39 3Q42 * IQ49 BAV99 COL 3Q31
FQ37 MP-OUT-VS IQ40
8
5Q00 * FQ17
9 FQ38 100R +5V +5V 10K
+3V3

+3V3 10 3Q96* IQ47 7Q05-1

3Q97
FQ40

4K7
11 SUPPLY-FAULT BC847BS
* 12
FQ24
3Q36* 47R (ODC 50/60Hz)
2Q85

100n

CTRL1-VIPER
B B

3Q99

3Q30
RES
100R
3Q93*
B12P-PH-K

4K7
100R 9Q62 IQ41
SCL-I2C4 SCL-MOP
FOR * *
* 3Q92
100R 1M49
FQ25 3Q72 100R
RES

2Q36

2Q89

2Q90
100p

100p

100p
FACTORY SDA-I2C4 1 2Q91
9Q60 SCL-UP-SW
100R IQ42 RES
USE 2 FQ26 3Q73 100R
+5V FQ07+5V 3 470p
IQ43 3Q32
4 +3V3
FQ55 +5V +5V 10K
5Q11 * B4B-PH-K
7Q05-2

2Q71

2Q72

9Q19

3Q98
100p

100p

4K7
BC847BS
5Q12 *
TO 1M49
+5VDISP IQ45

3Q29
9Q63 SDA-MOP

4K7
5Q13*

BAV99 COL

BAV99 COL
6H08
RES

6H09
C AMBI LIGHT C

6H05
9Q61 SDA-UP-SW
*
2Q86

2Q83

2Q88

BAV99 COL
RES
10n

10n

10n

IQ46

TO 1M63
MEMORY 1 +5V-CON
CARD 2
2Q41

100n

READER B2B-PH-K
D 2Q73
D
FQ46 FQ27 3Q74
100p BACKLIGHT-CNTRL-OUT
2Q74 100R
FQ47 FQ28 3Q75
100p POWER-OK-PLATFORM
2Q75 220R
FQ48 FQ29 3Q76
100p LIGHT-ON-OUT
100R
2Q93
FQ49 FQ30
100p
+5V-CON
1M03
1
2
2Q79
TO 1M03 3 FQ56 FQ61
100p 3Q79
4 STANDBY
E 5
6
FQ57 FQ62
2Q80
100p 100R 3Q80
PROT-AUDIOSUPPLY
E
2Q82 220R IQ54
FQ63
AUDIO STANDBY 78 100p +5V2-STBY_9V-STBY
3Q46
BACKLIGHT-CONTROL
FQ58 2Q81
10
9
FQ59 FQ31 100p 3Q81
* 100R
POWER-OK-DISPLAY

B10P-PH-K-S
3K3 3Q82
*
5K6 F_15400_039.eps
8204 000 8430.4 260405

1 2 3 4 5 6 7 8 9 10
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 65

SSB: Display Interface: MOP

1 2 3 4 5 6 7 8 9 10 11 12 13 14 0G00 I13
0G01 I14
3G59-2 D13
3G59-3 D13
1G02 H1 3G59-4 C13

DISPLAY INTERFACE: MOP 2G10 A1 3G60-1 D13

B6 B6 2G11 A2
2G12 A2
2G13 A2
2G14 A2
3G60-2 D13
3G60-3 D13
3G60-4 D13
3G61 F9
2G15 A3 3G62 F9
2G16 A3 5G01 A1
2G17 A3 6G01 I5
5G01 FG07 2G18 A3 7G00 D7
A +3V3 +3V3M DV-CLKIN
DV-OUT-HS
9G10
9G11
MP-CLK
MP-HS
MP-CLK
MP-HS
3G08
3G09 68R
MP-CLKOUT
MP-OUT-HS A 2G19 A3 7G01 G4
DV-OUT-VS 9G12 MP-VS MP-VS 3G10 68R MP-OUT-VS 2G20 B1 7G02 B2

47u 4V
2G10

2G11

2G12

2G13

2G14

2G15

2G16

2G17

2G18

2G19

2G37

2G38

2G39

2G40
100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n
DV-OUT-DE 9G13 MP-DE MP-DE 3G11 68R MP-OUT-DE 2G21 B3 7G03 C2
DV-OUT-FFIELD 9G14 MP-FF MP-FF 3G12 68R MP-OUT-FFIELD 2G22 B3 7G31-1 F11
68R
DV-ROUT-0 9G15 MP-R0 MP-R0 3G13 MP-ROUT-0
2G23 B3 7G31-2 G11
DV-ROUT-1 9G16 MP-R1 MP-R1 3G14 68R MP-ROUT-1 2G24 B3 7G32 F3
68R 2G25 B4 7G33 F13
7G02 DV-ROUT-2 1 9G21-1 8 MP-R2 MP-R2 3G55-1 1 8 MP-ROUT-2
LD2985BM25R 2 9G21-2 7 3G55-2 2 7 68R 2G26 B4 7G34 G12
DV-ROUT-3 MP-R3 MP-R3 MP-ROUT-3
DV-ROUT-4 3 9G21-3 6 MP-R4 MP-R4 3G55-3 3 6 68R MP-ROUT-4 2G27 B4 7G35-1 E2
FG08
+3V3 1 5 +2V5M DV-ROUT-5 4 9G21-4 5 MP-R5 MP-R5 3G55-4 4 5 68R MP-ROUT-5 2G28 C1 7G35-2 F2
IN OUT
68R
2G29 C2 7G37 I5
B B

22u 6.3V
3 4 DV-ROUT-6 1 9G22-1 8 MP-R6 MP-R6 3G56-1 1 8 MP-ROUT-6
INH BP 2G30 C3 9G10 A11
2G20

2G21

2G22

2G23

2G24

2G25

2G26

2G27
100n

100n

100n

100n

100n

100n

100n
DV-ROUT-7 2 9G22-2 7 MP-R7 MP-R7 3G56-2 2 7 68R MP-ROUT-7

100n
COM DV-ROUT-8 3 9G22-3 6 MP-R8 MP-R8 3G56-3 3 6 68R MP-ROUT-8 2G31 C3 9G11 A11
2G43 DV-ROUT-9 4 9G22-4 5 MP-R9 MP-R9 3G56-4 4 5 68R MP-ROUT-9 2G32 C4 9G12 A11
68R
2

DV-GOUT-0 9G17 MP-G0 MP-G0 3G15 MP-GOUT-0

2G33 C4 9G13 A11
DV-GOUT-1 9G18 MP-G1 MP-G1 3G16 68R MP-GOUT-1 2G34 C4 9G14 A11
68R 2G35 G11 9G15 A11
7G03 DV-GOUT-2 1 9G23-1 8 MP-G2 MP-G2 3G57-4 4 5 MP-GOUT-2
LD1117DT12 2 9G23-2 7 3G57-3 3 6 68R 2G36 G12 9G16 A11
DV-GOUT-3 MP-G3 MP-G3 MP-GOUT-3
DV-GOUT-4 3 9G23-3 6 MP-G4 MP-G4 3G57-2 2 7 68R MP-GOUT-4 2G37 A4 9G17 B11
FG09
+3V3 3 2 +1V2M DV-GOUT-5 4 9G23-4 5 MP-G5 MP-G5 3G57-1 1 8 68R MP-GOUT-5 2G38 A4 9G18 B11
IN OUT
68R
2G39 A4 9G19 C11
22u 6.3V

COM DV-GOUT-6 1 9G24-1 8 MP-G6 MP-G6 3G58-4 4 5 MP-GOUT-6

2G40 A4 9G20 C11
2G28

2G29

2G30

2G31

2G32

2G33

2G34
100n

100n

100n

100n

100n

100n
C DV-GOUT-7
DV-GOUT-8
2
3
9G24-2
9G24-3
7
6
MP-G7
MP-G8
MP-G7
MP-G8
3G58-3
3G58-2
3
2
6 68R
7 68R
MP-GOUT-7
MP-GOUT-8 C 2G41 E1 9G21-1 B11
1

DV-GOUT-9 4 9G24-4 5 MP-G9 MP-G9 3G58-1 1 8 68R MP-GOUT-9 2G42 E2 9G21-2 B11
68R
DV-BOUT-0 9G19 MP-B0 MP-B0 3G17 MP-BOUT-0
2G43 B2 9G21-3 B11
DV-BOUT-1 9G20 MP-B1 MP-B1 3G18 68R MP-BOUT-1 2G44 G3 9G21-4 B11
68R 3G01 E1 9G22-1 B11
+2V5M +3V3M +1V2M DV-BOUT-2 1 9G25-1 8 MP-B2 MP-B2 3G59-4 4 5 MP-BOUT-2
2 9G25-2 7 3G59-3 3 6 68R 3G02 E2 9G22-2 B11
DV-BOUT-3 MP-B3 MP-B3 MP-BOUT-3
DV-BOUT-4 3 9G25-3 6 MP-B4 MP-B4 3G59-2 2 7 68R MP-BOUT-4 3G03 E1 9G22-3 B11
7G00 DV-BOUT-5 4 9G25-4 5 MP-B5 MP-B5 3G59-1 1 8 68R MP-BOUT-5 3G04 H4 9G22-4 B11

134
120

106

126
138
115

133
121
62
48

19
34

75
91
54
43
66

61
49
XC3S400-4TQG144C 68R

3
9G26-1 3G60-4 4 5
3G05 I6 9G23-1 C11
VCCAUX TOP LEFT BOTTOMRIGHT VCCINT DV-BOUT-6 1 8 MP-B6 MP-B6 MP-BOUT-6
DV-BOUT-7 2 9G26-2 7 MP-B7 MP-B7 3G60-3 3 6 68R MP-BOUT-7 3G06 I5 9G23-2 C11
VCCO
D Φ
DV-BOUT-8
DV-BOUT-9
3
4
9G26-3
9G26-4
6
5
MP-B8
MP-B9
MP-B8
MP-B9
3G60-2
3G60-1
2
1
7 68R
8 68R
MP-BOUT-8
MP-BOUT-9 D 3G07 I5
3G08 A13
9G23-3 C11
9G23-4 C11
68R
SPARTAN-3 FPGA 3G09 A13 9G24-1 C11
TQ144 3G10 A13 9G24-2 C11
+3V3

BANK0 BANK4 3G11 A13 9G24-3 C11

DV-ROUT-1 141 70 MP-B6
140
IO_L01N_0|VRP_0 IO|VREF_4
69 3G12 A13 9G24-4 C11
DV-ROUT-0 IO_L01P_0|VRN_0 IO_L01N_4|VRP_4 MP-B7
137 68 MP-B8 3G13 A13 9G25-1 C11
IO_L27N_0 IO_L01P_4|VRN_4
135 65 DIN 3G14 B13 9G25-2 D11
IO_L27P_0 IO_L27N_4|DIN|D0
132 63 MP-B9
131
IO_L30N_0 IO_L27P_4|D1
60
3G15 B13 9G25-3 D11
IO_L30P_0 IO_L30N_4|D2 MP-VS
3G16 B13 9G25-4 D11
3G01

2G41

3G02
100K

130 59
10K
1u0

IO_L31N_0 IO_L30P_4|D3 MP-HS

IG10 129
IO_L31P_0|VREF_0 IO_L31N_4|INIT_B
58 INIT 3G17 C13 9G26-1 D11
E IG09
6 M27-MOP 3G19
100R
128
127
IO_L32N_0|GCLK7
IO_L32P_0|GCLK6
IO_L31P_4|DOUT|BUSY
IO_L32N_4|GCLK1
57
56
MP-FF
MP-DE
+5V +3V3 E 3G18 C13
3G19 E6
9G26-2 D11
9G26-3 D11
IG12 2 7G35-1 55 MP-CLK
IO_L32P_4|GCLK0
BC847BS 3G20 E13 9G26-4 D11
3G03

1
33K

BANK1 BANK5 3G21 E13 9G30 G11

RES
3G21

3G20
3 116 44

4K7

10K
CTRL2-MOP DV-OUT-DE
IO1_1 IO|VREF_5 3G22 F9 9G35 F13

RES
2G42

113 41
1n0

CTRL3-MOP IO_L01N_1|VRP_1 IO_L01N_5|RDWR_B DV-OUT-FFIELD

5 7G35-2 CTRL4-MOP 112 40 DV-OUT-HS 3G23 F12 FG01 I1
IO_L01P_1|VRN_1 IO_L01P_5|CS_B
BC847BS 119 47 3G22 SDA-MM-BUS1 3G24 F9 FG02 I1
FG11 IO_L28N_1 IO_L28N_5|D6 IG15
4 CTRL1-MOP 118 46 3G24 100R SCL-MM-BUS1
123
IO_L28P_1 IO_L28P_5|D7
51 3G61 100R 3G25 G12 FG03 I1
IO_L31N_1|VREF_1 IO_L31N_5|D4 SDA-MOP
122 50 3G62 100R SCL-MOP 7G33 3G26 G13 FG04 I1
IO_L31P_1 IO_L31P_5|D5
125
IO_L32N_1|GCLK5 IO_L32N_5|GCLK3
53 100R DV-CLKIN RES 3G27 G13 FG05 I1
124 52 +8V6-SW +8V6-SW +8V6-SW
IO_L32P_1|GCLK4 IO_L32P_5|GCLK2 3G28 G2 FG06 I1
F BANK2 BANK6
IG01
BC847BW F 3G29 G5 FG07 A2
108 36 DV-OUT-VS 3G30 G2 FG08 B3
IO_L01N_2|VRP_2 IO_L01N_6/VRP_6

3G51
107 35

47K
IO_L01P_2|VRN_2 IO_L01P_6/VRN_6 DV-BOUT-9 3G31 G5 FG09 C3

3G23
105 33

10K
DV-BOUT-8
3G48 FG12
7G32 104
IO_L20N_2 IO_L20N_6
32 RES
3G32 G13 FG11 F1
ON-MODE MP-R0 IO_L20P_2 IO_L20P_6 DV-BOUT-7 IG02
BC847BW IG03 3G33 G2 FG12 F3
100K MP-R1 103 31 DV-BOUT-6 7G31-1 9G35 LAMP-ON
IO_L21N_2 IO_L21N_6 BC847BPN
MP-R2 102 30 DV-BOUT-5 IG04 3G34 G11 IG01 F13
IO_L21P_2 IO_L21P_6 IG05 3G25
3G49

2G44
100K

+3V3M 100 28
10n

MP-R3 IO_L22N_2 IO_L22N_6 DV-BOUT-4 BC847BPN LIGHT-ON-OUT 3G35 G11 IG02 F13
+3V3M +2V5M +2V5M MP-R4 99 27 DV-BOUT-3 7G31-2 10K IG06
IO_L22P_2 IO_L22P_6 3G26 IG07 3G36 H3 IG03 F11
MP-R5 98 26 DV-BOUT-2 7G34 BACKLIGHT-CONTROL
IO_L23N_2|VREF_2 IO_L23N_6
MP-R6 97 25 DV-BOUT-1 BC847BW 3G37 H4 IG04 G12
IO_L23P_2 IO_L23P_6 4K7
3G28

3G27

RES
96 24
10K

2K2
7G01 MP-R7 IO_L24N_2 IO_L24N_6|VREF_6 DV-BOUT-0 3G38 H1 IG05 G11
18

19

20

3G29

XCF01SVOG20C 95 23
10K

MP-R8 IO_L24P_2 IO_L24P_6 DV-GOUT-9

3G39 H2 IG06 G13
G DIN
3G30 1
INT
D0
O
VCC
J
3G31
MP-R9
MP-G0
93
92
IO_L40N_2
IO_L40P_2|VREF_2
IO_L40N_6
IO_L40P_6|VREF_6
21
20
DV-GOUT-8
DV-GOUT-7 G 3G40 H2 IG07 G13
47R 3 7 3G41 H2 IG08 G10
CLK CF IG08 3G32
13 47R BANK3 BANK7 9G30
3G33 8
RESET CEO
2 76 4 3G42 H4 IG09 E1
INIT OE MP-B3 IO3_1 IO|VREF_7 DV-ROUT-4 RES 1K0
47R 10 9 MP-B4 74 2 DV-ROUT-3 3G43 I2 IG10 E3
CE IO_L01N_3|VRP_3 IO_L01N_7|VRP_7

3G34

3G35

2G35

2G36
100n

RES
RES
5 12 73 1 3G44 I4 IG12 E2

1K0

15K

1u0
TMS MP-B5 IO_L01P_3|VRN_3 IO_L01P_7|VRN_7 DV-ROUT-2
6 NC 14 MP-B1 78 6 DV-ROUT-6
4
TCK
15 77
IO_L20N_3 IO_L20N_7
5
3G45 I2 IG15 F13
TDI MP-B2 IO_L20P_3 IO_L20P_7 DV-ROUT-5
17 16 MP-G9 80 8 DV-ROUT-8 3G46 I2 IG16 I3

BACKLIGHT-CNTRL-OUT
TDO IO_L21N_3 IO_L21N_7
MP-B0 79
IO_L21P_3 IO_L21P_7
7 DV-ROUT-7 3G47 I2 IG17 I3
GND MP-G7 83 11 DV-GOUT-0
IO_L22N_3 IO_L22N_7 3G48 F2 IG18 I4
11

+2V5M MP-G8 82 10 DV-ROUT-9

IO_L22P_3 IO_L22P_7 3G49 G3
3G36

85 13
47R

MP-G5 IO_L23N_3 IO_L23N_7 DV-GOUT-2

3G51 F11
H +3V3M +3V3M +3V3M +3V3M
3G04
MP-G6
MP-G3
84
87
IO_L23P_3|VREF_3
IO_L24N_3
IO_L23P_7
IO_L24N_7
12
15
DV-GOUT-1
DV-GOUT-4 H 3G52 I3
3G37

86 14
10K

+2V5M MP-G4 DV-GOUT-3

90
IO_L24P_3 IO_L24P_7
18 3G53 I3
10K MP-G1 IO_L40N_3|VREF_3 IO_L40N_7|VREF_7 DV-GOUT-6
3G54 I4
3G38

3G39

3G40

3G41
RES

89 17
RES

RES

RES
10K

10K

10K

10K

MP-G2 IO_L40P_3 IO_L40P_7 DV-GOUT-5

3G55-1 B13
3G42 3G55-2 B13
1G02 72 38
FG01 3G43 CCLK M0 3G55-3 B13
47R 3G44 71 37
1 IG16 DONE M1 0G00 0G01
2 FG02 100R 3G45 47R 142
HSWAP_EN M2
39 3G55-4 B13
FG03 3G46 100R 143
3 PROG_B 3G56-1 B13
FG04 100R 3G47 110
4 TCK 3G56-2 B13
FG05 100R IG17 144
5 TDI
6 +3V3M
109
TDO
3G56-3 B13
3G52

330R

7 8 FG06 111 3G56-4 B13

TMS
IG18 6G01
3G57-1 C13
I B6B-PH-SM3-TBT
7G37
BC847BW
3G05
+3V3M
GND
I 3G57-2 C13
3G53

3G54
330R

330R

136
139
114
117
94
101
81
88
64
67
42
45
22
29
9
16

3G06 SML-310 470R

FOR 3G57-3 C13
FACTORY 100K 3G57-4 C13
3G58-1 C13
3G07

USE
100K

3G58-2 C13
3G58-3 C13
3G58-4 C13
F_15400_040.eps
8204 000 8437.3 260405
3G59-1 D13

1 2 3 4 5 6 7 8 9 10 11 12 13 14
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 66

SSB: HDMI
1 2 3 4 5 6 7 8 9 10 11 12 13 14
1B00 B3
1B01 A1

B7A HDMI
1B02 D8

B7A 1B03 B3
1B04 B3
1B05 B10
1B06 B10
1B07 B10
1B20 I4

100n
2B02

3B00

5B02
IB12 1B21 I11

4K7
3B01

3B13
4K7

4K7
1B30 D4

3B12

4K7
1B31 E4
A 1B01
ARX2+ ARX-DDC-SCL
IB63 PARX-DDC-SDA
PARX-DDC-SCL BRX-DDC-SCL
IB60
PBRX-DDC-SCL
A 1B32 G4
1
1B33 H4
2 IB64 IB14
ARX2- ARX-DDC-SDA +3V3 BRX-DDC-SDA PBRX-DDC-SDA 1B34 D10
3
4 ARX1+ 5B00 5B01 IB13 1B35 E10
5 AIN-5V BIN-5V 1B36 G10
ARX1- BSH112 BSH112
6 7B05 1B37 H10

0001-0015

0001-0015

0001-0015
ARX0+ 7B00 7B01 7B04
7 BSH112 2B00 B4

1B00

1B03

1B04

2B00

2B01

1B05

1B06

1B07

2B04

2B05
BSH112

100n

100n

100n

100n
8 IB66
9 ARX0-
3B02 3B14 IB10
2B01 B4
10 ARXC+ 2B02 A9
IB65 IB11
11 100R 3B03 100R 3B15 2B04 B10
12 ARXC-
FB09 9B00 P50-HDMI 2B05 B11
13 100R 100R
B 14
FB10
RES
ARX-DDC-SCL 7B02 7B03
B 2BA0 I5
2BA1 I4
15

3B04

3B16
FB11 M24C02-WDW6 M24C02-WDW6

10K

10K
ARX-DDC-SDA

8
16 2BA2 I12
Φ Φ

3B05

3B06

3B17

3B18
47K

47K

47K

47K
17
FB12
2BA3 I10
18 AIN-5V (256x8) FB35 (256x8) FB34 3B00 A6
19
FB13 ARX-HOTPLUG DDC NVM WC
7 DDC NVM WC
7
3B01 A6
21 20 EEPROM 3B07 EEPROM 3B19
23 22 FB14 HDMI 1 1
2
0 SCL
6
HDMI 2 1
2
0 SCL
6 3B02 B5
1 ADR 100R 3B08 1 ADR 100R 3B20 3B03 B7
1-1734011-2 3 5 3 5
2 SDA 2 SDA 3B04 B5
100R 100R 3B05 B5

4
3B06 B6
HDMI CONNECTOR 1 3B07 B5
C C 3B08 C5
3B09 C5

V
3B09
3B10 D5
3B11 E5
3BA2 3B12 A12
3B13 A13
ARXC- PARXC- 1B02 V
1 1B30 4
3B14 B12
1 BRX2+
4 1B34 1 3B15 B14
2 BRXC+ PBRXC+
2 3 BRX2- 3B16 B12
3
ARXC+ ACM PARXC+ BRX1+ BRXC- 3 2 PBRXC- 3B17 B12
4
5 ACM 3B18 B12
BRX1-
6 3B19 B11
D 7 BRX0+ D 3B20 C12

3B10
8
3B21 F5

V
9 BRX0-
BRXC+ 3B22 F5
V
10
11 3B23 I3
BRXC-
12
FB28
3B24 I10
13 P50-HDMI
9B03 RES 3B90 I4
14
FB29 BRX-DDC-SCL 3B91 I4
15
V

FB30 BRX-DDC-SDA 3BA9 3B92 I11

3B11

16
17 3B93 I10
FB31 BIN-5V
18 3BA0 G5
FB32 BRX-HOTPLUG 3BA3
19 3BA1 H5
21 20
E ARX0-
1 1B31 4
PARX0- 23 22 FB36 V E 3BA2 C11
3BA3 E11
ACM
1-1734011-2 BRX0- PBRX0- 3BA4 F11
2 3 3 2
3BA5 F11
ARX0+ ACM PARX0+ BRX0+ PBRX0+
4 1 3BA6 H11
1B35
HDMI CONNECTOR 2 3BA7 H11
3BA8 H11

V
3BA9 E11
3B21

3BA5
3BB0 H5
V

5B00 A4
5B01 A11
5B02 A8
F F 6B20 I4
6B21 I3
V
3B22

6B22 I10
6B23 I10
3BA4 7B00 A6
7B01 A7
ARX1+ PARX1+ V
ACM 3 7B02 B4
2 ACM 7B03 B10
BRX1- PBRX1-
3 2 7B04 A12
ARX1- 1 4 PARX1- BRX1+ PBRX1+ 7B05 A13
1B32
4 1B36 1 7B30 I5
7B31 I11
G G 9B00 B2
3BA0

9B03 E8

V
9B30 I6
V

9B31 I12
FB09 B1
FB10 B1
3BA6 FB11 B1
V

FB12 B1
FB13 B1
3BA1
FB14 C1
3BA7 FB28 D8
H ARX2+
ACM
PARX2+ V H FB29 E8
FB30 E8
2 3 ACM
BRX2- PBRX2- FB31 E8
3 2
1 4
FB32 E8
ARX2- 1B33 PARX2- BRX2+ PBRX2+
4 1 FB34 B11
1B37
3BA8
FB35 B5
FB36 E8
3BB0

V IB10 B1 4
V

IB11 B1 2
3B92 IB61
BRX-HOTPLUG IB12 A1 3
IB62 22R IB50 IB13 A1 1
3B90 9B31
ARX-HOTPLUG 7B31 VSYNC-HIRATE IB14 A1 3
I 22R
7B30
IB51
9B30 VSYNC-HIRATE
BC847BW
I IB50 I12
IB51 I5

2BA2
BC847BW

10n
IB60 A1 3

BAS316
BAS316
2BA0

2BA3
3B24
IB61 I11

6B23

6B22
3B93

100K

1B21
1K0
10n

4n7
IB62 I5
BAS316

BAS316

2BA1
3B23

6B21

6B20
3B91

100K

1B20
1K0

4n7

IB63 A6
BIN-5V IB64 A7
IB65 B6
AIN-5V IB66 B7
F_15400_041.eps
8204 000 8429.6 260405

1 2 3 4 5 6 7 8 9 10 11 12 13 14
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 67

SSB: HDMI: I/O & Control

1 2 3 4 5 6 7 8 9 10 11 12 13 2B21 B3
2B22 F3
3B99 E1
5B20 E2
2B23 B3 5B21 D2

B7B HDMI: I/O + CONTROL

2B24 B2 5B22 D2

B7B 2B25 F3
2B26 C2
2B27 D2
5B23 C2
5B24 B2
5B31 B2
2B28 F3 7B11-1 B5
2B29 D2 7B11-2 B11
2B30 C2 9B11 D12
2B31 E2 9B12 E10
A A 2B32 B2 9B13 C12
2B33 C2 9B14 C12
IB05
2B34 C2 9B15 C12
3B36
2B35 D2 9B16 B10
12K
AV1-AV6_FBL-HSYNC 2B36 E2 9B17 B10
AV6_VSYNC 2B21 2B37 E2 9B18 B9
AV2-AV4_G-Y
2B23
2B43 C4 9B19 C9
10n
AV1-AV5-AV6_G-Y 2B44 C4 9B20 D9
3B40
5B24 7B11-1 DV4-VALID 3V3-DIG +3V3
3B94 IB67 2B24 10n 3V3-DIG
AV2-AV4_R-PR TDA9975 1K0 2B45 D4 FB40 F6
B 470R 2u2 10n Φ B 2B46 D4 FB45 E6
2BA4

3B65

1K0 T10 E1 +3V3

6p8

15p

RBIAS IN/OUT VPA0 2BA4 B1 IB00 F3

2B32

E2
T16 VPA1 F1 3B56-1 33R DV4-DATA0_SOP
1 VPA2 2BA5 C1 IB01 F3

9B18

9B16

9B17
R16 F2 DV4-DATA1_ERR
HCSYNC VPA3
P16 G1 3B56-3 33R 33R 3B56-2 DV4-DATA2_0 7B11-2 2BA6 D1 IB02 F3
3 VPA4

3B45
DV4-DATA3_1 TDA9975

10K
IB68 G2 JTAG-TD-DVB-HDMI
3B95 5B31 2B26 VPA5 3B59-1 33R 3B56-4 DV4-DATA4_2 IB43 2BA7 D1 IB05 A4
AV1-AV5-AV6_R-PR N16 1 H1
VPA6 IB42 2BA8 E1 IB06 F4

9B15
M16 H2 33R DV4-DATA5_3
470R 2u2 10n VSYNC VPA7 CTRL
3B66

3B59-3 33R 3B59-2 DV4-DATA6_4 9B13

1K0

N15 J1 C11 K13

3 VPA8 TM0 TDI 2BA9 C1 IB20 F4
2BA5

J2 33R DV4-DATA7_5 C14 L13 9B14

6p8

15p

TM1 TDO JTAG-TD-HDMI-POD

T12 VPA9 K1 3B57-1 33R 3B59-4 DV4-DATA8_6 A14 L14 3B25 E6 IB21 D3
1 JTAG-TRST
2B33

VPA10 TM2 TRST

9B19
R12 K2 33R DV4-DATA9_7 A11 K14 JTAG-TMS
2B43
SOG VPA11 3B57-2
TM3 TMS 3B26 E6 IB22 D3
T11 33R J14 JTAG-TCK
C IB69 2B30
10n
T14
3
VPB0
L1
L2
H12
H13
AUX0
TCK
D3
C 3B27 E6 IB23 D4
AV2-AV4_G-Y 3B96 5B23 1 VPB1 3B57-3 DV5-DATA0_SOP
AUX1 OR G/Y 3B28 E6 IB24 D12
R14 M1 G12 C3
R/Pr VPB2 AUX2 OR B/U
470R 2u2
2B44 T13
3
M2 33R 3B57-4 DV5-DATA1_ERR G15
AUX3
B3 3B29 F6 IB41 E8
10n VPB3 OR R/V
2BA9

3B67

3B62-1 33R DV5-DATA2_0

1K0

N1 F15
6p8

15p

10n VPB4 3B62-2 DV5-DATA3_1 AUX4 3B30 G3 IB42 C9

T9 1 N2 33R E14 R4
AUX5 X0
2B34

VPB5
R9 G/Y P1 3B62-3 33R DV5-DATA4_2 E15
AUX6 X1
P4 3B32 G3 IB43 B10
VPB6 3B62-4 DV5-DATA5_3
2B45 T8 P2 33R E16 N4
3 VPB7 33R DV5-DATA6_4 AUX7 X2 3B34 F3 IB46 D12
R1 3B58-1
10n VPB8
5B22 IB70 2B29
T7 1 R2 33R DV5-DATA7_5 L12
CCLK CTL0
C6 3B36 A3 IB67 B2
3B97 VPB9 3B58-2 33R DV5-DATA8_6
AV1-AV5-AV6_G-Y R7 T1 3B58-3 C5
2B46
B/Pb VPB10
33R DV5-DATA9_7 CTL1 3B37 F3 IB68 B2
470R T6 T2 M13 C4 IB46
2u2 10n 3 VPB11 CKEXT CTL2
2BA6

3B68

33R 3B38 F3 IB69 C2

1K0

B4
6p8

15p

10n 3B58-4 CTL3

R13 E3 M14
2B35

IB24 3B40 B6 IB70 D2

D IB22
IB21 R8
R6
Rref
Gref
VPC0
VPC1
F3
G3 M27-HIRATE RES H15
COAST
AP0
A7
A6
9B11 SPDIF-HDMI D 3B41 E6 IB71 D2
IB23 Bref VPC2 GCP AP1
H3 9B20 B6
VPC3 AP2 3B43 F6 IB72 E2
5B21 2B27 PARX2+ A9 J3 HDMI-COAST H14 B5
3B98 IB71 RX2+A VPC4 CLAMP AP3
AV2-AV4_B-PB PARX2- A10
RX2-A
K3 3B45 B12
2u2 A12 VPC5 L3 H16 A5
470R PARX1+ RX1+A POWERDOWN-1394 PD 3B56-1 B6
10n VPC6 ACLK
2BA7

3B69

1K0

A13 M3 B7
6p8

15p

PARX1- RX1-A WS
VPC7

9B12
PARX0+ A15 N3 M135-CLK M15 3B56-2 B7
2B36

RX0+A VPC8 MCLK

PARX0- A16 P3
RX0-A VPC9 3B56-3 B6
PARXC+ F16 R3 J13
RXC+A VPC10 /OE
PARXC- G16
RXC-A
T3 3B56-4 C7
VPC11 3B60 L15
PARX-DDC-SCL K15 SCL-MM-BUS1 A0 K12
3B99 5B20 IB72 2B31 HSCL A FB45 3B41 3B57-1 C6
AV1-AV5-AV6_B-PB PARX-DDC-SDA K16 D1 DV4-CLK 100R DIS J12
HSDA A VCLK 3B61 SCL
470R 33R SDA-MM-BUS1 3B57-2 C7
E 2u2 10n SDA
E
2BA8

3B70

DV-HREF L16
1K0

C10 D2 3B25 33R

6p8

15p

PBRX2+ RX2+B 100R 3B57-3 C6

HREF
2B37

PBRX2- C9 C1 RES 3B26 33R DV-VREF

RX2-B VREF
PBRX1+ C13
RX1+B C2 RES 3B27 DV-FREF 3B57-4 C7
FREF RES 33R
PBRX1- C12
RX1-B 3B58-1 D6
PBRX0+ C16 IB41
RX0+B
PBRX0- C15 B2 VSYNC-HIRATE 3B58-2 D6
RX0-B CS 3B28
PBRXC+ G14 A2 DV-HREF
RXC+B HS 3B29 33R RES DV-VREF
3B58-3 D6
PBRXC- F14 A1
RXC-B VS
PBRX-DDC-SCL J15 FB40
33R RES 3B58-4 D6
HSCL B
2B28

J16 B1
10n

PBRX-DDC-SDA /VAI IRQ-HIRATE 3B59-1 C6

HSDA B
DE A3 10K
3B371K0 IB06 D15
RRXB PL
A4 3V3-DIG 3B59-2 C7
IB02 3B38 IB20 D16 RRXA 3B43 3B59-3 C6
F 1K0 F 3B59-4 C7
2B22

2B25
10n

10n

3B60 E9
3B34

39R

3B61 E10
IB01 3B62-1 C6
IB00
3B62-2 C7
3B62-3 C6
3B30

3B32
39R

39R

3B62-4 D7
3B65 B2
3B66 C2
3B67 C2
G G 3B68 D2
3B69 D2
3B70 E2
3B94 B1
3B95 C1
3B96 C1
3B97 D1
F_15400_042.eps
8204 000 8429.6 260405
3B98 D1

1 2 3 4 5 6 7 8 9 10 11 12 13
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 68

SSB: HDMI: Supply

1 2 3 4 5 6 7 8 9
2B38 F5

B7C HDMI: SUPPLY B7C 2B39 F6

2B40 A3
2B41 A3
HDMI SUPPLY 7B11-3 2B42 A4
TDA9975
2B49 C3
M5 2B51 C3
A HDMI SUPPLY PART N5 A
N7 P5
2B52 A2
5B17 FB57 3V3-APLL VDDAPLL
+3V3 3V3-APLL 3V3-AVI 1V8-PLL M7
VDD18APLL
R5 2B53 C4
T5
M11 M8
2B62 D3

2B52

2B40

2B41

2B42
100n

100n

100n

100n
N11 VDDR N8 2B64 D4
P6
M10 P7
2B67 B1
N10 VDDG P8 2B69 C2
P9
M9 GNDAVI R10
2B77 F4
3V3-AVI
5B10 FB50 N9 VDDB R11 2B79 C5
+3V3-AV 3V3-AVI M12
P10 P12
2B80 C5
B VDDBIAS B
P13 2B81 C5
47u 4V
2B67

P11 P14
VDDSOG
P15
2B89 E1
N12
VDDFRO
R15 2B90 F2
T15
N13
2B92 F4
3V3-PLL VDDPLL
1V8-PLL N14
VDD18PLL
M6 3B48 F1
GNDAPLL N6
5B11 FB51 +1V8 3B49 F1
+3V3 3V3-PLL 3V3-DIG E12
VDD18HDMI
+1V8
E13
VDD18RRX
A8 3B50 E2

2B79

100n
B8
3B51 E2
2B69

2B49

2B51

2B53
100n

100n

100n

100n
C8
D8
VDDRX2A
B9 3B52 D1
D9 B10
C D10
VDDRX2B
B11 C 3B53 D2
VDDRX1A
3V3-DIG
D11
VDDRX1B
GNDHDMI B12 3B54 D2
D12 B13
+1V8
D13
VDDRX0A
B14
3B55 D2
5B12 FB52 VDDRX0B
+3V3 3V3-DIG 3V3-DIG
D14
VDDRXC
B15 5B10 B1

2B80

2B81
100n

100n
B16
5B11 C1
2B62

2B64
100n

100n
+1V8
G13 1 E7 5B12 C1
E6 VDD18CORE E8
2
E9
5B17 A1
GNDCORE
IB45 E10 5B18 E3
+3V3 T4 E11
OTP7V 7B11-3 A8
F13
VDDIN 7B12 E1
D F12 D
GNDI2C 7B13 E2
3B52

3B53

3B54

3B55

7B38 F5
33R

33R

33R
1K0

D4
VDDQ0 C7
E4
F4
VDDQ1 D6 9B38 E5
VDDQ3 D7
3V3-DIG G4
VDDQ4 FB48 E6
H4 E5
IB47 VDDQ5 FB50 B2
J4 F5
IB48 VDDQ6 D5
K4
VDDQ7 GNDOUT FB51 C2
7B13 L4 G5
FB55 VDDQ8 FB52 C2
BC817-25 M4 J5
+1V8 VDDQ9 K5 FB55 E4
L5
IB44 H5 FB56 E4
E THERMAL GROUNDS E FB57 A2
3B51
TS431L

4R7

IB44 E2
3

2B89
7B12

10n

RES FB48
+3V3 9B38 IB45 D6
K

NC

F6
G6
H6
J6
K6
L6
F7
G7
H7
J7
K7
L7
F8
G8
H8
J8
K8
L8
F9
G9
H9
J9
K9
L9
F10
G10
H10
J10
K10
L10
F11
G11
H11
J11
K11
L11
IB49 3B50 5B18 FB56 IB47 D2
4 1V3
REF

1V8-PLL
470R IB48 E1
47u 4V
NC

2B90
A

7B38
IB49 E2
3B48

3B49

2B92

2B77
100n

100n

LD1117DT33
1K0

47K
5

3 2 +3V3-AV
+5V IN OUT
COM 330u 6.3V
2B38

2B39
1u0

F F
1

F_15400_043.eps
8204 000 8429.6 260405
1 2 3 4 5 6 7 8 9
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 69

SSB: USB2.0: Host

1 2 3 4 5 6 7 8 9 10
1N00 G8

B8 USB 2.0: HOST B8

1N62 F1
2N00 G9
2N01 G9
2N02 B6
+3V3 2N03 A6

+3V3
2N04 A6
A A 2N05 A6
2N06 A7

5N02
2N07 A7

2N03

2N04

2N05

2N06

2N07

2N08

2N09

2N10

2N11
100n

100n

100n

100n

100n

100n

100n

100n

100n
+5V2-STBY 2N08 A7
2N09 A7
2N10 A8
2N11 A8
2N12 B8

3N30

150R
3N31

150R
3N32

150R
+3V3 IN11
2N13 B8
B B

2N13
3N08 G6

1n0
2N02

5N01
100n
3N09 D5
IN13
3N12 E5
+3V3-STANDBY-B-TRANS 7N10 IN10 2N12
BC847B 3N13 E5
3N33
+3V3-STANDBY 1n0 3N14 E5
IN14 4R7 3N15 E5
7N00 3N20 D2

108
115
121

VAUXA_PLL 101
10
17
25
33
41
49
57
65
73
80

85

93
ISP1561BM

5
3N25 D2

VAUX_T1
VAUX_T2
VAUXA_T3
VAUXA_T4
+3V3 VCC VAUX
3N30 B4
C Φ
C 3N31 B4
3N32 B5
1 PCI 4
SEL48M PME 3N33 B5
2 7
3
SCL HOST IRQ1
8
SDA IRQ12 3N90 E2
+3V3
9
ADP_SEL
CONTROLLER A20OUT
11
12 15 3N92 E2
3N25 KBIRQ1 SMI
RESET-USB20 RESET-USB20 13 16 IRQ-USB20 5N00 H7
MUIRQ12 INTA
PCI-CLK-USB20 18 22 IN02 PCI-REQ
4K7 RST REQ 5N01 B8
19 72
3N20 CLK C0
PCI-GNT PCI-GNT IN01 20 PCI-CBE0 5N02 A8
GNT BE0
4K7 PCI-AD22 3N09 IN04 35 60 PCI-CBE1
IDSEL C1 7N00 C6
PCI-FRAME 100R 48 BE1
FRAME
PCI-IRDY 50 47 PCI-CBE2 7N10 B4
D PCI-TRDY 51
52
IRDY
TRDY
C2
BE2
34
D FN01 G8
PCI-DEVSEL DEVSEL C3 PCI-CBE3
PCI-STOP 54 BE3 FN10 F2
STOP
55 84 PCI-AD0
CLKRUN 0 FN11 G2
PCI-PERR 56 82 PCI-AD1
PERR 1
PCI-PAR 59 81 PCI-AD2 IN01 D6
PAR 2
107 79 PCI-AD3
3N90 RREF 3 IN02 D9
USB20-OC1 USB20-OC1 IN07 89 78 PCI-AD4
OC1 4
USB20-PWE1 IN12 90 77 PCI-AD5 IN03 E5
4K7 PWE 5
USB20-DM1 102 75 PCI-AD6
DM1 6 IN04 D5
USB20-DP1 103 74 PCI-AD7
DP1 7
91 71 PCI-AD8 IN05 F6
GL1 8
92 70 PCI-AD9
AMB1 9 IN06 G7
95 68 PCI-AD10
E 3N92
USB20-OC2 USB20-OC2 IN08 96
97
GRN1
OC2
10
11
67
66
PCI-AD11 E IN07 E4
4K7 PWE2 12 PCI-AD12
IN09 109 64 PCI-AD13
IN08 E4
DM2 13
IN03 110 63 PCI-AD14 IN09 E5
DP2 14
98 62 PCI-AD15
GL2 15 IN10 B8
99 AD 46 PCI-AD16
AMB2 16
3N13

3N12

3N14

3N15
100 44 PCI-AD17 IN11 B8
GRN2 17
105 43 PCI-AD18
OC3 18 IN12 E5
15K

15K

15K

15K
106 42 PCI-AD19
PWE3 19
116 40 PCI-AD20 IN13 B4
DM3 20
117 39 PCI-AD21
DP3 21 IN14 C4
112 38 PCI-AD22
GL3 22
113 36 PCI-AD23
AMB3 23
114 32 PCI-AD24
F 119
120
GRN3
OC4
24
25
31
30
PCI-AD25 F
PWE4 26 PCI-AD26
122 28 PCI-AD27
DM4 27
IN05

123 27 PCI-AD28
DP4 28
1N62 125 26 PCI-AD29
GL4 29
TO 1M64 1 FN10
USB20-DM1
126
127
AMB4 30
24
23
PCI-AD30
PCI-AD31
2 GRN4 31
3N08

USB20-DP1 58 PCI-SERR
12K

3 SERR
FN11 87
4 XI 2N00
5 6 88
XO
SSB

94 AGND_REF
33p

AGND_T1
AGND_T2
AGND_T3
AGND_T4
B4B-PH-SM4-TBT(LF)

1N00

12M
G DGND
G

FN01
2N01
6
14
21
29
37
45
53
61
69
76
83
86
128

104
111
118
124
33p

IN06
5N00

H H

F_15400_044.eps
8204 000 8431.3 260405

1 2 3 4 5 6 7 8 9 10
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 70

SSB: Ethernet (Optional)

1O00 C8 2O02 H4 2O06 D12 2O12 G10 2O16 C8 2O20 G11 2O24 G11 2O28 G10 3O03 C7 3O07 D1 3O11 D8 3O21 A8 3O25 C9 5O00 G9 7O00-1 B3 FO01 A10 FO05 C10 FO12 H9 IO04 G10 IO08 A12 IO13 F7
1O10 A10 2O03 H3 2O07 D11 2O13 B9 2O17 H9 2O21 G11 2O25 G10 3O00 C8 3O04 E8 3O08 E1 3O12 D9 3O22 A9 3O26 C9 5O01 H9 7O00-2 H7 FO02 B10 FO06 F9 IO01 E7 IO05 A9 IO10 C8 IO14 F8
2O00 D8 2O04 A11 2O10 E3 2O14 B9 2O18 H10 2O22 G11 2O26 G10 3O01 C7 3O05 F8 3O09 A11 3O13 D9 3O23 A9 3O27 C9 6O00 F8 9O16 C9 FO03 C10 FO07 F9 IO02 C7 IO06 C9 IO11 F7
2O01 D8 2O05 A12 2O11 G9 2O15 B10 2O19 G12 2O23 G11 2O27 G10 3O02 D3 3O06 F8 3O10 C11 3O14 D9 3O24 A9 3O28 C9 6O01 F8 AO01 C8 FO04 C10 FO08 E3 IO03 H3 IO07 D12 IO12 F7

1 2 3 4 5 6 7 8 9 10 11 12 13 14

B9A ETHERNET (Optional) +3V3-ET-DIG 3O09 IO08

B9A
+3V3-ET-DIG
220R
2O04 2O05

A 1n0 1n0
A
+3V3-ET-ANA
FO01

11

12
IO05 1O10
3O21 3O22 3O23 3O24 5-1605403-8

SH1
D1

D2
27R 27R 27R 27R

2O13

100n
1 RDP RJ-1
FO02

39

47

69

80

94

107

117

21

27

33

56

58

137
2 RDN RJ-2
2O15
3 RCT RJ-3
B 7O00-1
DP83816AVNG
+3V3-ET-ANA
2O14 100n 100n RJ-45
B
IAUXVDD PCIVDD AUXVDD
59 MacPhyter II
PMEM
10/100 Mb/s 54 ETHERNET
CLKRUN TPTDP
123 53 4 TCT RJ-4
CONNECTOR
PWRGOOD TPTDM

3O25

3O26
100R

100R
122 46 FO03 5 TDP RJ-5
3VAUX TPRDP

IRQ-ETHERNET 61 45 IO06 6 TDN RJ-6

INTA TPRDM 2O16 FO04
IO10 9O16
PCI-CLK-ETHERNET 60
PCICLK X1
17
100n
7 NC RJ-7
3O01 AO01 FO05

3O27

3O28
100R

100R
99 18 8 C1 RJ-8

SH2
C PCI-PAR PAR X2
C

D3

D4
470R
PCI-IRDY 92 40
IRDY VREF

10

13

14
IO02 3O00
PCI-TRDY 93 28
TRDY COL

3O03
10K
1M0 3O10
PCI-PERR 97 29 +3V3-ET-DIG
PERR CRS
1O00 270R
PCI-SERR 98 5
SERR MDC 2O07 2O06

PCI-FRAME 91 4 DSX840GA
FRAME MDIO 1n0 IO07 1n0
25M
PCI-GNT-A 63 6
3O07 GNT RXCLK
PCI-GNT-A
+3V3-ET-DIG

22p
96 31
D PCI-STOP
D

3O11

3O12

3O13

3O14
10K STOP TXCLK

2O01
22p
3O02 76 13
PCI-AD23

V
IDSEL RXOE

2O00
100R
PCI-DEVSEL 95 30
DEVSEL TXE

PCI-REQ-A 64 REQ 129

MCS
3O08 62 130
+3V3-ET-DIG RESET-ETHERNET RESET-ETHERNET RST MRD
10K 2O10 FO08
48 REGE 131
+3V3-ET-ANA MWR
1u0
128
EESEL
PCI-CBE0 111
0
100
E PCI-CBE1
PCI-CBE2 89
1
2 CMD/ BE 0
132 IO01 3O04
E
PCI-CBE3 75 133
3 CFGDIS
134
1K0
PCI-AD0 121 135
0
PCI-AD1 120 138
EEDO
PCI-AD2 119 139
PCI-AD3 118 MD<0:7> 140
PCI-AD4 116 141
7 IO11 3O05 FO06
PCI-AD5 115
PCI-AD6 113 270R
PCI-AD7 112 142
LEDACT IO12 6O00
PCI-AD8 110 143
LED10LNK
PCI-AD9 109 144
LED100LNK BAS316
108 1
F PCI-AD10
PCI-AD11 106
EEDI
EECLK
2
IO13 6O01 3O06 FO07
F
PCI-AD12 105 3 IO14 220R
MA5 BAS316
PCI-AD13 104 7
0
PCI-AD14 102 10
1
PCI-AD15 101 RXD 11
AD<0:31> 2
PCI-AD16 88 12
DATA 3
PCI-AD17 87 14
RXER
PCI-AD18 86 15
RXDV
PCI-AD19 83 22
0
PCI-AD20 82 23
1
PCI-AD21 81 TXD 24
2
PCI-AD22 79 25
3
PCI-AD23 78 5O00 IO04
74
G PCI-AD24
PCI-AD25 73
MA<0:15> +3V3 +3V3-ET-DIG
G

100n

100n
100n

100n

100n
2O28 100n

2O27 100n

2O26 100n

2O25 100n

2O24 100n
4u7 6.3V
PCI-AD26 72 41

2O11

2O12
100n
PCI-AD27 71
PCI-AD28 70 50

2O20

2O19
2O23

2O22

2O21
RESERVED
PCI-AD29 68
PCI-AD30 67 127
PCI-AD31 66
31

VSS
C1

5O01 FO12
+3V3 +3V3-ET-ANA
103

114

136

2O17

2O18
19

16

20

26

32

35

38

44

49

51

52

55

57

65

77

90

100n
H IO03 7O00-2
H
8

4u7
DP83816AVNG
34 84
NC1 NC6
36 85
10u 16V

NC2 NC7
2O03

2O02

100n

37 124
NC3 NC8
42 125
NC4 NC9
43 126
NC5 NC10

F_15400_045.eps
8204 000 8435.6 240505

1 2 3 4 5 6 7 8 9 10 11 12 13 14
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 71

SSB: UART SSB: POD: Out of Band

1M15 B6 1O02 C5 2O51 C5 3O16 C2 6O02-2 D4 FO11 C4 1 2 3 4
1O01 B5 2O50 B5 3O15 B3 6O02-1 A4 FO10 B4 2P50 B1
2P51 E1

1 2 3 4 5 6 7
B10B POD: OUT OF BAND B10B
3P50 F3
3P51 F3
3P52 F3
3P53 F4
7P10-1 D2

B9B UART B9B

7P10-2 E2
7P13 C2
POD-A(7) 9P30 QTX_POD-A(7) 9P30 A2
9P31 A2
A POD-A(6) 9P31 ETX_POD-A(6) A 9P32 A2
A A POD-A(5) 9P32 ITX_POD-A(5)
9P33 B2
9P34 B2
6O02-1 9P35 B2
1 2 9P36 B3
+3V3-STANDBY 9P37 B3
9P38 B3
BAV99S

6
MOCLKA 9P33 MOCLKA-POD POD-A(4) 9P36 CTX_POD-A(4)
B B

1O01

2O50

100p
9P34 POD-A(9) 9P37 DRX_POD-A(9)

1M15 9P35 9P38

3O15 FO10 VS2 VS2_MOCLKA-CI POD-A(8) CRX_POD-A(8)
TXD 1
UART B B
3O16 100R FO11 2 SERVICE
RXD 3
100R 5 4
CONNECTOR
+3V3
C C

1O02

2O51

100p
S3B-PH-SM4-TB

2P50
100n
3

BAV99S 7P13

16
74LVC257APW
+3V3-STANDBY PDIR 1
D 4
6O02-2
5
D ADOE 15
G1
EN
C C
2
MUX
POD-A(4) 1
F_15400_046.eps CTX-POD 3 4 CTX_POD-A(4)
1
POD-A(9) 5
8204 000 8435.6 260405 DRX-POD 6 7 DRX_POD-A(9)
POD-A(8) 11
1 2 3 4 5 6 7 CRX-POD 10
14
9 CRX_POD-A(8)

13 12

8
D D
+3V3

7P10-1

20
74LVC244APW
PDIR 1
EN

POD-A(7) 2 18 QTX_POD-A(7)
POD-A(6) 4 16 ETX_POD-A(6)
POD-A(5) 6 14 ITX_POD-A(5)
8 12

10
E E
+3V3

2P51
100n
7P10-2

20
74LVC244APW
PDOE 19
EN
RES 3P50
17 3 QTX-POD
QTX_POD-A(7) 15 5 33R
ETX_POD-A(6) 13 7
RES 3P51
ITX_POD-A(5) 11 9 ETX-POD
33R
F F

10
RES 3P52 ITX-POD
33R

3P53
10K
RES

F_15400_048.eps
8204 000 8434.6 090505
1 2 3 4
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 72

SSB: POD: Common Interface

1P01-A B1 0 2P06 A5 2P16 A5 2P23 D1 3P10 D3 3P15 A8 3P20 A8 3P25 E10 3P30 E10 3P40 E2 5P02 A5 7P74 E2 9P08 B7 FP36 D4 IP00 C7 IP06 A6 IP15 E7
1P01-B B9 2P07 A5 2P18 D2 2P24 C4 3P11 A4 3P16 A8 3P21 E9 3P26 E10 3P31 E10 3P43 D3 5P08 A4 9P01 B7 9P09 B7 FP37 D5 IP01 C7 IP07 A5 IP17 E2
2P02 A6 2P09 A4 2P19 C2 2P25 C4 3P12 B4 3P17 A8 3P22 E9 3P27 E10 3P32 C4 3P45 B7 6P00 E3 9P05 B7 9P10 D2 FP38 D5 IP02 D2 IP10 E5 IP18 C4
2P03 A6 2P10 A6 2P20 C1 2P40 E2 3P13 B4 3P18 A8 3P23 E9 3P28 E10 3P33 D6 3P74 D3 7P00 C1 9P06 B7 FP01 C3 FP39 D7 IP03 E3 IP11 E5 IP20 A4
2P04 A6 2P15 A4 2P22 D1 2P41 E3 3P14 B4 3P19 A8 3P24 E9 3P29 E10 3P35 B7 3P75 E3 7P03 A5 9P07 B7 FP02 C3 FP40 D7 IP05 B4 IP14 E7 IP23 E3

1 2 3 4 5 6 7 8 9 10

POD: COMMON INTERFACE +3V3

B10A VCC_EXTO +3V3

VCC_EXTO
B10A

5P02

3P15 10K

3P16 10K

3P17 10K

3P18 10K

3P19 10K

3P20 10K
2P09

5P08
1n0
IP06
VCC_EXTO

RESET-POD-CI
IP07

2P06

2P07

2P10

2P02

2P03

2P04
100n

100n

100n

100n

100n

100n
A A

RDY_IRQA
3P11

2P15

2P16
100n

100n
10K

WAITA

CD1

CD2

VS1

VS2
+3V3
7P03

90
40

13
86
63
38
89
STV0701
IP20 VCC_CORE
Φ VCC_EXT CABLE CARD INTERFACE

3P45

10K
COMMON INTERFACE ROW_B ROW_A
14 HARDWARE 1P01-B 1P01-A
3P14 RESET CONTROLLER
M27-POD IP05 12 6 9P01 JTAG-TCK GND3 GND1
CLK TCK 35 1
100R 17 4 9P06 JTAG-TMS CD1 CD1 D3 POD-D(3)
0 TMS 36 2
18 SA 2 9P07 JTAG-TD-HDMI-POD MDOA(3) D11 D4 POD-D(4)
3P12 1 TDI 37 3
SCL-MM-BUS1 10 5 9P08 JTAG-TRST MDOA(4) D12 D5 POD-D(5)
SCL TRST 38 4
B SDA-MM-BUS1 3P13 100R 16
SDA TDO
3 9P09 MDOA(5) D13
39 5
D6 POD-D(6) B
XIO-SEL2 100R 7 37 MDOA(6) D14 D7 POD-D(7)
CS TEST_MODE 40 6

9P05
XIO-RWn_WEn 8 MDOA(7) D15 CE1 CE1
RD 41 7
CE2 CE2 A10 POD-A(10)
XIO-AS_REn DIR 3P35 22R JTAG-TD-POD-CON 42 8
9 VS1 VS1 OE OE
WR 43 9
58 RSTA IORD IORD A11 POD-A(11)
STR RSTA 44 10
PCI-REQ-B 19 68 CE1 IOWR IOWR A9 DRX_POD-A(9)
WAIT 1 45 11
CE 69 CE2 MISTRTA A17 A8 CRX_POD-A(8)
ACK 2 46 12
IRQ-POD 20 70 REG MDIA(0) A18 A13 POD-A(13)
INT REG 47 13
62 71 OE MDIA(1) A19 A14 MOCLKA-POD
10K EXTCS OE 48 14
64 72 WE MDIA(2) A20 WE|P WE
VCC_EXTO EXTINT WE 49 15
3P32 73 IORD MDIA(3) A21 RDY|BSY RDY_IRQA
IP18 IORD 50 16

2P25
74 VCC2 VCC1

10n
IOWR

2P24
+5V 7P00 IOWR POD-VCC 51 17 POD-VCC
TPS2211AIDB 22 IP00 VPP2 VPP1

10n
VCCEN POD-VPP 52 18 POD-VPP
2P19

100n

C CD1 52
1 VPPEN
21 IP01 VCCEN MDIA(4) A22
53 19
A16 MIVALA C
2P20

100n

POD-VPP CD2 53 CD 66 VPPEN MDIA(5) A23 A15 MICLKA

FP01 2 DATOE 54 20
9 10 VS1 54 67 DATOE MDIA(6) A24 A12 POD-A(12)
VPPI VPP 1 DATDIR 55 21 QTX_POD-A(7)
VS2 55 VS 23 DATDIR MDIA(7) A25 A7
RDY_IRQA 2 PDOE 56 22 ETX_POD-A(6)
+3V3 57 24 PDOE VS2_MOCLKA-CI VS2 A6
RDY PDDIR 57 23
3 POD-VCC 59 PDIR RSTA RESET A5 ITX_POD-A(5)
FP02 IRQA ADOE 58 24
11 WAITA 56 60 ADOE WAITA WAIT A4 CTX_POD-A(4)
3V3 VCC_EXTO WAITA ADLE 59 25
2P22

100n

4 ADLE INPACK A3 POD-A(3)

60 26
2P18

100n

12 REG REG A2 POD-A(2)

VCC 3P33 100K 61 27
5 MOVALA BVD2|SPKR A1 POD-A(1)
FP36 FP39 62 28
+5V 13 FE-CLK 35 41 POD-CLK MOSTRTA BVD1|STSCHG A0 POD-A(0)
5V MICLK MOCLK 63 29
3P43

6 FE-SOP FP37 34 42 FP40 D8 D0

10K

MISTRT MOSTRT POD-SOP MDOA(0) 64 30 POD-D(0)

FE-VALID FP38 33 43 POD-VALID MDOA(1) D9 D1 POD-D(1)
MIVAL MOVAL 65 31
100n
2P23

FE-DATA0 32 44 POD-DATA0 MDOA(2) D10 D2 POD-D(2)

66 32
D VCCD0_
1 VCCEN FE-DATA1 31 45 POD-DATA1 CD2 CD2
67 33
WP|IOIS16 D
CISEL-3V3 FE-DATA2 30 46 POD-DATA2 GND4 GND2
68 34
2 9P10 FE-DATA3 29 47 POD-DATA3 72
VCCD1_ 71
FE-DATA4 28 MDI<0:7> MDO<0:7> 48 POD-DATA4 ICME68H-D1121NS
3P10
15 FE-DATA5 27 49 POD-DATA5 ICME68H-D1121NS
VPPD0
IP02 FE-DATA6 26 50 POD-DATA6
3P74 10K
14 VCC_EXTO FE-DATA7 25 51 POD-DATA7
VPPD1
IP17 4K7 VCC_EXTO IP14
SHDN_

8 VPPEN MICLKA IP10 91 85 MOCLKA

OC_ MICLKA MOCLKA

MOCLKA

MOSTRTA

MOVALA

MDOA(0)

MDOA(1)

MDOA(2)

MDOA(3)

MDOA(4)

MDOA(5)

MDOA(6)

MDOA(7)
GND

0P01 IP03 MISTRTA IP11 92 84 IP15 MOSTRTA

7P74 3P75 MISTRTA MOSTRTA
EMC HOLE MIVALA 93 83 MOVALA
PMST3904 MIVALA MIVALA
47K MDIA(0) 94 82 MDOA(0)
16

MDIA(1) 95 81 MDOA(1)
7

MDIA(2) 96 80 MDOA(2)
E MDIA(3) 97 79 MDOA(3) E

3P21 10K

3P22 10K

3P23 10K

3P24 10K

3P25 10K

3P26 10K

3P27 10K

3P28 10K

3P29 10K

3P30 10K

3P31 10K
IP23 MDIA(4) 98 MDIA<0:7> MDOA<0:7> 78 MDOA(4)
3P40 6P00
SUPPLY-FAULT MDIA(5) 99 77 MDOA(5)
220R MDIA(6) 100 76 MDOA(6)
BAS316
MDIA(7) 1 75 MDOA(7)
2P40

2P41
100n

100n

GND_CORE GND_EXT
15

65

11
88
61
36
39
87

F_15400_047.eps
8204 000 8434.6 260405
1 2 3 4 5 6 7 8 9 10
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 73

SSB: POD: Buffering

1 2 3 4 5 6 7 8 9
2P31 A3
2P32 C3
POD: BUFFERING
B10C B10C
2P33 E7
2P76 A7
2P77 C7
+3V3
3P60-1 B4
+3V3 3P60-2 C3
3P60-3 C4
A 3P76 A 3P60-4 C3

3P78

10K
+3V3 1K0 3P61-1 B4
7P76
IP21 3P61-2 B3

20
74LVC245A

2P76

100n
3P61-3 B4
1
3EN1 3P61-4 B3
FP31 3EN2 3P62-1 D3

2P31

100n
SEL-POD 19
G3
3P62-2 D4
POD-DATA0 2 18 DV1F-DATA0 3P62-3 D3
1
7P31 3P62-4 D4
74LVC573APW 2
POD-DATA1 3 17 DV1F-DATA1
3P63-1 E4

20
POD-DATA2 4 16 DV1F-DATA2
3P61-1 3P63-2 E3
ADOE 1 1 8 POD-A(0) POD-DATA3 5 15 DV1F-DATA3
EN
11 POD-DATA4 6 14 3P73 D7
B ADLE C1
2
3P61-2
7
47R
POD-A(1) POD-DATA5 7 13
DV1F-DATA4
DV1F-DATA5 B 3P76 A6
2 19 POD-DATA6 8 12 DV1F-DATA6
1D 3P61-3 3P77 C6
XIO-A0_CLE 3 18 3 6 POD-A(2) POD-DATA7 9 11 DV1F-DATA7
4 17
3P78 A6
3P61-4 3P79 D8

10
XIO-A1_ALE 5 16 4 5 POD-A(3)
6 15 7P31 B2
3P60-1
XIO-A2 7 14 1 8 POD-A(10) 7P32 D2
8 13 +3V3
3P60-2 47R 7P34 E6
XIO-A3 9 12 2 7 POD-A(11)
3P77 7P76 A7
3P60-3 7P77 C7
10

XIO-A10 3 6 POD-A(12) 1K0

IP22
7P77 9P79 C7
3P60-4

20
74LVC245A

2P77

100n
XIO-A11 4 5 POD-A(13) FP31 A6
1
C XIO-A12
3EN1
3EN2
C IP21 A6
IP22 C6
SEL-POD 19
G3
XIO-A13
+3V3 POD-SOP 2 18 DV1F-DATA9_SOP
1
2
3 17
2P32

100n

POD-CLK 4 16 9P79 DV1F-CLK

POD-VALID 5 15 DV1F-VALID
6 14
7 13

180R

270R
3P73

3P79
7P32 8 12
20

74LVC573APW 9 11
ADOE 1
EN

10
11
D ADLE C1
4
3P62-4
5 POD-A(4) D
XIO-A4 2 19 47R
1D 3P62-3
XIO-A8 3 18 3 6 POD-A(8) +3V3
XIO-A9 4 17 +3V3
3P62-2
XIO-A7 5 16 2 7 POD-A(9)
XIO-A6 6 15
3P62-1
XIO-A5 7 14 1 8 POD-A(7)

2P33

100n
8 13
3P63-1
9 12 1 8 POD-A(6)
3P63-2 47R
10

2 7 POD-A(5)
7P34

20
74LVC245A
1
E 3EN1
3EN2
DATDIR
E
19 DATOE
G3

PCI-AD24 18 2 POD-D(0)
1
2
PCI-AD25 17 3 POD-D(1)
PCI-AD26 16 4 POD-D(2)
PCI-AD27 15 5 POD-D(3)
PCI-AD28 14 6 POD-D(4)
PCI-AD29 13 7 POD-D(5)
PCI-AD30 12 8 POD-D(6)
PCI-AD31 11 9 POD-D(7)

F 10
F

F_15400_049.eps
8204 000 8434.6 260405

1 2 3 4 5 6 7 8 9
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 74

SSB: POD: TS Buffering

1 2 3 4 5 6 7 8 9 10 1P02 B6
2P34 B4

B10D POD: TS BUFFERING B10D 2P35 C4

2P80 C8
+3V3-STANDBY 2P81 C8
9P41 9P42 RES 2P82 C6
A A 3P36 A3

3P36

3P37

100K
3P37 A4

10K
3P38
3P38 A2
RESET-MAIN-NVM BC857BW
10K
7P18 3P57 F3
+3V3-STANDBY 3P80 B9
2P34
+3V3-STANDBY 3P81 C9
100n
7P14 3P82 F8

9P16
M24C64

8
Φ 3P83 D2
B (8Kx8) 7 RES
+3V3 B 3P84 D2
WC FP22
EEPROM 1P02
1 6
FP34
SCL-UP-VIP SCL-UP-VIP 9P39
RES 3P80
XIO-SEL0
3P85 D2
0 SCL 1
2
3
1 ADR
5
FP35
9P40
RES 2
FOR FACTORY USE 10K 3P86 E2
SDA-UP-VIP SDA-UP-VIP
2 SDA 3
5 4 3P88 E2

4
+3V3 3P81
7P14 B3

9P17
B3B-PH-SM4-TBT(LF) XIO-ACK
2K2 7P15-1 C3
+3V3
MAIN NVM 2P80 2P81
2P82 7P15-2 D3
100n 100n
7P81 100n 7P15-3 E3

20
74LVC245A
C RXD 9P18
RES
RXD-VIPER XIO-AS_REn 1 7P80
C 7P15-4 E3
3EN1

12

37
TC58DVM92F1TGI0
RES 3EN2
TXD 9P19 TXD-VIPER XIO-SEL0 19
G3
VCC
Φ VCCQ 7P16 F2
+5V2-STBY PCI-AD31 2 18 EEPROM 7P17 F3
2P35 1
26 (32Mx16)
7P15-1 PCI-AD30 3
2
17 28
0
8 XIO-AS_REn
7P18 A3
100n 1 RE
14

74HC4066PW PCI-AD27 4 16 30 9 XIO-SEL0

3P83
1 5 15 32
2 CE
16
7P80 C8
RXD 1 PCI-AD26 3 CLE XIO-A0_CLE
FP23 3P84 100R 1 2 RXD-UP PCI-AD24 6 14 40
4 ALE
17 XIO-A1_ALE 7P81 C5
13 PCI-AD25 7 13 42 18 XIO-RWn_WEn
X1 5 WE
100R PCI-AD29 8 12 44
6 WP
19 IP16 STBY-WP-NAND-FLASH 9P16 B4
7

PCI-AD28 9 11 46
7 9P17 C4
XIO-A16_D8 27 I/O 7 XIO-ACK
D 8 RY D

10
XIO-A17_D9 29
7P15-2 XIO-A18_D10 31
9 BY 9P18 C2
10
14

74HC4066PW XIO-A19_D11 33
4 41
11
1
9P19 C2
1 XIO-A20_D12 12
3P85 1 3 RXD-VIPER XIO-A21_D13 43
13
2 9P39 B6
UART-SWITCHn 5 XIO-A22_D14 45 3
X1 14
100R XIO-A23_D15 47
15
4 9P40 B6
7

5
3P86 23 10 9P41 A3
TXD 24 NC 11
7P15-3 34 14 9P42 A4
100R
14

74HC4066PW 35 15
+5V2-STBY
8 36
NC
20
FP22 B4
1
E 1 9 TXD-UP 38 21
E FP23 D2
6 39 22
X1
VSS
FP32 E2
3P88

GND
10K

FP33 F2

10K 6

48
25
13
UART-SWITCHn
FP32
7P15-4
FP34 B4
14

74HC4066PW
11
FP35 B4
1
UART-SWITCH 10 IP16 D9

3P82
1 TXD-VIPER
12
FP33 X1
7

7P16
PDTC114EU
F 10K F
3P57

7P17
PDTC114EU

F_15400_050.eps
8204 000 8434.6 260405

1 2 3 4 5 6 7 8 9 10
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 75

SSB: Firewire 1394: Main (Optional)

1 2 3 4 5 6 7 8 9 10 11 12 13 14
1Z05 F12 IZ04 F13

B11A FIREWIRE 1394: MAIN (Optional) B11A

1Z10 C14
1Z11 E14
IZ05 G1
IZ06 G1
1Z55 I7 IZ07 D8
+3V3-VCCD 2Z04 B9 IZ08 B5
5Z02 IZ00

2Z20

2Z21

2Z22

2Z23

2Z24

2Z25

2Z26

2Z27

2Z28
100n

100n

100n

100n

100n

100n

100n

100n

100n
+3V3-VCCA 2Z05 B10 IZ12 F8

12

18

24

35

44

54

61

70

78

84

90

95

107

113

120

132

138
7Z00
PDI1394L41BE 2Z06 B10 IZ13 F8
VDD 2Z07 B10 IZ14 F8
108 AV1D0 PHYD0 82 +3V3-VCCD 2Z08 B11 IZ15 F8
DV2A-DATA2_0 PHY-D(0)
2Z09 B11 IZ16 F8
DV2A-DATA3_1 109 AV1D1 PHYD1 81 PHY-D(1) IZ01
A 5Z00 A 2Z16 F12 IZ18 F2
+3V3 +3V3-VCCD
DV2A-DATA4_2 110 AV1D2 PHYD2 80 PHY-D(2) 2Z17 F13 IZ19 C2

TRANSMITTER AND RECEIVER

10u 16V
2Z18 G12 IZ20 H1

2Z38
DV2A-DATA5_3 111 AV1D3 PHYD3 79 PHY-D(3)
+3V3
2Z19 G12 IZ21 E1
DV2A-DATA6_4 114 AV1D4 PHYD4 76 PHY-D(4)
2Z20 A5 IZ22 F1
DV2A-DATA7_5 115 AV1D5 PHYD5 75 PHY-D(5) IZ02 2Z21 A6 IZ25 H1
2Z22 A6 IZ26 C6

3Z11

3Z10
116 AV1D6 PHYD6 74

10K

10K
DV2A-DATA8_6 PHY-D(6)
270R

5Z01 2Z23 A6 IZ27 C6

9KB BUFFER

2Z09
3Z47

100n
DV2A-DATA9_7 117 AV1D7 PHYD7 73 PHY-D(7)
MEMORY 2Z24 A6 IZ28 C7
DV2A-CLK DV2A-CLK 9Z47 99 AV1CLK LINK PHYCTL0 86 2Z25 A7
CORE +3V3-VCCD +3V3-VCCA 2Z26 A7
B
100 AV1FSYNC ISOCH & ASYNC PHYCTL1 85
B
180R

3Z48 2Z27 A7
DV2A-VALID 102 AV1VALID PACKETS LREQ 87
2Z28 A7
FZ04 3Z07
101 AV1SY SCLK 88 2Z29 H13
33R 2Z30 H13

2Z04

2Z05

2Z06

2Z07

2Z08
100n

100n

100n

100n

100n
DV2A-DATA0_SOP 103 AV1SYNC LPS 91
IZ08 3Z08 FIREWIRE 2Z38 A10
98 AV1ENDPCK CYCLEIN 56 +3V3-VCCD 3Z00 H1
10K CONNECTOR 1

AV1 LAYER
DV2A-DATA1_ERR 96 AV1ERR0 CYCLEOUT 57
FZ01 3Z01 H1
1Z10
97 AV1ERR1 CLK50 55 1 5Z05 2 FZ05 3Z07 B6
FZ02 1
IZ26
+3V3-VCCD
2
3Z08 C6
104 AV1EMI0 1394MODE 47 4 3 FZ06
C IZ27
3 C 3Z10 B7
DLW31S 5Z06 4
2 FZ07

25

26

61

62

30

31

42

51

52

56
105 AV1EMI1 PD 48 7Z01 1 5 7 3Z11 B7
PDI1394P23 6
+3V3-VCCD 3Z12 IZ19 IZ28 8 3Z12 C2
3 FZ08

DVDD1

DVDD2

DVDD3

DVDD4

AVDD1

AVDD2

AVDD3

AVDD4

AVDD5

PLLVDD
118 AV1READY LINKON 92 LINKON LINKON 4
10K NC1
16 DLW31S 353388-1 3Z13 C8

3Z13
ISON 93 54

10K
133 AV2D0
NC2
55 3Z18 F8
TS-DATA0

3Z55

3Z57
3Z50

3Z56
NC3
3Z20 E12
TS-DATA1 134 AV2D1

V
POWERDOWN-1394 15 LPS RECEIVED CABLE POWER CPS 24 3Z21 E12
TRANSMITTER AND RECEIVER

TS-DATA2 135 AV2D2 CONTROL IZ07

23 ISO_ DATA DETECTOR 3Z22 F12
AND RESET_ 42 RESET-1394 19 C|LKON DECODER/
3Z23 E12
TS-DATA3 136 AV2D3
STATUS TIMER
2 SYSCLK 3Z24 E13
D TS-DATA4 139 AV2D4 REGISTERS 49 1 LREQ LINK D
1 CABLE PORT 0 3Z25 F13
4 CTL0 INTERFACE
TS-DATA5 140 AV2D5
2
50 5 CTL1 I/O 3Z26 F13

3Z60
6 D0 TPA0+ 37

3Z51
PHY-D(0)
141 AV2D6 51 7 D1 TPA0- 36
3Z27 F13
TS-DATA6 PHY-D(1)

3Z58
3

3Z59
PHY-D(2) 8 D2 3Z28 F13
TS-DATA7 142 AV2D7 52 PHY-D(3) 9 D3 ARBITRATION

V
4
10 D4 3Z29 F14
PHY-D(4)

3Z23

3Z24
124 AV2CLK 58 11 D5 3Z30 F2

56R

56R
TS-CLK 5 PHY-D(5) CONTROL
PHY-D(6) 12 D6 1 5Z07 2 FZ09 1Z11
3Z40 125 AV2FSYNC 59 PHY-D(7) 13 D7 STATE TPB0+ 35 3Z33 F8
+3V3-VCCD +3V3-VCCD
ASYNC 6 MACHINE TPB0- 34 4 3
FZ10 1
3Z35 E8
10K TRANSMITTER 2
TS-VALID 127 AV2VALID 72 LOGIC
RESERVED

7 DLW31S 3 3Z37 E8
AND

3Z20

3Z21
56R

56R
E 3Z41 126 AV2SY 71 20 PC0 1 5Z08 2
FZ11 4 E 3Z38 F8
RECEIVER 8 5 7
3Z44

3Z46

21 PC1
10K

10K

6
AV2 LAYER

10K FZ12 8 3Z40 E2

TS-SOP 128 AV2SYNC 65 22 PC2 TPA1+ 46 4 3
10
3Z35 3 CNA TPA1- 45 DLW31S 353388-1 3Z41 E2
123 AV2ENDPCK 66 +3V3-VCCD 10K
CABLE PORT 1 TPB1+ 44
11 FZ03
TPB1- 43
3Z44 E1
IZ21 3Z37
121 AV2ERR0|LTLEND
12
67 FIREWIRE 3Z46 E1
IZ22 12K IZ03
CONNECTOR 2 3Z47 B1

3Z38

3Z25

3Z26

3Z28

3Z29
122 AV2ERR1|DATINV 68

56R

56R

56R

56R
82K
13 +3V3-VCCD IZ13

3Z22

2Z16

270p
3Z48 B1

5K1
129 AV2EMI0 144 3Z18 40 R0
BIAS
IZ04
16
6K8 41 R1 VOLTAGE 3Z50 D14
130 AV2EMI1 62 IZ12 AND 3Z51 D14
TESTPIN1
F +3V3-VCCD 3Z30 IZ18 38 TPBIAS0 CURRENT F 3Z55 D14

3Z33

3Z27

2Z17

270p
143 AV2READY 63 47 TPBIAS1 GENERATOR

10K

5K1
TESTPIN2 CRYSTAL
10K 3Z56 D14
TESTPIN3
64 IZ14 OSCILLATOR, XI 59
3Z57 D14
28 BRIDGE PLL SYSTEM, XO 60

24M576
1Z05
HIFAD0 22 XIO-D0 AND CLOCK 3Z58 D14
IZ15 27 TWOPORT TRANSMIT
HIFAD1 21 XIO-D1 DATA GENERATOR 3Z59 D14
IZ16

2Z18
14 PD ENCODER 3Z60 D14

8p2
33 HIFA0 HIFAD2 20 XIO-D2
5Z00 A10

PLLGND1

PLLGND2
RESET-1394 53 RESET_ 29
TEST0

DGND1

DGND2

DGND3

DGND4

AGND1

AGND2

AGND3

AGND4

AGND5

AGND6

2Z19
32 HIFA1 HIFAD3 19 5Z01 B10

8p2
XIO-A1_ALE XIO-D3

31 HIFA2 HIFAD4 16
5Z02 A10
XIO-A10 XIO-D4
5Z05 C13
G G

17

18

63

64

32

33

39

48

49

50

57

58
XIO-A11 30 HIFA3 HIFAD5 15 XIO-D5
8-BIT 5Z06 C13
XIO-A1_ALE XIO-A12 29 HIFA4 HIFAD6 14 XIO-D6 5Z07 E13
INTERFACE
+3V3-VCCD 7Z02 28 HIFA5 HIFAD7 13 5Z08 E14
XIO-A13 XIO-D7 IZ06 IZ05
74LVC1G86GW
7Z00 A3
+3V3-VCCD +3V3-VCCD XIO-A14 27 HIFA6 HIFD8 10 XIO-D8
7Z01 C9
26 HIFA7 HIFD9 9 7Z02 G1
5

XIO-A15 XIO-D9
2
9Z47 B2

2Z29

1u0
4 25 HIFA8 HIFD10 8 XIO-D10
3Z00

3Z01

1 FZ01 C6
10K

1K0

XIO-SEL1 36 HIFSC_ HIFD11 7 XIO-D11

FZ02 C6
3

H XIO-RWn_WEn 37 HIFWR_ HIFD12 4 XIO-D12

H FZ03 E8
IZ25 XIO-RWn_WEn
38 HIFINT_ HIFD13 3 FZ04 B6
IRQ-IEEE1394 IRQ-IEEE1394 XIO-D13
FZ05 C13
XIO-AS_REN 40 HIFRD_ HIFD14 2 XIO-D14
FZ06 C13
IZ20

2Z30

1u0
45 HIF16BIT HIFD15 1 XIO-D15 FZ07 C13
46 HIFMUX HIFALE 39 FZ08 C13
FZ09 E14
HIFWAIT 41
1Z55 FZ10 E14
GND FOR 1 SCL-DMA-BUS1 FZ11 E14
I FACTORY 2
SDA-DMA-BUS1
I FZ12 E14
106

112

119

131

137

3
11

17

23

34

43

53

60

69

77

83

89

94

IZ00 A10
USE 4 5
5

S3B-PH-SM4-TB IZ01 A10

IZ02 A10
IZ03 F12

F_15400_051.eps
8204 000 8432.5 260405
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 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 76

SSB: Firewire 1394: Buffering (Optional)

1 2 3 4 5 6
2Z50 A2
FIREWIRE 1394: BUFFERING (OPTIONAL)
B11B +3V3 5Z50 +3V3BUFF
+3V3BUFF B11B 2Z51 B3
2Z52 D2
2Z50
3Z53 F2
IZ50 100n 7Z10

20
74LVC245A 3Z54 F2
1 PCI-CBE1
A 3EN1 A 5Z50 A1
3EN2
19 XIO-SEL1
G3 7Z10 A3
PCI-AD28 18 2 XIO-D4 XIO-D4 9Z51 PCI-AD28
1 7Z11 B2
2
PCI-AD29 17 3 XIO-D5 XIO-D5 9Z52 PCI-AD29 7Z12 D3
PCI-AD25 16 4 XIO-D1 XIO-D1 9Z53 PCI-AD25
PCI-AD24 15 5 XIO-D0 XIO-D0 9Z54 PCI-AD24 9Z51 A6
PCI-AD26 14 6 XIO-D2 XIO-D2 9Z55 PCI-AD26
PCI-AD27 13 7 XIO-D3 XIO-D6 9Z65 PCI-AD30 9Z52 A6
PCI-AD30 12 8 XIO-D6 XIO-D3 9Z57 PCI-AD27
PCI-AD31 11 9 XIO-D7 XIO-D7 9Z66 PCI-AD31
9Z53 A6
9Z54 B6

10
B B 9Z55 B6
XIO-SEL0
PCI-CBE2 9Z56 C6
+3V3BUFF
9Z57 B6
2Z51

7Z11
9Z58 C6
100n

20
74LVC245A
1
9Z60 C6
3EN1
3EN2 9Z61 C6
19
G3
9Z62 C6
PCI-AD16 2 18 XIO-A16_D8 XIO-A21_D13 9Z60 PCI-AD21
1 9Z63 C6
C PCI-AD18 3
2
17 XIO-A18_D10 XIO-A19_D11 9Z61 PCI-AD19
C
PCI-AD17 4 16 XIO-A17_D9 XIO-A20_D12 9Z62 PCI-AD20
9Z64 C6
PCI-AD20 5 15 XIO-A20_D12 XIO-A17_D9 9Z63 PCI-AD17
6 14 9Z64
9Z65 B6
PCI-AD19 XIO-A19_D11 XIO-A18_D10 PCI-AD18
PCI-AD21 7 13 XIO-A21_D13 XIO-A22_D14 9Z58 PCI-AD22 9Z66 B6
PCI-AD22 8 12 XIO-A22_D14 XIO-A23_D15 9Z56 PCI-AD23
PCI-AD23 9 11 XIO-A23_D15 XIO-A16_D8 9Z67 PCI-AD16 9Z67 C6
9Z70 E6
10

9Z71 E6
+3V3BUFF 9Z72 E6
D 2Z52 D 9Z73 E6
100n 7Z12 9Z74 E6
20

74LVC245A
1 9Z75 E6
3EN1
3EN2
19 9Z76 E6
G3
18 2 9Z70
9Z77 E6
PCI-AD15 1 XIO-A15 XIO-A15 PCI-AD15
2 IZ50 A2
PCI-AD13 17 3 XIO-A13 XIO-A13 9Z71 PCI-AD13
PCI-AD11 16 4 XIO-A11 XIO-A11 9Z72 PCI-AD11 cZ01 F3
PCI-AD10 15 5 XIO-A10 XIO-A10 9Z73 PCI-AD10
PCI-AD14 14 6 XIO-A14 XIO-A14 9Z74 PCI-AD14 cZ02 F3
PCI-AD12 13 7 XIO-A12 XIO-A12 9Z75 PCI-AD12
E PCI-AD1 12 8 XIO-A1_ALE XIO-A1_ALE 9Z76 PCI-AD1
E cZ03 F3
PCI-AD0 11 9 XIO-A0_CLE XIO-A0_CLE 9Z77 PCI-AD0 cZ04 F3
10

cZ05 F3
cZ06 F3
PCI-AD2 cZ01 XIO-A2 cZ07 F3
PCI-AD3 cZ02 XIO-A3
PCI-AD4 cZ03 XIO-A4
cZ08 F3
PCI-AD5 cZ04 XIO-A5
PCI-AD6 cZ05 XIO-A6
PCI-AD7 cZ06 XIO-A7
PCI-AD8 cZ07 XIO-A8
F PCI-AD9 cZ08 XIO-A9
F
PCI-CBE1 3Z53 100R XIO-RWn_WEn
PCI-CBE2 3Z54 100R XIO-AS_REn

F_15400_052.eps
8204 000 8432.5 310505

1 2 3 4 5 6
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 77

SSB: Miscelaneous
1 2 3 4 5 1TG1 E4 IM13 C5
2M90 B2 IM14 C2

B12 MISCELLANEOUS B12 2M91 C2

2M92 D3
IM15 C2
IM16 C4
+3V3-STANDBY +3V3-STANDBY +3V3-STANDBY
2M93 C4 IM17 D2
2M94 D5
3M00 E1

3M72

3M09
10K

10K
3M70
3M01 E1

2K2
FM10
A 7M03 9M06 RESET-STBY A
NCP303LSN10T1 3
3M02 E2
RES
FM70 2
IN
3M03 E1
1 IM11 1 7M01
3
RST PDTC114EU 3M04 E2
GND
IM12 2 3M05 F2
5 4
CD NC 3M09 A4
3M14 C3
3M71

2M90

100n
1K2
3M70 A1
3M71 B1
+5V2-STBY
3M72 A3
B B 3M73 B1
+5V2-STBY
3M74 B3
3M75 B3
3M76 D2

3M74

3M75

3M82
150R

150R

150R
3M73

470R

3M77 D2

3M80

3M81
150R

150R
3M78 D2

3M79

1K0
IM14
3M79 C4
IM13
3M80 C5
IM15 IM16 3M81 C5
+3V3-STANDBY-B-TRANS 7M04 7M07
C 1V6 BC847B BC847B C 3M82 B3
1V9
3M85 E4

2M93

10n
3M86 E4
6M10 E3

NC
TS431AILT FM71 +1V2-STANDBY
2M91

3M14

4
4R7

REF
7M06
10n

3 1 6M11 F3
1V3

NC
7M01 A4
K

NC

10u 10V
3M78 FM72
4 IM17

2M94
REF

TS431AILT +3V3-STANDBY 7M03 A3

4V

2
7M05 1K0
NC

7M04 C3
A

10u 10V
3M76

3M77

2M92
1K0

1K5

5 2 7M05 D1
7M06 C4
D D
7M07 C5
7M10 E1
+3V3-STANDBY +5V2-STBY 7M11 E1
7M12 E2
IM00 9M00 F1
+3V3 9M01 E5
BAS316

9M02 E5
3M00

3M01

3M02

6M10
10K

10K

10K

9M04 E4
IM01 SCL-DMA-BUS1-ATSC
3M03 9M05 E5
SDA-DMA-BUS1-ATSC
E IM05 IM04 33K IM06
E 9M06 A3
3M04
3M85

3M86

9M04

9M05
4K7

4K7

IM02 FM07 F1
7M10 7M11 18K 7M12
FM10 A3
1TG1
9M01 FM70 A1
1 SDA-DMA-BUS1
2
9M02 SCL-DMA-BUS1 FM71 C5
BC847B BC847B BC847B
3 FM72 D3
+5V
BAS316

FM07 0V 4
3M05

6M11

IM00 D2
1K0

0V3 IM03 5 6
9M00 IM08
RES B4B-PH-SM4-TBT(LF)
IM01 E2
0V3
IM02 E3
FOR FACTORY
F F IM03 F3
USE
IM04 E1
POD-MODE

IM05 E1
ON-MODE

STANDBY

IM06 E1
IM08 F2
IM11 A3
F_15400_053.eps IM12 A2
8204 000 8425.5 260405
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 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 78

SRP Overview SSB

+12VS B1a +5VbM B3c AV1-STATUS B3f DATOE B10a DV3F-DATA8_6 B4b DV-ROUT-3 B6 I2S-MCH-CSW B5c MDOA(4) B10a MP-G1 B6 PBRX2+ B7a
+12VS B1b +5V-CON B1b AV1-STATUS B3g DATOE B10c DV3F-DATA8_6 B5c DV-ROUT-4 B5c I2S-MCH-LR B4a MDOA(5) B10a MP-G2 B6 PBRX2+ B7b
+12VS B4a +5V-CON B5e AV1-STATUS B4e DEBUG-BREAK B4e DV3F-DATA9_7 B4b DV-ROUT-4 B6 I2S-MCH-LR B5c MDOA(6) B10a MP-G3 B6 PBRXC- B7a
+12VSW B1a +5VDISP B4g AV1-STATUS-AV7-C B3f DEBUG-BREAK B5a DV3F-DATA9_7 B5c DV-ROUT-5 B5c I2S-MCH-SLR B4a MDOA(7) B10a MP-G4 B6 PBRXC- B7b
+12VSW B1b +5VDISP B5e AV2_C B3a DETECT-12V B4e DV3F-VALID B4b DV-ROUT-5 B6 I2S-MCH-SLR B5c MICLKA B10a MP-G5 B6 PBRXC+ B7a
+12VSW B2a +5VMPIF-MAIN B3a AV2_C B3f DETECT-1V2 B4e DV3F-VALID B5c DV-ROUT-6 B5c I2S-SUB-D B4a MISTRTA B10a MP-G6 B6 PBRXC+ B7b
+12VSW B3e +5VMPIF-MAIN B3b AV2_FBL B3f DETECT-3V3 B4e DV4-CLK B4b DV-ROUT-6 B6 I2S-SUB-D B5c MIVALA B10a MP-G7 B6 PBRX-DDC-SCL B7a
+12VSW B4e +5VMPIF-MAIN B3c AV2_FBL B4a DETECT-5V B4e DV4-CLK B7b DV-ROUT-7 B5c I2S-SUB-ND B4a MM_A0 B5b MP-G8 B6 PBRX-DDC-SCL B7b
+12VSW B4g +5V-OOB B2b AV2_Y-CVBS B3a DETECT-8V6 B4e DV4-DATA0_SOP B4b DV-ROUT-7 B6 I2S-SUB-ND B5c MM_A1 B5b MP-G9 B6 PBRX-DDC-SDA B7a
+12VSW B5e +5VTUN B2b AV2_Y-CVBS B3f DIN B6 DV4-DATA0_SOP B7b DV-ROUT-8 B5c I2S-WS-AVIP B4a MM_A10 B5b MP-GOUT-0 B4b PBRX-DDC-SDA B7b
+1V2 B1a +8V6 B1b AV2-AV4_B-PB B3a DRX_POD-A(9) B10a DV4-DATA1_ERR B4b DV-ROUT-8 B6 I2S-WS-AVIP B5c MM_A11 B5b MP-GOUT-0 B6 PCI-AD0 B11b
+1V2 B2a +8V6-CONN B3f AV2-AV4_B-PB B3f DRX_POD-A(9) B10b DV4-DATA1_ERR B7b DV-ROUT-9 B5c I2S-WS-MAIN B4a MM_A12 B5b MP-GOUT-1 B4b PCI-AD0 B5a
+1V2 B4e +8V6-SW B1b AV2-AV4_B-PB B7b DRX-POD B10b DV4-DATA2_0 B4b DV-ROUT-9 B6 I2S-WS-MAIN B5c MM_A2 B5b MP-GOUT-1 B6 PCI-AD0 B8
+1V2 B5d +8V6-SW B2b AV2-AV4_G-Y B3a DRX-POD B2a DV4-DATA2_0 B7b DV-VREF B4b I2S-WS-SUB B4a MM_A3 B5b MP-GOUT-2 B4b PCI-AD0 B9a
+1V2_ATSC B2a +8V6-SW B3b AV2-AV4_G-Y B3f DSNDL1 B3d DV4-DATA3_1 B4b DV-VREF B7b I2S-WS-SUB B5c MM_A4 B5b MP-GOUT-2 B6 PCI-AD1 B11b
+1V2M B6 +8V6-SW B3e AV2-AV4_G-Y B7b DSNDL1 B4a DV4-DATA3_1 B7b EA B4e IF-TER2 B2b MM_A5 B5b MP-GOUT-3 B4b PCI-AD1 B5a
+1V2-MAIN B2a +8V6-SW B3f AV2-AV4_R-PR B3a DSNDL2 B3d DV4-DATA4_2 B4b EJTAG-DETECT B1c IF-TER2 B3c MM_A6 B5b MP-GOUT-3 B6 PCI-AD1 B8
+1V2-STANDBY B12 +8V6-SW B3g AV2-AV4_R-PR B3f DSNDL2 B4a DV4-DATA4_2 B7b EJTAG-DETECT B4e INIT B6 MM_A7 B5b MP-GOUT-4 B4b PCI-AD1 B9a
+1V2-STANDBY B4e +8V6-SW B4e AV2-AV4_R-PR B7b DSNDR1 B3d DV4-DATA5_3 B4b EJTAG-TCK B1c IORD B10a MM_A8 B5b MP-GOUT-4 B6 PCI-AD10 B11b
+1V2-STANDBY B4f +8V6-SW B6 AV2-STATUS B3f DSNDR1 B4a DV4-DATA5_3 B7b EJTAG-TCK B5a IOWR B10a MM_A9 B5b MP-GOUT-5 B4b PCI-AD10 B5a
+1V8 B7c +8VaM B3c AV2-STATUS B4e DSNDR2 B3d DV4-DATA6_4 B4b EJTAG-TDI B1c IRQ-AVIP B4e MM_BA0 B5b MP-GOUT-5 B6 PCI-AD10 B8
+2V5 B1a +8V-AUD B3e AV6_VSYNC B3f DSNDR2 B4a DV4-DATA6_4 B7b EJTAG-TDI B5a IRQ-AVIP B5a MM_BA1 B5b MP-GOUT-6 B4b PCI-AD10 B9a
+2V5 B2a +8VMPIF-MAIN B3b AV6_VSYNC B3g DV1F-CLK B10c DV4-DATA7_5 B4b EJTAG-TDO B1c IRQ-AVIP-SUB B4e MM_CAS B5b MP-GOUT-6 B6 PCI-AD11 B11b
+2V5 B4d +8VMPIF-MAIN B3c AV6_VSYNC B4a DV1F-CLK B4b DV4-DATA7_5 B7b EJTAG-TDO B5a IRQ-AVIP-SUB B5a MM_CKE B5b MP-GOUT-7 B4b PCI-AD11 B5a
+2V5 B5d +VTUN B1b AV6_VSYNC B7b DV1F-CLK B5c DV4-DATA8_6 B4b EJTAG-TMS B1c IRQ-ETHERNET B5a MM_CLK_N B5b MP-GOUT-7 B6 PCI-AD11 B8
+2V5_ATSC B2a 1V8-PLL B7c AV7_C B3a DV1F-DATA0 B10c DV4-DATA8_6 B7b EJTAG-TMS B5a IRQ-ETHERNET B9a MM_CLK_P B5b MP-GOUT-8 B4b PCI-AD11 B9a
+2V5A-FAT-MAIN B2a 2NDSIFEXTM B3c AV7_C B3f DV1F-DATA0 B4b DV4-DATA9_7 B4b ENABLE-1V2 B1a IRQ-FE-MAIN B2a MM_CS0 B5b MP-GOUT-8 B6 PCI-AD12 B11b
+2V5A-FDC-MAIN B2a 3V3-APLL B7c AV7_Y-CVBS B3a DV1F-DATA0 B5c DV4-DATA9_7 B7b ENABLE-1V2 B4e IRQ-FE-MAIN B5a MM_DATA_0 B5b MP-GOUT-9 B4b PCI-AD12 B5a
+2V5A-MAIN B2a 3V3-AVI B7c AV7_Y-CVBS B3f DV1F-DATA1 B10c DV4-VALID B4b ENABLE-3V3 B1a IRQ-HD1 B4e MM_DATA_1 B5b MP-GOUT-9 B6 PCI-AD12 B8
+2V5A-PLL-MAIN B2a 3V3-DIG B7b BACKLIGHT-CNTRL-OUT B5e DV1F-DATA1 B4b DV4-VALID B7b ENABLE-3V3 B4e IRQ-HD1 B5a MM_DATA_10 B5b MP-HS B6 PCI-AD12 B9a
+2V5A-XTAL-MAIN B2a 3V3-DIG B7c BACKLIGHT-CNTRL-OUT B6 DV1F-DATA1 B5c DV5-DATA0_SOP B4b ENABLE-5V B4g IRQ-HD2 B4e MM_DATA_11 B5b MP-OUT-DE B4b PCI-AD13 B11b
+2V5D B1a 3V3-PLL B7c BACKLIGHT-CONTROL B4e DV1F-DATA2 B10c DV5-DATA0_SOP B7b ENABLE-5V B5e IRQ-HD2 B5a MM_DATA_12 B5b MP-OUT-DE B6 PCI-AD13 B5a
+2V5D B5b ADAC1 B3e BACKLIGHT-CONTROL B5c DV1F-DATA2 B4b DV5-DATA1_ERR B4b ETX_POD-A(6) B10a IRQ-HIRATE B4e MM_DATA_13 B5b MP-OUT-FFIELD B4b PCI-AD13 B8
+2V5D-DDR B5b ADAC1 B4a BACKLIGHT-CONTROL B5e DV1F-DATA2 B5c DV5-DATA1_ERR B7b ETX_POD-A(6) B10b IRQ-HIRATE B5a MM_DATA_14 B5b MP-OUT-FFIELD B6 PCI-AD13 B9a
+2V5-DDRPNX B4d ADAC2 B3e BACKLIGHT-CONTROL B6 DV1F-DATA3 B10c DV5-DATA2_0 B4b ETX-POD B10b IRQ-HIRATE B7b MM_DATA_15 B5b MP-OUT-HS B4b PCI-AD14 B11b
+2V5-DDRPNX B4f ADAC2 B4a BIN-5V B7a DV1F-DATA3 B4b DV5-DATA2_0 B7b EW-DRIVE B3b IRQ-IEEE1394 B11a MM_DATA_16 B5b MP-OUT-HS B6 PCI-AD14 B5a
+2V5D-PLL-MAIN B2a ADAC4 B3e BRX0- B7a DV1F-DATA3 B5c DV5-DATA3_1 B4b FAT-ADC-INN-MAIN B2a IRQ-IEEE1394 B5a MM_DATA_17 B5b MP-OUT-VS B4b PCI-AD14 B8
+2V5M B6 ADAC4 B4a BRX0+ B7a DV1F-DATA4 B10c DV5-DATA3_1 B7b FAT-ADC-INN-MAIN B2b IRQ-MAIN B5a MM_DATA_18 B5b MP-OUT-VS B4g PCI-AD14 B9a
+2V5-MAIN B2a ADAC7 B3e BRX1- B7a DV1F-DATA4 B4b DV5-DATA4_2 B4b FAT-ADC-INP-MAIN B2a IRQ-MPIF B3b MM_DATA_19 B5b MP-OUT-VS B5e PCI-AD15 B11b
+2V5-VPR B5c ADAC7 B4a BRX1+ B7a DV1F-DATA4 B5c DV5-DATA4_2 B7b FAT-ADC-INP-MAIN B2b IRQ-MPIF B5a MM_DATA_2 B5b MP-OUT-VS B6 PCI-AD15 B5a
+2V5-VPR B5d ADAC8 B3e BRX2- B7a DV1F-DATA5 B10c DV5-DATA5_3 B4b FAT-IF-AGC-MAIN B2a IRQ-POD B10a MM_DATA_20 B5b MP-R0 B6 PCI-AD15 B8
+3V3 B10a ADAC8 B4a BRX2+ B7a DV1F-DATA5 B4b DV5-DATA5_3 B7b FAT-IF-AGC-MAIN B2b IRQ-POD B4e MM_DATA_21 B5b MP-R1 B6 PCI-AD15 B9a
+3V3 B10b ADLE B10a BRXC- B7a DV1F-DATA5 B5c DV5-DATA6_4 B4b FDC-ADC-INN B2a IRQ-POD B5a MM_DATA_22 B5b MP-R2 B6 PCI-AD16 B11b
+3V3 B10c ADLE B10c BRXC+ B7a DV1F-DATA6 B10c DV5-DATA6_4 B7b FDC-ADC-INN B2b IRQ-SUB B5a MM_DATA_23 B5b MP-R3 B6 PCI-AD16 B5a
+3V3 B10d ADOE B10a BRX-DDC-SCL B7a DV1F-DATA6 B4b DV5-DATA7_5 B4b FDC-ADC-INP B2a IRQ-USB20 B5a MM_DATA_24 B5b MP-R4 B6 PCI-AD16 B8
+3V3 B11a ADOE B10b BRX-DDC-SDA B7a DV1F-DATA6 B5c DV5-DATA7_5 B7b FDC-ADC-INP B2b IRQ-USB20 B8 MM_DATA_25 B5b MP-R5 B6 PCI-AD16 B9a
+3V3 B11b ADOE B10c BRX-HOTPLUG B7a DV1F-DATA7 B10c DV5-DATA8_6 B4b FDC-AGC B2a ITX_POD-A(5) B10a MM_DATA_26 B5b MP-R6 B6 PCI-AD17 B11b
+3V3 B12 AIN-5V B7a CD1 B10a DV1F-DATA7 B4b DV5-DATA8_6 B7b FDC-AGC B2b ITX_POD-A(5) B10b MM_DATA_27 B5b MP-R7 B6 PCI-AD17 B5a
+3V3 B1a ALE B4e CD2 B10a DV1F-DATA7 B5c DV5-DATA9_7 B4b FE-CLK B10a ITX-POD B10b MM_DATA_28 B5b MP-R8 B6 PCI-AD17 B8
+3V3 B1c A-PLOP B3e CE1 B10a DV1F-DATA8_ERR B4b DV5-DATA9_7 B7b FE-CLK B2a JTAG-TCK B10a MM_DATA_29 B5b MP-R9 B6 PCI-AD17 B9a
+3V3 B2a A-PLOP B3g CE2 B10a DV1F-DATA8_ERR B5c DV-BOUT-0 B5c FE-DATA0 B10a JTAG-TCK B4e MM_DATA_3 B5b MP-ROUT-0 B4b PCI-AD18 B11b
+3V3 B3e A-PLOP B4a CISEL-3V3 B10a DV1F-DATA9_SOP B10c DV-BOUT-0 B6 FE-DATA0 B2a JTAG-TCK B5a MM_DATA_30 B5b MP-ROUT-0 B6 PCI-AD18 B5a
+3V3 B4a A-PLOP B5a CLK-MPIF B3b DV1F-DATA9_SOP B4b DV-BOUT-1 B5c FE-DATA1 B10a JTAG-TCK B7b MM_DATA_31 B5b MP-ROUT-1 B4b PCI-AD18 B8
+3V3 B4e ARX0- B7a CLK-MPIF B4a DV1F-DATA9_SOP B5c DV-BOUT-1 B6 FE-DATA1 B2a JTAG-TD-CON-VIPER B5a MM_DATA_4 B5b MP-ROUT-1 B6 PCI-AD18 B9a
+3V3 B4g ARX0+ B7a C-MON-OUT B3f DV1F-VALID B10c DV-BOUT-2 B5c FE-DATA2 B10a JTAG-TD-DVB-HDMI B4e MM_DATA_5 B5b MP-ROUT-2 B4b PCI-AD19 B11b
+3V3 B5a ARX1- B7a C-MON-OUT B5c DV1F-VALID B4b DV-BOUT-2 B6 FE-DATA2 B2a JTAG-TD-DVB-HDMI B7b MM_DATA_6 B5b MP-ROUT-2 B6 PCI-AD19 B5a
+3V3 B5c ARX1+ B7a COM-SND B3g DV1F-VALID B5c DV-BOUT-3 B5c FE-DATA3 B10a JTAG-TD-HDMI-POD B10a MM_DATA_7 B5b MP-ROUT-3 B4b PCI-AD19 B8
+3V3 B5d ARX2- B7a COM-SND B4e DV2A-CLK B11a DV-BOUT-3 B6 FE-DATA3 B2a JTAG-TD-HDMI-POD B7b MM_DATA_8 B5b MP-ROUT-3 B6 PCI-AD19 B9a
+3V3 B5e ARX2+ B7a CRX_POD-A(8) B10a DV2A-CLK B4b DV-BOUT-4 B5c FE-DATA4 B10a JTAG-TD-POD-CON B10a MM_DATA_9 B5b MP-ROUT-4 B4b PCI-AD2 B11b
+3V3 B6 ARXC- B7a CRX_POD-A(8) B10b DV2A-CLK B5c DV-BOUT-4 B6 FE-DATA4 B2a JTAG-TD-POD-CON B5a MM_DQM_0 B5b MP-ROUT-4 B6 PCI-AD2 B5a
+3V3 B7a ARXC+ B7a CRX-POD B10b DV2A-DATA0_SOP B11a DV-BOUT-5 B5c FE-DATA5 B10a JTAG-TD-VIPER-PNX2015 B4e MM_DQM_1 B5b MP-ROUT-5 B4b PCI-AD2 B8
+3V3 B7b ARX-DDC-SCL B7a CRX-POD B2a DV2A-DATA0_SOP B4b DV-BOUT-5 B6 FE-DATA5 B2a JTAG-TD-VIPER-PNX2015 B5a MM_DQM_2 B5b MP-ROUT-5 B6 PCI-AD2 B9a
+3V3 B7c ARX-DDC-SDA B7a CTRL1-MOP B4g DV2A-DATA0_SOP B5c DV-BOUT-6 B5c FE-DATA6 B10a JTAG-TMS B10a MM_DQM_3 B5b MP-ROUT-6 B4b PCI-AD20 B11b
+3V3 B8 ARX-HOTPLUG B7a CTRL1-MOP B6 DV2A-DATA1_ERR B11a DV-BOUT-6 B6 FE-DATA6 B2a JTAG-TMS B4e MM_DQS0 B5b MP-ROUT-6 B6 PCI-AD20 B5a
+3V3 B9a AUDIO-HDPH-L-AP B3e CTRL1-STBY B4e DV2A-DATA1_ERR B4b DV-BOUT-7 B5c FE-DATA7 B10a JTAG-TMS B5a MM_DQS1 B5b MP-ROUT-7 B4b PCI-AD20 B8
+3V3-AV B7c AUDIO-HDPH-L-AP B3f CTRL1-STBY B4g DV2A-DATA1_ERR B5c DV-BOUT-7 B6 FE-DATA7 B2a JTAG-TMS B7b MM_DQS2 B5b MP-ROUT-7 B6 PCI-AD20 B9a
+3V3BUFF B11b AUDIO-HDPH-R-AP B3e CTRL1-STBY B5e DV2A-DATA2_0 B11a DV-BOUT-8 B5c FE-SOP B10a JTAG-TRST B10a MM_DQS3 B5b MP-ROUT-8 B4b PCI-AD21 B11b
+3V3-ET-ANA B9a AUDIO-HDPH-R-AP B3f CTRL1-VIPER B4g DV2A-DATA2_0 B4b DV-BOUT-8 B6 FE-SOP B2a JTAG-TRST B1c MM_RAS B5b MP-ROUT-8 B6 PCI-AD21 B5a
+3V3-ET-DIG B9a AUDIO-IN1-L B3d CTRL1-VIPER B5c DV2A-DATA2_0 B5c DV-BOUT-9 B5c FE-VALID B10a JTAG-TRST B4e MM_WE B5b MP-ROUT-9 B4b PCI-AD21 B8
+3V3M B6 AUDIO-IN1-L B3f CTRL1-VIPER B5e DV2A-DATA3_1 B11a DV-BOUT-9 B6 FE-VALID B2a JTAG-TRST B5a MOCLKA B10a MP-ROUT-9 B6 PCI-AD21 B9a
+3V3-MAIN B2a AUDIO-IN1-R B3d CTRL2-MOP B4g DV2A-DATA3_1 B4b DV-CLKIN B5c FM-TRAP B2a JTAG-TRST B7b MOCLKA B10b MP-VS B6 PCI-AD22 B11b
+3V3-STANDBY B10d AUDIO-IN1-R B3f CTRL2-MOP B6 DV2A-DATA3_1 B5c DV-CLKIN B6 FM-TRAP B2b KEYBOARD B3f MOCLKA-POD B10a OE B10a PCI-AD22 B5a
+3V3-STANDBY B12 AUDIO-IN2-L B3d CTRL2-VIPER B4g DV2A-DATA4_2 B11a DV-FREF B4b FRONT_C B3a KEYBOARD B4e MOCLKA-POD B10b ON-MODE B12 PCI-AD22 B8
+3V3-STANDBY B4e AUDIO-IN2-L B3f CTRL2-VIPER B5c DV2A-DATA4_2 B4b DV-FREF B7b FRONT_C B3f LAMP-ON B4e MOSTRTA B10a ON-MODE B1b PCI-AD22 B9a
+3V3-STANDBY B4g AUDIO-IN2-R B3d CTRL3-MOP B4g DV2A-DATA4_2 B5c DV-GOUT-0 B5c FRONT_Y-CVBS B3a LAMP-ON B6 MOVALA B10a ON-MODE B4e PCI-AD23 B11b
+3V3-STANDBY B8 AUDIO-IN2-R B3f CTRL3-MOP B6 DV2A-DATA5_3 B11a DV-GOUT-0 B6 FRONT_Y-CVBS B3f LED1 B3f MP-B0 B6 ON-MODE B4g PCI-AD23 B5a
+3V3-STANDBY B9b AUDIO-IN5-L B3d CTRL3-STBY B4e DV2A-DATA5_3 B4b DV-GOUT-1 B5c FRONT-DETECT B4e LED1 B4e MP-B1 B6 ON-MODE B6 PCI-AD23 B8
+3V3-STANDBY-B-TRANS B12 AUDIO-IN5-L B3f CTRL3-STBY B4g DV2A-DATA5_3 B5c DV-GOUT-1 B6 FS-OUTN B2a LED1-3V3 B4e MP-B2 B6 P50 B3g PCI-AD23 B9a
+3V3-STANDBY-B-TRANS B8 AUDIO-IN5-R B3d CTRL4-MOP B4g DV2A-DATA6_4 B11a DV-GOUT-2 B5c FS-OUTN B2b LED2 B3g MP-B3 B6 P50 B4e PCI-AD24 B10c
+3V3-UART B1c AUDIO-IN5-R B3f CTRL4-MOP B6 DV2A-DATA6_4 B4b DV-GOUT-2 B6 FS-OUTP B2a LED2 B4e MP-B4 B6 P50-HDMI B4e PCI-AD24 B10d
+3V3-VCCA B11a AUDIO-L B3e CTRL4-STBY B4e DV2A-DATA6_4 B5c DV-GOUT-3 B5c FS-OUTP B2b LED2-3V3 B4e MP-B5 B6 P50-HDMI B7a PCI-AD24 B11b
+3V3-VCCD B11a AUDIO-L B3g CTRL4-STBY B4g DV2A-DATA7_5 B11a DV-GOUT-3 B6 GLINK-IR-OUT B3g LIGHT-ON-OUT B5e MP-B6 B6 PARX0- B7a PCI-AD24 B5a
+5V B10a AUDIO-OUT1-L B3d CTRL4-STBY B5e DV2A-DATA7_5 B4b DV-GOUT-4 B5c GLINK-IR-OUT B5a LIGHT-ON-OUT B6 MP-B7 B6 PARX0- B7b PCI-AD24 B8
+5V B12 AUDIO-OUT1-L B3f CTRL4-VIPER B4g DV2A-DATA7_5 B5c DV-GOUT-4 B6 GLINK-IR-OUT-VIP B5a LIGHT-SENSOR B3g MP-B8 B6 PARX0+ B7a PCI-AD24 B9a
+5V B1a AUDIO-OUT1-R B3d CTRL4-VIPER B5a DV2A-DATA8_6 B11a DV-GOUT-5 B5c GLINK-RXD B1c LIGHT-SENSOR B4e MP-B9 B6 PARX0+ B7b PCI-AD25 B10c
+5V B1b AUDIO-OUT1-R B3f CTRL-DISP1 B4g DV2A-DATA8_6 B4b DV-GOUT-5 B6 GLINK-RXD B3g LINKON B11a MP-BOUT-0 B4b PARX1- B7a PCI-AD25 B10d
+5V B2b AUDIO-OUT2-L B3d CTRL-DISP2 B4g DV2A-DATA8_6 B5c DV-GOUT-6 B5c GLINK-RXD B5a LVDS-3V3 B4f MP-BOUT-0 B6 PARX1- B7b PCI-AD25 B11b
+5V B3b AUDIO-OUT2-L B3f CTRL-DISP3 B4g DV2A-DATA9_7 B11a DV-GOUT-6 B6 GLINK-TXD B1c M135-CLK B5a MP-BOUT-1 B4b PARX1+ B7a PCI-AD25 B5a
+5V B3e AUDIO-OUT2-R B3d CTRL-DISP4 B4g DV2A-DATA9_7 B4b DV-GOUT-7 B5c GLINK-TXD B3g M135-CLK B7b MP-BOUT-1 B6 PARX1+ B7b PCI-AD25 B8
+5V B3g AUDIO-OUT2-R B3f CTX_POD-A(4) B10a DV2A-DATA9_7 B5c DV-GOUT-7 B6 GLINK-TXD B5a M27-CLK B4a MP-BOUT-2 B4b PARX2- B7a PCI-AD25 B9a
+5V B4e AUDIO-R B3e CTX_POD-A(4) B10b DV2A-VALID B11a DV-GOUT-8 B5c HDMI-COAST B5a M27-CLK B5a MP-BOUT-2 B6 PARX2- B7b PCI-AD26 B10c
+5V B5a AUDIO-R B3g CTX-POD B10b DV2A-VALID B4b DV-GOUT-8 B6 HDMI-COAST B7b M27-HIRATE B4a MP-BOUT-3 B4b PARX2+ B7a PCI-AD26 B10d
+5V B5e AUDIO-SW B3e CVBSOUTIF-MAIN B3a DV2A-VALID B5c DV-GOUT-9 B5c HSYNC-HIRATE B3g M27-HIRATE B7b MP-BOUT-3 B6 PARX2+ B7b PCI-AD26 B11b
+5V B6 AUDIO-SW B3g CVBSOUTIF-MAIN B3c DV3F-CLK B4b DV-GOUT-9 B6 HSYNC-HIRATE B5a M27-MOP B4a MP-BOUT-4 B4b PARXC- B7a PCI-AD26 B5a
+5V B7c AUX-IF-AGC-MAIN B2a CVBS-TER-OUT B3f DV3F-CLK B5c DV-HREF B4b HV-PRM-MAIN B3a M27-MOP B6 MP-BOUT-4 B6 PARXC- B7b PCI-AD26 B8
+5V2-CONN B3f AUX-IF-AGC-MAIN B2b DAC-CVBS B3b DV3F-DATA0_SOP B4b DV-HREF B7b HV-PRM-MAIN B4a M27-PNX B4a MP-BOUT-5 B4b PARXC+ B7a PCI-AD26 B9a
+5V2-STBY B10d AV1_CVBS B3a DAC-CVBS B5c DV3F-DATA0_SOP B5c DV-OUT-DE B5c I2C-SCL-TUNER-MAINNXT B2a M27-PNX B4e MP-BOUT-5 B6 PARXC+ B7b PCI-AD27 B10c
+5V2-STBY B12 AV1_CVBS B3f DATA1N-MAIN B3a DV3F-DATA1_ERR B4b DV-OUT-DE B6 I2C-SCL-TUNER-MAINNXT B2b M27-POD B10a MP-BOUT-6 B4b PARX-DDC-SCL B7a PCI-AD27 B10d
+5V2-STBY B1a AV1_CVBS-AV7-Y-CVBS B3f DATA1N-MAIN B4a DV3F-DATA1_ERR B5c DV-OUT-FFIELD B5c I2C-SDA-TUNER-MAINNXT B2a M27-POD B4a MP-BOUT-6 B6 PARX-DDC-SCL B7b PCI-AD27 B11b
+5V2-STBY B1b AV1-AV5-AV6_B-PB B3a DATA1P-MAIN B3a DV3F-DATA2_0 B4b DV-OUT-FFIELD B6 I2C-SDA-TUNER-MAINNXT B2b MDIA(0) B10a MP-BOUT-7 B4b PARX-DDC-SDA B7a PCI-AD27 B5a
+5V2-STBY B1c AV1-AV5-AV6_B-PB B3g DATA1P-MAIN B4a DV3F-DATA2_0 B5c DV-OUT-HS B5c I2S-BCLK-AVIP B4a MDIA(1) B10a MP-BOUT-7 B6 PARX-DDC-SDA B7b PCI-AD27 B8
+5V2-STBY B3e AV1-AV5-AV6_B-PB B7b DATA2N-MAIN B3a DV3F-DATA3_1 B4b DV-OUT-HS B6 I2S-BCLK-AVIP B5c MDIA(2) B10a MP-BOUT-8 B4b PBRX0- B7a PCI-AD27 B9a
+5V2-STBY B3f AV1-AV5-AV6_G-Y B3a DATA2N-MAIN B4a DV3F-DATA3_1 B5c DV-OUT-VS B5c I2S-BCLK-MAIN B4a MDIA(3) B10a MP-BOUT-8 B6 PBRX0- B7b PCI-AD28 B10c
+5V2-STBY B4a AV1-AV5-AV6_G-Y B3g DATA2P-MAIN B3a DV3F-DATA4_2 B4b DV-OUT-VS B6 I2S-BCLK-MAIN B5c MDIA(4) B10a MP-BOUT-9 B4b PBRX0+ B7a PCI-AD28 B10d
+5V2-STBY B4e AV1-AV5-AV6_G-Y B7b DATA2P-MAIN B4a DV3F-DATA4_2 B5c DV-ROUT-0 B5c I2S-BCLK-SUB B4a MDIA(5) B10a MP-BOUT-9 B6 PBRX0+ B7b PCI-AD28 B11b
+5V2-STBY B4g AV1-AV5-AV6_R-PR B3a DATA3N-MAIN B3a DV3F-DATA5_3 B4b DV-ROUT-0 B6 I2S-BCLK-SUB B5c MDIA(6) B10a MP-CLK B6 PBRX1- B7a PCI-AD28 B5a
+5V2-STBY B8 AV1-AV5-AV6_R-PR B3g DATA3N-MAIN B4a DV3F-DATA5_3 B5c DV-ROUT-1 B5c I2S-MAIN-D B4a MDIA(7) B10a MP-CLKOUT B4b PBRX1- B7b PCI-AD28 B8
+5V2-STBY_9V-STBY B1b AV1-AV5-AV6_R-PR B7b DATA3P-MAIN B3a DV3F-DATA6_4 B4b DV-ROUT-1 B6 I2S-MAIN-D B5c MDOA(0) B10a MP-CLKOUT B6 PBRX1+ B7a PCI-AD28 B9a
+5V2-STBY_9V-STBY B5e AV1-AV6_FBL-HSYNC B3g DATA3P-MAIN B4a DV3F-DATA6_4 B5c DV-ROUT-2 B5c I2S-MAIN-ND B4a MDOA(1) B10a MP-DE B6 PBRX1+ B7b PCI-AD29 B10c
+5VaM B3c AV1-AV6_FBL-HSYNC B4a DATDIR B10a DV3F-DATA7_5 B4b DV-ROUT-2 B6 I2S-MAIN-ND B5c MDOA(2) B10a MP-FF B6 PBRX2- B7a PCI-AD29 B10d
+5V-AUD B3e AV1-AV6_FBL-HSYNC B7b DATDIR B10c DV3F-DATA7_5 B5c DV-ROUT-3 B5c I2S-MCH-CSW B4a MDOA(3) B10a MP-G0 B6 PBRX2- B7b PCI-AD29 B11b
F_15400_106.eps
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 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 79

SRP Overview SSB

1.1. Introduction
PCI-AD29 B5a PLL-3V3 B4f POD-SOP B10a SDA-UP-VIP B4e TUN-VIPER-RX-DATA9 B4c VSYNC-HIRATE B7b
PCI-AD29 B8 PLL-OUT B5a POD-SOP B10c SDA-UP-VIP B5a TUN-VIPER-RX-DATA9 B5c WAITA B10a
PCI-AD29 B9a PNX-MA-0 B4d POD-VALID B10a SDM B3b TUN-VIPER-TX-BUSY B4c WE B10a
SRP (Service Reference Protocol) is a software tool that creates a list with all references to signal lines. The list contains
PCI-AD3 B11b PNX-MA-1 B4d POD-VALID B10c SDM B4e TUN-VIPER-TX-BUSY B5c XIO-A0_CLE B10c references to the signals within all schematics of a PWB. It replaces the text references currently printed next to the signal
PCI-AD3 B5a PNX-MA-10 B4d POD-VCC B10a SEL-IF-LL1 B5a TUN-VIPER-TX-CLKN B4c XIO-A0_CLE B10d names in the schematics. These printed references are created manually and are therefore not guaranteed to be 100%
PCI-AD3 B8 PNX-MA-11 B4d POD-VPP B10a SEL-IF-LL2 B3c TUN-VIPER-TX-CLKN B5c XIO-A0_CLE B11b correct. In addition, in the current crowded schematics there is often none or very little place for these references.
PCI-AD3 B9a PNX-MA-12 B4d POWERDOWN-1394 B11a SEL-IF-LL2 B5a TUN-VIPER-TX-CLKP B4c XIO-A1_ALE B10c Some of the PWB schematics will use SRP while others will still use the manual references. Either there will be an SRP
PCI-AD30 B10c PNX-MA-2 B4d POWERDOWN-1394 B5a SEL-POD B10c TUN-VIPER-TX-CLKP B5c XIO-A1_ALE B10d reference list for a schematic, or there will be printed references in the schematic.
PCI-AD30 B10d PNX-MA-3 B4d POWERDOWN-1394 B7b SEL-POD B2a TUN-VIPER-TX-DATA0 B4c XIO-A1_ALE B11a
PCI-AD30 B11b PNX-MA-4 B4d POWER-OK-DISPLAY B4e SOUND-ENABLE B3g TUN-VIPER-TX-DATA0 B5c XIO-A1_ALE B11b
PCI-AD30 B5a PNX-MA-5 B4d POWER-OK-DISPLAY B5e SOUND-ENABLE B5a TUN-VIPER-TX-DATA1 B4c XIO-A10 B10c 1.2. Non-SRP Schematics
PCI-AD30 B8 PNX-MA-6 B4d POWER-OK-PLATFORM B5a SOUND-ENABLE-VPR B5a TUN-VIPER-TX-DATA1 B5c XIO-A10 B11a
PCI-AD30 B9a PNX-MA-7 B4d POWER-OK-PLATFORM B5e SPDIF-HDMI B5c TUN-VIPER-TX-DATA10 B4c XIO-A10 B11b
PCI-AD31 B10c PNX-MA-8 B4d POWER-OK-PLATFORM-3V3 B4e SPDIF-HDMI B7b TUN-VIPER-TX-DATA10 B5c XIO-A11 B10c There are several different signals available in a schematic:
PCI-AD31 B10d PNX-MA-9 B4d POWER-OK-PLATFORM-3V3 B5a SPDIF-IN1 B3e TUN-VIPER-TX-DATA11 B4c XIO-A11 B11a
PCI-AD31 B11b PNX-MBA0 B4d PROT-AUDIOSUPPLY B3e SPDIF-IN1 B5c TUN-VIPER-TX-DATA11 B5c XIO-A11 B11b
PCI-AD31 B5a PNX-MBA1 B4d PROT-AUDIOSUPPLY B3g SPDIF-OUT1 B3e TUN-VIPER-TX-DATA12 B4c XIO-A12 B10c 1.2.1. Power Supply Lines
PCI-AD31 B8 PNX-MCAS B4d PROT-AUDIOSUPPLY B4e SPDIF-OUT1 B5c TUN-VIPER-TX-DATA12 B5c XIO-A12 B11a
PCI-AD31 B9a PNX-MCKE B4d PROT-AUDIOSUPPLY B5e SPI-1 B3e TUN-VIPER-TX-DATA13 B4c XIO-A12 B11b All power supply lines are available in the supply line overview (see chapter 6). In the schematics (see chapter 7) is not
PCI-AD4 B11b PNX-MCLK-N B4d PSEN B4e SPI-1 B3g TUN-VIPER-TX-DATA13 B5c XIO-A13 B10c
indicated where supplies are coming from or going to.
PCI-AD4 B5a PNX-MCLK-P B4d QTX_POD-A(7) B10a SPI-CLK B4e TUN-VIPER-TX-DATA14 B4c XIO-A13 B11a
PCI-AD4 B8 PNX-MCS-0 B4d QTX_POD-A(7) B10b SPI-CSB B4e TUN-VIPER-TX-DATA14 B5c XIO-A13 B11b It is however indicated if a supply is incoming (created elsewhere), or outgoing (created or adapted in the current schematic).
PCI-AD4 B9a PNX-MDATA-0 B4d QTX-POD B10b SPI-OUT B3e TUN-VIPER-TX-DATA15 B4c XIO-A14 B11a
PCI-AD5 B11b PNX-MDATA-1 B4d RC B3f SPI-OUT B3g TUN-VIPER-TX-DATA15 B5c XIO-A14 B11b +5V +5V
PCI-AD5 B5a PNX-MDATA-10 B4d RC B4e SPI-PROG B3b TUN-VIPER-TX-DATA2 B4c XIO-A15 B11a
PCI-AD5 B8 PNX-MDATA-11 B4d RDY_IRQA B10a SPI-PROG B4e TUN-VIPER-TX-DATA2 B5c XIO-A15 B11b Outgoing Incoming
PCI-AD5 B9a PNX-MDATA-12 B4d REG B10a SPI-SDI B4e TUN-VIPER-TX-DATA3 B4c XIO-A16_D8 B10d
PCI-AD6 B11b PNX-MDATA-13 B4d REGIMBEAU B3f SPI-SDO B4e TUN-VIPER-TX-DATA3 B5c XIO-A16_D8 B11b 1.2.2. Normal Signals
PCI-AD6 B5a PNX-MDATA-14 B4d REGIMBEAU B5a SPI-WP B4e TUN-VIPER-TX-DATA4 B4c XIO-A17_D9 B10d
PCI-AD6 B8 PNX-MDATA-15 B4d REGIMBEAU-AV6-VSYNC B3f STANDBY B12 TUN-VIPER-TX-DATA4 B5c XIO-A17_D9 B11b
PCI-AD6 B9a PNX-MDATA-2 B4d RESET-1394 B11a STANDBY B5e TUN-VIPER-TX-DATA5 B4c XIO-A18_D10 B10d For normal signals, a schematic reference (e.g. B14b) is placed next to the signals.
PCI-AD7 B11b PNX-MDATA-3 B4d RESET-1394 B5a STBY-WP-NAND-FLASH B10d TUN-VIPER-TX-DATA5 B5c XIO-A18_D10 B11b
PCI-AD7 B5a PNX-MDATA-4 B4d RESET-AUDIO B4a STBY-WP-NAND-FLASH B4e TUN-VIPER-TX-DATA6 B4c XIO-A19_D11 B10d
PCI-AD7 B8 PNX-MDATA-5 B4d RESET-AUDIO B4e STROBE1N-MAIN B3a TUN-VIPER-TX-DATA6 B5c XIO-A19_D11 B11b B14b signal_name
PCI-AD7 B9a PNX-MDATA-6 B4d RESET-ETHERNET B5a STROBE1N-MAIN B4a TUN-VIPER-TX-DATA7 B4c XIO-A2 B10c
PCI-AD8 B11b PNX-MDATA-7 B4d RESET-ETHERNET B9a STROBE1P-MAIN B3a TUN-VIPER-TX-DATA7 B5c XIO-A2 B11b
PCI-AD8 B5a PNX-MDATA-8 B4d RESET-FE-MAIN B2a STROBE1P-MAIN B4a TUN-VIPER-TX-DATA8 B4c XIO-A20_D12 B10d
PCI-AD8 B8 PNX-MDATA-9 B4d RESET-FE-MAIN B5a STROBE2N-MAIN B3a TUN-VIPER-TX-DATA8 B5c XIO-A20_D12 B11b
PCI-AD8 B9a PNX-MDQM-0 B4d RESET-MAIN-NVM B10d STROBE2N-MAIN B4a TUN-VIPER-TX-DATA9 B4c XIO-A21_D13 B10d 1.2.3. Grounds
PCI-AD9 B11b PNX-MDQM-1 B4d RESET-MAIN-NVM B4e STROBE2P-MAIN B3a TUN-VIPER-TX-DATA9 B5c XIO-A21_D13 B11b
PCI-AD9 B5a PNX-MDQS-0 B4d RESET-MIPS B4e STROBE2P-MAIN B4a TXD B10d XIO-A22_D14 B10d For normal and special grounds (e.g. GNDHOT or GND3V3 etc.), nothing is indicated.
PCI-AD9 B8 PNX-MDQS-1 B4d RESET-MIPS B5a STROBE3N-MAIN B3a TXD B1c XIO-A22_D14 B11b
PCI-AD9 B9a PNX-MRAS B4d RESET-PNX2015 B4e STROBE3N-MAIN B4a TXD B9b XIO-A23_D15 B10d
PCI-CBE0 B5a PNX-MWE B4d RESET-POD-CI B10a STROBE3P-MAIN B3a TXD-UP B10d XIO-A23_D15 B11b 1.3. SRP Schematics
PCI-CBE0 B8 POD-A(0) B10a RESET-POD-CI B5a STROBE3P-MAIN B4a TXD-UP B4e XIO-A3 B10c
PCI-CBE0 B9a POD-A(0) B10c RESET-STBY B12 SUPPLY-FAULT B10a TXD-VIPER B10d XIO-A3 B11b
PCI-CBE1 B11b POD-A(1) B10a RESET-STBY B4e SUPPLY-FAULT B1a TXD-VIPER B5a XIO-A4 B10c SRP is a tool, which automatically creates a list with signal references, indicating on which schematic the signals are used.
PCI-CBE1 B5a POD-A(1) B10c RESET-SYSTEM B1c SUPPLY-FAULT B4e TXPNXA- B4b XIO-A4 B11b A reference is created for all signals indicated with an SRP symbol, these symbols are:
PCI-CBE1 B8 POD-A(10) B10a RESET-SYSTEM B4e SUPPLY-FAULT B5e TXPNXA- B4g XIO-A5 B10c
PCI-CBE1 B9a POD-A(10) B10c RESET-SYSTEM B5a TEMP-SENSOR B4e TXPNXA+ B4b XIO-A5 B11b
PCI-CBE2 B11b POD-A(11) B10a RESET-USB20 B5a TS-CLK B11a TXPNXA+ B4g XIO-A6 B10c +5V +5V
Power supply line.
PCI-CBE2 B5a POD-A(11) B10c RESET-USB20 B8 TS-CLK B5c TXPNXB- B4b XIO-A6 B11b
PCI-CBE2 B8 POD-A(12) B10a RSTA B10a TS-DATA0 B11a TXPNXB- B4g XIO-A7 B10c
PCI-CBE2 B9a POD-A(12) B10c RXD B10d TS-DATA0 B5c TXPNXB+ B4b XIO-A7 B11b
PCI-CBE3 B5a POD-A(13) B10a RXD B1c TS-DATA1 B11a TXPNXB+ B4g XIO-A8 B10c name name
Stand alone signal or switching line (used as less as possible).
PCI-CBE3 B8 POD-A(13) B10c RXD B9b TS-DATA1 B5c TXPNXC- B4b XIO-A8 B11b
PCI-CBE3 B9a POD-A(2) B10a RXD-UP B10d TS-DATA2 B11a TXPNXC- B4g XIO-A9 B10c
PCI-CLK-ETHERNET B5a POD-A(2) B10c RXD-UP B4e TS-DATA2 B5c TXPNXC+ B4b XIO-A9 B11b name name
PCI-CLK-ETHERNET B9a POD-A(3) B10a RXD-VIPER B10d TS-DATA3 B11a TXPNXC+ B4g XIO-ACK B10d
PCI-CLK-USB20 B5a POD-A(3) B10c RXD-VIPER B5a TS-DATA3 B5c TXPNXCLK- B4b XIO-ACK B5a Signal line into a wire tree.
PCI-CLK-USB20 B8 POD-A(4) B10b SCL-DMA B5a TS-DATA4 B11a TXPNXCLK- B4g XIO-AS_REn B10a
PCI-CLK-VPR B5a POD-A(4) B10c SCL-DMA-BUS1 B11a TS-DATA4 B5c TXPNXCLK+ B4b XIO-AS_REn B10d
name name
PCI-DEVSEL B5a POD-A(5) B10b SCL-DMA-BUS1 B12 TS-DATA5 B11a TXPNXCLK+ B4g XIO-AS_REn B11a
PCI-DEVSEL B8 POD-A(5) B10c SCL-DMA-BUS1 B5a TS-DATA5 B5c TXPNXD- B4b XIO-AS_REn B11b
Switching line into a wire tree.
PCI-DEVSEL B9a POD-A(6) B10b SCL-DMA-BUS1-ATSC B12 TS-DATA6 B11a TXPNXD- B4g XIO-D0 B11a
PCI-FRAME B5a POD-A(6) B10c SCL-DMA-BUS1-ATSC B2a TS-DATA6 B5c TXPNXD+ B4b XIO-D0 B11b
PCI-FRAME B8 POD-A(7) B10b SCL-DMA-BUS2 B3b TS-DATA7 B11a TXPNXD+ B4g XIO-D1 B11a name

PCI-FRAME B9a POD-A(7) B10c SCL-DMA-BUS2 B4e TS-DATA7 B5c TXPNXE- B4b XIO-D1 B11b
PCI-GNT B5a POD-A(8) B10b SCL-DMA-BUS2 B5a TS-SOP B11a TXPNXE- B4g XIO-D10 B11a Bi-directional line (e.g. SDA) into a wire tree.
PCI-GNT B8 POD-A(8) B10c SCL-I2C4 B4g TS-SOP B5c TXPNXE+ B4b XIO-D10 B5a
PCI-GNT-A B5a POD-A(9) B10b SCL-I2C4 B5a TS-VALID B11a TXPNXE+ B4g XIO-D11 B11a name
PCI-GNT-A B9a POD-A(9) B10c SCL-I2C4 B5e TS-VALID B5c UART-SWITCH B10d XIO-D11 B5a
PCI-INTA B5a POD-CLK B10a SCL-I2C4-DISP B4g TUNERAGC-MON B2a UART-SWITCH B4e XIO-D12 B11a Signal line into a wire tree, its direction depends on the circuit (e.g. ingoing for PDP, outgoing for LCD sets).
PCI-IRDY B5a POD-CLK B10c SCL-MM B3g TUNERAGC-MON B2b UART-SWITCHn B10d XIO-D12 B5a
PCI-IRDY B8 POD-D(0) B10a SCL-MM B5a TUN-VIPER-RX-BUSY B4c UP-3V3 B4f XIO-D13 B11a Remarks:
PCI-IRDY B9a POD-D(0) B10c SCL-MM-BUS1 B10a TUN-VIPER-RX-BUSY B5c USB1-DM B5a XIO-D13 B5a
PCI-PAR B5a POD-D(1) B10a SCL-MM-BUS1 B5a TUN-VIPER-RX-CLKN B4c USB1-DP B5a XIO-D14 B11a • When there is a black dot on the "signal direction arrow" it is an SRP symbol, so there will be a reference to the signal
PCI-PAR B8 POD-D(1) B10c SCL-MM-BUS1 B6 TUN-VIPER-RX-CLKN B5c USB20-DM1 B8 XIO-D14 B5a name in the SRP list.
PCI-PAR B9a POD-D(2) B10a SCL-MM-BUS1 B7b TUN-VIPER-RX-CLKP B4c USB20-DP1 B8 XIO-D15 B11a • All references to normal grounds (Ground symbols without additional text) are not listed in the reference list, this to keep
PCI-PERR B5a POD-D(2) B10c SCL-MOP B5e TUN-VIPER-RX-CLKP B5c USB20-OC1 B5a XIO-D15 B5a it concise.
PCI-PERR B8 POD-D(3) B10a SCL-MOP B6 TUN-VIPER-RX-DATA0 B4c USB20-OC1 B8 XIO-D2 B11a • Signals that are not used in multiple schematics, but only once or several times in the same schematic, are included
PCI-PERR B9a POD-D(3) B10c SCL-UP-SW B4e TUN-VIPER-RX-DATA0 B5c USB20-OC2 B8 XIO-D2 B11b
PCI-REQ B5a POD-D(4) B10a SCL-UP-SW B5e TUN-VIPER-RX-DATA1 B4c USB20-PWE1 B5a XIO-D3 B11a
in the SRP reference list, but only with one reference.
PCI-REQ B8 POD-D(4) B10c SCL-UP-VIP B10d TUN-VIPER-RX-DATA1 B5c USB20-PWE1 B8 XIO-D3 B11b Additional Tip:
PCI-REQ-A B5a POD-D(5) B10a SCL-UP-VIP B4e TUN-VIPER-RX-DATA10 B4c USB2-DM B5a XIO-D4 B11a
PCI-REQ-A B9a POD-D(5) B10c SCL-UP-VIP B5a TUN-VIPER-RX-DATA10 B5c USB2-DP B5a XIO-D4 B11b When using the PDF service manual file, you can very easily search for signal names and follow the signal over all the
PCI-REQ-B B10a POD-D(6) B10a SDA-DMA B5a TUN-VIPER-RX-DATA11 B4c USB-BUS-PW B5a XIO-D5 B11a schematics. In Adobe PDF reader:
PCI-REQ-B B5a POD-D(6) B10c SDA-DMA-BUS1 B11a TUN-VIPER-RX-DATA11 B5c USB-OVERCUR B5a XIO-D5 B11b • Select the signal name you want to search for, with the "Select text" tool.
PCI-SERR B5a POD-D(7) B10a SDA-DMA-BUS1 B12 TUN-VIPER-RX-DATA12 B4c VCC_EXTO B10a XIO-D6 B11a
PCI-SERR B8 POD-D(7) B10c SDA-DMA-BUS1 B5a TUN-VIPER-RX-DATA12 B5c VCCEN B10a XIO-D6 B11b
• Copy and paste the signal name in the "Search PDF" tool.
PCI-SERR B9a POD-DATA0 B10a SDA-DMA-BUS1-ATSC B12 TUN-VIPER-RX-DATA13 B4c VDISP B4g XIO-D7 B11a • Search for all occurrences of the signal name.
PCI-STOP B5a POD-DATA0 B10c SDA-DMA-BUS1-ATSC B2a TUN-VIPER-RX-DATA13 B5c VDISP2 B4g XIO-D7 B11b • Now you can quickly jump between the different occurrences and follow the signal over all schematics. It is advised to
PCI-STOP B8 POD-DATA1 B10a SDA-DMA-BUS2 B3b TUN-VIPER-RX-DATA14 B4c VISUAL-CHECK B3c XIO-D8 B11a "zoom in" to e.g. 150% to see clearly, which text is selected. Then you can zoom out, to get an overview of the complete
PCI-STOP B9a POD-DATA1 B10c SDA-DMA-BUS2 B4e TUN-VIPER-RX-DATA14 B5c VPPEN B10a XIO-D8 B5a schematic.
PCI-TRDY B5a POD-DATA2 B10a SDA-DMA-BUS2 B5a TUN-VIPER-RX-DATA15 B4c VREF-AUD B3e XIO-D9 B11a
PCI-TRDY B8 POD-DATA2 B10c SDA-I2C4 B4g TUN-VIPER-RX-DATA15 B5c VREF-AUD-POS B3b XIO-D9 B5a E_14700_101.eps
PCI-TRDY B9a POD-DATA3 B10a SDA-I2C4 B5a TUN-VIPER-RX-DATA2 B4c VREF-AUD-POS B4a XIO-RWn_WEn B10a
PS. It is recommended to use at least Adobe PDF (reader) version 6.x, due to better search possibilities in this version.
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PDIR B10a POD-DATA3 B10c SDA-I2C4 B5e TUN-VIPER-RX-DATA2 B5c VREF-DEFL B3b XIO-RWn_WEn B10d
PDIR B10b POD-DATA4 B10a SDA-I2C4-DISP B4g TUN-VIPER-RX-DATA3 B4c VREF-PNX B4c XIO-RWn_WEn B11a
PDOE B10a POD-DATA4 B10c SDA-MM B3g TUN-VIPER-RX-DATA3 B5c VREF-PNX B4d XIO-RWn_WEn B11b
PDOE B10b POD-DATA5 B10a SDA-MM B5a TUN-VIPER-RX-DATA4 B4c VREF-VPR B5b XIO-SEL0 B10d
PHY-D(0) B11a POD-DATA5 B10c SDA-MM-BUS1 B10a TUN-VIPER-RX-DATA4 B5c VS1 B10a XIO-SEL0 B11b
PHY-D(1) B11a POD-DATA6 B10a SDA-MM-BUS1 B5a TUN-VIPER-RX-DATA5 B4c VS2 B10a XIO-SEL0 B5a
PHY-D(2) B11a POD-DATA6 B10c SDA-MM-BUS1 B6 TUN-VIPER-RX-DATA5 B5c VS2 B10b XIO-SEL1 B11a
PHY-D(3) B11a POD-DATA7 B10a SDA-MM-BUS1 B7b TUN-VIPER-RX-DATA6 B4c VS2_MOCLKA-CI B10a XIO-SEL1 B11b
PHY-D(4) B11a POD-DATA7 B10c SDA-MOP B5e TUN-VIPER-RX-DATA6 B5c VS2_MOCLKA-CI B10b XIO-SEL1 B5a
PHY-D(5) B11a POD-MODE B12 SDA-MOP B6 TUN-VIPER-RX-DATA7 B4c VSW B1a XIO-SEL2 B10a
PHY-D(6) B11a POD-MODE B1a SDA-UP-SW B4e TUN-VIPER-RX-DATA7 B5c VSW B1b XIO-SEL2 B5a
PHY-D(7) B11a POD-MODE B4e SDA-UP-SW B5e TUN-VIPER-RX-DATA8 B4c VSYNC-HIRATE B5a Y-CVBS-MON-OUT B3b
PLL-1V2 B4f POD-MODE B4g SDA-UP-VIP B10d TUN-VIPER-RX-DATA8 B5c VSYNC-HIRATE B7a Y-CVBS-MON-OUT B3f

F_15400_107.eps
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 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 80

Layout Small Signal Board (Overview Top Side)

1B01 C4 1H00 D2 1Z05 E4 2AA4 A1 2B39 C4 2B89 B4 2G10 F2 2J24 B3 2L07 C3 2L91 C2 2LN7 B3 2N01 C4 2O14 D4 2Q03 E2 2Q23 D2 2Q43 E2 2Q66 E3 2U02 G1 2U50 G2 2Z25 E4 3A31 A3 3A66 A3 3B10 C4 3B32 B4 3B62 B4 3BA7 B4 3C76 A2 3H03 D2 3H29 E3 3H86 D3 3J31 B1 3L01 C3 3L27 C3 3L93 C2 3LB6 B3 3LD6 C3 3LG6 B3 3Q47 D3 5L52 C2 9A47 A1
1B02 B4 1H01 D1 1Z10 E4 2AB7 B3 2B40 B4 2B90 B4 2H00 D2 2J25 B3 2L08 C2 2L92 B2 2LN8 B3 2N02 C4 2O15 D4 2Q04 D3 2Q24 E3 2Q44 E2 2Q69 D2 2U03 G1 2U58 G2 2Z27 E4 3A32 A3 3A70 A3 3B11 C4 3B34 B4 3B65 B4 3BA8 B4 3G09 F1 3H06 E3 3H31 E3 3H87 D2 3J32 B1 3L02 C3 3L29 C3 3L94 B2 3LB7 C3 3LD7 C3 3LG7 C3 3Q48 D3 5LA1 C3 9A52 A1
1B30 C4 1H07 F3 1Z11 E4 2B04 C4 2B41 B4 2B92 B4 2H01 D2 2J37 C1 2L58 B1 2LA0 B3 2LP0 C3 2N03 C4 2O16 D4 2Q05 E3 2Q25 E3 2Q45 E2 2Q70 D2 2U04 G1 2V02 E2 2Z29 E4 3A33 A3 3A78 B2 3B12 C4 3B36 B4 3B66 B4 3BA9 B4 3G10 F1 3H07 E3 3H32 E3 3H88 D3 3J42 C1 3L03 C3 3L31 C3 3L95 C2 3LB8 C3 3LD8 C3 3LG8 C3 3Q49 D3 5LA2 C3 9A54 A1
1B31 C4 1LA0 C4 2A20 A2 2B05 C4 2B42 B4 2BA1 C4 2H02 D2 2J60 B1 2L59 C2 2LA1 B3 2LP2 B3 2N04 C4 2O17 D4 2Q06 E2 2Q26 E3 2Q46 E2 2Q71 E1 2U05 G1 2V03 E2 2Z30 E4 3A34 A3 3A79 B1 3B13 C4 3B37 C4 3B67 B4 3BB0 C4 3G11 F2 3H08 D2 3H48 E3 3H90 E3 3J43 C1 3L04 C3 3L33 C3 3L96 C2 3LB9 C3 3LD9 C3 3LG9 B3 3Q50 D2 5LA3 B3 9A55 A1
1B32 C4 1M03 F1 2A21 A2 2B21 B4 2B43 B4 2BA4 B4 2H03 D2 2J64 C1 2L60 C2 2LA2 C3 2LP3 B2 2N07 C4 2O18 D4 2Q07 E3 2Q27 E3 2Q47 E2 2Q72 E1 2U06 G1 2V04 F2 2Z38 E4 3A35 A3 3A87 B3 3B14 C4 3B38 C4 3B68 B4 3C31 A2 3G12 F2 3H09 E2 3H49 E3 3H93 D3 3J44 C1 3L05 C3 3L35 C3 3L97 C2 3LC0 C3 3LE0 C3 3LH0 C2 3Q51 D3 5LN0 C3 9A56 A1
1B33 C4 1M15 D4 2A22 B2 2B22 B4 2B44 B4 2BA5 B4 2H06 E3 2J67 B1 2L61 C2 2LA4 B3 2LP4 C2 2N09 C4 2O19 D4 2Q08 E3 2Q28 E3 2Q48 D2 2Q73 F1 2U07 G1 2V05 F2 2Z50 D4 3A36 A3 3A88 B3 3B15 C4 3B41 C4 3B69 B4 3C33 B2 3G13 F1 3H10 E2 3H50 D2 3H94 E3 3J45 C1 3L08 C3 3L38 C3 3L98 B2 3LC1 C3 3LE2 C3 3LH1 C2 3Q52 E2 5LN1 B3 9A57 A1
1B34 B4 1M46 G1 2A23 B2 2B23 B4 2B45 B4 2BA6 B4 2H07 E3 2J68 B1 2L62 C2 2LA5 B3 2LP7 C3 2N12 C4 2O20 D4 2Q09 E2 2Q29 E3 2Q49 D3 2Q74 F1 2U17 G2 2V35 E2 2Z51 D4 3A39 B3 3A89 B3 3B16 C4 3B43 C4 3B70 B4 3C35 A2 3G14 F1 3H11 E2 3H51 D2 3H95 D3 3J46 C1 3L09 C3 3L39 C2 3LA0 B3 3LC2 B3 3LE3 C3 3LH3 B2 3Q53 D3 5LN2 C3 9A58 A1
1B35 B4 1M49 E1 2A24 B2 2B24 B4 2B46 B4 2BA7 B4 2H08 D2 2J69 C1 2L63 B2 2LA6 B3 2LP8 C3 2N13 C4 2O21 D4 2Q10 E3 2Q30 E3 2Q50 D3 2Q75 F1 2U22 G2 2Z04 E4 2Z52 D4 3A40 A3 3A90 B3 3B17 C4 3B45 C4 3B91 C4 3C36 A2 3G15 F1 3H12 E3 3H70 D3 3H97 E3 3J47 C1 3L10 C2 3L40 B2 3LA1 B3 3LC3 B3 3LE4 C3 3LH4 B2 3Q55 D3 5LN3 C3 9A59 A1
1B36 B4 1M52 A1 2A31 A1 2B25 B4 2B49 C4 2BA9 B4 2H09 D2 2J70 C1 2L64 B2 2LA7 B3 2LP9 B2 2O00 D4 2O22 D4 2Q11 E3 2Q31 E3 2Q51 E2 2Q79 E1 2U24 G2 2Z05 E4 3A01 B1 3A46 A3 3A91 B3 3B18 C4 3B48 B4 3B94 B4 3C37 A2 3G16 F1 3H13 E2 3H71 D2 3H98 E2 3J49 C1 3L11 C2 3L41 B2 3LA2 B3 3LC4 C3 3LE5 C3 3LH5 C3 3Q57 D3 5LN4 B3 9A60 A1
1B37 B4 1M63 F1 2A32 A3 2B26 B4 2B51 B4 2C01 A2 2J01 B3 2J75 B1 2L80 C2 2LA8 B3 2LR0 C3 2O01 D4 2O23 D4 2Q12 E3 2Q32 E3 2Q52 E2 2Q80 E1 2U25 G2 2Z06 E4 3A02 B1 3A47 A3 3A92 B3 3B19 C4 3B49 B4 3B95 B4 3C38 A2 3G19 G2 3H14 E3 3H72 D3 3H99 E2 3J50 C1 3L12 C2 3L42 B2 3LA3 B3 3LC5 C3 3LE6 C3 3LH6 B3 3Q59 D3 5N00 C4 9A61 A1
1C33 A2 1M64 C2 2A80 B1 2B27 B4 2B52 B4 2C02 A2 2J03 B3 2K58 B3 2L81 C2 2LA9 B3 2LR2 C3 2O02 D4 2O24 C4 2Q13 D3 2Q33 E3 2Q53 D3 2Q81 E1 2U27 G3 2Z07 E4 3A04 A1 3A48 A3 3A93 B3 3B20 C4 3B50 B4 3B96 B4 3C42 A2 3G22 F2 3H15 D3 3H73 E2 3J01 B2 3J51 C1 3L13 C2 3L43 B2 3LA4 B3 3LC6 B3 3LE7 C3 3LH8 B3 3Q61 D3 5N01 C4 9A62 A1
1C53 A2 1N00 C4 2A85 A3 2B28 B4 2B53 B4 2C32 A2 2J06 B3 2K60 B3 2L82 B2 2LB0 C3 2LR4 B3 2O03 D4 2O25 D4 2Q14 E3 2Q34 E3 2Q54 D2 2Q82 F1 2U28 G2 2Z08 E4 3A05 A1 3A49 A3 3A94 B3 3B21 C4 3B51 B4 3B97 B4 3C43 A2 3G24 F2 3H16 D2 3H74 E2 3J03 B3 3J52 C2 3L14 C2 3L44 C2 3LA5 C4 3LC7 B3 3LE8 C3 3LH9 B3 3Q63 D3 5N02 C4 9A63 A1
1C54 A1 1N62 C4 2A86 A3 2B29 B4 2B62 C4 2C33 A2 2J08 B3 2K61 A3 2L83 B2 2LB1 C3 2LR5 C3 2O04 D4 2O26 D4 2Q15 E3 2Q35 E3 2Q55 D2 2Q83 D1 2U29 G2 2Z09 E4 3A06 A1 3A50 A3 3A95 B3 3B22 C4 3B52 B4 3B98 B4 3C44 A2 3G40 F2 3H18 E3 3H75 D2 3J07 B3 3J53 C2 3L15 C2 3L45 C2 3LA6 B3 3LC8 C3 3LE9 C3 3LJ0 C3 3Q65 D2 5O00 D4 9A64 A1
1C63 A2 1O00 D4 2A87 A3 2B30 B4 2B64 C4 2C34 A2 2J10 B3 2K63 A3 2L84 B2 2LB3 C3 2LR6 C3 2O05 D4 2O27 D4 2Q16 E3 2Q36 D1 2Q56 D2 2Q84 E1 2U30 G2 2Z16 E4 3A13 B2 3A51 B2 3A96 B3 3B24 B4 3B53 B4 3BA0 C4 3C46 A2 3G46 G2 3H19 E3 3H79 E3 3J08 B3 3J54 C1 3L16 C3 3L46 C2 3LA7 C3 3LC9 C3 3LF0 C3 3LJ1 C3 3Q66 D3 5O01 D4 9A65 A1
1D40 D1 1O10 D4 2A88 A3 2B31 B4 2B67 B4 2C37 A2 2J13 B2 2K67 A3 2L85 C2 2LB4 C3 2LR8 C2 2O06 C4 2O28 D4 2Q17 D2 2Q37 E3 2Q57 E2 2Q87 E1 2U34 G3 2Z17 E4 3A15 B1 3A52 B2 3A97 B2 3B25 C4 3B54 B4 3BA1 C4 3C47 A2 3G55 F1 3H20 E3 3H80 D3 3J09 B3 3J55 C2 3L17 C2 3L47 C2 3LA8 C3 3LD0 C3 3LF1 C1 3LJ2 B2 3Q67 D3 5Q01 D2 9A66 A1
1E40 A1 1P01 G4 2A91 B2 2B32 B4 2B69 B4 2C42 A2 2J16 B2 2K68 A3 2L86 C2 2LN2 B3 2LR9 C3 2O07 D4 2O50 D4 2Q18 E3 2Q38 E3 2Q58 E2 2Q88 D1 2U35 G2 2Z18 E4 3A16 B2 3A53 B2 3A98 B2 3B26 C4 3B55 B4 3BA2 B4 3C51 A2 3G56 F1 3H21 E3 3H81 D3 3J11 B3 3J56 C2 3L18 C2 3L48 C2 3LB1 C3 3LD1 C3 3LF2 C3 3LJ3 B3 3Q68 D3 5Q02 E2 9A67 A1
1E62 B2 1T04 A3 2A96 B3 2B33 B4 2B77 B4 2C43 A2 2J18 B3 2K75 A3 2L87 C2 2LN3 B3 2LS5 B3 2O10 D4 2O51 D4 2Q19 E3 2Q39 E3 2Q59 D2 2Q89 D1 2U36 G2 2Z19 E4 3A17 B1 3A54 B2 3A99 B2 3B27 C4 3B56 C4 3BA3 B4 3C70 A2 3G61 F2 3H22 E3 3H82 D2 3J12 B2 3J88 C1 3L19 C3 3L49 C2 3LB2 C3 3LD2 C3 3LF8 B3 3LJ4 C3 3Q72 E1 5Q03 D2 9A68 A1
1E63 B1 1U01 G1 2AA0 A2 2B34 B4 2B79 C4 2C52 A2 2J20 B3 2K76 A3 2L88 B2 2LN4 C3 2LT0 C3 2O11 D4 2Q00 E3 2Q20 E3 2Q40 E2 2Q63 E2 2Q93 F1 2U42 G2 2Z21 E4 3A18 B2 3A55 A3 3AA1 A3 3B28 C4 3B57 B4 3BA4 B4 3C73 A2 3G62 F2 3H23 E3 3H83 D2 3J13 B2 3J91 C1 3L21 C3 3L90 C2 3LB3 C3 3LD3 B3 3LF9 C3 3LJ5 C3 3Q73 E1 5Q04 E3 9A69 B1
1G02 F2 1U03 G2 2AA1 A3 2B35 B4 2B80 C4 2C53 A2 2J22 B3 2L01 C3 2L89 C2 2LN5 C3 2LT2 C2 2O12 D4 2Q01 E2 2Q21 D2 2Q41 F1 2Q64 E2 2U00 G1 2U45 G2 2Z23 E4 3A19 B2 3A57 A3 3AA2 B3 3B29 C4 3B58 B4 3BA5 B4 3C74 A2 3H01 E3 3H27 E2 3H84 D3 3J23 C1 3JA2 B2 3L23 C3 3L91 B2 3LB4 B4 3LD4 C3 3LG3 C3 3LJ6 C3 3Q74 F1 5Q05 E3 9A70 B1
1G50 C1 1U04 G1 2AA2 A3 2B36 B4 2B81 C4 2C75 A1 2J23 B3 2L06 C2 2L90 C2 2LN6 C3 2N00 C4 2O13 D4 2Q02 E3 2Q22 D3 2Q42 E3 2Q65 D2 2U01 G1 2U46 G3 2Z24 E4 3A28 B2 3A58 A3 3B09 C4 3B30 B4 3B59 B4 3BA6 B4 3C75 A2 3H02 E2 3H28 E3 3H85 D2 3J24 C1 3L00 C3 3L25 C3 3L92 C2 3LB5 B3 3LD5 C3 3LG5 B3 3LJ7 C3 3Q75 F1 5Q09 E1 9A71 B1
3LJ8 C3 3Q76 F1 5Q10 E1 9A72 B1
3LJ9 C3 3Q79 E1 5U00 G3 9A73 B1
3LK0 C3 3Q80 E1 5U01 G1 9A74 B1
3LK1 C3 3Q81 E1 5U02 G1 9A80 B3
3LK2 C3 3Q89 E1 5U03 G2 9A81 A3
3LK3 C3 3Q90 E1 5U04 G1 9A88 B2
Part 2 3LK4
3LK5
C3
C3
3Q91
3Q92
D1
D1
5U05
5U06
G1
G1
9B00
9B11
C4
C4
F_15400_054b.eps 3LK6
3LK7
C3
C3
3Q93
3Q96
D1
D1
5U07
5U08
G1
G1
9B12
9B13
B4
B4
3LK8 C3 3Q99 E1 5U09 G3 9B14 B4
3LL0 C3 3U20 G2 5V01 E2 9B15 B4
3LL1 C3 3U21 G3 5V02 E2 9B16 C4
3LL2 C3 3U25 G2 5Z00 E4 9B17 C4
3LL3 C3 3U40 G2 5Z01 E4 9B18 C4
3LL4 C3 3U44 G2 5Z02 E4 9B19 C4
3LL5 C3 3U47 G2 5Z05 E4 9B20 B4
3LL6 C3 3U48 G2 5Z06 E4 9C47 A1
3LL7 C3 3U49 G2 5Z07 E4 9C48 B1
Part 1 3LL8 C3 3U50 G2 5Z08 E4 9C49 B2
3LL9 C3 3U51 G2 5Z50 D4 9G11 F2
F_15400_054a.eps 3LQ7 B1 3U58 G3 6A02 B2 9G15 F2
3LQ8 B1 3U59 G3 6B20 C4 9G16 F2
3LR2 C3 3U79 F3 6B21 C4 9G17 F2
3LS2 C3 3U81 F2 6H00 D3 9G18 F2
3LS8 B3 3U84 G2 6H01 E3 9G19 F2
3LS9 B3 3UA0 G2 6H03 E3 9G20 F2
3LT0 B3 3UA7 G3 6H04 F1 9G21 F2
3LT1 B3 3V44 E2 6H05 F2 9G22 F2
3LT2 B3 3V78 E2 6H06 D1 9G23 F2
3LT9 C2 3Z01 E4 6J03 B1 9G24 F2
3LU0 C2 3Z07 E4 6J04 B1 9G25 F2
3LU1 C2 3Z08 E4 6J07 C3 9G26 F2
3LU2 C2 3Z12 E4 6J08 C3 9H03 E3
3LU3 C2 3Z13 E4 6L03 C2 9H04 E2
3N08 C4 3Z18 E4 6O00 D4 9H05 D3
3N09 C4 3Z20 E4 6O01 C4 9H06 D2
3N12 C4 3Z21 E4 6O02 D4 9H07 D2
3N13 C4 3Z22 E4 6U05 F3 9H08 D2
3N14 C4 3Z23 E4 6U06 F3 9H13 D2
3N15 C4 3Z24 E4 6U07 F3 9H15 E3
3N30 C4 3Z25 E4 6U08 F3 9H16 E2
3N31 C4 3Z26 E4 6U11 G2 9H18 E3
3N32 C4 3Z27 E4 6U18 G2 9H19 E3
3N33 C4 3Z28 E4 6U25 G2 9H26 E3
3N90 C4 3Z29 E4 7A05 A3 9H27 E3
3N92 C4 3Z30 E4 7A07 A3 9H29 E3
3O00 D4 3Z33 E4 7A08 B3 9H30 E3
3O01 D4 3Z35 E4 7A09 A3 9H32 E3
3O02 D4 3Z37 E4 7A11 A3 9H33 E3
3O03 D4 3Z38 E4 7A15 B3 9H34 E3
3O04 D4 3Z40 E4 7A16 B3 9J15 B1
3O05 C4 3Z41 E4 7A18 B3 9J16 B1
3O06 D4 3Z44 E4 7B03 C4 9J17 B1
3O07 D4 3Z46 E4 7B04 C4 9J22 B2
3O08 D4 3Z50 E4 7B05 C4 9J24 B2
3O09 D4 3Z51 E4 7B12 B4 9LA0 B3
3O10 D4 3Z54 D4 7B13 B4 9LA1 B3
3O11 D4 3Z55 E4 7C00 A2 9LA2 B3
3O12 D4 3Z56 E4 7C32 A2 9LA3 C3
3O13 D4 3Z57 E4 7C56 A2 9LA6 B3
3O14 D4 3Z58 E4 7C57 A2 9LA8 B2
3O15 D4 3Z59 E4 7G00 F2 9LA9 B2
3O16 D4 3Z60 E4 7J01 C3 9LC6 C3
3O21 D4 5A06 B1 7J02 C3 9LC7 C3
3O22 D4 5A07 A1 7J04 B1 9O16 D4
3O23 D4 5B01 C4 7J09 C2 9Q19 E1
Part 3 3O24
3O25
D4
D4
5B10
5B11
B4
B4
7L50
7LA3
B1
B3
9Q65
9Q66
E2
E2
F_15400_054c.eps 3O26
3O27
D4
D4
5B12
5B17
C4
B4
7LA7
7LB3
B3
C2
9U04
9U05
G1
G1
3O28 D4 5B18 B4 7N10 C4 9U06 F3
3Q00 E3 5B21 B4 7U01 G2 9U10 G1
3Q02 E2 5B22 B4 7U03 G2 9U11 G1
3Q03 E2 5B23 B4 7U08 G2 9U12 G2
3Q04 E2 5B24 B4 7U09 G2 9Z51 D4
3Q05 F2 5B31 B4 7U16 G1 9Z52 D4
3Q06 E3 5C34 A2 7U26 G2 9Z53 D4
3Q07 F2 5C37 A2 7V01 E2 9Z54 D4
3Q08 F2 5C52 A2 7V02 E2 9Z55 D4
3Q09 E3 5C53 A2 7Z01 E4 9Z56 D4
3Q11 E3 5C54 A2 9A01 A1 9Z57 D4
3Q12 E3 5G01 G2 9A02 A1 9Z58 D4
3Q13 E3 5H01 D2 9A03 A1 9Z60 D4
Part 4 3Q14 E3 5H05 D2 9A04 A1 9Z61 D4
3Q15 E3 5J00 B3 9A05 A1 9Z62 D4
F_15400_054d.eps 3Q17 D1 5J01 B3 9A06 A1 9Z63 D4
3Q18 D1 5J02 B3 9A07 A1 9Z64 D4
3Q19 D1 5J03 B3 9A09 B1 9Z65 D4
3Q22 D1 5J04 B2 9A10 B1 9Z66 D4
3Q25 F2 5J05 B2 9A11 A1 9Z67 D4
3Q26 F2 5J06 B3 9A16 A1 9Z70 D4
3Q27 E2 5J07 B3 9A21 B1 9Z71 D4
3Q28 F2 5J10 C1 9A22 B1 9Z72 D4
3Q33 D3 5J11 C1 9A32 B1 9Z73 D4
3Q34 F2 5J12 C1 9A33 B1 9Z74 D4
3Q35 D3 5J50 C1 9A34 B1 9Z75 D4
3Q36 D1 5J52 C1 9A35 B1 9Z76 D4
3Q37 D3 5J54 C1 9A36 B1 9Z77 D4
3Q38 D3 5J56 C1 9A37 B1
3Q39 D3 5J58 C1 9A38 B1
3Q40 D3 5J60 C1 9A39 A1
3Q41 D3 5J82 B1 9A40 A1
3Q43 D3 5J85 B1 9A41 A1
3Q44 F2 5L01 C3 9A44 A1
F_15400_054.eps 3Q45 D3 5L50 C2 9A45 A1
3104 313 6037.6 260405 3Q46 F1 5L51 C2 9A46 A1
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 81

Layout Small Signal Board (Part 1 Top Side)

Part 1

F_15400_054a.eps
310405
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 82

Layout Small Signal Board (Part 2 Top Side)

Part 2

F_15400_054b.eps
260405
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 83

Layout Small Signal Board (Part 3 Top Side)

Part 3

F_15400_054c.eps
260405
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 84

Layout Small Signal Board (Part 4 Top Side)

Part 4

F_15400_054d.eps
260405
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 85

Layout Small Signal Board (Overview Bottom Side)

1C51 A2 2A38 A4 2A59 A4 2A81 A2 2AB5 A3 2C13 A3 2C50 A3 2G18 F4 2G39 F3 2J46 C4 2L52 B3 2P02 F1 2P40 F1 2T05 A1 2T28 A1 2TG5 A1 2TK6 A1 2U12 G2 2U47 G3 2V23 D3 3A20 A2 3A62 A2 3B00 C1 3C40 B3 3G06 F3 3G38 F3 3H25 D2 3J67 B4 3L58 B3 3LK9 C2 3LR4 C2 3LU6 C3 3M70 A2 3P14 G1 3P36 F1 3P79 F1 3U68 G3 5TG3 A1 7U11 G3
1C52 A3 2A39 A4 2A60 A4 2A82 A4 2AB6 B4 2C14 A3 2C55 A3 2G19 F4 2G40 G3 2J47 C4 2L53 B3 2P03 G1 2P41 F1 2T06 A1 2T30 A1 2TG6 B1 2TK7 A1 2U13 G3 2U55 G3 2V24 E3 3A21 A2 3A63 A2 3B01 C1 3C41 B3 3G07 F3 3G39 F3 3H26 D2 3J68 B4 3L59 B3 3LM0 B2 3LR5 C2 3LU7 C3 3M71 A2 3P15 G1 3P37 F1 3P80 F1 3U69 G3 5TG4 A1 7U13 G2
1C61 A3 2A40 A4 2A61 A4 2A83 A2 2AB8 A3 2C15 A3 2C57 A3 2G20 F3 2G41 G3 2J48 C4 2L54 B3 2P04 G1 2P50 F1 2T07 A1 2T31 B1 2TG7 A1 2TK8 A1 2U14 G2 2U60 F2 2V25 E4 3A22 A2 3A64 A2 3B02 C1 3C45 A3 3G08 F3 3G41 F3 3H40 D3 3J69 B3 3L60 B3 3LM1 B1 3LR6 C2 3LU8 C3 3M72 A2 3P16 G1 3P38 F1 3P81 F1 3U70 G3 5TG5 A1 7U14 G4
1C62 A3 2A41 B4 2A62 A4 2A84 A2 2B00 C1 2C16 B3 2C58 A3 2G21 F3 2G42 F3 2J49 C4 2L55 C4 2P06 F1 2P51 G2 2T08 A2 2T32 B1 2TG8 B1 2TK9 A1 2U15 G3 2U61 F2 2V26 D3 3A23 A2 3A65 A2 3B03 C1 3C50 A3 3G17 F4 3G42 F4 3H41 D3 3J70 B4 3L61 B3 3LM2 B2 3LR7 C2 3LU9 C4 3M73 B2 3P17 G1 3P40 F1 3P82 F1 3U71 G3 5TG6 A1 7U15 G2
1E41 A4 2A42 B4 2A63 A4 2A89 A2 2B01 C1 2C17 B3 2C60 A3 2G22 F3 2G43 F3 2J57 C4 2L56 B3 2P07 F1 2P76 F1 2T09 A1 2T33 B1 2TG9 B1 2TL0 A1 2U16 G3 2U63 F2 2V27 D3 3A24 B2 3A67 A2 3B04 C1 3C53 A3 3G18 F4 3G43 F3 3H89 D3 3J71 B4 3L62 B3 3LM3 B1 3LR8 C2 3LV0 C4 3M74 A2 3P18 G1 3P43 G1 3P83 F1 3U72 F2 5TG7 B1 7U17 G3
1P02 G1 2A43 B4 2A64 A4 2A90 B2 2B02 C1 2C18 B3 2C63 A3 2G23 F4 2G44 F3 2J61 C4 2L57 B3 2P09 G1 2P77 F1 2T10 A1 2T34 B1 2TJ0 A1 2TL7 A1 2U18 G3 2U64 F2 2V28 E3 3A25 B2 3A68 A2 3B05 C1 3C55 A3 3G20 F3 3G44 F3 3H92 E2 3J72 B3 3L63 C3 3LM4 B2 3LR9 C2 3LV1 C4 3M75 B2 3P19 G1 3P45 F1 3P84 F1 3U73 F2 5TG8 A1 7U18 G3
1T41 A2 2A44 B4 2A65 A4 2A92 A4 2B37 B1 2C19 B3 2C65 A3 2G24 F3 2H11 E2 2J71 C4 2LT1 B4 2P10 F1 2P80 F1 2T11 A1 2T35 A1 2TJ1 A1 2TL9 B1 2U19 G3 2U65 F3 2V29 E3 3A26 A2 3A69 A2 3B06 C1 3C56 A3 3G21 F3 3G45 F3 3J02 C3 3J73 B3 3L64 C3 3LM5 B1 3LS0 C2 3LV2 C4 3M76 A2 3P20 G1 3P50 G1 3P85 F2 3U74 F2 5U10 G4 7U19 G3
1T44 A1 2A45 B4 2A66 A4 2A93 A2 2B38 B1 2C20 B3 2C67 A3 2G25 F3 2H12 E2 2J72 C4 2LT3 C3 2P15 G1 2P81 F1 2T12 A1 2T43 A1 2TJ2 A1 2TM2 A1 2U20 G3 2U66 F3 2V30 D3 3A27 A2 3A71 A2 3B07 C1 3C57 A3 3G23 F3 3G47 F3 3J05 C3 3J74 B4 3L65 C3 3LM6 B1 3LS1 C2 3LV3 C4 3M77 A2 3P21 F2 3P51 G1 3P86 F2 3U75 F2 5U11 G4 7U20 F2
1T55 A2 2A46 B4 2A67 A4 2A97 A4 2BA0 B1 2C22 B3 2C68 A3 2G26 F4 2H13 E2 2J73 C4 2LT4 C4 2P16 F1 2P82 F1 2T13 A1 2T45 A1 2TJ3 B1 2TM3 A1 2U21 G3 2U71 G4 2V31 E3 3A29 A2 3A72 A2 3B08 C1 3C58 A3 3G25 F3 3G48 F3 3J06 C2 3J75 B3 3L66 C3 3LM7 B2 3LS3 B1 3LV4 C4 3M78 B2 3P22 F2 3P52 G1 3P88 F1 3U76 F2 5U12 G4 7U21 F2
1TG0 A1 2A47 B4 2A68 A4 2A98 A2 2BA2 B1 2C23 B3 2C70 A3 2G27 F4 2J30 B4 2J74 B4 2LT5 C4 2P18 G1 2Q60 D2 2T14 A1 2T48 A1 2TJ4 A1 2TM4 A1 2U23 G3 2U72 G3 2Z20 E1 3A30 A2 3A73 A2 3B23 C1 3C59 A3 3G26 F3 3G49 F3 3J14 C2 3J76 B3 3L67 C3 3LN0 C1 3LS4 B1 3LV5 C4 3M79 A2 3P23 F2 3P53 G1 3Q01 E2 3U77 F2 5U13 G4 7U22 F2
1TG1 B1 2A48 A4 2A69 B4 2A99 A2 2BA3 B1 2C27 B3 2C72 A3 2G28 F3 2J31 B4 2J76 C4 2LT6 C2 2P19 G1 2Q61 D2 2T15 A1 2T51 A1 2TJ5 A1 2TM5 A1 2U26 G3 2U73 G3 2Z22 E1 3A37 A2 3A74 A2 3B40 B1 3C60 A3 3G27 F3 3G51 F4 3J25 C4 3J77 B3 3L68 C3 3LN1 C2 3LS5 B1 3LV6 C4 3M80 B2 3P24 F2 3P57 F1 3Q10 F2 3U80 G3 5U14 G4 7U24 G2
1U02 F3 2A49 A4 2A70 B4 2AA3 B3 2BA8 B1 2C28 B3 2C78 A3 2G29 F3 2J32 B4 2K40 A3 2M90 B2 2P20 F1 2Q62 D2 2T16 A1 2T53 A1 2TJ6 A1 2TM7 A1 2U31 G3 2U85 G3 2Z26 E1 3A38 A2 3A75 A2 3B60 C1 3C61 A3 3G28 F3 3G52 F3 3J26 C4 3J86 C4 3L69 C3 3LN2 C2 3LS6 B1 3LV7 C4 3M81 B2 3P25 F2 3P60 F2 3Q16 D4 3U82 G3 6A00 A2 7U27 G4
1Z55 E1 2A50 A4 2A71 B4 2AA5 B2 2C03 A3 2C31 A3 2C79 A3 2G30 F3 2J33 B4 2K41 A3 2M91 B2 2P22 G1 2Q67 D3 2T17 A1 2T55 A2 2TJ7 A1 2TM8 A1 2U32 G3 2V00 E3 2Z28 E1 3A41 A2 3A76 A2 3B61 B1 3C65 A3 3G29 F3 3G53 F3 3J28 C4 3J87 C4 3L70 C3 3LN3 C2 3LS7 B1 3LV8 C4 3M82 B2 3P26 F2 3P61 F2 3Q20 D3 3U83 G3 6A01 A2 7U28 G4
2A01 B4 2A51 A4 2A72 B4 2AA6 B2 2C04 A3 2C35 A3 2C83 A3 2G31 F4 2J34 B3 2K43 A3 2M92 B2 2P23 G1 2Q85 E4 2T18 A2 2T56 A2 2TJ8 A1 2TN0 B1 2U33 G4 2V01 D3 3A03 A4 3A42 B2 3A77 A4 3B90 B1 3C66 A3 3G30 F3 3G54 F3 3J48 C4 3J92 C4 3L71 C3 3LN4 C2 3LT3 B4 3M00 A2 3M85 B1 3P27 G2 3P62 G1 3Q21 D3 3U85 G2 6A10 A4 7U29 G3
2A25 B4 2A52 A4 2A73 B4 2AA8 B4 2C05 A3 2C36 A3 2G11 F4 2G32 F4 2J35 B3 2K45 A3 2M93 A2 2P24 F2 2Q86 D4 2T19 A1 2T58 A1 2TJ9 A1 2TN1 A1 2U37 G2 2V16 D3 3A07 B3 3A43 A2 3A80 B2 3B92 B1 3C67 A3 3G31 F3 3G57 F4 3J60 B4 3J94 C4 3L89 B3 3LN5 C2 3LT4 B4 3M01 A2 3M86 B1 3P28 G2 3P63 G1 3Q23 D3 3U86 G2 6B22 B1 7V00 E3
2A29 A4 2A53 A4 2A74 B4 2AA9 B4 2C06 A3 2C39 A3 2G12 G3 2G33 F3 2J40 C4 2K46 A3 2M94 A1 2P25 G2 2Q90 D4 2T20 A1 2T98 A1 2TK0 A1 2TN3 A1 2U38 G3 2V17 D3 3A08 B3 3A44 B2 3A81 B2 3B93 B1 3C71 A3 3G32 F3 3G58 F4 3J61 B4 3J99 C4 3L99 C3 3LN6 C2 3LT5 B4 3M02 A2 3N20 C1 3P29 G2 3P73 F1 3Q24 D3 3U87 G2 6B23 B1 7Z00 E1
2A33 A4 2A54 A4 2A75 A4 2AAA B4 2C07 A3 2C40 B3 2G13 F3 2G34 F3 2J41 C4 2K47 A3 2N05 C1 2P31 F2 2Q91 F4 2T21 A1 2TG0 B1 2TK1 A1 2TN4 B1 2U39 G4 2V18 E3 3A09 B3 3A45 B2 3A82 B2 3B99 B1 3G01 F3 3G33 F3 3G59 F4 3J62 B4 3L50 B3 3LA9 C2 3LN7 C2 3LT6 B4 3M03 A2 3N25 C1 3P30 G2 3P74 G1 3Q29 E4 3U88 G2 6C51 A3 7Z02 E1
2A34 A4 2A55 A4 2A76 A4 2AAB B4 2C08 A3 2C41 A3 2G14 F3 2G35 F3 2J42 C4 2K64 A3 2N06 C1 2P32 G1 2Q92 F3 2T23 A1 2TG1 A1 2TK2 A1 2U08 G2 2U40 G3 2V19 D4 3A10 B3 3A56 A2 3A83 B2 3C30 A3 3G02 F3 3G34 F3 3G60 F4 3J63 B4 3L51 C4 3LE1 C2 3LQ6 C2 3LT7 B4 3M04 A2 3P10 G1 3P31 G2 3P75 G1 3Q30 E4 3U89 G2 6C52 A3 7Z10 D1
2A35 A4 2A56 A4 2A77 A4 2AB1 B2 2C09 A3 2C44 B3 2G15 F3 2G36 F3 2J43 C4 2K65 A3 2N08 C1 2P33 G1 2T01 A1 2T24 A1 2TG2 A1 2TK3 A1 2U09 G3 2U41 G3 2V20 D3 3A11 B3 3A59 A2 3A84 B2 3C32 A3 3G03 F3 3G35 F3 3H04 E2 3J64 B4 3L52 B3 3LG2 C2 3LR0 C2 3LT8 B4 3M05 A2 3P11 G1 3P32 F1 3P76 F1 3Q31 F3 3U90 F3 6C59 A3 7Z11 D1
2A36 A4 2A57 A4 2A78 A4 2AB2 A2 2C11 A3 2C45 A3 2G16 F3 2G37 F4 2J44 C4 2L50 C3 2N10 C1 2P34 F1 2T02 A1 2T25 A1 2TG3 A1 2TK4 B1 2U10 G3 2U43 G2 2V21 E4 3A12 B3 3A60 A3 3A85 B2 3C34 A3 3G04 G3 3G36 F3 3H05 E2 3J65 B4 3L56 B3 3LH2 C2 3LR1 C2 3LU4 C3 3M09 A2 3P12 F1 3P33 G1 3P77 F1 3Q32 F3 3U91 F3 6G01 F4 7Z12 D1
2A37 A4 2A58 A4 2A79 B2 2AB3 B2 2C12 A3 2C46 A3 2G17 F4 2G38 G4 2J45 C4 2L51 C3 2N11 C1 2P35 F1 2T04 A1 2T27 A1 2TG4 B1 2TK5 A1 2U11 G3 2U44 G2 2V22 E3 3A14 B2 3A61 A3 3A86 B4 3C39 B3 3G05 F4 3G37 F3 3H24 D2 3J66 B4 3L57 B3 3LH7 C2 3LR3 C2 3LU5 C3 3M14 A2 3P13 G1 3P35 F1 3P78 F1 3Q42 D4 3U92 F3 6H07 C3 9A08 A4
3Q64 E2 3U93 G2 6H08 D3 9A19 A4
3Q82 E4 3U94 G2 6H09 D3 9A29 A4
3Q97 F3 3U95 G2 6J01 C4 9A75 B4
3Q98 F3 3U96 G3 6J06 C4 9A77 B4
3T02 A1 3U97 G3 6L00 C4 9A78 B4
3T03 A1 3U98 F3 6L01 C4 9A79 B3
3T04 A1 3U99 F2 6L02 C3 9A82 A2
3T05 A1 3UA1 G3 6M10 A2 9A83 A2
3T06 A1 3UA2 G3 6M11 A2 9A86 B2
3T07 A1 3UA3 G3 6P00 F1 9A90 B2
3T08 A1 3UA4 G3 6U00 G2 9B03 C1
3T09 B1 3UA5 G3 6U01 G2 9B30 B1
3T10 A1 3UA6 G2 6U12 G3 9B31 B1
3T11 A1 3UA8 G4 6U17 G3 9B38 B1
3T12 B1 3UA9 G4 6U21 G3 9C46 B4
3T13 B1 3V00 E3 6U22 G4 9C50 A3
3T14 B1 3V01 D3 6U23 G4 9C51 A3
3T15 A1 3V02 E3 7A01 B4 9C52 A3
3T16 A1 3V03 D3 7A02 B3 9C53 A3
3T17 A1 3V04 E3 7A04 A2 9C54 A3
3T18 A1 3V05 D3 7A06 B2 9C56 A3
3T19 B1 3V06 E3 7A10 A2 9C57 A3
3T20 B1 3V07 D3 7A12 A2 9C58 A3
3T21 B1 3V08 E3 7A13 B4 9C59 A3
3T22 B1 3V09 D3 7A14 B2 9C60 A3
3T23 B1 3V10 E3 7A20 B4 9C61 A3
3T24 B1 3V11 D3 7A21 B4 9G10 F4
3T25 A1 3V12 E3 7B00 C1 9G12 F3
3T26 B1 3V13 D3 7B01 C1 9G13 F3
3TG2 A1 3V14 E3 7B02 C1 9G14 F3
3TG3 A1 3V15 D3 7B11 B1 9G30 F3
3TG4 A1 3V16 E3 7B30 B1 9G35 F3
3TG5 A1 3V17 D3 7B31 B1 9H14 E2
3TG6 A1 3V18 E3 7B38 B1 9H40 D3
3TG8 B1 3V19 E3 7C31 A3 9J18 C4
Part 2 3TG9 B1 3V20 E3 7C53 A3 9J19 C4
3TH0 A1 3V21 D3 7C54 A3 9J20 B3
F_15400_055b.eps 3TH3 A1 3V22 E3 7C55 A3 9J21 B3
3TH4 A1 3V23 E3 7G01 F4 9LA5 B1
3TH5 A1 3V32 E3 7G02 F3 9LA7 C2
3TH6 B1 3V33 D3 7G03 F3 9M00 A2
3TH7 B1 3V34 E3 7G31 F4 9M01 B2
3TH9 A1 3V35 E3 7G32 G3 9M02 B1
3TJ0 B1 3V36 E3 7G33 F3 9M04 B1
3TJ1 B1 3V37 D3 7G34 F3 9M05 B2
3TJ2 A1 3V38 E3 7G35 F3 9M06 A2
Part 1 3TJ3 B1 3V39 E3 7G37 F4 9P01 F1
3TJ4 A1 3V40 E3 7H01 F4 9P05 F1
F_15400_055a.eps 3TJ5 A1 3V41 D3 7H02 D3 9P06 F1
3TJ6 B1 3V42 E3 7J00 C2 9P07 F1
3TJ7 B1 3V43 D3 7J06 C4 9P08 F1
3U00 G3 3Z00 E1 7J07 C4 9P09 F1
3U01 G3 3Z10 E1 7J08 C2 9P10 G1
3U02 G3 3Z11 E1 7J10 B4 9P16 F1
3U03 G3 3Z47 E1 7J11 B4 9P17 F1
3U04 G3 3Z48 E1 7J12 B3 9P18 F1
3U05 G3 3Z53 D1 7J13 B4 9P19 F2
3U06 G3 5A01 A4 7LA2 B1 9P30 G1
3U07 G3 5A02 A4 7LB0 C4 9P31 G1
3U08 G3 5A03 A4 7LB1 C4 9P32 G1
3U09 G2 5A04 A4 7LB2 C3 9P33 F2
3U10 G3 5A05 A4 7LB4 B4 9P34 F2
3U11 G3 5A08 B4 7LB5 B4 9P35 G1
3U12 G3 5A10 B4 7M01 A2 9P36 F2
Part 4 3U13 G3 5B00 C1 7M03 A2 9P37 F2
3U14 G3 5B02 C1 7M04 A2 9P38 F1
F_15400_055d.eps 3U15 G3 5B20 B1 7M05 B2 9P39 F1
3U16 G3 5C01 B3 7M06 A1 9P40 F1
3U17 G3 5C03 B3 7M07 A2 9P41 F1
3U18 G3 5C33 A3 7M10 A2 9P42 F1
3U19 G2 5C35 B3 7M11 A2 9P79 F1
3U22 G3 5C36 B3 7M12 A2 9Q13 D3
3U23 G3 5C57 A3 7N00 C1 9Q14 D3
3U24 G3 5H02 D3 7O00 D1 9Q15 D3
3U26 G3 5H03 D3 7P00 F1 9Q16 D3
3U27 G3 5H04 D3 7P03 G1 9Q17 D3
3U28 G3 5J08 B4 7P10 G2 9Q18 C3
3U29 G3 5J09 B4 7P13 F2 9Q30 D4
3U30 G3 5J13 C2 7P14 F1 9Q60 F3
3U31 G3 5J14 C4 7P15 F1 9Q61 F3
3U32 G3 5J15 B4 7P16 F1 9Q62 F3
3U33 G3 5J16 B4 7P17 F1 9Q63 F3
3U34 G4 5P02 F1 7P18 F1 9T04 A1
Part 3 3U35
3U36
G4
G3
5P08
5Q00
F1
E4
7P31
7P32
F2
G1
9T10
9T11
B1
B1
F_15400_055 c.eps 3U37
3U38
G3
G3
5Q06
5Q07
E2
D2
7P34
7P74
G2
G1
9TG2
9TG3
A1
A1
3U39 G2 5Q08 D2 7P76 F1 9U01 F3
3U41 G3 5Q11 D4 7P77 F1 9U02 F3
3U42 G3 5Q12 D4 7P80 F1 9U03 G3
3U43 G4 5Q13 D4 7P81 F1 9U07 F3
3U45 G3 5T10 A1 7Q01 D3 9U13 F2
3U46 G3 5T11 B1 7Q05 F3 9U14 F2
3U52 G4 5T42 A2 7T00 A2 9U15 F3
3U53 G4 5T44 A1 7T10 B1 9U16 F2
3U54 G2 5T45 A1 7T11 A1 9Z47 E1
3U55 G2 5T46 A1 7T12 B1
3U56 G2 5T47 A1 7T41 A1
3U57 G2 5T48 A1 7T43 A1
3U60 G2 5T49 A1 7TG0 B1
3U61 G2 5T50 A1 7TG1 A1
3U62 G3 5T51 A1 7TG3 A1
3U63 G3 5T53 A1 7TG4 A1
3U64 G3 5T55 A2 7U00 G3
F_15400_055.eps 3U65 G3 5TG0 A1 7U05 G3
3U66 G3 5TG1 A1 7U07 G4
3104 313 6037.6 260405
3U67 G3 5TG2 A1 7U10 G3
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 86

Layout Small Signal Board (Part 1 Bottom Side)

Part 1

F_15400_055a.eps
260405
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 87

Layout Small Signal Board (Part 2 Bottom Side)

Part 2

F_15400_055b.eps
260405
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 88

Layout Small Signal Board (Part 3 Bottom Side)

Part 3

F_15400_055c.eps
260405
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 89

Layout Small Signal Board (Part 4 Bottom Side)

Part 4

F_15400_055d.eps
260405
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 90

External I/O Panel: Externals A

1 2 3 4 5 6 7 8 9 10 11 12 13
1000 G1 3050 D1 I017 G6
1001 E1 3051 D3 I018 B12

BE1 EXTERNALS A BE1

1002-1 C1
1002-2 D1
1002-3 B1
3052 D1
3060 E2
3061 E3
I019 B12
I020 B11
I021 C12
1003 H1 3065 F11 I022 C12
1004 I10 3070 B7 I023 C11
1005 F10 3071 B7 I024 E11
1006 I1 3072 B8 I025 D12
A +8V +8V
A 1007 D10 3073 B7 I026 E12

MONITOR - OUT EXTERNAL I/O 1 VREF EXTERNAL I/O 3 VREF

1008 G10
1009 H6
3074 B6
3075 C6
I028 C3
I029 C1
+8V 1011 H7 3076 C7 I030 D1

2036

100n

2004

100n
1012 E10 3077 C7 I031 C3
1014 I6 3078 C8 I032 I2

3070

3006
22K

22K
I005 3038 Y-CVBS-MON-OUT
7003 PR PR 1015 F6 3079 C7 I033 C10
BC847BW 1030-3 1050-3
100R F017 2035 3071 I037 F026 2007 3007 I018 1016 B1 3080 E6 I034 B10
CVBS F016 5 6 7010 F025 5 6 7000
1002-3 BC847BW BC847BW 1017 G6 3081 D7 I035 E10
F024 F005 3040 I004 6045 22u 16V I048 100R 3072 AV1-AV5-AV6_R-PR 6004 22u 16V I020 100R 3010 1018 C1 3082 E7 I036 E2
2 1 9005 YKC21-5637 YKC21-5637 AV2-AV4_R-PR
1019 D1 3083 E7 I037 B7

3074

3011
75R

75R
68R RES RED I038 100R RED I019 100R
B YKC21-4782N
B 1020-1 I5 3084 E8 I038 B8

560R

560R
3073

3014
YELLOW I039 BAV99 COL I034 BAV99 COL 1020-2 G5 5000 I3 I039 B5
560R
3042

3043

1024

1022
PDZ6.8-B

10K
1020-3 F5 6000 G1 I040 C7
1016

6020

PDZ6.8-B

PDZ6.8-B
1021 H10 6001 H10 I041 C8

6007
6046
1022 B10 6002 G1 I042 C5

2037

100n

2014

100n
1023 G11 6003 H10 I043 E7
1024 B5 6004 B10 I044 E8
VREF +8V VREF +8V
1025 D5 6005 H1 I045 E7
I028 10u 16V
3044
AUDIO-OUT2-L +8V +8V 1026 E5 6006 I10 I046 E5
LEFT 150R
1027 E1 6007 B10 I047 C7
2019

3076

3017
1002-1 1030-1 E5 6008 H1 I048 B7

22K

22K
F006 3046 I006
6 5 6 PB PB 1030-2 C5 6009 I10 I050 E2
C 1030-2 1050-2
C
PDZ6.8-B

100R 3047 I031 F019 2038 3077 I040 F027 2015 3020 I021 1030-3 B5 6010 C10 I051 E3
6023

YKC21-4782N 7004-1 2 A-PLOP 3 4 7011 3 4 7001

WHITE BC847BS BC847BW BC847BW 1040-1 I1 6011 D10 I052 I3
I008 1K0 6047 22u 16V I047 100R 3078 AV1-AV5-AV6_B-PB 6010 22u 16V I023 100R 3022
1 YKC21-5637 YKC21-5637 AV2-AV4_B-PB 1040-2 G1 6012 G12
100K
1018

3048

2021

100p

3075

3023
1040-3 F1 6013 H7

75R

75R
I029 BLUE I041 100R BLUE I022 100R
1050-1 D9 6014 E10

560R

560R
3079

3024
PDZ6.8-B

I042 BAV99 COL I033 BAV99 COL 1050-2 C9 6015 E10

6024

1025

1007
1050-3 B9 6017 I6

PDZ6.8-B

PDZ6.8-B
1060-1 I9 6018 F6

6011
6048
3049 10u 16V 1060-2 H9 6019 F6
AUDIO-OUT2-R 1060-3 F9 6020 B1
RIGHT +8V
1002-2
150R I009 2022
+8V +8V +8V
1070 H5 6021 G6
3050 I011 1080 G9 6022 G6
D 4 3 F007 3 VREF VREF
D 2002 G2 6023 C1
PDZ6.8-B

100R 3051
6025

2016

100n
YKC21-4782N 7004-2 5 A-PLOP 2004 A12 6024 D1

2039

100n
RED BC847BS
I010 1K0 2005 H11 6025 D1

3027
4

22K
Y 2007 B11 6026 E1
100K
1019

3052

2023

100p

I030 2010 H2 6027 F10

3081
1050-1

22K
F029 2017 3030 I025
Y 1 2 2012 I11 6029 I2
PDZ6.8-B

7002
6026

1030-1 I043 BC847BW 2014 B10 6030 I2

F021 2040 3082 6014 22u 16V I024 100R 3031
1 2 7012 YKC21-5637 AV2-AV4_G-Y
2015 C11 6040 E2

3032
BC847BW

75R
6049 22u 16V I045 100R 3084 AV1-AV5-AV6_G-Y GREEN I026 100R 2016 D12 6041 E2
YKC21-5637
2017 D11 6045 B6

560R
3080

3033
75R
GREEN I044 100R I035 BAV99 COL
2018 F7 6046 B5

1012
SPDIF OUT
1001
E E

560R
3083
2019 C3 6047 C6

PDZ6.8-B
I050 I051 2042 I046 BAV99 COL
2 1 3061
1026

6015
SPI-OUT 2020 G6 6048 D5

PDZ6.8-B
220R 100n 2021 C2 6049 E6
YKC21-3894N 6040 6050
2022 D3 6050 E5
RES
120R
1027

3060

2030

100p

BLACK
+8V 2023 D2 7000 B12
PDZ6.8-B
I036 2030 E3 7001 C12
6041 +8V 2035 B7 7002 E12

PDZ6.8-B
H EXTERNAL I/O 2 2036 A8
2037 B6
2038 C7
7003 B2
7004-1 C2
7004-2 D2
1020-3
F014 AV1-AV6_FBL-HSYNC
CVBS 2039 D8 7010 B8
5 6 1060-3 2040 E7 7011 C8
F010 3065
F 5 6
F
PDZ6.8-B
AV2_Y-CVBS
YKC21-5637
6018
2041 I3 7012 E8

EXTERNAL I/O 1
100R 2042 E3 9005 B2
BLACK YKC21-5637

PDZ6.8-B
2I24 I3 F000 F1

1005

3018
6027

75R
YELLOW
I016
1015

3039

2018
3000 F2 F001 G1

1K0
LEFT

47p
1040-3
PDZ6.8-B
I001 3002 H10 F002 G11
3000
6019

5 6 F000 AUDIO-IN1-L 3004 G2 F003 G10

PDZ6.8-B

100R 3005 H11 F005 B1

6000

YKC21-5637
WHITE SVHS
3006 B11 F006 C1
100K
3004

2002

100p

V 1080 3007 B12 F007 D1

1000

I000 1020-2 1
F015 YKF51-5535 3008 G2 F008 H10
3 4
PDZ6.8-B

AV6_VSYNC
3010 B13 F009 I10
6002

PDZ6.8-B

5 3
3011 B11 F010 F10
G G
6021

YKC21-5637
F002 3025
BLACK 6 4 AV2_C 3012 I10 F011 I1
100R 3014 B12 F012 H7
I017
1017

3045

2020

RIGHT

PDZ6.8-B
1K0

2
47p

3015 H2 F013 I6

1008

1023

3028

6012
1040-2
PDZ6.8-B

75R
F001 3008 I003 3016 I11 F014 F6
6022

3 4 AUDIO-IN1-R F003
3017 C11 F015 G6
PDZ6.8-B

100R
3018 F10 F016 B4
6005

YKC21-5637
RED 3020 C12 F017 B5
100K
3015

2010

100p

SVHS LEFT 3021 I2 F018 I4

1003

I002 1070 1060-2 F008 3002 I012 3022 C13 F019 C5

YKF51-5535 3 4
PDZ6.8-B

1 AUDIO-IN2-L
3023 C11 F020 I9
6008

PDZ6.8-B
100R
5 3024 C12 F021 E5

6001
3 YKC21-5637
H F012 3026
WHITE
H 3025 G12 F023 I1

100K
3005

2005

100p
6 4 AV7_C
I014
3026 H8 F024 B1

1021
100R 3027 D11 F025 B9
PDZ6.8-B

PDZ6.8-B
2
3028 G12 F026 B10
1009

1011

3029

6013

6003
75R

3029 H7 F027 C10

SPDIF IN
1040-1
EXTERNAL I/O 3 RIGHT
BLACK
1060-1
3030 D12
3031 E13
3032 E11
F029 D10
I000 G1
I001 F2
5000 I052 2041 F009 I013
F023
1 2
F011
SPI-1 1 2
3012
AUDIO-IN2-R
3033 E12 I002 H1
F020
3035 I7 I003 G2

PDZ6.8-B
100n 100R

6006
YKC21-5637 6029 CVBS YKC21-5637 3037 I6 I004 B2
1006

3021

2I24

1020-1
75R

12p

BLACK F013 RED 3038 B2 I005 B2

3035
I I

100K
3016

2012

100p
F018 1 2 AV7_Y-CVBS
PDZ6.8-B I015 3039 F6 I006 C2

1004
I032 100R 3040 B1 I008 C3
YKC21-5637

PDZ6.8-B
6030
3042 B2 I009 D2

6009
YELLOW
PDZ6.8-B
1014

6017

3037

3043 B2 I010 D2
75R

PDZ6.8-B
3044 C2 I011 D2
3045 G6 I012 H12
F_15400_057.eps 3046 C1 I013 I12
3104 313 6048.4 090505 3047 C3
3048 C2
I014 H10
I015 I10
3049 D2 I016 F6
1 2 3 4 5 6 7 8 9 10 11 12 13
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 91

External I/O Panel: Externals B

1 2 3 4 5 6 7 8 9
1010 E8 F110 B3
1100 E8 F111 B3

BE2 EXTERNALS B BE2 1101 E8

1102 F8
F112 B3
F113 B3
1E40 A3 F114 B3
1E62 D3 F115 B3
1E40 1M20 E3 F117 C3
AV2-AV4_R-PR F100 I111 I100
1 3153 1M36 B9 F118 C3
AV2-AV4_G-Y F101 I123
2 +8V FRONT_C 1X01 F5 F119 C3
AV2-AV4_B-PB F102 9210
3 1R0
I109 1X02 F6 F120 E2

100u 16V
4 I124 FRONT_Y-CVBS

2124

100n

2125

2126

2252

100p
1X03 F7 F121 F3

1u0
A AV2_C
AV2_Y-CVBS
F103
5
6 5100
9211
I125 AUDIO-IN5-L
A 1X04 F8 F122 F3

2249

100p
F104 +8V6 I110
7 1X05 F8 F124 C3
+8V6 F105 9212
8 I126 AUDIO-IN5-R 2124 A6 F125 C3

2248

100p
Y-CVBS-MON-OUT F106
9
9213 2125 A6 F126 C3
10

2247

100p
11 3154 I101 2126 A7 F127 D3
AV6_VSYNC VREF 2127 B6 F128 E8
12

BZX384-C2V7
13 680R F217 F200 F201 2128 B7 F133 D3

22u 10V
14 F214 2129 C6 F134 D3

6102

2127

2128

100n
15
AUDIO-OUT2-L F109 2130 C7 F136 D3
16
AUDIO-OUT2-R F110
17 2131 D7 F137 E3
F111
18 TO 1E40 1M36 2132 D6 F138 E3
AUDIO-HDPH-L
B AUDIO-HDPH-R F112
19
20 1
B 2133 E2
2134 E2
F139 E2
F140 E2
21 2
AV7_Y-CVBS F113 2135 F2 F141 F9
22 3
AV7_C F114
23 SSB Bx2.x I120 I121 3156 I122 I102 4 TO 1M36 2136 F3 F142 F9
+5V2-STBY F115 +5V2-STBY +5V 2137 F3 F143 D3
24 5
25 1R0 6 2138 F2 F144 E8

100u 16V
26 7 2139 F2 F145 E8

2129

100n

2130
AUDIO-IN1-L F117
27 8
AUDIO-IN1-R F118 SIDE I/O 2140 F2 F146 C3
28 9
29 10 2141 F2 F147 F2
AUDIO-IN2-L F119 2247 A9 F148 F2
30 11
AUDIO-IN2-R F146
31
B11B-PH-K
2248 A8 F149 F2
32 2249 A8 F150 F2
FRONT_Y-CVBS GNDB
C FRONT_C
33
34
F204
9220
AUDIO-HDPH-L C 2250 C9 F151 E3
35 2251 D8 F152 E3

2250

100p
AUDIO-IN5-L 36 2252 A8 F153 E3

+5V

+5V
AUDIO-IN5-R
F124
37 3153 A6 F154 E3
LED1 38
KEYBOARD F125 3154 A6 F155 E3
39
RC F126 GNDB 3156 B6 F156 D3
F127
40
40FMN-BMT-A-TFT GEMSTAR 2131
F203
9221
AUDIO-HDPH-R
3157 D6
3158 D6
F157 D3
F158 D3

3157

2251

100p
1E62

4K7
AV1-AV5-AV6_R-PR
3159 D7 F159 D3
F156
1 16V 10u 3160 E6 F200 B8
AV1-AV5-AV6_G-Y F157
2
AV1-AV5-AV6_B-PB F158 I103 I104 3161 E6 F201 B8
3 3158
GNDB 3999 F9 F203 D8
D AV1-AV6_FBL-HSYNC F159
4
5 4K7 6101
D 5100 A6 F204 C8
6 2132 6100 E6 F205 F9
F133 BC857BW
7 7106 PLVA2650A 6101 D9 F214 B8
SPI-1 F134
9222
8 TO 1E62 7107
100p 3159 I108
6102 B6 F217 B7
9 GLINK-IR-OUT
SPI-OUT F136 PDTC114EU 7106 D7 I100 A6
10 10R
GLINK-IR-OUT F143 I105 7107 D6 I101 A7
11
GLINK-TXD F137
12 9100 E1 I102 B6
GLINK-RXD F138
13 SSB Bx2.x 9101 E1 I103 D6
A-PLOP F151
14
F128
9104 F3 I104 D7
15
SCL-MM-BUS2 F152
16 9105 F3 I105 D7
SDA-MM-BUS2 F153 1 1010 9106 E1 I108 D8
17
LED2 F154 2
E LIGHT-SENSOR F155
18
19 GLINK-TXD
RES 3160 F144
5
4
GEMSTAR
CONNECTOR
E 9107 F1
9108 F1
I109 A6
I110 A6
20 220R F145
KEYBOARD 9100 F139 3161 3 9109 F1 I111 A6
GLINK-RXD
2133 20FMN-BMT-A-TFT 220R RES LGY3319-0111 9110 F1 I120 B5
100p 1100
LED1 9101 F140 9205 F9 I121 B6
1M20
2134 6100
9106 100p F120
1101 9210 A9 I122 B6
RC 1
2135 9211 A9 I123 A9
LIGHT-SENSOR 2 PLVA2650A RES 1102
9107 100p F147 9212 A9 I124 A9
2138
3 TO 1M20 F141 3999 F142
4 9213 A9 I125 A9
100p
5 100R 9220 C9 I126 A9
+8V6 9105 F121 1X01 1X02 1X03 1X04 1X05
2136
6 9221 D9 I213 F9
7 EMC HOLE EMC HOLE EMC HOLE EMC HOLE EMC HOLE
100p LED PANEL 9205 9222 D3
F LED2 9108
2139
F148
9104
8
9 I213 F F100 A3
+5V2-STBY F122
10
F205 F101 A3
100p 2137
SCL-MM-BUS2 11 F102 A3
9109 F149 100p
2140
12 GNDB F103 A3
SDA-MM-BUS2 9110 100p F150 F104 A3
2141 B12P-PH-K F105 A3
100p F106 A3
F109 B3
F_15400_058.eps
3104 313 6048.4 290405

1 2 3 4 5 6 7 8 9
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 92

Layout External I/O Panel (Top Side) Layout External I/O Panel (Bottom Side)
1001 D1
2002 A1 6049 B1
1002 D2
2005 C1 6050 B1
1010 D2
2010 A1 7003 D1
1020 A1
2012 C1 7012 B2
1030 A1
1040 A2 2014 B1 9005 D1
1050 D2 2018 A2 9108 A1
1060 D2 2020 A2 9109 A1
1070 B1 2021 D2 9110 A1
1080 C1 2023 D1 9205 A2
1E40 A1 2030 D2 9211 A2
1E62 C1 2037 A1 9212 A2
1M20 A2 2039 B1 9213 A2
1M36 A1 2041 B1 9220 A2
2004 B1 2042 D2 9221 A2
2007 B2 2124 A1
2015 C1 2126 A1
2016 C1 2139 A1
2017 D1 2140 A1
2019 D1 2141 A1
2022 D2 2247 A2
2035 A2 2248 A2
2036 A2 2249 A2
2038 A2 2250 A2
2040 B2 2251 A2
2125 A2 2I24 B1
2127 A2 3000 A1
2128 A2 3002 C1
2129 D2 3004 A1
2130 D2 3005 C1
2131 D2 3008 A1
2132 D2 3011 B1
2133 A2 3012 C1
2134 A2 3014 B2
2135 A2 3015 A1
2136 A2 3016 C1
2137 A2
3018 C1
2138 A2
3021 B1
2252 A1
3023 C1
3006 B2
3025 C2
3007 B2
3026 B2
3010 B1
3028 C2
3017 C1
3020 C1 3029 B2
3022 C1 3032 C1
3024 C1 3035 B2
3027 C1 3037 B2
3030 C1 3038 D1
3031 C1 3039 A2
3033 C1 3040 D1
3070 A2 3042 D1
3071 A2 3043 D1
3072 A2 3044 D2
3073 A2 3045 A2
3076 A2 3046 D2
3077 A2 3047 D1
3078 A2 3048 D2
3079 A2 3049 D1
3154 A2 3050 D1
3156 D2 3051 D2
3157 D2 3052 D1
3158 D2 3060 D2
3159 D2 3061 D2
3160 D2 3065 B1
3161 D2 3074 A1
5100 A2 3075 A1
6100 D2 3080 B1
6101 D2 3081 B1
6102 A2 3082 B1
7000 B2 3083 B2
7001 C1 3084 B2
7002 D1 3153 A1
7004 D2 3999 B1
7010 A2 5000 B1
7011 A2
6000 A1
7106 D2
6001 C1
7107 D2
6002 A1
9100 A2
6003 C1
9101 A2
6004 C1
9104 A2
6005 B1
9105 A2
9106 A2 6006 C1
9107 A2 6007 B1
9210 A1 6008 B1
9222 C1 6009 D1
6010 C1
6011 C1
6012 C2
6013 B2
6014 C1
6015 C1
6017 B2
6018 A2
6019 A2
6020 D1
6021 A2
6022 A2
6023 D2
6024 D2
6025 D1
6026 D1
6027 B1
6029 B1
6030 B1
6040 D2
6041 D2
3104 313 6048.4 6045 A1
6046 A1
F_15400_060.eps 6047 A1

F_15400_059.eps
3104 313 6048.4 090505 6048 A1

090505
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 93

Audio Amplifier Panel

0001 A15 2705 B10 2717 A8 2729 H10 2745 B7 2758 G5 2772 G2 2790 G15 3703 A2 3715 B8 3727 D6 3739 F9 3751 H13 3763 H7 3775 H9 5709 E9 7706 D3 7718-1 G2 9707 H7 F709 C11 F721 G12 F734 A15 I700 G13 I712 A9 I724 B9 I736 D2 I748 G15 I760 H14 I772 H2
1735 C12 2706 A3 2718 B5 2731 C9 2746 C7 2759 G11 2773 G3 2791 D14 3704 A10 3716 C10 3728 D4 3740 F15 3752 H14 3764 A10 3776 H9 5714 H8 7707 D2 7718-2 G4 9708 H7 F710 E13 F722 H8 F735 A14 I701 H13 I713 C2 I725 C8 I737 D2 I749 G1 I761 H4 I773 H10
1736 A13 2707 C5 2719 A4 2732 C10 2747 C2 2760 G6 2774 G3 2793 H1 3705 A5 3717 C5 3729 D2 3741 G10 3753 H11 3765 D10 3777 D3 6700 D13 7708 E6 7719-1 H6 9709 G14 F711 E14 F723 H8 F740 A12 I702 G11 I714 C2 I726 B10 I738 D3 I750 G3 I762 H9 I774 G10
1738 G13 2708 F9 2720 B5 2733 G9 2748 C2 2761 G1 2775 H5 2794 H3 3706 A4 3718 C2 3730 D1 3742 G14 3754 G4 3766 H10 3778 D10 6702 D5 7709 E5 7719-2 H6 F700 A12 F712 E13 F724 H6 F741 A12 I703 A2 I715 A8 I727 D10 I739 D4 I751 G14 I763 H5 I775 C9
1M02 A13 2709 A6 2721 B6 2736 D10 2749 C3 2762 G2 2776 A6 2795 H3 3707 A8 3719 C2 3731 D3 3743 G5 3755 H5 3767 H9 3999 A15 6703 E3 7710 E4 7720 H15 F701 A12 F713 D15 F725 G7 F742 A13 I704 A3 I716 A10 I728 G9 I740 E4 I752 G5 I764 H3 I776 B10
1M06 A14 2710 A7 2722 B4 2737 D10 2750 G9 2763 H5 2778 E9 2796 H3 3708 A10 3720 D10 3732 E4 3744 G5 3756 H5 3768 G10 5700 A10 6704 G13 7711 F5 9700 E12 F702 A11 F714 F13 F726 A7 F743 B13 I705 A3 I717 D2 I729 D13 I741 G11 I753 G5 I765 H15 I777 A11
1M52 E14 2711 A2 2723 B8 2739 D6 2751 F4 2764 E8 2779 E8 2797 H4 3709 A3 3721 C3 3733 E6 3745 G11 3757 G3 3769 H8 5701 D14 6705 H13 7712 G6 9701 E12 F703 B13 F715 F13 F727 A5 F744 C7 I706 A4 I718 A8 I730 D3 I742 E3 I754 G5 I766 G1
2700 A3 2712 A10 2724 H10 2740 F11 2752 G5 2766 H11 2780 A10 2798 H4 3710 B8 3722 A3 3734 E4 3746 G13 3758 G2 3770 H2 5702 C10 7700-1 C4 7713 G6 9702 E12 F704 A13 F716 F13 F728 B6 F745 C12 I707 C3 I719 A10 I731 G7 I743 F3 I755 G2 I767 H3
2701 B10 2713 A4 2725 H10 2741 E6 2754 D15 2767 H11 2782 F8 2799 H9 3711 B9 3723 A3 3735 F5 3747 G5 3759 G7 3771 H3 5704 G9 7700-2 A4 7714 F8 9703 E13 F705 B13 F717 F13 F729 C5 F747 E8 I708 D4 I720 B8 I732 D14 I744 F5 I756 G4 I768 H10
2702 H11 2714 G14 2726 B4 2742 G11 2755 G2 2768 H5 2783 G8 3700 A2 3712 B3 3724 C2 3736 F3 3748 G15 3760 E2 3772 H2 5705 A7 7701 A7 7715 G15 9704 G12 F706 B12 F718 F13 F730 D6 F748 G3 I709 D5 I721 B4 I733 D10 I745 F6 I757 G5 I769 H11
2703 A7 2715 A10 2727 C9 2743 E5 2756 G7 2770 A15 2788 H8 3701 A10 3713 C13 3725 D2 3737 F3 3749 G5 3761 H11 3773 H2 5706 G10 7702 C14 7716 G14 9705 H12 F707 C12 F719 G12 F731 B8 F749 G12 I710 A4 I722 C9 I734 D3 I746 F9 I758 H11 I770 H3
2704 A7 2716 A10 2728 H10 2744 E3 2757 G7 2771 H6 2789 D10 3702 C2 3714 B4 3726 D4 3738 F5 3750 G2 3762 H9 3774 H2 5708 C7 7705 D5 7717 H14 9706 G7 F708 C12 F720 G12 F733 H4 F750 G7 I711 G10 I723 B4 I735 H7 I747 G10 I759 H5 I771 H1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

C AUDIO AMPLIFIER C
1736

VDDOPAMP

-19-16VS1
3709 2719 +19-16VS1
F726 5705
+19-16V
3704 I777
DC
C (4x) F700 F740
3
TO
AUDIO-L 5700 100K F702 F701 F741 2
LEFT

470u 25V
22u 100V
4K7 I710 470n I712 1 F735 3999 F734

2703

220n

2704
2776
2713 33u
SPEAKER

2712

470n
I706 B3B-PH-K 1K0

120K
3722
4n7
3703

2715

470n
2716
8K2

15n
3706 2709 3764

8
5 -19-16VS1 2710 I716
A F727 A
I705 3K9 7 100K 0001
2711 I704 3723 220n -19-16VS1 2770
I703 6 220n 1

13

2780

470n
5
4
1u0 470R 10n GND screw
Φ
7700-2 7701 VDD1 VDD2
LM393PT TDA8925ST I715 3707
560R
3700

2700

2706

3705

2K2
2n7

3n9
CLASS-D +19-16VS1
AMPLIFIER 39K I719

2717
1 6

1u0
SW1 BOOT1

3708

3701
2 1M02 1M06

47R

47R
REL1 F704 F742
4 1 1
EN1
OUT1
7
I718 -19-16V
2 2 TO 1M02 TO
F703 3 3

2718

100n
9
F728 STAB F731 F743 4 4
OR SDI

22u 100V
3 +19-16V F705 5 5
DIAG

2720

2721

100n
15 I720 3711 I726 6 6
POWERUP 3710 2701
12
+19-16VS1 +19-16VS1 DC-PROT F706 1V2 7 7
PDP SUPPLY
B 3712 I721 2722 BOOT2 39K 5R6 560p B

2723
17 B7B-PH-K B7B-EH-A

1u0
AUDIO-R
4K7 470n
16
SW2
REL2 2705
SUPPLY
14 11 I776 -19-16VS1
2726 EN2 OUT2
I723 -6V7
VSS1 VSS2 560p
4n7

10
3714
120K
3719

3717

2K2
2745 3715 I724 2727 1735
3702

F744
8K2

3K9 I725 +19-16VS1

3
8
220n 5R6 560p
F707 F745
3
TO
I707 1 -19-16V 5708
2747 2746 2
I713
I714 3721 2 F729 2731 1 RIGHT
4

1u0 470R 7700-1 470u 25V I775 -19-16VS1

LM393PT 560p B3B-PH-K SPEAKER
560R
3718

2748

2749
1n5

3n9

C C
2707

100n -19-16VS1 3716 C (4x)

DC +19-16V
I722 5702 100K F709

3713

3K3
+19-16VS1 33u F708 7702

2732

470n
BC847BW 3
3724 I730

2736

470n
2737
1

15n
3765 I729
I727 I732 5701 F713

BZX384-C15
1K0
2
100K VDDOPAMP
3777

6700

2791

220n
1K0

3726 F730

22u 100V
3725

2789

470n
47K

2754
15K 3
D I734 +19-16VS1 3728 I708 6702 I709 D
3727

2739

100n
1
10K

3 7705 I733
I717 BC847BW
3729 15K BZX384-C39
I736 1 7706 2

3720

3778
3 BC847BW

47R

47R
47K
I737 2 I739 -19-16VS1
3730 1 3731
SOUND-ENABLE 7707 I738
BC847BW
BZX384-C3V3

22K 1K0
2 7708
3760

2744

100n

6703
22K

BC857BW
2

3 9700 9703
3733

2741

220p

AUDIO-C
5K6

3732 I740
E POR 1 7709 9701 E
1

3 BC847BW
22K
I742 2 5709 9702
F747
3734

2743

1 1M52
22K

1n0

7710 +19-16VS2 +19-16V F710

BC847BW AUDIO-L TO 1M52 TO 1J04

470u 25V
1

22u 100V

2779

220n

2778
2 F711
2

2764
-19-16VS1 AUDIO-R F712 3
4
+19-16VS1 2782
F714
5 OR
3737

F715
47K

-19-16VS2 6
270K
3735

2708 PROT-AUDIOSUPLLY F716 4V7

220n 7
2 I745
-19-16VS2
SOUND-ENABLE
POR F717
F718 0V3
0V
8 SSB SSB
3738 220n 9
BC857BW 7714 BP2.x / FTP2.x LC4.x

13
7711 1 TDA8925ST B9B-PH-K

5
F I744 100K F
Φ
3736 I743 VDD1 VDD2
DC-PROT
3
C (4x)
DC
47K CLASS-D PROT-AUDIOSUPLLY
AMPLIFIER I746 3739 2740
3 3 1 6
47u 25V

SW1 BOOT1 +19-16VS2 +19-16VS2 +19-16V 3740

2751

2
REL1 39K 560p

2750
1 7712 7713 1 4

1u0
VDDOPAMP 100K

BZX384-C10
EN1

2790

100n
2755 BC847BW BC847BW 7 3
OUT1 I747 3741 I702 2742

6704
2 2 I748
F725 -19-16VS2
9 I774 I741 3 1 7715
I749 3750 100n STAB 5R6 560p
I750 3 I751 BC847BW
3754 DIAG 3742

9704
330R 2752 I752 3743 I753 15 1 7716 2
3744 POWERUP I700
I766 I755 BC847BW
2761 2762 470R 3759 1738 100K
8

AUDIO-C 3 7718-1 12 2

100u 16V
G F748 2773 2774 I756 120p 3K3 100K -19-16VS2 BOOT2 5706 3745 C (4x) F719 F749 G
8

9706

2733

3746

2714

9709
1 5 7718-2 17

2K2
1u0
1u0 1u0 2K2 SW2 DC 3
3747

2 7 16
47K

LM833D 1u0 1u0 REL2 33u 100K F721 F720 2

22u 100V
3758

3757

6 14 11
22K

8K2
4

LM833D EN2 OUT2 I728 3768 1 3748

2756

2757

100n

3749 +19-16VS2
4

I757 2758 I731

2772 VSS1 VSS2 B3B-PH-K
2760 39K 1 100K

2759

470n
8

10

1u0 F750 5704 I711

10K
TO

2766

470n
2767

9705

3751

2K2
15n
-19-16VS2 100n I754 100n 2783
2793 I771 3773 I772 3774 2763 33u 3766 3
2
4

I761 F733
1
F724
-19-16VS2 220n F723 I758 CENTER 3752 I760 3
9707

2724

470n
2798 2 I701 7717
120p 3K3 100K 220p 100K
-19-16VS2 LM393PT 2788 SPEAKER 10K
BC847BW 1 7720

BZX384-C10
2702

470n
3 7719-1 BC847BW
560p 2797
8

2768 -19-16VS2 3767 I765

6705
3770 2794 2771 I768 2
I767 +19-16VS2 25V 470u
3772

47K

560p 470n 100K 3753

5714

3776

18K

10K 1u0 3755 100n I769

2725

470n

2795 I770 -19-16VS2 22R

H VDDOPAMP H
3763

2728

470n
2729
2K2

15n
3K9 -19-16V 3775 -19-16V
I763
220p 3761
4

DC C (4x)
2775 I759 3756 7 I735 120K 2799 3762
6 9708
2796 I773 100K
39n 8K2 LM393PT F722 22R
5 470p
7719-2
8

470n I764 3769

3771
5R6 I762
3104 313 6056.4 3K9 F_15400_061.eps
090505
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 94

Layout Audio Amplifier Panel (Top Side) Layout Audio Amplifier Panel (Bottom Side)

0001 C1 2700 D1 3740 C1 9808 C1

1735 E1 2701 D1 3741 A1 9809 C1
2702 B1 3742 C1 9812 C1
1736 E1 2703 E1 3743 A1 9813 C1
1738 B1 2705 D1 3744 A1 9814 C1
1M02 C1 2706 D1 3745 B1
2707 C1 3746 C1
1M06 C1 2708 A1 3747 A1
1M52 B1 2709 E1 3748 D1
2704 D1 2710 E1 3749 A1
2711 D1 3750 A1
2714 C1 2712 E1 3751 D1
2715 E1 2713 D1 3752 D1
2720 D1 2716 E1 3754 A1
2717 D1 3755 A1
2728 B1 2718 C1 3756 A1
2736 E1 2719 C1 3757 A1
2746 D1 2721 E1 3758 A1
2722 C1 3759 A1
2751 B1 2723 D1 3760 B1
2754 C1 2724 B1 3761 B1
2756 A1 2725 B1 3763 A1
2726 C1 3764 E1
2764 A1 2727 E1 3765 E1
2766 B1 2729 B1 3766 A1
2776 D1 2731 E1 3767 A1
2732 E1 3768 A1
2778 A1 2733 A1 3769 A1
2788 A1 2737 E1 3770 A1
3753 B1 2739 E1 3771 A1
2740 A1 3772 A1
3762 A1 2741 E1 3773 A1
5700 E1 2742 A1 3774 A1
5702 E1 2743 B1 3775 A1
2744 B1 3776 A1
5704 A1 2745 D1 3777 B1
5705 D1 2747 C1 3778 E1
2748 C1 3999 A1
5706 A1
2749 C1 5701 C1
5708 D1 2750 A1 6700 C1
5709 B1 2752 A1 6702 E1
2755 A1 6703 B1
5714 A1
2757 A1 6704 C1
7701 D1 2758 A1 6705 D1
7714 A1 2759 B1 7700 C1
2760 A1 7702 C1
9704 B1 2761 A1 7705 E1
9705 B1 2762 A1 7706 B1
9708 A1 2763 A1 7707 B1
9800 2767 B1 7708 B1
9715 E1 2768 A1 7709 B1
9716 B1 2770 B1 7710 B1
9721 A1 2771 A1 7711 B1
2772 A1 7712 B1
9723 B1 2773 A1 7713 B1
9724 A1 2774 A1 7715 C1
9725 A1 2775 A1 7716 C1
2779 A1 7717 D1
9726 C1 2780 E1 7718 A1
9727 A1 2782 A1 7719 A1
9728 B1 2783 A1 7720 D1
2789 E1 9700 C1
9730 B1 2790 D1 9701 C1
9731 A1 2791 C1 9702 B1
9732 A1 2793 A1 9703 C1
2794 A1 9706 A1
9733 A1 2795 A1 9707 A1
9734 A1 2796 A1 9709 C1
9735 B1 2797 A1 9710 D1
2798 A1 9711 E1
9739 D1 2799 A1 9712 D1
9740 D1 3700 C1 9713 D1
9741 E1 3701 E1 9748 D1
3702 C1 9757 D1
9742 D1 3703 D1 9758 D1
9744 D1 3704 E1 9759 D1
9745 D1 3705 D1 9760 D1
3706 D1 9761 D1
9747 E1 3707 D1 9762 D1
9749 A1 3708 E1 9763 D1
9774 A1 3709 C1 9764 D1
3710 D1 9765 D1
9797 C1 3711 D1 9766 D1
9798 B1 3712 C1 9768 D1
9799 B1 3713 C1 9770 D1
3714 C1 9775 A1
9801 C1 3715 D1 9776 A1
9804 C1 3716 E1 9777 A1
9805 C1 3717 D1 9778 A1
3718 C1 9779 A1
9810 C1 3719 C1 9780 A1
9811 C1 3720 E1 9781 A1
3721 C1 9782 A1
3722 D1 9783 A1
3723 D1 9784 A1
3724 B1 9785 A1
3725 B1 9786 A1
3726 E1 9787 A1
3727 E1 9788 A1
3728 E1 9789 A1
3729 B1 9790 C1
3730 B1 9792 A1
3731 B1 9793 A1
3732 B1 9795 D1
3733 E1 9796 B1
3734 B1 9800 B1
3735 B1 9801 C1
3736 C1 9802 B1
3737 B1 9803 C1
3738 B1 9806 B1
F_15400_062.eps F_15400_063.eps 3739 A1 9807 C1
3104 313 6056.4 090505 3104 313 6056.4 090505
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 95

Side I/O Panel

1 2 3 4 5 6 7 8 9 1001 B2 F002 A2
1002-1 B1 F003 B2
SIDE I/O JAGUAR ONLY
D F012 5000 F013
D 1002-2 C1
1002-3 D1
1005 A8
F004 C2
F005 C2
F006 D2

PDZ6.8-B
F001 1010 E1 F007 E2
C

6000
1101

3000

1112
75R
1050 A7 F008 E2
Y / CVBS I004 1101 A3 F009 E2
A 1H01 A

PDZ6.8-B
OR
1102 B3 F010 F8

6001
2 4 3 1 F002 1M60 1005 1106 C3 F011 F9
TO 1H01 1
2
F014 1050 F015 1
USB 1108 D3 F012 A6
2 1109 E3 F013 A7
3 F016 F017 3
F020 4
DLW31S 5 6
4 CONNECTOR 1110 F3 F014 A6

VIPER 6 5 1111 E3 F015 A7

PDZ6.8-B
1112 A7 F016 A6

1102

6002
1001
1H01 A6 F017 A7
5 1M36 B8 F018 F7

3004

75R
B I009 B 1M37 B8 F019 F2
TO 1M36

PDZ6.8-B
F003 2003 C5 F020 B4

6003
2004 C3 F021 C6
1
1002-1 1M36
2005 C4 F022 C6
1M37
YELLOW
1 1 SSB EM6 2006 D3
2007 D4
F023 C6
F024 E6
2 2 2
3009 F022 3
4
3
4
OR 2008 F2 F025 E6
1K0 5 5 2009 F5 I001 C2
4
TO 1M36
PDZ6.8-B
F004 F021 6 6
1002-2 2010 E2 I002 C3
1106

2004

680p

3010

2005

100p
6004

33K
WHITE GND_AUD 7 7
C F005 8 8 C 2011 E5 I003 D2
5 6 9004 9 9 3000 A4 I004 A3

3011

3008

RES 2003

9003
3K9

2K2

1u0
I002 F023
I001
10
11
13
SCART 3 EM6
10
11 3004 B3 I005 F4
PDZ6.8-B

GND_AUD GND_AUD GNDB 12

3008 C5 I006 F4
6005

B11B-PH-SM3-TBT OR 3009 C4 I007 E4

3010 C4 I008 E4
7 F006 GND_AUD 3012 TO 1M36 3011 C5 I009 B3
9005

1002-3 1K0
RED 3012 D4 I010 D3
PDZ6.8-B
1108

2006

680p

3013

2007

100p
6006

33K 3013 D4 I011 F7

8 9 I003 SSB BP2 3016 F5 I012 F8
D D
I010 3020 E5 I013 F3
3999 F9 I014 E3
PDZ6.8-B

GND_AUD GND_AUD
6007

5000 A7
6000 A3
6001 A3
GND_AUD
F007 6002 B3
F024
6003 B3
1109

6004 C3
6005 C3
GNDB
E GNDB E 6006 D3
I008 F025
9011 6007 D3
1010 5
PDZ6.8-B

I007
6008 F3
2010

1111

4
22n

6010
3020

2011

2 9010
10K

F008
10n

6009 F3
F009 I014
3 GNDB GNDB 6010 E3
7 6011 F3
PDZ6.8-B

F019
6011

8
1 GNDB GNDB 9003 C6
GNDB 9004 C2
GNDB I006
9009 9005 D2
F I005 9006 9007 3999 F 9006 F7
PDZ6.8-B
2008

1110

3016

2009
10K
22n

10n

6008
9008 9007 F8
I011 I012 150R
I013 F018 9008 F4
GNDB GNDB GNDB GNDB
9009 F4
PDZ6.8-B

GNDB GND_AUD F010 F011

6009
9010 E4
9011 E4
GNDB F_15400_064.eps F001 A2
3104 313 6008.4 300505
1 2 3 4 5 6 7 8 9
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 96

Layout Side I/O Panel (Top Side) Layout Side I/O Panel (Bottom Side)

1001 B1 2003 A1
1002 A1 2004 A1
1005 A1 2005 A1
1010 A1 2006 A1
1050 A1 2007 A1
1H01 A1 2008 A1
1M36 B1 2009 A1
1M37 B1 2010 A1
5000 A1 2011 A1
3000 B1
3004 B1
3008 A1
3009 A1
3010 A1
3011 A1
3012 A1
3013 A1
3016 A1
3020 A1
3999 B1
6000 B1
6001 B1
6002 B1
6003 B1
6004 A1
6005 A1
6006 A1
6007 A1
6008 A1
6009 A1
6010 A1
6011 A1
9003 A1
9004 A1
9005 A1
9006 A1
9007 B1
9008 A1
9009 A1
9010 A1
9011 A1

F_15400_066.eps
3104 313 6008.4 090505
F_15400_065.eps
3104 313 6008.4 090505
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 97

Control Board
1701 A1 1704 A2 1M01 A4 3004 C1 3007 C1 3999 C4 9003 C2 F003 C4 I007 C1 I010 C2 I102 B1 I105 B3
1702 A1 1705 A1 3002 C2 3005 C1 3008 C1 9001 C3 F001 A4 F004 C4 I008 C1 I100 B1 I103 B2 Personal Notes:
1703 A2 1706 A3 3003 C2 3006 C1 3009 C2 9002 C1 F002 A4 I006 C1 I009 C2 I101 B1 I104 B2

1 2 3 4

CONTROL BOARD
E E
1M01
F001
KEYBOARD
F002 1
2
A 3 A
SKQNAB

SKQNAB

SKQNAB

SKQNAB

SKQNAB

SKQNAB
1701

VOLUME+ 1702

1705

1704

CHANNEL+ 1703

1706
CHANNEL-
VOLUME-

MENU

ON / OFF
B I100 I101 I102 I103 I104 I105 B
390R

100R

680R
3005

3004

3002
3006

3003
1K0

1K0

I006 I007 I008 I009 I010

F003 F004
C 3999
C
100R

100R
9002

3007

3008

3009

9003

9001
1K0

10K

D D

F_15400_067.eps
3104 313 6071.2 090505

1 2 3 4

E_06532_012.eps
131004
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 98

Layout Control Board (Top Side)

1701 -- 1702 -- 1703 -- 1704 -- 1705 -- 1706 -- 1M01 --

F_15400_068.eps
3104 313 6071.2 090505

Layout Control Board (Bottom Side)

3002 -- 3003 -- 3004 -- 3005 -- 3006 -- 3007 -- 3008 -- 3009 -- 3999 -- 9001 -- 9002 -- 9003 --

F_15400_069.eps
3104 313 6071.2 090505
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 99

LED Panel
1 2 3 4 5 6 7 8 9 10 11 12 13 14
0001 A10 9119 E2
0002 A11 9120 B10

J LED PANEL J
0345 D2
1040 F9
1M01 C2
9121 B11
9122 F11
F010 A3
1M20 A2 F011 A3
0001 0002
EMC HOLE EMC HOLE 2014 C4 F012 A3
A 1M20
F010
9015 KEYBOARD "RED" A 2030 G5 F013 B3

STATUS-POWER

LED1
TO 1M20 2040 F9 F014 B3
1 F011 3011
"BLUE" or 2070 F12 F015 A3

+5V2-STBY
2 COM-SND
2071 G12 F016 B3
3 100R

+8V
SSB 4
JL2.x / LC4.x 5
6
F012
F015
9016

9017
LED1

RC
"GREEN" 3011 A4
3030 G4
3031 G5
F017 B3
F018 B2
F021 C3
OR

+5V2-STBY
TO 1M20 7 F017 3032 G5 F038 B12

9120

9121
8 LIGHT-SENSOR
3033 G5 F039 B12
9 F013

+8V
10 +8V 3034 G6 F083 D3

330R

560R
(RES)
3051

3052
EXTERNALS 11 F014 3035 G6 F084 D3

9064
FTx2.x / Bx2.x 12 3036 G7 F086 E3
B 13 14
F016
9012 LED2 B 3037 G7 F089 E3
3040 F9 I010 F2
F018 F038 3999 F039

330R

560R
3061

3062
I053 3041 G9 I011 G2
+5V2-STBY 10K 3042 F9 I012 E3

9065

SML512BC4T
3051 B8 I013 E4

1
OPT_LED
3052 B8 I026 F12
3053 C8 I033 G4

6051
I062
3054 C8 I037 G7

2
3055 C8 I038 G6
9053
3056 D6 I039 G4
7062 7051
TO 1M01 BC857B
I065 3061 B6 I040 G5
BC847BW
1M01 3062 B6 I041 G9
C C

9011

9052
1 F021
3063 D5 I042 G9
2 KEYBOARD 3064 D5 I043 F9
CONTROL
3 I052 3070 G11 I044 F9
BOARD 4 5 I095 3071 F12 I045 F9

100n

SML512BC4T
2014 3072 G13 I046 E9

100R
3053

3054

3055
10K

10K
6060
3073 G13 I047 G4
(RES) 3074 F13 I048 G5
I063 3075 F14 I049 G7
9063
3076 G14 I051 D8
I061 7061
BC847BW 3077 G12 I052 C8
7052

(RES)
100R
3063

3064

9062
3078 G11 I053 B9

10K
BC847BW

9066
D D 3091 G2 I054 D7

9054
3092 F2 I061 D6
9083 3093 F3 I062 C6
+5V2-STBY
I054 3094 F2 I063 D7

(RES)
3056

9056
I051

10K
I064
0345
F083 3096 G3 I064 D5
9110 9111 LIGHT-SENSOR 3999 B12 I065 C9
TO 0345 1
9112 F084 9113 KEYBOARD
2 6030 G4 I071 F11
9114 I012 9115 RC
3 6031 G4 I072 F14

LED1

LED1

LED2
9116 F086 9117 I013 BLACKLIGHT-TC
4 9081 6051 C8 I073 G12
TOP CONTROL 9118 LED1
5 9082 F089
9119
6 LED2 6060 C6 I074 G12
7 8 6070 G11 I075 F12

RC

LIGHT-SENSOR

LIGHT-SENSOR
+5V2-STBY
7030 G6 I076 F13
E E 7031 G7 I093 F2
7032 G4 I094 F3
7051 C8 I095 C6
I046 7052 D8

+5V2-STBY
7061 D6
+5V2-STBY

7062 C6

330R
3040
7070-1 F12
2070 I026 7070-2 G13
I044 7092 F2
3092

10K

470n 9011 C6
I094

+5V2-STBY
9012 B4

+5V2-STBY
+5V2-STBY

3071 3074 I072 9015 A4

9041

9043

9122

9070
F F

100u 16V
3042

2040
9016 A4

6K8
I010 3094 I093 4M7 +8V 10K
3093

10K

COM-SND 7092 9017 A4

BC847BW 1040
10K I043 9031 G4

4
9071
VS I045 I071 9040 G9

8
I075 2 5 I076
"LED DIMMING" OUT
1 7 3075 9041 F9

6070
LM358P

TEMD5000
3030

3035

3036

3037
3 6 9042 G9

2R2

2R2
4K7

4K7

8
7070-1 7070-2 4K7
+8V LM358P 9043 F9

4
GND
TSOP34836YA1 I042 9052 C9
I073 +8V 3073 9053 C8
9093

3041
9031

10K
I038 I049 I074
3034 9054 D9

9040

9042
I011 3096 I037 3K3

3076
9056 D7

3K3
STATUS-POWER

10u 16V
6030 I047 3031 I040 3033 I048 1K0
I039

3078

9072

3070

2071

3077

3072
2M2

4M7
G G

3K3

1K0
10K BC857BW BCP53 9062 D7
7030 7031
3091

10K

BAS316 100K 1K0 9063 D6

6031 I033 3032
BLACKLIGHT-TC
9064 B7
10u 16V

I041
9065 B7
2030

7032 180K
BC847BW BAS316 9066 D7
9070 F11
9071 F11
9072 G11
9081 E4
"IR RECEIVER" "LIGHT SENSOR" 9082 E3
9083 D3
9093 G2
H H 9110 D2
9111 D4
9112 D2
9113 D4
9114 E2
F_15400_070.eps 9115 E4
3104 313 6074.3 090505 9116 E2
9117 E4
9118 E2
1 2 3 4 5 6 7 8 9 10 11 12 13 14
 Circuit Diagrams and PWB Layouts BP2.3U AA 7. EN 100

Layout LED Panel (Top and Bottom Side)

0345 --
1040 --
1M01 --
Personal Notes:
3031 --
3032 -- 1M20 --
3033 -- 2014 --
3055 -- 2030 --
3056 -- 2040 --
3070 -- 2070 --
6030 -- 2071 --
6031 -- 3011 --
6051 -- 3030 --
6060 -- 3034 --
6070 -- 3035 --
7030 -- 3036 --
7031 -- 3037 --
7052 -- 3040 --
7062 -- 3041 --
9011 -- 3042 --
9031 -- 3051 --
9054 -- 3052 --
9056 -- 3053 --
9066 -- 3054 --
9110 -- 3061 --
9112 -- 3062 --
9114 -- 3063 --
9116 -- 3064 --
9118 -- 3071 --
9119 -- 3072 --
9120 -- 3073 --
3074 --
3075 --
3076 --
3077 --
3078 --
3091 --
3092 --
3093 --
3094 --
3096 --
3999 --
7032 --
7051 --
7061 --
7070 --
7092 --
9012 --
9015 --
9016 --
9017 --
9040 --
9041 --
9042 --
9043 --
9052 --
9053 --
9062 --
9063 --
9064 --
9065 --
9070 --
9071 --
9072 --
9081 --
9082 --
9083 --
9093 --
9111 --
9113 --
9115 --
9117 --
9121 --
9122 --
E_06532_012.eps
131004
F_15400_071.eps
3104 313 6074.3 090505
 Alignments BP2.2U, BP2.3U 8. EN 101

8. Alignments
Index of this chapter: IF AFC
8.1 General Alignment Conditions Alignment procedure:
8.2 Hardware Alignments 1. During the IF AFC-parameter adjustment, one can see
8.3 Software Alignments OSD feedback on the screen.
8.4 Option Settings 2. The OSD feedback can give four kinds of messages:
3. The first item ("IN/OUT") informs you whether you are in or
out of the AFC-window.
8.1 General Alignment Conditions 4. The second item ("HIGH/LOW") informs you whether the
AFC-frequency is too high or too low.
8.1.1 Start Conditions
Table 8-1 AFC
Perform all electrical adjustments under the following
conditions: AFC-window AFC-frequency vs. reference
• Power supply voltage: 120 VAC / 60 Hz (± 10%).
Out High
• Connect the set to the AC Power via an isolation
transformer with low internal resistance. In High
• Allow the set to warm up for approximately 15 minutes. [ In ] [ Low ]
• Measure voltages and waveforms in relation to chassis Out Low
ground (with the exception of the voltages on the primary
side of the power supply).
Caution: It is not allowed to use heatsinks as ground. 1. Adjust the IF AFC parameter until the first value is within
• Test probe: Ri > 10 Mohm, Ci < 20 pF. the AFC window (= IN).
• Use an isolated trimmer/screwdriver to perform 2. Next, adjust the IF AFC parameter until the second value
alignments. is LOW.

8.1.2 Initial Settings Tuner AGC

Purpose: To keep the tuner output signal constant as the input
signal amplitude varies.
Perform all electrical adjustments with the following initial
settings (via the "Active Control" button on the RC):
1. To avoid the working of the lightsensor, set ACTIVE Default value: “32”.
CONTROL to OFF.
2. Set SMART PICTURE to NATURAL/ECO. In case the default value gives problems, use the next method:
1. Set the video generator to a color bar test pattern and a RF
8.1.3 Alignment Sequence amplitude of 1 mV.
2. Select the channel with the test picture.
3. Measure the DC voltage on pin 1 of the (main) Tuner.
• First, set the correct options:
4. Adjust this voltage via TUNER AGC to just below 3.5 V.
– In SAM, select (SERVICE) OPTIONS -> OPT. NO,
– Fill in the option settings according to the set sticker
(see also paragraph "Option Settings"), 8.3.2 White Point
– Select STORE OPTIONS and push OK on the remote
control, • Set ACTIVE CONTROL to OFF.
– After storing, the set must be restarted! • In the [MENU] -> PICTURE user menu, set:
• Warming up (>10 minutes). – DYNAMIC CONTRAST to OFF.
• White point alignment. – COLOUR ENHANCEMENT to OFF.
– COLOUR to "0".
– CONTRAST to "100".
8.2 Hardware Alignments – BRIGHTNESS to "50".
• Go to the SAM and select ALIGNMENTS -> WHITE
Not applicable. POINT.

Method 1 (with color analyzer):

8.3 Software Alignments
Put the set in SAM mode (see the "Service Modes, Error Codes
and Fault Finding" section). The SAM menu will now appear on
the screen. Select ALIGNMENTS and go to one of the sub
menus. The alignments are explained below.
Notes:
• All changes must be stored manually.
• If an empty EAROM (permanent memory) is detected, all
settings are set to pre-programmed default values.
8.3.1 General
For the next alignments, supply the following test signals via a
video generator to the RF input: NTSC M/N TV-signal with a
signal strength of at least 1 mV and a frequency of 61.25 MHz
(channel 3).
• Use a 100% white screen as input signal and set the
following values:
– COLOR TEMPERATURE: "Tint to be aligned".
– All WHITE POINT values to: "127".
– RED and GREEN BL OFFSET values to: "3".
• Measure with a calibrated (phosphor- independent) color
analyzer in the centre of the screen. Consequently, the
measurement needs to be done in a dark environment.
• Adjust, by means of decreasing the value of one or two
white points, the correct x,y coordinates (see table "White
D alignment values"). Tolerance: dx,dy: ± 0.004.
• Repeat this step for the other Color Temperatures that
need to be aligned.
• When finished press STORE (in the SAM root menu) to
store the aligned values to the NVM.
• Restore the initial picture settings after the alignments.
EN 102 8. BP2.2U, BP2.3U Alignments

Table 8-2 White D alignment values

Color Temp. Cool Normal Warm

x 0.276 0.285 0.313
y 0.282 0.293 0.329

When such equipment is not available, use “method 2”.

Method 2 (without color analyzer):

If you do not have a color analyzer, you can use the default
values. This is the next best solution. The default values are
average values coming from production (statistics).
1. Select a COLOUR TEMPERATURE (e.g. COOL,
NORMAL, or WARM).
2. Set the RED, GREEN and BLUE default values according
to the values in the "Tint settings" table.
3. When finished press STORE (in the SAM root menu) to
store the aligned values to the NVM.
4. Restore the initial picture settings after the alignments.

Table 8-3 Tint settings (42”/50”)

Default Values (42”/50”)

Cool Normal Warm
R ? ? ?
G ? ? ?
B ? ? ?

Note: These values were not available at the time of writing. As

soon as they become available, a Service Info or Service
Manual update will be issued via the appropriate channels.

8.4 Option Settings

8.4.1 Introduction

The microprocessor communicates with a large number of I2C

ICs in the set. To ensure good communication and to make
digital diagnosis possible, the microprocessor has to know
which ICs to address. The presence / absence of these specific
ICs (or functions) is made known by the option codes.

Notes:
• After changing the option(s), save them with the STORE
command.
• The new option setting is only active after the TV is
switched "off" and "on" again with the Mains switch (the
EAROM is then read again).
 Alignments BP2.2U, BP2.3U 8. EN 103

8.4.2 Dealer Options

Table 8-4 Dealer options

Menu item Subjects Options Description

Personal Options Picture Mute
Virgin Mode
On Picture mute active in case no picture detected
Off Noise in case of no picture detected
On TV starts up (once) with a language selection menu after the Mains switch is turned "on" for
the first time (virgin mode)
Off TV does not start up (once) with a language selection menu after the Mains switch is turned
"on" for the first time (virgin mode)

8.4.3 (Service) Options

Select the sub menu's to set the initialization codes (options) of

the set via text menus.

Table 8-5 Service options

Menu-item Subjects Options Description

PIP/DS Dual Screen None / 1 tuner / 2 tuners no DS / DS with one tuner / DS with two tuners
Data TV Guide US On / Off Feature present / not present
Display Screen “Value” Used screen size, type, and resolution
Scanning Backlight On / Off Feature present / not present
Dimming Backlight On / Off Feature present / not present
Video Repro Picture Processing Spider / No Spider Feature present / not present
Combfilter None / 2D / 3D Only selectable when Columbus is present
Ambient Light None / Mono / Stereo Inverter not present / one inverter / two inverters
MOP On / Off Feature present / not present (for sets with AmbiLight this is “on”)
Source Selection HDMI 1 None / Audio / No Audio No HDMI / HDMI with analog audio / HDMI without analog audio
HDMI 2 None / Audio / No Audio No HDMI / HDMI with analog audio / HDMI without analog audio
USB version None / 1.1 / 2.0 + CR No USB / USB 1.1 in side I/O panel / USB 2.0 in cardreader panel
IEEE1394 Yes / No Connector present / not present
Ethernet Yes / No Connector present / not present
S/PDIF inputs None / 1 conn. / 2 conn. None / 1 connector present (in)/ 2 connectors present (in/out)
Audio Repro Subw. Internal Present Yes / No Internal sub woofer present / not present
Acoustic System None n.a.
(Cabinet design, used for Entry ME5 5W n.a
setting dynamic audio
Entry ME5 15W 42/50PF7320A
parameters).
(Soft) Wrap n.a.
Top n.a.
Entry+ 42/50PF9630A, 50PF9830A
Others n.a.
Miscellaneous Alternative Tuner Philips / Alps Tuner brand
Tuner Type TD1336S Tuner type
Opt. no. Group 1 xxxxx xxxxx xxxxx xxxxx (see set sticker)
Group 2 xxxxx xxxxx xxxxx xxxxx (see set sticker)

8.4.4 Opt. No. (Option numbers)

Select this sub menu to set all options at once (expressed in
two long strings of numbers).
An option number (or "option byte") represents a number of
different options. When you change these numbers directly,
you can set all options very quickly. All options are controlled
via eight option numbers.
When the EAROM is replaced, all options will require resetting.
To be certain that the factory settings are reproduced exactly,
you must set both option number lines. You can find the correct
option numbers on a sticker inside the TV set.
The first line (group 1) indicates hardware options 1 to 4, the
second line (group 2) indicates software options 5 to 8.
Every 5-digit number represents 16 bits (so the maximum value
will be 65536 if all options are set).
When all the correct options are set, the sum of the decimal
values of each Option Byte (OB) will give the option number.
See next table for the option overview.

Example: The options sticker gives the following option

numbers:
• 04368 00005 01066 08707
• 00000 00032 00512 00000
EN 104 8. BP2.2U, BP2.3U Alignments

Table 8-6 Option code overview

Byte Bit (dec. value) Subject Options Settings (in decimal values) Remarks
1 0 (1) Video Repro Picture Processing 0= No Spider, 1= Spider Spider availability, influences,
digital options.
1 (2)
2 (4)
3 (8) Comb Filter 0= None, 8= 2D Comb (Columbus without DRAM),
16= 3D Comb (Columbus with DRAM)
4 (16)
5 (32) Ambient Light 0= None, 32=Ambi-light Stereo, 64= Ambi-light Mono
6 (64)
7 (128)
8 (256) Dual Screen 0= None, 256= One Tuner DS, 512= Two Tuner DS
9 (512)
10 (1024) MOP 0= Off, 1024= On Matrix Output Processor (or EBILD)
11 (2048) JOP 0= Off, 2048= On Jaguar Output Processor (or EBILD)
Reserved for future use
12 (4096) POD 0= Off, 4096= On
13 (8192) n.a.
14 (16384) n.a.
15 (32768) n.a.
2 0 (1) Sound Repro Acoustic System (Cabinet) 0= None, 1= Entry_ ME5_5W, 2= Entry_ME5_15W, 3= (Soft)Wrap, 4= Top, Cabinet design, used for setting dy-
5= Entry+, 15= Others namic audio parameters.
1 (2)
2 (4)
3 (8)
4 (16) Aux Headphone Sound 0= Off, 16= On Dual AC3 sound in Aux available.
5 (32) n.a.
6 (64) n.a.
7 (128) n.a.
8 (256) n.a.
9 (512) Sub woofer Internal 0= Not Present, 512= Present
10 (1024) Centre Mode Support 0= Not Supported, 1024= Supported
11 (2048) n.a.
12 (4096) n.a.
13 (8192) n.a.
14 (16384) n.a.
15 (32768) n.a.
3 0 (1) Source Select HDMI1 0= None, 1= With analog audio, 2= Without analog audio
1 (2)
2 (4) HDMI2 0= None, 4= With analog audio, 8= Without analog audio
3 (8)
4 (16) n.a.
5 (32) USB Version 0= None, 32= USB 1.1, 64= USB 2.0 + Card reader USB support.
6 (64)
7 (128) IEEE1394 0= Not Present, 128= Present
8 (256) Ethernet 0= LAN not present, 256= LAN present
9 (512) n.a.
10 (1024) S/PDIF Inputs 0= None, 1024= 1 Connector, 2048= 2 Connectors
11 (2048)
12 (4096) LCOS I/O 0= Not Present, 4096= Present
13 (8192) n.a.
14 (16384) n.a.
15 (32768) n.a.
4 0 (1) Region Region 0= EU, 1= AP-P, 2= AP-N, 3= US, 4= Latam
1 (2)
2 (4)
3 (8) Interconnect China IF 0= Off, 8= On
4 (16) Alternative Tuner 0= Philips, 16= Alps Tuner make.
5 (32) Tuner Type 0= TD1336s (B-Chassis US), 32= TD1331(J-Chassis US), Tuner type
64= UV1318 (Analogue EU), 96= TD1316 (Hybrid EU) (B-chassis US is e.g "BP2.3U").
6 (64)
7 (128) Source Select n.a.
8 (256) AV1 0= CVBS/RGB, 256= CVBS/YC/LR, 512= CVBS/YC/YPbPr/HV/LR Input type.
9 (512)
10 (1024) AV2 0= CVBS/YC/RGB/P50, 1024= CVBS/YC/LR Input type.
11 (2048)
12 (4096) AV3 0= Not Available, 4096= CVBS, 8192= YPbPr Input type.
13 (8192)
14 (16384) AV4 0= Not Available, 16384= YPbPr Input type.
15 (32768)
 Alignments BP2.2U, BP2.3U 8. EN 105

Byte Bit (dec. value) Subject Options Settings (in decimal values) Remarks
5 0 (1) Display Screen 000 (0000)= 42-inch PDP (SDI) HD V3, 001 (0256)= 50-inch PDP (SDI) HD V3, Screen size, type, and resolution.
002 (0512)= 42-inch PDP (FHP) ALiS, 003 (0768)= 30-inch LCD (LPL),
1 (2) 004 (1024)= 37-inch LCD (LPL), 005 (1280)= 42-inch LCD (LPL),
2 (4) 006 (1536)= 32-inch LCD (Sharp), 007 (1792)= 42-inch PDP (SDI) SD,
008 (2048)= 37-inch PDP (FHP) ALiS, 009 (2304)= Reserved,
3 (8) 010 (2560)= 30-inch LCD (AUO), 011 (2816)= 32-inch LCD (LPL),
4 (16) 012 (3072)= 32-inch LCD (AUO), 013 (3328)= 37-inch LCD (Sharp),
014 (3584)= 42-inch LCD (LPL) HD, 015 (3840)= 37-inch PDP (SDI) SD,
5 (32) 016 (4096)= 37-inch PDP (FHP) ALiS, 017 (4352)= 42-inch PDP (FHP) ALiS,
018 (4608)= 55-inch PDP (FHP), 019 (4864)= Reserved,
6 (64)
020 (5120)= Reserved, 021 (5376)= 26-inch LCD (LPL),
7 (128) 022 (5632)= 32-inch LCD (LPL) scan. BL, 023 (5888)= 42-inch PDP (LG) SD,
024 (6144)= 42-inch PDP (SDI) SD V4, 025 (6144)= 42-inch PDP (SDI) HD V4,
026 (6400)= 42-inch PDP (FHP) HD A2, 027 (6656)= 50-inch PDP (SDI) HD V4,
028 (6912)= 37-inch LCD (Sharp) HD
8 (256) n.a.
9 (512) n.a.
10 (1024) Dimming Backlight 0= Off, 1024= On
11 (2048) Scanning Backlight 0= Off, 2048= On
12 (4096) n.a.
13 (8192) n.a.
14 (16384) n.a.
15 (32768) n.a.
6 0 (1) Miscellaneous Monitor 0= Off, 2= On Reserved for future use
1 (2) n.a.
2 (4) Stand Alone 0= Off, 4= On Reserved for future use
3 (8) n.a.
4 (16) n.a.
5 (32) n.a.
6 (64) Proximity Sensor 0= Off, 64= On
7 (128) n.a.
8 (256) Touch Pad 0= Off, 256= On Reserved for future use
9 (512) n.a.
10 (1024) n.a.
11 (2048) n.a.
12 (4096) n.a.
13 (8192) n.a.
14 (16384) n.a.
15 (32768) n.a.
7 0 (1) Personal Self Learning TV 0= Off, 1= On Reserved for future use
1 (2) Auto Store Mode 0= None, 2= PDC/VPS, 4= TXT Page, 6= PDC/VPS/TXT Page Fixed to: "None" in the AP-N and
US versions.
2 (4)
3 (8) 2CS Korea 0= Off, 8= On, 16= Auto
4 (16)
5 (32) Picture Mute 0= Off, 32= On
6 (64) n.a.
7 (128) Virgin Mode 0= Off, 128= On
8 (256) Hotel Mode 0= Off, 256= On
9 (512) Content Browser 0= Not Present, 512= Present
10 (1024) Connected Planet 0= Off, 1024= Full Connected Planet + logo support
11 (2048)
12 (4096) n.a.
13 (8192) EPG 0= None, 8192= TXT Guide only, 16384= NextView 2C3, 24576 = NexTView 2
14 (16384)
15 (32768) TV Guide USA (Gemstar) 0= Off, 32768= On
8 0 (1) n.a. n.a.
1 (2) n.a. n.a.
2 (4) n.a. n.a.
3 (8) n.a. n.a.
4 (16) n.a. n.a.
5 (32) n.a. n.a.
6 (64) n.a. n.a.
7 (128) n.a. n.a.
8 (256) n.a. n.a.
9 (512) n.a. n.a.
10 (1024) n.a. n.a.
11 (2048) n.a. n.a.
12 (4096) n.a. n.a.
13 (8192) n.a. n.a.
14 (16384) n.a. n.a.
15 (32768) n.a. n.a.
EN 106 9. BP2.2U, BP2.3U Circuit Descriptions, Abbreviation List, and IC Data Sheets

9. Circuit Descriptions, Abbreviation List, and IC Data Sheets

Index of this chapter: When the input channel is an analog channel, the signal is
9.1 Introduction processed via the NTSC decoder and the VBI data decoder.
9.2 Power Supply
9.3 Inputs Digital Reception
9.4 Front-End As depicted in the block diagram, the POD module consists of
9.5 POD (Point Of Deployment) the following functional blocks: POD Common Interface, Out of
9.6 MPIF (PNX 3000) Band part, and buffering. These blocks are interfacing with the
9.7 PNX2015 ATSC In Band (IB) channel decoder and Out of Band (OOB)
9.8 PNX2015: AVIP channel decoder. The interface is connected to the VIPER.
9.9 PNX2015: Columbus (Comb Filter) Also the POD Interface outgoing Transport Stream (TS) is
9.10 PNX2015: HD Subsystem routed to the VIPER.
9.11 PNX2015: LVDS Transmitter
9.12 PNX2015: Stand-by Processor
The TV receives multimedia information by tuning to one of
9.13 VIPER 2 (PNX 8550) many 6 MHz input channels available via a cable connection.
9.14 MOP
When the input channel is a digital channel, it is processed via
9.15 Ambient Light (if present)
the QAM demodulator and then passed to the CableCARD
9.16 Abbreviation List device (POD) where secure and scrambled information is
9.17 IC Data Sheets
processed. Non-scrambled information is passed through the
CableCARD Device to the MPEG-2 Transport Demultiplexer.
Notes: When the CableCARD Device is not inserted, the output of the
• Only new circuits (circuits that are not published recently) QAM demodulator is routed directly to the MPEG-2 Transport
are described. Demultiplexer. The multi-media processor (VIPER) handles
• Figures can deviate slightly from the actual situation, due the synchronization and display of audio-visual material.
to different set executions.
• For a good understanding of the following circuit
The OpenCable Host Device also receives control information
descriptions, please use the wiring, block (chapter 6) and
and other data by tuning to an Out-Of-Band (OOB) Forward
circuit diagrams (chapter 7). Where necessary, you will find Data Channel (FDC) channel. The terminal will remain tuned to
a separate drawing for clarification.
the OOB Forward Data Channel (own tuner) to continuously
receive information. This information is passed to the
9.1 Introduction CableCARD Device for processing, and relevant information is
passed back to the TV.
The BP2.x is a new TV chassis, specifically developed for
ATSC reception. The key components are: Signal Processing
• POD circuitry. The AVIP together with the MPIF device is used to perform the
• MPIF (PNX3000). input decoding of a single stream of analog audio and video
• AVIP/COLUMBUS (PNX2015). broadcast signals. In addition, the AVIP is used for decoding
• VIPER 2 (PNX8550). and presentation of audio output streams. The main data
connection between MPIF and AVIP is done via an I2D bus.
The AVIP converts the incoming video data to ITU-656 format
9.1.1 Features
for communication to the VIPER IC.
The audio data is transferred between the AVIP and VIPER
The main features for this chassis are: using I2S.
• The move from the analog world to the digital world. W.o.w.
from signal processing via "hardware circuits" to signal
The AVIP IC is controlled by the VIPER via the I2C bus.
processing via "software algorithms". This means: no
software = no picture and sound!
• Fit for both analog and digital signal processing, this by The key part in the system, the VIPER, performs almost all key
converting analog signals into digital transport streams and features, like video quality enhancement, motion
allowing seamless zapping between all possible signal compensation, picture-in-picture processing, and others. It is a
sources. This makes the chassis applicable for e.g. completely digital IC with a TriMedia DSP (Digital Signal
receiving ATSC in an integrated product form. Processor) core and a MIPS microcontroller core. The DSP
• AmbiLight (BP2.2): To be able to control lamps at the rear and some additional cores are used to do the video feature
of the TV with respect to the measured ambient light level processing and some auxiliary sound feature processing. The
from the light sensor or the picture content, a control output MIPS microcontroller core is used for all internal and external
from AutoTV has been foreseen. controlling tasks including a system wide I2C bus.
• The internal digital processing allows new "Multi-Media"
applications such as Content Browser, Memory Card Slot, The VIPER provides a primary digital (YUV or RGB) output to
Local Area Network support and all kinds of streaming the LVDS transmitter. For models with the AmbiLight feature,
applications. an EPLD is connected between VIPER output and LVDS
• The chassis can be upgraded in the future with internal Transmitter input. This EPLD (or MOP) is used for the
functionality such as Personal Video Recording, DVD/RW. AmbiLight processing and some picture enhancements.

9.1.2 Chassis Block Diagram

Description below refers to the block diagrams in chapter 6

“Block Diagrams, Test Point Overview, and Waveforms”.

Analog Reception
The TV receives multimedia information by tuning to one of
many 6 MHz input channels available via a cable connection.
 Circuit Descriptions, Abbreviation List, and IC Data Sheets BP2.2U, BP2.3U 9. EN 107

SSB Cell Layout

USB LVDS

DC/DC CONV. DISPLAY INTERFACE SIGNAL PROCESSING SOURCE SELECTION

MOP

RS232 MPIF

POD
TUNER

I/O

IEEE IEEE LAN

1394-1 1394-2
UART
HDMI-1 HDMI-2
(OPT) (OPT) (OPT)

F_15400_009.eps
210405

Figure 9-1 SSB top view

LVDS USB

SIGNAL PROCESSING

SOURCE SELECTION
DISPLAY INTERFACE DC/DC CONV.

2V5
SAW

1V2

RS232
AVIP
COLUMBUS STBY VIPER
CONTROLLER

POD
TUNER
SAW

I/O

DECODER
DEMODU- HDMI
LATOR RECEIVER
NAND
FLASH
(SET SW
SAW

XTAL + KEYS)

F_15400_010.eps
300505

Figure 9-2 SSB bottom view

EN 108 9. BP2.2U, BP2.3U Circuit Descriptions, Abbreviation List, and IC Data Sheets

9.2 Power Supply 9.2.5 +12V Switch

9.2.1 Introduction
The Main Power Supply is a buy-in module (it belongs to the
PDP), and therefore is a “black box” for Service. When
defective, a new panel must be ordered and after receipt, the
defective panel must be send for repair.
This Power Supply delivers the following supply voltages to the
chassis:
• +12VS.
• +8V6.
• +5V2.
• +5V.
As the VIPER and many other ICs on the SSB require low
supply voltages at high current (up to 3 A for the main
voltages), onboard DC/DC converters are implemented.
The circuit on the SSP provides the 3.3 and 1.2 voltages.
A DC/DC converter has the following advantages:
• The DC/DC converter is directly on the SSB near the
circuits that needs to be powered.
• Some circuits on the SSB need high current by low voltage,
so there is no risk to have power dips or voltage loss in
connections between the PSU and the SSB panel.
9.2.2 Block Diagram
• The +12V switch is activated when the POD-MODE signal
is "low".
• The rise time of the output voltage is set by components
2U42, 3U43, and 3U95 at about 30 ms.
• The switch "off" is fast, because there can be fault currents
that must be interrupted.
• When the input voltage (+12VS) is higher than 15 V, the
switch is disabled via circuit 6U12, 3U52, 3U53, 2U71, and
7U14-2.
9.2.6 Internal Protection
• Provides a SUPPLY-FAULT signal (active "low"), when the
output voltage of any DC/DC converter is out of its limits (±
10% of the normal value). In such cases, the Stand-by
Processor will immediately stop the supplies by sending a
"high" control signal towards the external and internal
supplies: ENABLE-xVx, POD-MODE, ON-MODE, and
STAND-BY.
Note: The SUPPLY-FAULT control signal is "low" when
any DC/DC converter is disabled by its control signal
(ENABLE-xVx) and +12VSW is present, therefore it is
ignored during start-up!
• The internal protection works together with the output over-
voltage detector transistors 7U15-1, 7U15-2, 7U29-1, and
7U29-2.

See also diagrams B1A and B1B.

9.2.7 1.2V and 3.3V DC/DC Converters
+8V6-SW

+5V
8V6 +2V5D Introduction
+8V6 +5V2_STBY LINEAR +2V5D
ON-MODE
SWITCH
STABILISER The circuit used is a so-called "synchronous buck converter".
Some characteristics:
+12VS
+5V
12V +12VSW +2V5
+2V5
• Switching frequency: approx. 250 kHz.
SWITCH LINEAR
POD-MODE STABILISER • Efficiency: approx. 90%.
+12VSW
• Built-in output over-voltage and over-current protections
VTUN VSW 12V/1V2 12V/3V3
• Soft start.
GENERATOR DC/DC CONV. DC/DC CONV. • Software controlled “on/off” (via ENABLE line).
SUPPLY-FAULT

Block diagram
VTUN +1V2 +3V3
F_15400_004.eps TS1
ENABLE-1V2 ENABLE-3V3 210405

D S L1
Vin Vout
Figure 9-3 DC/DC converter block diagram
G
9.2.3 PSU Start-up Sequence FB TS2 D

PWM GENERATOR
C1
1. If the input voltage of the DC/DC converters is around 12 V & MOSFET DRIVER G

(measured on the decoupling capacitors 2U17/2U25/

2U45) and the ENABLE signals are "low" (active), then the
output voltages should have their normal values.
2. First, the Stand-by Processor activates the +1V2 supply
(via ENABLE-1V2).
3. Then, after this voltage becomes present and is detected
OK (about 100 ms), the other two voltages (+2V5 and
+3V3) will be activated (via ENABLE-3V3).
4. The current consumption of controller IC 7U00 is around 20
mA (that means around 200 mV drop voltage across
resistor 3U22).
9.2.4 +2V5D Linear Stabilizer
• Provides the +2V5D voltage, and is derived from the +5V2-
STBY voltage coming from the Main Power Supply.
• The output current is limited to a few tenths of mA.
• Output over-voltage protection is done by zener diode
6U17.
S
GND GND
F_15400_005.eps
090505
Figure 9-4 Block diagram synchronous buck converter.
The advantage of a "synchronous buck converter" over a
"classical buck converter" is its better efficiency (about 90%).
The difference between the two is that in a synchronous buck
converter the "low -side" diode is replaced by a MOSFET TS2
(item 7U03). This, because the voltage drop across a MOSFET
is smaller than the forward voltage drop of a diode.
This second MOSFET TS2 conducts current during the "off"
times of the first MOSFET TS1 (item 7U01 at the input side).
The upper MOSFET TS1 conducts, to transfer energy from the
input to the inductor L1 and load RL, while the lower MOSFET
TS2 conducts to circulate the inductor current (free wheel). The
synchronous PWM control block regulates the output voltage
by modulating the conduction intervals of the upper and lower
MOSFETs.
 Circuit Descriptions, Abbreviation List, and IC Data Sheets BP2.2U, BP2.3U 9. EN 109

PWM Generator and MOSFET Drivers 9.2.10 Useful Data

This circuit is a one-chip solution (item 7U00). It contains all the
circuitry for two independent buck regulators (3V3 and 1V2).
Voltage Name Value [V] Tolerance [%]
The MOSFETs T7U01 and T7U03 are the switching
+5V2 5.2 5
transistors, they are conducting alternatively.
+5V 5.1 5
• Time sequence 1: T7U01 is conducting; energy is stored in
+8V6 8.6 5
coil 5U00/5U03. The current is flowing from the +12VSW
+12VS 12 5
power supply source.
+VTUN 33 5
• Time sequence 2: T7U01 is blocked; energy is stored in
+1V2 1.26 3
coil 5U00/5U03.
+2V5 2.6 4
• Time sequence 3: T7U03 is conducting, and the current
+2V5D 2.6 (2.5) * 4 (5) *
circuit is now closed via T7U03, Coil 5U00/5U03, C2U24/
+3V3 3.3 5
2U22, and the load. So the energy stored in the coil during
+5V2S 5.1 5
time sequence T1 is consumed during sequence T3. The
+8V6-SW 8.6 5
signal on the gate T7U03 is 180 degrees turned compared
+12VSW 12 5
with the signal on the gate T7U01.
*) ON mode (STAND-BY mode)

Voltage Booster
This circuit is build around capacitors 2U11 and 2U26, resistor
3U11, diodes 6U22 and 6U23, and transistor 7U07.
It generates the +18 V boost voltage on pin 4 of item 7U00, to
drive the "high-side" power MOS-FET 7U01. The voltage is
generated only during normal operation of the converter;
therefore, any drop in its value means an internal fault
condition, which is sensed by the internal protection circuit.
The AC component of the voltage on the source of transistor
7U01 is rectified by the diodes and added to the input voltage,
resulting into the boost voltage. The resistor 3U11 limits the
peak current through the rectifier diodes.

Over-current Detection
Over-current detection is done via components 3U07, 3U08,
3U82, 3U83, and 2U18 for the 3.3 V converter and 3U09, 3U10,
3U96, 3U97, and 2U12 for the 1.2 V converter.

Under-voltage Detection
There is an additional circuit (7U10 and 7U11) to switch "off"
the 3.3 V converter in case the +12VS drops below 9 V.

Service Tips
• When a power MOS-FET is found defective, replace the
other power MOS-FET and fuse 1U01 as well.
• For a normal operation of the converter, it is important to
check the switching frequency, the value of the boost
voltage, and the amplitude of the gate voltage of transistor
7U04 (it should be close to the boost voltage).

9.2.8 VTUN Generator

The +VTUN supply voltage (value 31...35 V at 4 mA) for the

analog tuner(s) is generated by a boost converter. It uses the
incoming +12 VDC and the pulses have a duty cycle of about
10% from those of the 1.2 V DC/DC converter.

9.2.9 8V6 Switch

• Provides the +8V6-SW supply voltage from the incoming

+8V6.
• It is activated by the ON-MODE signal, which is active
"low". This is needed to switch "off" the +8V6-SW in POD
Stand-by mode, to lower the power consumption.
Note: It is not active if the +5V voltage is not present.
EN 110 9. BP2.2U, BP2.3U Circuit Descriptions, Abbreviation List, and IC Data Sheets

Main Supply SUPPLY DISTRIBUTION IN STANDBY MODE

d.c. power: 0.24 (W) a.c. power: 0.94 (W)
STDBY POD STDBY ON
+12VS +8V6 +5V2 +5V
power 0.00 0.00 0.24 0.00 (W)

SSB
DC-DC DC-DC
12V/3.3V 12V/1.2V
(mA)

1.2V 15 Stdb uP
and 12 (PNX2015)
3.3V
stabilizers 1 Serial Flash

(mA) 0 0 45 0 0 0 0 0
LEDs + IR sensor
8
(outside SSB)
+12V switch

0 Splitter +OOB tuner

0
0 NXT2003
0

0 STV701

CAM
0

+2V5D stabilizer

0
0 Viper2
0

9 DDR

0 NAND Flash

0 Tuner

0 IF amplifier

0
PNX3000
0

0 HDMI

0
0 PNX2015
0

0 DDR

0 MOP

0 Ethernet

0 1394 Link
0 1394 Physical

0
USB 2.0
0

0
0
Audio + I/O
0
0
+12VSW +12VS +8V6 +5V2 +5V +3V3 +2V5D +2V5 +1V2
F_15400_006.eps
100505

Figure 9-5 Supply distribution: STANDBY Mode (mentioned values are indicative)
 Circuit Descriptions, Abbreviation List, and IC Data Sheets BP2.2U, BP2.3U 9. EN 111

Main Supply SUPPLY DISTRIBUTION IN POD MODE

d.c. power: 10.78 (W) a.c. power: 15.40 (W)
STDBY POD STDBY ON
+12VS +8V6 +5V2 +5V
power 8.48 0.00 0.35 1.91 (W)

SSB
DC-DC DC-DC
12V/3.3V 12V/1.2V
(mA)

1.2V 30 Stdb uP
and 18 (PNX2015)
3.3V
stabilizers 10 Serial Flash

(mA) 707 0 67 375 1266 100 298 433

LEDs + IR sensor
9
(outside SSB)
+12V switch

144 Splitter +OOB tuner

53
120 NXT2003
16

24 STV701

CAM
760

+2V5D stabilizer

190
85 Viper2
70

100 DDR

1 NAND Flash

0 Tuner

0 IF amplifier

200
PNX3000
50

28 HDMI

190
85 PNX2015
70

8 DDR

80 MOP

17 Ethernet

10 1394 Link
50 1394 Physical

130
USB 2.0
0

10
31
Audio + I/O
0
50
+12VSW +12VS +8V6 +5V2 +5V +3V3 +2V5D +2V5 +1V2
F_15400_007.eps
100505

Figure 9-6 Supply distribution: POD STDBY Mode (mentioned values are indicative)
EN 112 9. BP2.2U, BP2.3U Circuit Descriptions, Abbreviation List, and IC Data Sheets

Main Supply SUPPLY DISTRIBUTION IN ON MODE

d.c. power: 23.66 (W) a.c. power: 47.38 (W)
STDBY POD STDBY ON
+12VS +8V6 +5V2 +5V
power 20.62 2.18 0.35 12.11 (W)

SSB
DC-DC DC-DC
12V/3.3V 12V/1.2V
(mA)

1.2V 30 Stdb uP
and 18 (PNX2015)
3.3V
stabilizers 10 Serial Flash

(mA) 1718 254 67 2375 2911 250 735 2595

LEDs + IR sensor
9
(outside SSB)
+12V switch

144 Splitter +OOB tuner

285
235 NXT2003
40

30 STV701

CAM
780

+2V5D stabilizer

1110
250 Viper2
180

250 DDR

30 NAND Flash

130 Tuner

34 IF amplifier

300
PNX3000
50

330 HDMI

1200
125 PNX2015
300

125 DDR

500 MOP

116 Ethernet

200 1394 Link

81 1394 Physical

314
USB 2.0
1900

10
31
Audio + I/O
90
50
+12VSW +12VS +8V6 +5V2 +5V +3V3 +2V5D +2V5 +1V2
F_15400_008.eps
100505

Figure 9-7 Supply distribution: ON Mode (mentioned values are indicative)

 Circuit Descriptions, Abbreviation List, and IC Data Sheets BP2.2U, BP2.3U 9. EN 113

9.3 Inputs drawn from the USB ports, the protection becomes active (=
"high").
9.3.1 USB During stand-by, when there is no +5V available (and VIPER is
not active), the USB port does not work. This is controlled by
the VIPER via the USB_BUS_PW line (see diagram B5A),
These chassis have different USB specifications:
which switches the 5V input to the outputs of IC7Q01.
• Chassis BP2.2 features USB2.0. This USB version is
hosted by a separate IC (7N00) which communicates with
USB2.0
the VIPER via a PCI bus.
• Chassis BP2.3 features USB1.1. This USB version is
hosted directly by the VIPER.

Each USB port has four lines: POWER Cardreader USB 2.0
+5V
1. 5V (red). GND SUPPLY
2. D- (white).
3. D+ (green).
4. GND (black).
Card slot 0
media CF I, CFII, MD
USB 1.1 interface Card slot 1
VIPER MS, MSpro, SD,
MMC, SM, xD
USB 1.1 5V
HOST USB
2.0
EN
Current
OC limiter USB A
conn Card
Reader
overcurrent protec USB 2.0 slot A
enable 5V +5V
USB USB 2.0
tion D-
USB USB 2.0 D+
cable USB 2.0 GND
D+ 2.0
HUB
D-
overcurrent prote USB 2.0 slot B
enable 5V
USB 2.0
ction +5V
D-
D+
GND

F_15400_109.eps
180505

Figure 9-9 Multimedia card reader assy

USB 2.0 9.3.2 HDMI

VIPER

Introduction
5V
power Note: Text below is an excerpt from the ”HDMI Specification”
PCI cable that is issued by the HDMI founders (see http://www.hdmi.org).
Card
USB A Reader
conn This High-Definition Multimedia Interface is developed for
ISP1561 transmitting digital television audiovisual signals from DVD
USB
cable players, set-top boxes and other audiovisual sources to
Not used
television sets, projectors and other video displays.
USB 2.0 HDMI can carry high quality multi-channel audio data and can
HOST
carry all standard and high-definition consumer electronics
video formats. Content protection technology is available.
F_15400_108.eps HDMI can also carry control and status information in both
250505
directions.

Figure 9-8 USB configurations As shown in the HDMI block diagram, the HDMI connector
carries four differential pairs that make up the TMDS
USB1.1 (Transition Minimized Differential Signalling) data and clock
The USB1.1 is a hardware block in the VIPER. There are two channels. These channels are used to carry video, audio, and
USB ports. Each port has a D+ and D- line; this is the auxiliary data. In addition, HDMI carries a VESA DDC channel.
differential signal path for USB. There is also one over-current The DDC is used for configuration and status exchange
detect and power enable line that is used for both ports (these between a single source device and a single sink device.
lines are controlled by VIPER).
A tandem USB connector is mounted on the SSB, on which you
can connect two USB devices; one device will be the SCM
digital media card-reader. Only USB mass storage class device
is supported, so other USB devices (card-readers) have to be
compliant with this class.
The host (= SSB) needs to provide the power supply to the
attached devices (like memory cards or other USB devices).
Since it is not known what the customer will attach (e.g. a USB
hub with multiple USB devices), and these USB devices draw
current from the SSB, these supply lines must be protected
against over-current and/or too many connected devices.
This is controlled by the VIPER via the USB_OVERCUR line
(see diagram B5A): when more then 500 mA per channel is
EN 114 9. BP2.2U, BP2.3U Circuit Descriptions, Abbreviation List, and IC Data Sheets

– HDMI connectors (Video, Audio, HDCP, Control).

HDMI Source HDMI Sink
– Analogue (YPbPr, RGB, and H/V).
• Control signals:
– I2C coming from TDA9975 (MM-BUS1).
Video Video
TMDS Channel 0 – 13.5 MHz clock for analog format detection.
TMDS Channel 1
– JTAG.
Audio Transmitter TMDS Channel 2 Receiver Audio
• Output to PNX2015: Video (DV4 and DV5):
– YUV 4:2:2 20 bit (10 bit Y, 10 bit UV multiplexed) +
TMDS Clock Channel
clock + sync.
EDID
ROM
– ITU-656 (compressed DVD video) encoded in data
stream.
Display Data Channel (DDC) • Output to VIPER:
– Audio: S/PDIF.
E_13950_062.eps – Interrupt signal.
120304

Data Content
Figure 9-10 HDMI block diagram HSYNC

vertical blanking
45 lines
Control
Audio, video, and auxiliary data is transmitted across the three
Period Video
TMDS data channels. The video pixel clock is transmitted on V
S
Y Data
the TMDS clock channel and is used by the receiver as a N
C Period
frequency reference for data recovery on the three TMDS data

525 total lines

channels. Data
Island

480 active lines

Period
Active Video
Video data is carried as a series of 24-bit pixels on the three
TMDS data channels. TMDS encoding, converts the 8 bits per
channel into the 10 bit DC-balanced transition minimized
sequence, which is then transmitted serially across the pair at
a rate of 10 bits per pixel clock period. F_15400_011.eps
210405

Video pixel rates can range from 25 MHz to 165 MHz. Video
formats with rates below 25 MHz (e.g. 13.5 MHz for 480i/ Figure 9-11 Typical video frame
NTSC) can be transmitted using a pixel-repetition scheme. The
video pixels can be encoded in either RGB, YCBCR 4:4:4, or A typical video frame is built up with the following info blocks:
YCBCR 4:2:2 formats. In all three cases, up to 24 bits per pixel • Control Period.
can be transferred. – Transmission of the pre-amble.
– Character synchronization.
In order to transmit audio and auxiliary data across the TMDS • Data Island Period.
channels, HDMI uses a packet structure. In order to attain the – Audio and auxiliary information are carried in packets
higher reliability required of audio and control data, this data is within a Data Island.
protected with a BCH error correction code and is encoded – HSYNC, VSYNC are also carried during Data Island
using a special error reduction coding to produce the 10-bit Period.
word that is transmitted. – Packet Types:
Basic audio functionality consists of a single IEC 60958 audio – Audio Sample.
stream at sample rates of 32 kHz, 44.1 kHz, or 48 kHz. This can – Audio Clock Recovery.
accommodate any normal stereo stream. Optionally, HDMI can – InfoFrame: Aux. Video IF, Audio IF, MPEG IF,
carry a single such stream at sample rates up to 192 kHz or vendor-defined IF.
from two to four such streams (3 to 8 audio channels) at sample • Video Data Period.
rates up to 96 kHz. HDMI can also carry IEC 61937 – Carries the pixels of an active video line.
compressed (e.g. surround-sound) stream at sample rates up – TMDS encoding.
to 192 kHz.
Data Islands: Audio Formats
The DDC is used by the source to read the sink’s Enhanced • All current CE audio formats can be transmitted.
Extended Display Identification Data (E-EDID) in order to • Supports compressed formats like:
discover the sink’s configuration and/or capabilities. – Dolby Digital.
– Dolby Digital EX (THX-EX).
HDMI is backward compatible with DVI (1.0). Compared with – DTS.
DVI, HDMI offers extra: – Etc.
• YUV 4:4:4 (3 x 8-bit) or 4:2:2 (up to 2 x 12-bit), where DVI • Supports uncompressed formats (“discrete” PCM audio):
offers only RGB 4:4:4 (3 x 8 bit). – Up to 8 channels, up to 192 kHz, up to 24 bits.
• Digital audio in CD quality (16-bit, 32/44.1/48 kHz), higher • CD-quality audio is always available, so the user will
quality available (8 channels, 192 kHz). always hear sound.
• Remote control via CEC bus (Consumer Electronics – 2 channel, 16 bit at 32 kHz (STB), 44.1kHz (CD), or 48
Control): allows user to control all HDMI devices with the kHz (DVD)
TV's remote control and menus.
• Smaller connector (SCART successor). Data Islands: InfoFrames (EIA/CEA-861B)
• Less cables: e.g. from 10 audio/9 video cables to 3 HDMI • Auxiliary Video Information (AVI):
cables. – Specifies active aspect ratio, colorimetric info, pixel
encoding, etc.
Implementation • Audio InfoFrame:
The IC used is the TDA9975 (triple 10-bit video converter – Describes audio stream, speaker/channel allocation,
interface), item 7B11 on the SSB. etc.
• Power supply: 3V3 and 1V8. • Source Product Info:
• Inputs:
 Circuit Descriptions, Abbreviation List, and IC Data Sheets BP2.2U, BP2.3U 9. EN 115

– Contains manufacturer name, product name, type, etc.

FRONT-END VIPER
(replaced by CEC).
• MPEG Source: RF FAT DEMOD DEMUX A/V
TUNER
DECODER
– Contains flags that permit optimized display of de- MPEG MPEG
(SCRAMBLED)
compressed video. QPSK (DESCRAMBLED)
FDC DEMOD
• Vendor unique info. RX BYPASS CPU
EMM QPSK
MESSAGES SYMBOLS COMMANDS

Content Protection: HDCP 7P03

STV0701
HOST-POD INTERFACE CONTROLLER CHIP
• HDCP (High-bandwidth Digital Content Protection) for
HDMI encrypts and protects video, audio, and other
OOB CAS
auxiliary data. PROCESSOR PROCESSOR
F_15400_073.eps
• If a source device is HDCP coded and is connected to a POD MODULE 130505
HDTV display or projector via DVI/HDMI without the proper
HDCP decoding mechanism, the picture is relegated to Figure 9-12 In Band channel reception (without POD inserted)
"snow" or in some cases, a very low (480p) resolution. In
order to see HDTV with HDCP compliance, both the source
and display devices must be equipped with DVI/HDMI FRONT-END VIPER

connections that can enable HDCP using "software key" 1

5
FAT A/V
RF TUNER DEMOD DEMUX
decoding. DECODER
MPEG MPEG
• HDCP requires that decoding takes place in the display QPSK (SCRAMBLED) (DESCRAMBLED)
DEMOD 4
device (no external converters). FDC
RX BYPASS CPU
EMM QPSK 2
MESSAGES SYMBOLS COMMANDS
CEC Bus (Consumer Electronics Control) 7P03
HOST-POD INTERFACE CONTROLLER CHIP
STV0701
• This is the successor of the P50 protocol.
• It allows the user to control all HDMI devices with the TV's
remote control and menus. OOB CAS
3 PROCESSOR
PROCESSOR
• High-level functions such as “One-touch play”. F_15400_074.eps
POD MODULE 300505
• Optional for device to implement protocol.
• Mandatory to implement wire pass-through.
Figure 9-13 In Band channel reception (with POD inserted)

9.4 Front-End POD Working Principle

See description in paragraph “Introduction” -> “Chassis Block
Diagram”.
9.5 POD (Point Of Deployment)
9.5.1 Introduction
This chassis is provided with a special slot called
CableCARD™. This means that it is not necessary to have a
separate Set Top Box to receive digital cable SDTV and HDTV
programs (however this is still possible).
The CableCARD (or POD) is a removable card distributed by
cable companies, which is inserted into the slot at the bottom
of the television. It allows you to tune digital and high definition
scrambled or encrypted cable channels through the cable
antenna. The CableCARD is also required to receive premium
digital TV channels and services (where available) through the
cable. A CableCARD functionality includes conditional access
and copy protection.
9.5.2 Implementation
The POD is a removable CAM, implementing the CA system
for a Host (i.e. the TV set). The POD module is inserted into a
standard PCMCIA slot in the Host.
When the POD is inserted into the Host, it goes through an
initialization procedure, which is called the "POD personality
change". This initialization procedure consists of:
• POD and Host verify each other’s identity by means of
certificate and/or key exchange.
• Reporting POD-ID and Host-ID to the Cable Head end, in
order to entitle the POD for descrambling services. In case
of uni-directional operation (as for this chassis), this
reporting requires user-interaction.
• Key generation for secure communication between POD
and Host.
After initialization, the POD is used to unscramble any
particular scrambled service in the In Band (IB) transport
stream. The host must provide the selection choice (which
program to descramble). The host can only do so if it gets
specific data like PSIP (Program and System Information
Protocol) data from the POD.
The POD implements a copy protection system, so the
unscrambled Transport Stream signal from POD to Host can
be re-scrambled.

1. The receiver receives the digital data stream.
2. The data flows into the Conditional Access Module, which
contains the content provider's unscrambling algorithms.
3. This module verifies the existence of a smart card (POD)
that contains the subscriber's authorization code.
4. If the authorization code is accepted, the CAM
unscrambles the data and returns the data to the receiver
(if the code is not accepted, the data remains scrambled,
restricting access).
5. The receiver then decodes the data and outputs it for
viewing.
Copy Protection (CP)
• Every TV-set has its own unique Host-certificate (with
Host-ID). These certificates are stored on a dedicated PC
at the TV supplier.
• The CP-key is refreshed at the following times:
– At the end of the authentication process.
– Periodically at a rate set by max_key_session_period.
– At every power cycle.
– When initiated by the CA System.
– At every hard reset.
– At power-up, the POD checks the Auth-key to see if the
host is still the same, after this the re-authentication
takes place.
– During CP-refresh is the transport stream in the clear
(<1s)

POD Stand-by Mode

• POD stack still alive:
EN 116 9. BP2.2U, BP2.3U Circuit Descriptions, Abbreviation List, and IC Data Sheets

– Active Front-End. – Application code download.

– Active VIPER, Stby-uP. – Only from cable operator towards user.
• Allows the POD to request services: – Service Information (SI) like:
– Listen to OOB. – PMT: TS Program Map Table.
– Firmware upgrade. – PAT: Program Association Table.
– CAT: Conditional Access Table.
Connector – STT: System Time Table.
• Mechanical – Emergency Alert Service (EAS)= US federal system
– 68 pins PCMCIA connector. for alerting the public to emergencies; works before
– Voltage keying (LV type). and after CableCARD insertion
– Type I, II, III.
• Hot plug ability
9.6 MPIF (PNX 3000)
– Initial, VCC is applied to the socket.
– Card detection (CD1 & CD2 = low).
– Voltage sense pins (VS1 & VS2). 9.6.1 Introduction
– Power controller to set VCC and VPP.
• CIS structure The MPIF (Multi Platform InterFace, type number PNX3000,
– All PCMCIA cards have a CIS structure. item number 7C00) is an analog video and audio pre-
– Information about size, speed, functions, ... processing unit for the AVIP TV processor. It contains the high
– Distinguish between PC-card and Cable-card. frequent IF part and all the analog video and audio source
– Before reading the CIS, the PCMCIA driver is in an 8- switching for external in- and outputs. The MPIF can handle
bit memory card mode with reduced address- and CVBS, Y/C, RGB (1fH/2fH) and YPbPr (1fH/2fH) video signals
control lines (only purpose is to read the CIS). as well as stereo, I2S, and second sound IF audio signals. The
– After reading the CIS, there is a personality change MPIF converts the selected video and audio streams from the
and the driver is ready to communicate with a Cable- analog to the digital domain. Via three high-speed serial data
card. links (I2D), the digitized audio and video signals are streamed
– Once a card's client driver successfully parses the CIS (594 Mbit/s) to the AVIP IC for further processing.
and obtains the system resources required by the card, The MPIF uses a clock coming from the AVIP of 13.5 MHz and
it assigns the resources to the card via the COR is I2C driven. The supply voltage for the MPIF is 5V.
(Configuration Option Register).
• POD pinning. The MPIF uses the following input signals:
• CVBS, Y/C, YPbPr, or RGB video format.
• 1fH or 2fH video.
COPY
MPEG-2 PROTECTION • Clock 13.5 MHz from the AVIP.
MPEG-2 TRANSPORT ENGINE
TRANSPORT DEMULTIPLEXER • I2C from the VIPER.
STREAM AND
REMULTIPLEXER PAYLOAD • Clamping-pulse from the AVIP.
DECRYPTION
ENGINE
POD
INTERFACE
SECURE 9.6.2 Block Diagram
OUT OF BAND LOGIC OUT OF BAND
CPU uP
SERIAL DATA PROCESSING
Following figure shows the MPIF block diagram:
COMMAND
MEMORY CONTROLLER
INTERFACE

Control Video Sound

FLASH RAM CVBS_out
POD MODULE
PCMCIA F_15400_075.eps
CONNECTOR 100505
Video Video
Video Video
IF output
IF Processing ADC
Figure 9-14 Example of POD design Selection

Video Video Multi- I2D I2D

Source plexer Link
9.5.3 Communication Channels Base
Selection
band

Sound Sound Sound

Sound IF
In Band (IB) IF
Processing
2nd IF IF ADC
Selection
• Forward Application Transport channels (FAT): Sound
low-IF Audio Audio
– 256 QAM modulation (8 bits/symbol). Base band Base band
AM
– 54 - 864 MHz. Demod.
Selection ADC

– 6 MHz bandwidth. Audio Audio I2C

Base Output Clocking I2C
– Carry information via MPEG-2 streams. band Selection
Interface

– Scrambled In-Band Channels.

– TS packet header. LR_out
CL 36532058_065.eps
281003

– In-the-Clear channels.
• NTSC analog channels:
– 8-VSB modulation (3 bits/symbol). Figure 9-15 MPIF block diagram
– 54 - 806 MHz (UHF and VHF)
– 6 MHz bandwidth. 9.6.3 IF Processing
– Not via POD, but via MPIF.
– With VBI (Vertical Blanking Interval) signals for closed The MPIF is capable of demodulation of RF signals.
captioning.
Analogue Vision IF Processing
Out Of Band (OOB) Some specifications:
• Forward Data Channels (FDC): • Synchronous demodulation of the IF vision carrier.
– DQPSK modulation (2 bits/symbol). Selectable frequency and auto-calibration of the VCO
– 70 - 130 MHz. (Voltage controlled oscillator).
– 6 MHz bandwidth. • Group delay correction for BG system.
– Spaced between 6 MHz FAT and analog channels.
– Control and Access messages.
 Circuit Descriptions, Abbreviation List, and IC Data Sheets BP2.2U, BP2.3U 9. EN 117

• AGC at vision IF level to give fixed CVBS output level, and

cntv cnta
AGC at RF level (tuner AGC) to limit output level of the SCART2 out / Ext2 out

Jaguar system
tuner.
MPIF-

SCART1 out
• AGC gating for bad reception conditions.

Line out
Source Selection

• CVBS amplitude correction and mute. DSND1

DSND2
• Detections for AFC and video presence. AM int
AM ext Audio
L1+R1 outputs
L2+R2 selectors

The video signal is demodulated by means of an alignment- L3+R3

L4+R4
AD I2D
conversion transmission
free PLL carrier regenerator with an internal VCO. This VCO is L5+R5

calibrated by means of a digital control circuit, which uses an Primary audio

datalinks - audio block

Primary/
external crystal frequency as reference. The frequency setting Secondary
A/D datalink1

audio
for the various standards (33.4, 33.9, 38.0, 38.9, 45.75 and selector Secondary audio
A/D datalink2
58.75 MHz) is realized via the I2C bus.
The AFC output is generated by the digital control circuit of the SIF
switch
SIF
A/D datalink3
IF-PLL demodulator and can be read via the I2C bus. SIF
external
AUDIO

The AGC-detector operates on "top sync" or "top white" level. datalinks - video block

The MPIF IC has an integrated sound trap filter. The trap CVI1
CVI switch
Y
U
A/D
Y
Switch datalink1
CVI2 V
frequencies can be switched via the I2C-bus. A/D

YC_COMB
Also, a group delay correction filter is integrated. The filter can CVBS_IF
Primary
UV datalink2
CVBS1 Primary video
be switched between the PAL BG curve and a flat group delay CVBS2
video
selector
A/D

CVBS/YC3
response characteristic. This has the advantage that in multi- CVBS/YC4

standard receivers the video SAW filter does not need to be

switchable (cost effective). Secondary
video/ Secondary video
A/D datalink3
outputs
selectors

Analogue Sound IF Processing CVBS_DTV

Some specifications: VIDEO

• A switch to select QSS or inter-carrier mode.

• Sound carrier frequency conversion at second IF sound
frequency (SSIF)
• A switch to select internal or external SSIF.
• AGC at sound IF level (for QSS (quasi-split-sound) mode)
and AGC at SSIF level (for inter-carrier and QSS modes).
• Demodulation of AM modulated carrier (L and L'
standards).
The MPIF has a separate sound IF input to enable Quasi Split
Sound (QSS) applications. The sound IF amplifier is similar to
the vision IF amplifier and has a gain control range of about 55
dB.
The AGC detector measures the SIF carrier levels (average
level of AM or FM carriers) and ensures a constant signal
amplitude for the AM demodulator and QSS mixer.
For applications without SIF SAW filter, the IC can also be used
in intercarrier mode. In this mode, the composite video signal
from the VIF amplifier is fed to the QSS mixer and converted to
the intercarrier frequency. AM sound demodulation is realized
in the analog domain with the QSS mixer.
9.6.4 Source Selection
E_14700_068.eps
CVBS A out CVBS B out 021104
SetVideoConnection()
SetAudioConnection()
Figure 9-16 MPIF analog source selection block
Video Selectors
The CVI switch (Composite Video Input, including RGB, YUV,
and YPbPr) is selecting the signal from one of the two CVI
inputs; the output is always a YUV signal.
The primary video selector is selecting a signal from the CVBS
and YC inputs; the video coding of the output signal equals to
the video coding of the input signal.
The primary video selector has an extra input (YC_COMB),
capable of selecting an Y/C signal from the comb filter. This
input cannot be downscaled to a CVBS signal and fed back to
the CVBS_A or CVBS_B output. It is also advisable not to
connect other sources to the YC_COMB input because it is
treated as an internal one that is not available for the outside
world.
Two video output selectors are responsible for the contents of
CVBS_A and CVBS_B video out.

Below the main functions and features of the main blocks in the
MPIF for video and audio are explained.
Audio Selectors
The primary audio selector is selecting a signal from five
external stereo inputs and one stereo input that handles two
mono signals (AM internal and AM external). The AM internal
signal is demodulated in the IF part and is internally routed, so
not available as external input. Additionally, the AM internal
signal is available on the left channel whereas the AM external
signal is available on the right channel.
The secondary audio selector is selecting a signal from the
same range as the primary audio selector; the second audio
selector can work in stereo or mono mode. In case the stereo
mode is selected, it is alike the primary audio selector. In mono
mode, the input stereo signal L+R is transformed into a mono
signal (L+R)/2 and put on the left channel of the stereo output.
When the stereo input (handling two mono signals) is selected
and the selector works in mono mode, the AMint and AMext
can be swapped on the primary as well as on the secondary
audio channel. It is also possible to digitize the mono + AM on
the secondary audio channel.
Further it is possible to select the AM signal on the analog
audio outputs independently from the AM signal that is selected
for the secondary (digital) audio channel.
Three audio output selectors are responsible for the content of
the Line, SCART1, and SCART2 outputs. These selectors
EN 118 9. BP2.2U, BP2.3U Circuit Descriptions, Abbreviation List, and IC Data Sheets

allow selection of the output out of five L+R inputs, two mono In the normal mode the data links can handle up to three video
signals (AM internal or AM external) and two externally signals: CVBS or YC signal from the primary video selector,
connected DSND streams. CVI 1fH source selected on the CVI switch, and CVBS signal
from the secondary video selector.
SIF Switching
SIF (Sound Intermediate Frequency) switching allows YUV 2fH Mode
selecting between internal or external SIF signals. In the YUV 2fH mode (higher bandwidth signal) the data links
content is as follows:
AD Converters
The second part of the MPIF is responsible for conversion of Table 9-2 YUV 2fH mode
the chosen signals into digital signals and grouping them into
three data streams. Each data stream handles both video and Data Stream Video Audio
audio. These data streams are fed into three data links and
1 Y 2fH (L+R) primary
send via I2D to the outside.
2 UV 2fH (L+R) secondary
The MPIF contains four video ADCs for analog and digital 3 CVBS secondary SIF
video broadcast signals. The clock frequency for these ADCs Data link Mode bit: DM= 1
is either 27 MHz or 54 MHz. In some cases, two analog signals
are multiplexed at the input of one ADC. In these cases, the
The data link 1 can output only one of two input signals: the
clock frequency of the ADCs is 54 MHz, while the sample
frequency for each of the two signals is 27 MHz. output of the primary video selector or the Y output of the CVI
switch. Only one can be active at a moment, and that is
determined by the data link mode bit (DM). It means, that for
The sample frequency for standard 1fH video signals is 27
MHz. For the YUV channel the sample frequency of the U and data links working in YUV 2fH mode, the data link 1 carries the
Y component of the YUV 2fH signal, the data link 2 carries the
V components is half the sample frequency of the Y signal.
UV component, and the data link 3 contains the signal that is
For 2fH YPbPr or RGB input signals (for instance 480p or 1080i
ATSC signals), the frequency that is used to sample the YUV connected through the secondary video selector.
signals is twice as high as for 1fH signals. The sample
frequency is 54 MHz for Y and 27 MHz for U and V. 9.7 PNX2015
Due to the high sample frequency, two data links are needed
for transport of the video data to the digital video processor.
The functional blocks of the PNX2015 (item 7J00) are:
2
• Audio Video Input Processor (AVIP).
I D Data Link • 3D Comb Filter (COLUMBUS).
The digital interface between MPIF and AVIP is called Data • High Definition MPEG Decoder (HD Subsystem).
Link (or I2D Link). This is a serial interface that transfers the • LVDS transmitter.
data from MPIF to AVIP over three Data Link interfaces. Each • Stand-by Processor for low-power control.
Data Link has a data signal and a strobe signal. The
synchronization information is distributed over the data and the BLOCK DIAGRAM
strobe signal. To minimize EMC, both signal outputs are low
DLINK1
voltage differential swing signals, with a swing of about 300 D
L
I
N
K
VIDDEC DCU ITU
656
PNX2015
PNX3000-1 AUDIO
mV. SYNC DSP/DEMDEC

AVIP-1
Each Data Link has four lines, one differential pair for the data, COLUMBUS
DV1
PNX8550

and one differential pair for the strobe. The data rate is 594 DLINK2 D
L
I
N
VIDDEC DCU ITU
656
K COLMUX
Mbit/s. Each Data Link can carry two 27 MHz sampled video PNX3000-2
SYNC
AUDIO
DSP/DEMDEC
DV1MUX

memory
streams (or one 54 MHz sampled 2fH video stream) and two AVIP-2
controller
SYNC DV3
audio channels sampled at 6.75 MHz. PNX8550
DV4
direct 0-9
video VIP VO-1
DV5 DV3MUX
10-19
In the MPIF, the (video and audio) data to be transmitted is
HUB
multiplexed in an output register of 44 bits (including the 2 bit RX/TX 0-9 DV2
PNX8550 SOUTH PNX8550
sync information). The content of that 44 bits register is serial TUNNEL
VO-2
10-19
transmitted on one of the three data links. In the AVIP, the DV2MUX

serial data is de-multiplexed into parallel streams. The data on 16-bit

200 MHz MEMORY
MBS
DDR CONTROLLER
the data link is divided in several groups of signals (video, audio PNX8550
TV
and strobe signals). Obvious it is important that the transmitter Microcontroller Power Control
video RX/TX NORTH
and receiver are in the same transmitting mode coprocessor TUNNEL VMPG

HD SUBSYSTEM

Data links can operate in two different modes called: RGB,

HV TA, TB, TC, TD, TE, CLK
PNX8550 LVDS_TX LCD panel
1. Normal mode.
F_15400_105.eps
2. YUV2fH. 180505

Normal Mode Figure 9-17 Block diagram PNX2015

In the normal mode the content of the data links is as follows:
These different blocks are described separately in the next
Table 9-1 Normal mode paragraphs.

Data Stream Video Audio

1 CVBS/YC primary (L+R) primary
2 YUV 1fH (L+R) secondary
3 CVBS secondary SIF
Data link Mode bit: DM= 0
 Circuit Descriptions, Abbreviation List, and IC Data Sheets BP2.2U, BP2.3U 9. EN 119

9.8 PNX2015: AVIP The receiver block gets the serial data stream and converts it
to a parallel stream. This parallel data is fed to the "de-
9.8.1 Introduction multiplexer and formatter " block where the selected audio/
video stream is forwarded to the video and audio decoder for
further processing. This communication bus is completely
The AVIP (Audio Video Input Processor) receives the digital
digital and very difficult to monitor.
data via the I2D link (coming from MPIF). It reformats this data
and maps (synchronizes) the data to the clock of the AVIP.
The I2D link has the following characteristics.
Then a digital AGC is passed. After this, the video decoding is
• The data-link runs at 297 MHz / 594 Mbps.
performed in the VIDDEC-block of the AVIP. The decoded • The driver rise/fall time is around 200 ps.
video is sent to an output block, which formats the data to an
• The data-link uses differential signals.
ITU-656 compatible standard data stream.
The AVIP power supply is 1.2 V and 3.3 V. To ensure
synchronization of video streams processed across the VIPER VIDDEC (Video Decoder)
and PNX2015 devices, a 27 MHz is coming from the VIPER. Video Decoder
The AVIP is I2C driven.
Initialization of this IC begins with a hard reset (MIPS-RESET) Yyc
CVBS/Yyc
YUV
provided by the VIPER. Besides video decoding, the AVIP is Digital Multi
also used for decoding and presentation of all audio output Standard Decoder
Yuv/Cyc
Cyc (DMSD)
streams in the system. AGC
Yuv mux YUV
Uyuv Uyuv (Fast blank)
9.8.2 Block Diagrams Vyuv Vyuv

Sync FBL1

Below the main functions and features in the AVIP for video FBL1/Hsync1
FBL2/Hsync2 sync FBL2
and audio are given.
Vsync1
Vsync2 HVsync

E_14700_071.eps
021104
I2D1 CVBS/YC/YUV Cvbs_yyc
VIDDEC
Figure 9-20 VIDDEC block diagram
ITU-656
I2D2 ITU-656
I2D
The CVBS/YC/YUV signals (coming from the I2D receiver
DCU
I2D3 VBI bytes block) enter the DMSD block (Digital Multi Standard Decoder)
via the AGC (Automatic Gain Control) block. The multiplexer
SIF or L/R
L block (MUX) takes care of the correct output signal. The sync
DemDec Audio signals are processed in the sync block.
Processing
R
GP The VIDDEC has the following main functions:
• Multi standard color decoder.
• Automatic system recognition.
I2SIn E_14700_069.eps • Fully programmable static or automatic (AGC) for all
I2Sout 310505
analog video base band signals.
• AGC on sync amplitude in digital domain.
Figure 9-18 AVIP block diagram
• Selectable peak white control.
• AGC for chrominance (PAL and NTSC only).
Main AVIP function: • Programmable Luminance and Chrominance bandwidth
• I2D receiver. for CVBS and Y/C sources.
• Color decoding into ITU-601 compatible format (1fH/2fH). • Programmable clamp window for the selected video base
• Interface with 3D comb filter (called Columbus in this band signals.
chassis). • Digital PLL for synchronization on 2fH and ATSC
• VBI data capture via DCU (Teletext, CC, etc.). standards.
• ITU-656 formatting. • Horizontal (including 3-level sync for 2fH) and vertical sync
• Audio demodulation and decoding via DEMDEC. detection.
• Audio processing and D/A conversion. • Automatic detection of 50/60Hz ATSC field frequency.
• Adaptive 2/4-line delay comb filter for two-dimensional
I2D Receiver Chrominance/Luminance separation.
• Copy protected source detection according to MacroVision
I2D transmitter I2D AVIP
up to version 7.01
CVBSpri /YC/
Yyuv • Possibility of RGB insertion through fast blanking in CVBS
I2D I2D CVBSpri /Yyc
transmitter receiver input mode, not in Y/C.
v id e o d e m u lti p le x e r /

L1/R1
Yyuv / Cyc
fo r m a t te r

VAL1 UVyuv

CVBSsec
YUV/ UVyuv
I2D I2D VAL
VAL2
transmitter L2/R2 receiver
a u d i o d e m u lt i p le x e r /

L1/R1
f o r m a tt e r

VAL3
CVBSsec L2/R2
I2D I2D
transmitter SIF receiver SIF

E_14700_070.eps
300505

Figure 9-19 I2D receiver block diagram

EN 120 9. BP2.2U, BP2.3U Circuit Descriptions, Abbreviation List, and IC Data Sheets

DCU (Data Capturing Unit) DEMDEC (Demodulator and Decoder)

Data Capture Unit f pilot DEMDEC DSP
MPX 2
demod.
I2d Data_1
(cvbs) Packet VBI data SAP / EIAJ 2 DEC L/A
Decimator Data Slicer SERPAR packets demod.
DEC R/B
Formatter

dematri x & sel ect

I2d Data_2 fs = 27 MHz
FM / AM
pre-process
SRC MONO
(Y) decimation demod.
SIF ch. 1 decimation SAP
down
mixer filters, 5 channels
FM / AM PIPMONO
decimation demod.
deemph.,
ch. 2 dbx, 2 ADC
FM ident select
H/V Sync f1 f2 noise
Acquisition NICAM
detector

Field Id Timing demod. &

decoder
4
ADC1,2, PIPMONO, Ext. AM

E_14700_072.eps
hardware DDEP (DemDec Easy Programming)
310505 control &
status reg.
control / status registers (XMEM)

Figure 9-21 DCU block diagram E_14700_074.eps

300505

The purpose of this block is to acquire digital data (containing Figure 9-23 DEMDEC block diagram
Teletext, Closed Captions, ...) from a CVBS/Y/C video input
source. It performs processing on the received data and
The demodulator and decoder (DEMDEC) is responsible for
provides the data to the ITU-656 formatter unit.
demodulating and decoding incoming SIF signals.
The decimator reduces the sample rate (from 27 MHz to 13.5
MHz) of the incoming digitized CVBS or Y data stream from the
The main features of the DEMDEC are:
I2D receiver. From the video input, the data slicer reconstructs
• Auto Standard Detection (ASD).
the transmitted bit stream and associated clock. The SERPAR
• DQPSK demodulation for different standards,
block converts the serial bits, coming from the data slicer, into
simultaneously with 1-channel demodulation.
parallel bytes. The packet processor performs data decoding
• NICAM decoding (B/G, I, D/K, and L standard).
and some error correction, assembles received bytes into
• Two-carrier multi standard FM demod. (B/G, D/K and M).
packet structure, and streams out the data to the ITU-656
• Optional AM demodulation for system L, simultaneously
formatter.
with NICAM.
The acquisition-timing block locks onto sync signals, and
• Identification A2 systems (B/G, D/K and M standard) with
provides timing information to the other blocks of the data
different identification time constants.
capture unit.
• FM pilot carrier present detector.
• BTSC MPX decoder.
ITU656 Output Formatter • SAP decoder.
ITU656 Formatter
• dBx noise reduction.
• Japan (EIAJ) decoder.
• FM radio decoder.
YUV Video Data
ITU_out (9:0)
Processing Audio Processing
SERPAR ITU_Clk 6
Level Adj.

I2S IN 1 to 6
ADC (L/A, R/B)

VBI data PIPMONO

VBI Data
DEC (L/A,R/B, Mono, SAP)
(L+R)/2
packets L,R (M,ST, 5.1)

Processing ITU_DATA_VALID L,R,C,Ls,Rs (DPL II) MAIN MAIN

L,R L,R (DPL II)
AVL L,R
OFF/ I-Mono /

DPL II ® Contr.
MAIN MSel

Ba/Tr SM
L, R

5 + DAFO1
or EQ
Acoustical Compensation
MAIN

L,R (M,ST, 5.1)

I-Stereo

in L,R or SUB
Master Volume & Trim
DUB or DBE

Loudn. DAFO2
L,R VIRT or
Automatic Volume Leveling

L,R VIRT Beeper DAFO3

C IN
VDS ® BBE®
Bass Management
S/Ls C

522,523
Digital Input Crossbar ( SSel, Matrix )

Digital Output Crossbar

S/Ls IN
VDD ® DAFO4
SW Filter

Rs IN 522,523 C VIRT C
SUB
C
Rs

SUB

Ba/Tr
C SM DAFO5
C (DPL II) or EQ
C IN
MSel Loudn.
E_14700_073.eps DAFO6
C Hall/Matrix
Ls C
310505 (L+R)/2 Ls/Rs SM +
C

Hall/ DAFO7
Ls,Rs (DPL II) Ba/Tr
Matrix S/Ls IN S,Ls Rs or EQ
Rs IN Rs Ls DAFO8
Rs Ls

Ls
Delay

MSel SM
S Hall (L+R)/2 I2S1L,R OUT
Figure 9-22 ITU656 formatter block diagram S Matrix (L-R)/2 LFE Level Rs
Rs
LFE

Adj. SM to
Noise/
AUX1

Silence I2S6L,R OUT

Gen. AUX1/ HP AUX1 AUX1 AUX1 DAC1
Ba/Tr Vol/Trim SM +
The ITU656 formatter gets YUV data as video input signal, L,R

AUX2,3,4,5,6 AUXx AUXx

AUX2-6

DAC2
coming from the VIDDEC block. These YUV data are either 5 equal channels for I2S, DAC1, DAC2
Vol/Trim SM L,R
Audio Monitor
decoded CVBS signals, matrixed RGB signals, or YUV input E_14700_075.eps
250505

signals. The second input data are VBI sliced data coming from
the DCU. The output of the ITU delivers a data stream, which Figure 9-24 Audio processing block diagram
is ITU-601/656/1364 compliant, and includes video as well as
the VBI data. Main features are:
• Master volume control and Balance.
• Tone control (Loudness, Bass, Treble, Equalizer).
• Dolby ProLogic delay.
• Incredible Mono and Stereo.
• Virtual Dolby Surround (VDS 522, 523).
• Virtual Dolby Digital (VDD 522, 523).
• Digital audio I/O interface (stereo I2S input interface).
• Eight audio DACs for six channel loudspeaker outputs and
stereo headphones output.
• Audio DACs for stereo SCART output and stereo LINE
output.
• Serial data link interface for interfacing with the analog
multi-purpose interface IC PNX3000 (MPIF).
 Circuit Descriptions, Abbreviation List, and IC Data Sheets BP2.2U, BP2.3U 9. EN 121

9.9 PNX2015: Columbus (Comb Filter) the banks via I2C, by programming bits [2:0] of the
SYSTEM_SELECT register. The bits [6:4] of the
9.9.1 Introduction SYSTEM_SELECT register select, which register bank is used
by Columbus to define the filter settings.

This block provides the following picture improvement
functions:
• Enhanced 2D combing for PAL and NTSC.
• 3D field combing for PAL and NTSC.
• 3D frame combing for PAL and NTSC.
• Spatial noise reduction for all component video standards.
• Temporal noise reduction for all component video
standards.
The comb filter is controlled via a separate I2C interface on the
PNX2015, this is to ensure registers containing measurement
information, are accessed at appropriate times. The
measurement information is also available as ancillary data
within the video stream (ITU-656).
For certain features of the comb filter, access to external
memory is required. The PNX2015 has a unified memory that
both comb filter and HD subsystem’s share concurrently.
9.9.2 Block Diagram
CONTROL
Bank number System
0 PAL B, G, H, I, D, K
1 PAL M
2 PAL N
3 NTSC
4 Bypass
Internal Test Generators
There are two test generators inside the COLUMBUS chip:
• The "656 test generator" generates a 656 compliant stream
and is used for testing the functionality of the 656 encoder
and decoder. The 656 stream can be injected at the front
end or the back end of the chip.
• A second internal test pattern generator enables testing of
the device and attached external memory (if present). The
test pattern generator signal can be inserted at the front
end of the chip (passing through the 3D Comb and noise
reduction system and external memory) or at the back end
of the chip. Test patterns are available for both PAL/
SECAM and NTSC systems.
A(11:0) DQ(16:1)

Memory Interface 9.10 PNX2015: HD Subsystem

656
Test
Generator

Pattern
The HD subsystem performs MPEG video decoding on HD/SD
Test
Generator transport streams. It interfaces with the PNX8550 and video
Y (ITU656) coprocessor via tunnel interfaces, HD/SD using DV4 and DV5
Mux
656 Encoder
Mux

inputs, and PNX8550 using DV1, DV2 and DV3 outputs. The
Local Regression

Noise Reduction
656 Decoder

PAL & NTSC

SWAN 3D
3D Comb

SEL656
Y/CVBS
HD subsystem can also perform horizontal and vertical scaling
&

WEB/DAVB of video images, and perform a range of video measurements

WEA/DAVA UV (ITU656)
Mux

UV on a transport stream.
SEL656

Noise
Measurement E_14700_083.eps
300505
9.11 PNX2015: LVDS Transmitter

Figure 9-25 COLUMBUS internal block diagram Low Voltage Differential Signaling (LVDS) is a low-power, low-
noise differential technology for high speed data transmission
Figure above, shows a block diagram of the Columbus comb over two PWB traces, or a balanced cable. LVDS allows single-
filter in the PNX2015 device. An input video signal is supplied channel data transmission at hundreds, or even up to a
by the AVIP and fed to the Columbus block. The signal is thousand Mbps. Low swing and current-mode driver outputs
supplied in digitized components of: create low noise and provide very low power consumption
• CVBS or Y. across frequency ranges.
• Uncombed U. The LVDS transmitter IP provides a connection interface to
• Uncombed V. FPDs.

The CVBS signal is combed, extracting the luminance Differences between standard and LVDS signalling:
components and rejecting the chroma components. The UV • Standard single ended signal (TTL):
signals are combed, rejecting the left over luminance – Requires 28 signal lines and more than 14 grounds.
components, from a previous filtering (normally band pass – Single ended signals up to 3 V.
filtered). – Wide flat ribbon cable.
– EMI/EMC problems.
The outputs from the 3D comb filter are: – Feasible up to VGA/NTSC resolution (limited to 250
• Combed luminance signal (Y). Mb/s).
• Combed U signal. • LVDS:
• Combed V signal. – Five low voltage (350 mV) differential pairs: one clock
pair and four data pairs.
– Five grounds.
The output from the 3D comb filter feeds the SWAN and LORE
– EMI/EMC friendly.
noise reduction block, which performs spatial/temporal noise
– WXGA and HD-1280x720p (up to 1 Gb/s).
reduction, for both luminance and chrominance components.
LVDS offers superior performance compared to the standard
Control Register Interface single ended signal (TTL).
The control registers are accessed via I2C. Most signals that It is even "protocol independent" so it requires no software.
can be written via I2C are double buffered. The fast I2C
interface implemented on the COLUMBUS is a 5V compliant,
400 kHz slave receiver/transmitter. The I2C will not be blocked
during voltage shorts or opens.

For the system dependent parameters of the 3D-Comb filter,

five register banks are present. Data can be written in one of
EN 122 9. BP2.2U, BP2.3U
- Lower Voltage Swing (only 350 mV vs. 3 V)
- Allows faster Clocking
- Standard open Ended: 250Mbps
- LVDS: >1 Gbps
Standard Single Ended
1 0 1 0
- Differential Signals (Two Signals) ...Low Noise!
- Receiver reads a 1 or 0 based on the delta of the two signals.
- Noise Impacts both lines and cancels out each others.
Low Voltage Differential Signalling
Noise
1 0 1 0
Two Signals & Smaller Voltage Swing
Figure 9-26 LVDS technology
The digital video output from the VIPER is connected to the
display via the LVDS interface. This transmitter converts 28 bits
of LVCMOS/LVTTL data into four LVDS (Low Voltage
Differential Signalling) data streams. A phase-locked transmit
clock is transmitted in parallel with the data streams over a fifth
LVDS link. With every cycle of the transmit clock, 28 bits of
input data are sampled and transmitted. At a transmit clock
frequency of 85 MHz, 24 bits of RGB data and 3 bits of LCD
timing and control data (FPLINE, FPFRAME, DRDY) are
transmitted at a rate of 595 Mbps per LVDS data channel.
Using a 85 MHz clock, the data throughput is 297.5 Mbytes/
sec.
9.12 PNX2015: Stand-by Processor
9.12.1 Introduction
The Stand-by Processor’s sub system is isolated from the other
sub systems within thePNX2015. It has its own power supply
(1.2V and 3.3V), together with separate clocking (16MHz) and
reset. This allows for it to be active while all other sub systems
are either inactive, via clock being disabled, or powered down.
The main tasks of the Stand-by Controller are:
• RC5/RC6 remote control handling.
• P50.
• Keyboard handling (side control, “on/off” switch).
• Detection and protection of the power supplies.
• Status detection on EXTernals.
• SAM/SDM entering.
• Provide boot-scripts to the VIPER.
• Start-up behavior of the set; sequentially enabling the
power supplies via the ENABLE lines.
9.12.2 TV Start-up Behavior and Fault Detection
1. The Stand-by Controller is powered by the +5V2 voltage
(3V3_STBY voltage is derived from the +5V2), which
becomes available when the set is connected to the Mains
/ AC Power.
2. By default, all I/O lines of the controller are “high”, this state
is also the state that will not trigger protections or cause
supplies to rise, since enabling a supply requires that an IO
line is pulled "low". Also all protections are active "low".
3. The 16 MHz crystal starts running.
4. Reset IC 7M03 will generate a RESET_STBY pulse.
Circuit Descriptions, Abbreviation List, and IC Data Sheets
5. All I/O lines will be set in default state, as “told” by the
software.
– RESET_SYSTEM will be "low" (this will hold the
VIPER in reset).
– LAMP_ON will be "low".
Single Signal & Larger
Voltage swing
6. The system waits for an RC or functional switch command:
when this command is "low" the set will start-up.
The Stand-by Microprocessor is responsible for the start-up of
the VIPER, by providing the correct timing for the DC/DC
converted voltages (for timing of DC/DC converter voltages see
description in paragraph "Power Supply").
The +12V switch (via POD_MODE) and the DC/DC converters
(via ENABLE) are switched "on" (active "low"). Once these
voltages are switched "on", the Stand-by Controller is
monitoring these voltages via a voltage detector circuit
connected to port P2.x. When one of the voltages is missing,
the fault detection will be active "low" on port P2.x. An error
code will be written in the error buffer.
There is a common SUPPLY_FAULT line; connected to port
P1.3 (INT5) that is active "low" when there is a problem
detected on one of the DC/DC power supplies driver circuits.
CL 36532053_073.eps One input (P2.6) is used for the Audio Supply protection from
310703
the audio amplifier.
The RESET_SYSTEM line (P4.0) is "low" in Stand-by and at
Start-up to keep the VIPER in reset state. Once the VIPER core
supply is available, the RESET_SYSTEM line will become
"high". The VIPER is starting up and will provide a RESET-
MIPS active "high" to the Stand-by Processor P3.3, AVIP, and
COLUMBUS.
9.12.3 I/O Stand-by Processor
The inputs on the Stand-by Microprocessor are used to detect
the AV status from the front inputs (see also the control block
diagram in chapter 6 "Block diagrams,...").
An UART communication line via an electronic switch is
available on a connector and will be used for Service to
communicate with ComPair. The UART line is switched to the
Stand-by Processor when the UART_SWITCH line (P0.7) is
"high". Otherwise it is switched to the VIPER.
9.13 VIPER 2 (PNX 8550)
9.13.1 Introduction
The PNX8550 is a highly integrated media processor intended
for deployment in analog, digital, and hybrid TV receivers. It
can be used for 100 Hz interlaced as well as 60 Hz progressive
screens. It is fully capable of performing advanced video
improvement algorithms, such as Digital Natural Motion™, on
Standard Definition analog or digital sources. It includes an HD
capable de-interlacer for converting interlaced HD
transmission signals to progressive output for driving wide-
XGA class Plasma or LCD displays. Two 32-bit 240 MHz VLIW
media processors, referred to as the TriMedia TM3260 CPU
core, carry out the advanced video improvement processing as
well as all audio operations. Fixed hardware functions perform
stable core video functions, such as picture level MPEG2
decoding, scaling, image composition and pixel post
processing.
The PNX8550 provides a primary digital (YUV or RGB) output
to connect to the display specific output processor. In addition,
a secondary analog video output (CVBS or S-Video) for a VCR
is available. This is the so-called DENC-out. It can operate
either in analog PAL/NTSC or digital mode.
 Circuit Descriptions, Abbreviation List, and IC Data Sheets BP2.2U, BP2.3U 9. EN 123

9.13.2 Block Diagram de-interlacing and scaling tasks. It reads images from memory,
performs a transformation, and writes the result back in
memory.
2x225 MHz, 32-bit wide DDR
Optional external coprocessors
including video enhancement chip
The MBS main features are:
Peak rate: 12bit/cycle each way • De-interlacing using either a median, 2-field majority
MMI
select, or 3-field majority select algorithm with an edge
Tunnel
detect/correct post-pass (these three provide increasing
PNX8550
MBS2 V Peaking
quality, at expense of increased bandwidth).
TS_OUT • Edge detect/correct on an input frame that has been
656 30 656/HD/VGA QVCP5L_OUT
software de-interlaced (this provides future capabilities in
t s & 656 r o u t er

DV1 656/TS VIP1 QVCP1

10 656 QVCP2L_OUT

656 analog Y/C,cvbs case we develop a better core de-interlacer than 3-field
VIP2 QVCP2 DENC
DV2* 656/TS majority select).
TS 8 ch + 8 ch I2S audio

DV3 656/TS
MSP1 AO1-2 • Horizontal and vertical scaling (on the input image, or on
TS
MSP2 SPDO
SPDIF audio
the result of edge detect/correct stage).
I2S audio
• Linear and non-linear aspect ratio conversion.
AI1-2 TSDMA
• Anti-flicker filtering.
SPDIF audio
SPDI 1-2 MBS • Conversions from any input pixel format to any non-
UART1-2
QTNR
indexed pixel format, including conversions between 4:2:0,
Remote Control
Gen. Purpose I/O 16
misc. I/O,
timers/
VMPG 4:2:2 and 4:4:4, indexed to true color conversion, color
(1 HD or 2 SD)
USB host i/f (2 port)
Smartcard1-2
counters, expansion / compression, de-planarisation / planarisation
semaphores VLD2
I2C (4x) (to convert between planar and packed pixel formats),
27 MHz
DE (2D) programmable color space conversion.
xtal boot, reset, clock
DVD-CSS
bound. scan
JTAG
TM-DBG (2x) E-DMA
Supported video measurement functions during scaling or de-
interlacing pass:
2xTM3260 Media Processor
5 issue, 240 MHz PR4450 MIPS CPU • Gather a histogram of luminance values (this data is used
250 MHz
64 kB
16 kB 2-port 16 kB
EJTAG debug by software to control histogram modification).
128 32-bit regs 16 kB
MMU
• Measure noise level inside a rectangular window.
PCI
• Measure the lowest level luminance within a rectangular
33 MHz, 32-bit PCI 2.2 window (used to control black stretch in QVCP).
(includes NAND/nor flash, IDE drive and 68k peripheral capability) • Measure UV bandwidth inside a rectangular window.
E_14700_076.eps
091104

QTNR (Quality Temporal Noise Reduction and Video

Figure 9-27 VIPER 2 internal block diagram Measurement)
The QTNR block has two primary functions: Temporal Noise
Control Reduction: reading two video fields from memory, "current"
An embedded MIPS32 processor (PR4450) running at 266 (noisy) and "previous" (noise reduced) and producing a noise-
MHz is available to run the Operating System. The PR4450 reduced version of "current" in memory. While doing this, or as
processor is primarily responsible for running the demand a separate "measurement only" pass, perform video
paged graphics-intensive operating system, while the TM3260 measurements:
media processors are responsible for running all real-time • Gather a histogram of luminance values (this data is used
media functions. All hardware resources inside the PNX8550 by software to control histogram modification).
are accessible by both the MIPS processor and the TM3260 • Measure noise level inside a rectangular window.
CPUs. A "'sandbox" style system protection provision ensures • Measure the lowest level luminance within a rectangular
that selected MIPS memory regions and critical peripherals window (used to control black stretch in QVCP).
cannot be corrupted or inspected. • Measure UV bandwidth inside a rectangular window.
• Measure the position of top and bottom black bars in the
VIP (Video Input Processor) image.
The Video Input Processors (VIP) handles incoming digital
video and processes it for use by other components of the QVCP (Quality Video Composition Processor)
PNX8550. It provides the following functions: The PNX8550 contains two QVCPs, which are responsible for
• Receives 10-bit YUV4:2:2 digital video data from the combining and displaying video and graphics images from
selected DVx video port (input signal coming from the AVIP main memory. The primary QVCP serves as the main display
or Columbus IC output). The data is dithered down to in- pipeline, the second one is targeted to be connected to a record
memory 8-bit data format. device (VCR). The primary QVCP allows composition of up to
• Performs horizontal down scaling or up scaling by 2x (not five layers, and can output in ITU-656/HD/VGA format in 10 bits
available in HD video capture mode). per component up to 81 Mpix/s.
• Provides an internal Test Pattern Generator with NTSC,
PAL, and variable format support. The secondary QVCP allows composition of up to two layers,
• Acquire VBI data using a separate acquisition window from can output in 656 10-bit component mode up to 81 MHz (40.5
the video acquisition window. Mpix/s). The secondary QVCP is connected to an on-chip
• ANC header decoding or window mode for VBI data Digital Video Encoder (DENC), allowing direct analog CVBS or
extraction. S-video output.
• Interrupt generation for VBI or video written to memory In analog output mode, standard definition interlaced NTSC or
input mode. PAL is supported (SCART2-out signal, for VCR-recording).
• Color space conversion (mutual exclusive with horizontal The encoder has two DACs. DAC1 provides CVBS or
scaling). luminance for S-video. DAC2 provides chrominance for S-
• Raw data mode captures of 8- or 10-bit data. video.
Internal sensors allow software to test loading on the S-video
MBS (Memory Based Scaler) Chrominance line to decide whether to output luminance or
The PNX8550 contains a Memory Based Scaler that performs CVBS on DAC1.
operation on images in main memory. The MBS can either be
controlled task by task by a TM3260, or it can be given a list of
EN 124 9. BP2.2U, BP2.3U Circuit Descriptions, Abbreviation List, and IC Data Sheets

The primary and secondary QVCP each contain a series of • MODE: In case the set is "On", to toggle the smart modes.
layers and mixers. The QVCP creates a series of display data
layers (pixel streams) and mixes them logically from back to Specifications:
front to create the composite output picture. • Lamp current frequency= 43 kHz.
• Lamp dimming frequency= 85 Hz.
Some of the features the QVCP provides are: • PWM duty cycle range= 30%
• Video Quality Enhancement. • Each lamp is only driven one third of the period to avoid
• Luminance Transient Improvement. crosstalk (drive lamps at 33.3% to have no losses in
• Color Dependent Sharpening. output).
• Horizontal Dynamic Peaking.
• Histogram Modification. 9.15.2 Block Diagram
• Digital Color Transient Improvement.
• Black Stretch.
All mentioned blocks (from "Cycle Generator" to "HSV-to-RGB
• Skin Tone Correction.
Converter" are implemented in the main software. Via I2C, the
• Blue Stretch and Green Enhancement. RGB values are sent to the MOP (where a selection is made
• Video and Graphics horizontal up scaling.
between "active" and "passive" mode) and again via I2C the
• Color space unification of all the display surfaces.
Inverter board is addressed.
• Contrast and Brightness Control. In "passive" mode, the RGB values from the "HSV-to-RGB
• Screen timing generation adopted to the connected display
Converter" are used, while in "active" mode the picture content
requirements (SD-TV standards, HD-TV standards,
is used to steer the ambient lights.
progressive, interlaced formats).

Cycle Generator
9.14 MOP The Cycle Generator (for fade in/out) starts with a long press
on the "On/Off" button on the RC. It stops when the button is
released.
VIPER MOP LVDS Display
RGB RGB LVDS
QVCP PNX2015 LCD Light Sensor
Vid eo
5L LVDS Tx
The light sensor influences the Brightness: when the room is
PDP darker, the ambient light is reduced. The amount of dimming is
V Sync
Video-F lo w
set according to an algorithm in the Auto TV software. In
"active" Ambient Light mode, the light sensor does not
CTRL-flo w Disp lay CTRL
influence the Brightness.
I2C4 Control
Signals

PNX2015 Suppl y Ramp Up/Down

Am bi -light The Brightness is changing with a speed from min. to max. in
Stand-by
µP Ambi-light Module Left 2 s.
Control
Signals
Module Right
HSV to RGB Converter.
F_15400_012.eps
300505
The HSV (Hue, Saturation, Value) values are converted to
RGB values.
Figure 9-28 Block diagram of video output with MOP
Outputs
In the BP2.2 chassis an EPLD (or MOP) is used for AmbiLight The outputs are RGB values and can individually be
processing and for some picture enhancements, like blue and decreased.
green stretch. For sets without AmbiLight (like BP2.3), the
picture enhancements are done in the VIPER. MOP (EPLD)
In "passive" mode, the EPLD sends the info from the OTC
directly to the inverter board. In "active" mode, the EPLD
9.15 Ambient Light (if present) calculates the RGB values. Hue and Saturation are not
adjustable, Brightness is adjustable.
9.15.1 Introduction
9.15.3 Inverter Board
At the rear left and right side of the TV-set, three gas
discharging lamps are mounted. With the red, green, and blue This board is for Service a "Black Box". This means that it is not
lamps, each color can be made. repairable on component level, but when found defective, the
• Ambient light is adjustable with three variables: Hue, board must be swapped. See the Spare Parts List for the order
Saturation, and Brightness. code.
• Hue and saturation are controlled via menu control or via
smart settings. Some specifications:
• The brightness is controlled via menu or via a cycle • There are three inverters to drive the lamps, each inverter
generator. drives the Left and Right lamp for one color.
• The light sensor influences the brightness. • DC-to-AC converter: 2.3 kV.
• Switching "on" or "off" goes via a ramp up or down. • Able to drive Cold Cathode Fluorescent Lamps (CCFL).
• The ambient light may be active or passive. There are two lamp units, three lamps (RGB) per unit= six
lamps.
In the user set up menu the following items are added: • The lamps are driven with Pulse Width Modulation (PWM).
• Ambient Light. • The inverters and lamps are supplied with 12V from main
• Lights "On/Off". supply.
• Ambient Light: "Personal/Normal/Warm/Cool".

Two extra keys are added on the Remote Control:

• ON/OFF: A (normal) press on this key switches the
Ambient Light "On/Off".
 Circuit Descriptions, Abbreviation List, and IC Data Sheets BP2.2U, BP2.3U 9. EN 125

OTC SOFTWARE
Picture
Profiles
content

SetHue (H) EPLD

Inverter board CCFL

SetSaturation (S) Profiles
personal
RED RED left

HSV to RGB
inverter

Converter
RED right
SetLightState RGB

GREEN GREEN left

SW2 inverter GREEN right
RampUp
GND Down
SW1
SetValue (V) BLUE BLUE left
inverter BLUE right

Start
Cycle
Stop Generator
Light sensor Passive/Active AL

CyclingValue
E_14620_007.eps
070504

Figure 9-29 Ambient light block diagram

EN 126 9. BP2.2U, BP2.3U Circuit Descriptions, Abbreviation List, and IC Data Sheets

9.16 Abbreviation List CVBS Composite Video Blanking and

Synchronization
0/6/12 SCART switch control signal on A/V DAC Digital to Analogue Converter
DBE Dynamic Bass Enhancement: extra
board. 0 = loop through (AUX to TV), 6
low frequency amplification
= play 16:9 format, 12 = play 4:3
format DDC See "E-DDC"
D/K Monochrome TV system. Sound
2DNR Spatial (2D) Noise Reduction
carrier distance is 6.5 MHz
3DNR Temporal (3D) Noise Reduction
AARA Automatic Aspect Ratio Adaptation: DFU Directions For Use: owner's manual
DNR Digital Noise Reduction: noise
algorithm that adapts aspect ratio to
reduction feature of the set
remove horizontal black bars; keeps
the original aspect ratio DRAM Dynamic RAM
DSP Digital Signal Processing
ACI Automatic Channel Installation:
DST Dealer Service Tool: special remote
algorithm that installs TV channels
directly from a cable network by control designed for service
technicians
means of a predefined TXT page
DTCP Digital Transmission Content
ADC Analogue to Digital Converter
AFC Automatic Frequency Control: control Protection; A protocol for protecting
digital audio/video content that is
signal used to tune to the correct
traversing a high speed serial bus,
frequency
AGC Automatic Gain Control: algorithm that such as IEEE-1394
DVD Digital Versatile Disc
controls the video input of the feature
DVI(-d) Digital Visual Interface (d= digital only)
box
AM Amplitude Modulation EAS Emergency Alert Signalling; A cable
TV standard (SCTE18) to signal
ANR Automatic Noise Reduction: one of the
emergency information to digital
algorithms of Auto TV
AP Asia Pacific terminal devices
ECM Entitlement Control Message
AR Aspect Ratio: 4 by 3 or 16 by 9
E-DDC Enhanced Display Data Channel
ASF Auto Screen Fit: algorithm that adapts
aspect ratio to remove horizontal black (VESA standard for communication
channel and display). Using E-DDC,
bars without discarding video
the video source can read the EDID
information
ATSC Advanced Television Systems information form the display.
EDID Extended Display Identification Data
Committee, the digital TV standard in
(VESA standard)
the USA
EEPROM Electrically Erasable and
ATV See Auto TV
Auto TV A hardware and software control Programmable Read Only Memory
EMI Electro Magnetic Interference
system that measures picture content,
EMM Entitlement Management Message
and adapts image parameters in a
dynamic way EPLD Erasable Programmable Logic Device
EU Europe
AV External Audio Video
EXT EXTernal (source), entering the set by
AVIP Audio Video Input Processor
B/G Monochrome TV system. Sound SCART or by cinches (jacks)
FAT Forward Application Transport
carrier distance is 5.5 MHz
channel
BTSC Broadcast Television Standard
Committee. Multiplex FM stereo sound FBL Fast BLanking: DC signal
accompanying RGB signals
system, originating from the USA and
FDC
used e.g. in LATAM and AP-NTSC
countries FDS Full Dual Screen (same as FDW)
FDW Full Dual Window (same as FDS)
B-TXT Blue TeleteXT
FLASH FLASH memory
C Centre channel (audio)
CA(M) Conditional Access (Module) FM Field Memory or Frequency
Modulation
CEC Consumer Electronics Control bus:
FTV Flat TeleVision
remote control bus on HDMI
connections Gb/s Giga bits per second
G-TXT Green TeleteXT
CIS Card Information Structure: Protocol
H H_sync to the module
which identifies the card in a POD
module HD High Definition
HDD Hard Disk Drive
CL Constant Level: audio output to
HDCP High-bandwidth Digital Content
connect with an external amplifier
COLUMBUS COlor LUMinance Baseband Protection: A "key" encoded into the
HDMI/DVI signal that prevents video
Universal Sub-system
data piracy. If a source is HDCP coded
ComPair Computer aided rePair
CP Connected Planet / Copy Protection and connected via HDMI/DVI without
the proper HDCP decoding, the
CSM Customer Service Mode
picture is put into a "snow vision"
CSS Content Scrambling System; An
encryption method for MPEG-2 video mode or changed to a low resolution.
For normal content distribution the
on DVDs. The algorithm and keys
source and the display device must be
required to decode the disc are stored
on the DVD-player enabled for HDCP "software key"
decoding.
CTI Color Transient Improvement:
HDMI High Definition Multimedia Interface
manipulates steepness of chroma
transients HP HeadPhone
I Monochrome TV system. Sound
carrier distance is 6.0 MHz
 Circuit Descriptions, Abbreviation List, and IC Data Sheets BP2.2U, BP2.3U 9. EN 127

I2 C Integrated IC bus PAL Phase Alternating Line. Color system

I2 D Integrated IC Data bus mainly used in West Europe (color
I2 S Integrated IC Sound bus carrier= 4.433619 MHz) and South
IB In Band channel America (color carrier PAL M=
IF Intermediate Frequency 3.575612 MHz and PAL N= 3.582056
Interlaced Scan mode where two fields are used MHz)
to form one frame. Each field contains PCB Printed Circuit Board (same as
half the number of the total amount of "PWB")
lines. The fields are written in "pairs", PCM Pulse Code Modulation
causing line flicker. PCMCIA Personal Computer Memory Card
IR Infra Red International Association
IRQ Interrupt Request PDP Plasma Display Panel
ITU-656 The ITU Radiocommunication Sector PFC Power Factor Corrector (or Pre-
(ITU-R) is a standards body conditioner)
subcommittee of the International PIP Picture In Picture
Telecommunication Union relating to PLL Phase Locked Loop. Used for e.g.
radio communication. ITU-656 (a.k.a. FST tuning systems. The customer
SDI), is a digitized video format used can give directly the desired frequency
for broadcast grade video. POD Point Of Deployment: A removable
Uncompressed digital component or CAM module, implementing the CA
digital composite signals can be used. system for a host (e.g. a TV-set)
The SDI signal is self-synchronizing, POR Power On Reset, signal to reset the uP
uses 8 bit or 10 bit data words, and has Progressive Scan Scan mode where all scan lines are
a maximum data rate of 270 Mbit/s, displayed in one frame at the same
with a minimum bandwidth of 135 time, creating a double vertical
MHz. resolution.
ITV Institutional TeleVision; TV sets for PSIP Program and System Information
hotels, hospitals etc. Protocol: A standard for (broadcast)
JOP Jaguar Output Processor (or EBILD) digital television. PSIP consists of
LS Last Status; The settings last chosen channel mapping data, program guide
by the customer and read and stored data, information about closed
in RAM or in the NVM. They are called captions and content advisory ratings,
at start-up of the set to configure it and other data related to the current
according to the customer's and future programs.
preferences PTC Positive Temperature Coefficient,
LATAM Latin America non-linear resistor
LCD Liquid Crystal Display PWB Printed Wiring Board (same as "PCB")
LED Light Emitting Diode PWM Pulse Width Modulation
L/L' Monochrome TV system. Sound QAM Quadrature Amplitude Modulation;
carrier distance is 6.5 MHz. L' is Band modulation method
I, L is all bands except for Band I QTNR Quality Temporal Noise Reduction
LORE LOcal REgression approximation QVCP Quality Video Composition Processor
noise reduction RAM Random Access Memory
LS Loudspeaker RGB Red, Green, and Blue. The primary
LVDS Low Voltage Differential Signalling color signals for TV. By mixing levels
Mbps Mega bits per second of R, G, and B, all colors (Y/C) are
M/N Monochrome TV system. Sound reproduced.
carrier distance is 4.5 MHz RC Remote Control
MOP Matrix Output Processor (or EBILD) RC5 / RC6 Signal protocol from the remote
MOSFET Metal Oxide Silicon Field Effect control receiver
Transistor, switching device RESET RESET signal
MPEG Motion Pictures Experts Group ROM Read Only Memory
MPIF Multi Platform InterFace R-TXT Red TeleteXT
MUTE MUTE Line SAM Service Alignment Mode
NC Not Connected S/C Short Circuit
NICAM Near Instantaneous Compounded SCART Syndicat des Constructeurs
Audio Multiplexing. This is a digital d'Appareils Radiorecepteurs et
sound system, mainly used in Europe. Televisieurs
NTC Negative Temperature Coefficient, SCL Serial Clock I2C
non-linear resistor SCL-F CLock Signal on Fast I2C bus
NTSC National Television Standard SD Standard Definition
Committee. Color system mainly used SDA Serial Data I2C
in North America and Japan. Color SDA-F DAta Signal on Fast I2C bus
carrier NTSC M/N= 3.579545 MHz, SDI Serial Digital Interface, see “ITU-656”
NTSC 4.43= 4.433619 MHz (this is a SDRAM Synchronous DRAM
VCR norm, it is not transmitted off-air) SECAM SEequence Couleur Avec Memoire.
NVM Non-Volatile Memory: IC containing Color system mainly used in France
TV related data such as alignments and East Europe. Color carriers=
O/C Open Circuit 4.406250 MHz and 4.250000 MHz
OOB Out Of Band channel SIF Sound Intermediate Frequency
OSD On Screen Display SMPS Switched Mode Power Supply
OTC On screen display Teletext and SOG Sync On Green
Control; also called Artistic (SAA5800) SOPS Self Oscillating Power Supply
P50 Project 50: communication protocol S/PDIF Sony Philips Digital InterFace
between TV and peripherals SRAM Static RAM
EN 128 9. BP2.2U, BP2.3U Circuit Descriptions, Abbreviation List, and IC Data Sheets

SSB Small Signal Board

STBY STandBY
SOG Sync On Green
SVGA 800x600 (4:3)
SVHS Super Video Home System
SW Software
SWAN Spatial temporal Weighted Averaging
Noise reduction
SXGA 1280x1024
TFT Thin Film Transistor
THD Total Harmonic Distortion
TMDS Transmission Minimised Differential
Signalling
TXT TeleteXT
TXT-DW Dual Window with TeleteXT
uP Microprocessor
UXGA 1600x1200 (4:3)
V V-sync to the module
VCR Video Cassette Recorder
VESA Video Electronics Standards
Association
VGA 640x480 (4:3)
VL Variable Level out: processed audio
output toward external amplifier
VSB Vestigial Side Band; modulation
method
WYSIWYR What You See Is What You Record:
record selection that follows main
picture and sound
WXGA 1280x768 (15:9)
XTAL Quartz crystal
XGA 1024x768 (4:3)
Y Luminance signal
Y/C Luminance (Y) and Chrominance (C)
signal
YPbPr Component video. Luminance and
scaled color difference signals (B-Y
and R-Y)
YUV Component video
 Circuit Descriptions, Abbreviation List, and IC Data Sheets BP2.2U, BP2.3U 9. EN 129

9.17 IC Data Sheets electrical diagrams (with the exception of "memory" and "logic"
ICs).
This section shows the internal block diagrams and pin
configurations of ICs that are drawn as "black boxes" in the

9.17.1 Diagram B1A, NCP5422AD (IC 7U00)

Block Diagram VCC ROSC

BIAS CURRENT
+ SOURCE
GEN RAMP1 RAMP2
−
+ VCC
8.6 V BST
−
7.8 V
IS+1
CLK1
+ BST
OSC GATE(H)1
IS−1
− + − CLK2 S
Reset non−overlap
IS+2 70 mV Dominant VCC
PWM FAULT GATE(L)1
+ Comparator 1 R
IS−2
− + − FAULT

70 mV S Q FAULT
Set RAMP1
Dominant
− 0.425 V BST
R GATE(H)2
+ − S
+ + non−overlap
− 0.25 V Reset
FAULT Dominant VCC
PWM GATE(L)2
Comparator 2 R
RAMP2 FAULT
E/A OFF
GND
+ E/A OFF
− 0.425 V 1.2 mA FAULT
5.0 A + E/A1 −
1.0 V −
− +
+

E/A2
1.0 V

VFB1 COMP1 VFB2 COMP2

Pin Configuration

SO−16
1 16
GATE(H)1 GATE(H)2
GATE(L)1 GATE(L)2
NCP5422A

GND VCC
AWLYWW

BST ROSC
IS+1 IS+2
IS−1 IS−2
VFB1 VFB2
COMP1 COMP2

A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
F_15400_129.eps
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Figure 9-30 Internal block diagram and pin configuration

EN 130 9. BP2.2U, BP2.3U Circuit Descriptions, Abbreviation List, and IC Data Sheets

9.17.2 Diagram B2A, NXT2003 (IC 7TG0)

Block Diagram

FAT VSB/QAM MPEG

IF In A/D
text text FEC
text
Demodulator Transport

Sense
32K x 8
RF Gain text
SRAM
AGC BERT
IF AGC
text text
RF AGC

FDC
FDC QPSK Receive
IF In A/D
text text
Demodulator
Data Out

FDC
AGC
text
AGC
µC
text
FDC Freq
LO text
Synth

Tuner
I2C
Control
Compatible
GPIO I2C Interface
text
Slave
Smart Antenna
(CEA 909)

Pin Configuration
I2C_SLAVE_ADDR
I2C_SLAVE_ADDR
BIAS_RES

GPIO_10
GPIO_1
GPIO_0
GPIO_2

GPIO_3
GPIO_4

GPIO_5

GPIO_8

GPIO_9
VDD1.2

VDD3.3

VDD1.2

VDD3.3
DGND
DGND

DGND

DGND
DGND
DGND
DGND
AVDD

AVDD
NC
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103

AGND 1 102 GPIO_11

DVDD_PLL 2 101 GPIO_12
AVDD_PLL 3 100 DGND
DGND 4 99 GPIO_13
AGND 5 98 VDD1.2
FAT_VREF_N 6 97 DGND
FAT_VREF_P 7 96 DGND
FAT_INCM 8 95 DGND
FAT_INP 9 94 DGND
FAT_INN 10 93 MPEG_DATA_0
AVDD_FAT 11 92 VDD3.3
AVDD_FAT 12 91 MPEG_DATA_1
AVDD_FAT 13 90 MPEG_DATA_2
AGND 14 89 DGND
AGND 15 88 MPEG_DATA_3
AGND 16 87 MPEG_DATA_4

NXT2003
VDD1.2 17 86 DGND
VDD2.5 18 85 VDD2.5
DGND 19 84 VDD1.2
DGND 20 128-pin LQFP 83 MPEG_DATA_5
AGND 21 82 DGND
AGND 22 (14 x 20 x 1.4 mm) 81 DGND
AGND 23 80 DGND
AVDD_FDC 24 79 /POWER_RESET
AVDD_FDC 25 78 VDD3.3
AVDD_FDC 26 77 MPEG_DATA_6
FDC_INN 27 76 DGND
FDC_INP 28 75 MPEG_DATA_7/SER_DATA
FDC_INCM 29 74 MPEG_DATA_EN
FDC_VREF_P 30 73 DGND
FDC_VREF_N 31 72 MPEG_PKT_SYNC
VDD1.2 32 71 VDD1.2
DGND 33 70 MPEG_CLK
AGND 34 69 VDD3.3
FS_OUTP 35 68 MPEG_ERR
FS_OUTN 36 67 GPIO_6
DGND 37 66 DGND
FDC_AGC 38 65 GPIO_7
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
PDET_COMP_IN
DET_REF_OUT

U C _EN

POD_DRX
POD_CRX
DGND

DGND

DGND
I2C_SCL
NC
OSC_CLK
OSC_XTAL_IN
SC_XTAL_OUT

I2C_SDA
IF_AGC

RF_AGC
AGND
VDD2.5

VDD3.3
VDD1.2
AVDD_OSC

VDD1.2

VDD3.3

VDD1.2
AVDD

AUX_AGC

F_15400_128.eps
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Figure 9-31 Internal block diagram and pin configuration

 Circuit Descriptions, Abbreviation List, and IC Data Sheets BP2.2U, BP2.3U 9. EN 131

9.17.3 Diagram B2B, UPC3220GR (IC 7T43)

Block Diagram and Pin Configuration

(Top View)

AGC IN1 1 AGC AMP. MIXER 16 MIX OUT2

AGC IN2 2 15 MIX OUT1

VAGC 3 14 GND

GND 4 OSC OUT 13 IN1

BUFFER AMP.

OSC IN1 5 12 IN2

OSC IN2 6 11 GND

VIDEO AMP.

VCC1 7 10 OUT1

VCC2 8 9 OUT2

F_15400_130.eps
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Figure 9-32 Internal block diagram and pin configuration

EN 132 9. BP2.2U, BP2.3U Circuit Descriptions, Abbreviation List, and IC Data Sheets

9.17.4 Diagram B3x, PNX3000HL (IC 7C00)

Block Diagram 1× CVBSOUTA

CVBSOUTB
2NDSIFEXT
(FMRAD)
SIFAGC CVBSOUTIF

QSS
2 SIF MIXER
SIFIN 2nd SIF internal
AMP &
AM SND
DEMOD
DTV 1st IF 2
SWITCH DTVOUT
Fpc

2
VIFIN
IF 2 VIF VIF DTV 2nd IF
2 SWITCH AMP PLL
DTVIFIN
& SNDTRAP
DTVIFAGC DTVIF &
TUNERAGC MIXER GROUP PNX3000
DTVIFPLL DELAY
VIFPLL

CVBS0 CVBS_IF
CVBS1 CVBS/Y_PRIM
CVBS2
CVBS A 10
CVBS/Y3
C3 PRIM. C D DATA 4
SWITCH DLINK1
CVBS/Y4 LINK 1
C4
VIDEO CLK
YCOMB
IDENT
CCOMB
CVBS_DTV ICLP 297 MHz
CLP_PRIM
2ndSIF
2NDSIFAGC
AGC
DET
AM sound
CVBS
OUT VCA
SWITCH A 10 DATA 4
& DLINK3
D LINK 3
CVBS CVBS_SEC
SEC.
SWITCH CLK
ICLP 297 MHz
CLP_SEC
CLP_YUV ICLP
DATA 4
ICLP A 10 DLINK2
Yyuv LINK 2
R1/PR1/V1 D
G1/Y1/Y1
RGB/YUV
B1/PB1/U1 U CLK
MATRIX
297 MHz BGDEC
& A
R2/PR2/V2 L1/AMint L A 10
SWITCH V
G2/Y2/Y2 D D VDEFLO
B2/PB2/U2
R1/AMext A 2 primary digital audio CLK VDEFLS
R VDEFL
D secondary digital audio BAND
GAP VAUDO
297 MHz REF
L2/MIC1/PipMono A L 2 VAUDS
2 DATALINK VAUD
MIC1 D
PLL RREF
MIC
AMPS
R2/MIC2/AM A R VD2V5
2 27 MHz
MIC2
D 13.5 MHz 54 MHz

MIC1 MIC2 6.75 MHz

ADC XREF
AM CLOCK DIVIDER
int 13.5 or 27 MHz
AUDIO SWITCH PLL
AUDIO SWITCH (ANALOG OUT)
(DIGITAL OUT)
CLP_PRIM HV_PRIM
TIMING
CLP_YUV
CIRCUIT
AUDIO CLP_SEC HV_SEC
AMPS

VOLTAGE
I2C-BUS
TO IRQ
INTERFACE
CURRENT

MCE430
REW
R1 R2 R3 R4 R5 DSNDL1 LINEL SCART2R ADR SCL SDA
L1 L2 L3 L4 L5 DSNDR1 LINER SCART2L
AM DSNDL2 SCART1L
EXT DSNDR2 SCART1R EWVIN EWIOUT

Pin Configuration

F_15400_131.eps
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Figure 9-33 Internal block diagram and pin configuration

 Circuit Descriptions, Abbreviation List, and IC Data Sheets BP2.2U, BP2.3U 9. EN 133

9.17.5 Diagram B4x, PNX2015E (IC 7J00)

Block Diagram
16-BIT 225 MHz DDR

16
PNX2015
MEMORY CONTROLLER

video
NORTH TUNNEL SOUTH TUNNEL PNX8550
coprocessor

DV4
VIP
HD input
(TDA9975)
DV5
MEMORY
VO-1
BASED SCALER

VIDEO MPEG
VO-2
DECODER
HUB
12 × DACS speakers

AUDIO1 AUDIO1
DEMDEC DSP
PNX8550
PNX3000 I2D1
DV1
VIDDEC1
2D/3D
MUX DV2 PNX8550
COMB FILTER
VIDDEC2
DV3
PNX3000 I2D2

AUDIO2 AUDIO2
PNX8550
DEMDEC DSP

PNX8550 LVDS to LCD panel

TV MICROCONTROLLER SUBSYSTEM

001aab086
remote keyboard I 2 C-bus UART AV link
control

Pin Configuration
index area 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

A
B
C
D
E
F
G
H
J PNX2015
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
Transparent top view F_15400_132.eps
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Figure 9-34 Internal block diagram and pin configuration

EN 134 9. BP2.2U, BP2.3U Circuit Descriptions, Abbreviation List, and IC Data Sheets

9.17.6 Diagram B4A, CY2305SC-1 (IC 7J08)

Block Diagram Pin Configuration

SOIC/TSSOP
Top View
PLL CLKOUT
MUX REF 1 16 CLKOUT
REF CLKA1 CLKA1 2 15 CLKA4
CLKA2 3 14 CLKA3
CLKA2 VDD 4 13 VDD
GND 5 12 GND
CLKA3
CLKB1 6 11 CLKB4
CLKA4 CLKB2 7 10 CLKB3
S2 8 9 S1

S2 CLKB1
SOIC
Select Input CLKB2
Top View
Decoding
REF 1 8 CLKOUT
S1 CLKB3 2 7 CLK4
CLK2
CLK1 3 6 VDD
CLKB4
GND 4 5 CLK3

E_14620_146.eps
200804

Figure 9-35 Internal block diagram and pin configuration

9.17.7 Diagram B4E, NCP303LSN (IC 7LB0 - 7LB4)

Block Diagram
NCP303LSNxxT1
Open Drain Output Configuration
2 Input 1 Reset Output

RD

Vref

3 Gnd 5 CD

Pin Configuration

Reset
1 5 CD
Output
xxxYW

Input 2

Ground 3 4 N.C.

xxx = 302 or 303

Y = Year
W = Work Week
(Top View) F_15400_133.eps
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Figure 9-36 Internal block diagram and pin configuration

 Circuit Descriptions, Abbreviation List, and IC Data Sheets BP2.2U, BP2.3U 9. EN 135

9.17.8 Diagram B5x, PNX8550EH (IC 7V00)

Block Diagram
Streaming Interface
32-Bit 225 MHz DDR Optional External from Tunnel
Video Improvement
Processing

PNX8550
Memory 30 (dig)
DVD-CSS Controller 5-Layer
Tunnel Primary
TS Output Video Out
TS Out HD/VGA/656
Video/TS Router

10
1SD+1HD 2-Layer Analog
YUV422 Secondary DENC
3x656 20
TS Inputs Video In Video Out S-Video or
CVBS
Dual
Cond. Scaler and
Access De-interlacer
Temporal
2x Smartcard Noise Redux
2x I2S Audio Out 2x I2S
Audio In SPDIF
SPDIF
250 MHz
2D DE MIPS32
Dual SD CPU
Single HD
MPEG2
Decoder
2x 240 MHz
TM3260
Media Processor

MemoryStick/ UARTs USB1.1 GPIO PCI2.2 Flash IDE

MultiMedia Card

Pin Configuration
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
shape 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
optional (4x) E_14700_088.eps
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Figure 9-37 Internal block diagram and pin configuration

EN 136 9. BP2.2U, BP2.3U Circuit Descriptions, Abbreviation List, and IC Data Sheets

9.17.9 Diagram B5A, LM3526MX (IC 7Q01)

Block Diagram

Pin Configuration

LM3526-L F_15400_134.eps
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Figure 9-38 Internal block diagram and pin configuration

 Circuit Descriptions, Abbreviation List, and IC Data Sheets BP2.2U, BP2.3U 9. EN 137

9.17.10 Diagram B7B & B7C, TDA9975EL (IC 7B11)

Block Diagram
τ ORR/V

I²C AGC τ ORB/U

REFG/Pb τ ORG/Y

B/Pb1
ADC
B/Pb2 10
B/Pb3 I²C 10/12
I²C I²C
CLAMP
BIAS I²C I²C I²C I²C I²C
BIAS
CONTROL B/Pb CHANNEL

RANGE CONTROL
VPA[11:0]

DOWNSAMPLE
REFG/Y

CONVERSION

FORMATTER

VIDEO PORT
SELECTION
I²C

COLOUR

FILTERS
G/Y1
G/Y CHANNEL

4:2:2

4:2:2
G/Y2 10 VPB[11:0]
G/Y3
10/12
I²C

REFR/Pr VPC[11:0]
I²C
R/Pr1
R/Pr CHANNEL
(GAIN)

R/Pr2 10
R/Pr3 I²C
(CLAMP)

10/12
I²C I²C

I²C +
- FREF

CLAMP VHREF TIMING I²C

+ VREF
GAIN GENERATOR -
I²C
+ HREF
I²C -
(CLKPIX) I²C
MCLK LINE TIME
MEASUREMENT (CLKFOR)

I²C (CLKOUT)
VCLK
COAST

I²C
AVI CLOCKS
SOG/Y1 PL
SOG/Y2
SYNC I²C (COAST) GENERATOR
I²C
SOG/Y3 SLICERS
I²C UPSAMPLE I²C I²C
I²C

H(C)SYNC1
τ
DETECTION

SELECTION

+ HS
ACTIVITY

H(C)SYNC2 -
SYNC

SDRS

H(C)SYNC3
I²C I²C
I²C
VSYNC1
VSYNC2
VSYNC3
τ +
- VS

VAI
I²C I²C I²C TDA9975 DEREPEATER I²C
I²C
I²C I²C

&
RXA0+ + CS
DECODER/ ALIGNEMENT

RXA0- PARALLEL -
EXTRACTION
XOR

2 8 I²C
RXB0+ RECOVERY
PACKET

I²C
RXB0- 8 I²C
2 I²C 8
RXA1+
RXA1- PARALLEL (HDMI CLOCKx2) + DE
-
RXB1+
2
RECOVERY (HDMI CLOCK)
τ I²C
RXB1- I²C
2 I²C I²C
RXA2+
RXA2- PARALLEL
2
RXB2+
RXB2-
RECOVERY τ CTL[3:0]
2 (CTL3) I²C 4
I²C
FORMATTER

RXAC+ AP[3:0]
RXAC-
HDCP AUDIO FIFO
AUDIO

2 I²C
RXBC+
RXBC- I²C
CIPHER I²C WS
2 I²C SERIAL AUDIO PLL
INTERFACE ACLK
MEMORY
FRO I²C I²C
I²C
TERMINATION SERIAL POWER
OE
RESISTANCE HDMI RECEIVER I²C I²C INTERFACE MANAGEMENT
CONTROL I²C
HSDAA

HSDAB

HSCLA

HSCLB

SDA

DIS
SCL

A0
RRXA

RRXB

PD

Pin Configuration

F_15400_135.eps
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Figure 9-39 Internal block diagram and pin configuration

EN 138 9. BP2.2U, BP2.3U Circuit Descriptions, Abbreviation List, and IC Data Sheets

9.17.11 Diagram B8, ISP1561BM (IC 7N00)

Block Diagram
SMI# SEL48M SCL SDA

PME# 15 1 2 3
4