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library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- uncomment the following lines to use the declarations that are


-- provided for instantiating xilinx primitive components.
--library unisim;
--use unisim.vcomponents.all;

entity gamerz is

port ( clk, res : in std_logic;


p1 : in std_logic_vector (3 downto 0);
p2 : in std_logic_vector (3 downto 0);
win, tagain, lose : out std_logic);
end gamerz;

architecture behavioral of gamerz is


signal count : std_logic_vector (1 downto 0):="00";
begin

process (clk, p1, p2, res)

begin

if res = '1' then


win <= '0';
tagain <= '0';
lose <= '0';

end if;

if clk'event and clk = '1'


then

if p1 = p2
then win <= '1';
tagain <='0';
lose <='0';

else tagain <= '1';


win <='0';
count <= count +'1';

if count = "10"
then lose <= '1';
tagain <= '0';
else

end if;
end if;
end if;
end process;
end behavioral;