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library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- uncomment the following lines to use the declarations that are


-- provided for instantiating xilinx primitive components.
--library unisim;
--use unisim.vcomponents.all;

entity game is

port (p1: in std_logic_vector (3 downto 0);


p2: in std_logic_vector (3 downto 0);
clk: in std_logic;
-- t : out std_logic_vector;
l,w : out std_logic);

end game;

architecture behavioral of game is


signal temp : std_logic_vector (3 downto 0);
signal temp2 : std_logic;
signal t : std_logic_vector (1 downto 0);
begin

temp <= (p1 xor p2);

process (temp2)
begin

if (clk='1' and clk'event and temp="0000") then

w<='1';

else

t<="01";

end if;

if (clk='1' and clk'event and temp="0000" and t="01") then

w<='1';

else

t<="10";

end if;

if (clk='1' and clk'event and temp="0000" and t="10") then

w<='1';
else
l<='1';

end if;

end process;

end behavioral;