ACER Aspire TimelineX 5820TG

5
VER : 1A
ZR7B SYSTEM BLOCK DIAGRAM
BOM P/N
Description
31ZR7MB0000
ZR7B MB(UMA,BT)W/O CPU
31ZR7MB0010
ZR7B MB(SG,MADS,SAM,BT,3G)W/O CPU
Channel A
64MB/128MB x 8
Channel C
Arrandale
rPGA 989
Dual Channel DDR III
800/1066 MHZ
DDRIII-SODIMM1
DDRIII-SODIMM2
P4, 5, 6, 7
Madison-Pro
Park
ATI-GPU
PCI-E x16
IMC
GFX
EXT_CRT
P14,15
P16, 17, 18, 21, 22, 23
FDI
SLG8LV595
CLOCK
GENERATOR
X'TAL
14.318MHz
P19, 20
EXT_HDMI
FDI
P24
SN74CBT3257 x3
DMI
LVDS/CRT
SWITCH
DMI(x4)
P3
CRT Con.
TS3DV421
EXT_LVDS
P24
INT_LVDS
CLK
LVDS/CCD/MIC
Con.
USB-8
INT_CRT
DMI
P24
Int. MIC
Display
C
SATA 0
SATA - HDD
P29
INT_HDMI
SATA
PS8101
LS
P25
SATA 1
SATA - ODD
P29
Ibex Peak-M
USB
P34
MINI CARD
WLAN
USB-13
PCH
USB-3/9/11
USB/B Con.
(USB Port x3)
P34
P28
PCIE-2
P8, 9, 10, 11, 12, 13
MINI CARD
3G
USB-10
USB-4
Bluetooth Con.
P25
PCIE-6
PCI-E x1
USB-1
USB Port
HDMI Con.
EXT_HDMI
X'TAL
32.768KHz
P34
SIM Card FFC

Conn
P28
P28
Cardreader
P32
AU6437-GBL
Cardreader control
PCIE-1
AR8151
GIGA LAN
X'TAL 25MHz
USB-12
RJ45
P26
P27
P32
P8
BATTERY
Azalia
X'TAL
25MHz
RTC
SPI ROM
SPI
IHDA
P8
LPC
ISL88731A
Batery Charger
LPC
Int. MIC
ALC271X-GRR
AUDIO CODEC
NPCE781
EC
P30
X'TAL
32.768KHz
P37
UP6111AQDD
P38
RT8206B
3V/5V
BOM Option Table

Reference
MIC JACK
IV@
SW@
for Switchable Graphic only SKU
MP@
for Madison & Park different parts
VRAM@
for different VRAM parts
3G@
for 3G function
Speaker
P31
Description
for UMA only SKU
Power
Board Con.
P33
P31
HP/SPDIF
K/B Con.
P31
P35
SW/B
W25X16VSS1G
SPI FLASH P37
Touch Pad
Board Con.
P33
+1.1V_VTT
EM-6781-T3
Fan Driver
HALL SENSOR
(PWM Type)
P24
+1.5V_SUS
+VGPU_CORE
+VGPU_IO
P46
+1.8V/+1V
P47
Discharger
P44
ISL62872
P41
+VGFX_AXG
TPS54418RTE x2
P43
MAX8792ETD+T
P40
UP6111AQDD
P35
ISL62881HRZ-T
P42
RT8207A
P39
ISL62882
CPU core
+1.05V
P47
P48
Quanta Computer Inc.

P35
PROJECT : ZR7B
do not stuff
Size
Document Number
Date:
Friday, March 05, 2010
Rev
1A
Block Diagram
5
Thermal Protection
P45
Sheet
1
of
50
GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)

+3.3V
VIN
+3V_D
VDDR3
dGPU_VRON
PG_GPUIO_EN
VDDC
MOS (AO3413)
P22
ISL6264
+1.5V
PG_1V_EN
VDDCI
ISL62872
P44
+VGPU_CORE (20A)
+3_D (0.5A)
VIN
+1.5V_SUS
+1V (DP PLL PWR)
PG_1.5V_EN
G9334ADJ & MOS
P45
PG_1.5V_EN
+1V (3A)
+5V
PG_1.5V_EN
VDDR4
MOS (AO4710)
P43
P47
+VGPU_IO (4.5A)
VDDR1
+1.8V
MOS (AO6402)
P43
+1.5V_GPU (10A)
dGPU_PWROK
BJT
dGPU_PWR_EN#
P22
+1.8V_GPU (3A)
MOS
AO3413
P22
+5_GPU
GPU PWR CTRL Option 2 (VDDR3 after VDDR1)

VIN
VIN
PG_GPUIO_EN
VDDC
dGPU_VRON
ISL6264
PG_1V_EN
VDDCI
ISL62872
P44
+VGPU_CORE (20A)
+1.5V
+1V (DP PLL PWR)
+1.5V_SUS
PG_1.5V_EN
+VGPU_IO (4.5A)
+1.5V_GPU
VDDR1
G9334ADJ & MOS
P45
+1V (3A)
+1.8V
+3V_D
VDDR3
+1.5V_GPU (10A)
+5V
PG_1.5V_EN
VDDR4
MOS (AO3413)
P22
MOS (AO4710)
P43
P47
MOS (AO6402)
P43
+3_D (0.5A)
dGPU_PWROK
BJT
dGPU_PWR_EN#
P22
+1.8V_GPU (3A)
MOS
AO3413
P22
+5_GPU
Thermal Follow Chart
Power States
+3.3V
POWER PLANE
VOLTAGE
DESCRIPTION
CONTROL
SIGNAL
VIN
+10V~+19V
MAIN POWER
ALWAYS
ALWAYS
+VCCRTC
+3V~+3.3V
RTC POWER
ALWAYS
ALWAYS
+3VPCU
+3.3V
EC POWER
ALWAYS
ALWAYS
+5VPCU
+5V
CHARGE POWER
ALWAYS
ALWAYS
+15V
+15V
CHARGE PUMP POWER
ALWAYS
ALWAYS
+3V_S5
+3.3V
LAN/BT/CIR POWER
S5_ON
S0-S5
+5V_S5
+5V
USB POWER
S5_ON
S0-S5
+5V
+5V
HDD/ODD/Codec/TP/CRT/HDMI POWER
MAINON
S0
+3V
+3.3V
PCH/GPU/Peripheral component POWER
MAINON
S0
+1.5VSUS
+1.5V
CPU/SODIMM CORE POWER
SUSON
S0-S3
+0.75V_DDR_VTT
+0.75V
SODIMM Termination POWER
MAINON
S0
+VGFX_AXG
variation
Internal GPU POWER
GFX_ON
S0
+1.8V
+1.8V
CPU/PCH/Braidwood POWER
MAINON
S0
+1.5V
+1.5V
MINI CARD/NEW CARD POWER
MAINON
S0
ACTIVE IN
B
NTC
Thermal
Protection
CPU
CORE PWR
H_ORICHOT#
H/W Throttling
PM_THRMTRIP#
CPU
3V/5 V
SYS PWR
SYS_SHDN#
WIRE-AND
SML1ALERT#
FAN Driver
PCH
FAN
SM-Bus
CPU VTT POWER
MAINON
S0
+1.05V
+1.05V
PCH CORE POWER
MAINON
S0
S0
+1.1V_VTT
+1.05V or +1.1V
+VCC_CORE
variation
CPU CORE POWER
VRON
LCDVCC
+3.3V
LCD POWER
LVDS_VDDEN
+5V_GPU
+5V
SWITCHABLE PWM IC POWER
dGPU_PWR_EN#
EC
CPUFAN#
S0
Discrete enable
+GPU_CORE
+0.9V~+1.1V
GPU CORE POWER
+3V_D
Discrete enable
+GPU_IO
+0.9V~+1.1V
GPU I/O POWER
PG_GPUIO_EN
Discrete enable
+1.5V_GPU
+1.5V
VRAM CORE POWER
PG_1.5V_EN
Discrete enable
+1.8V_GPU
+1.8V
GPU_CRE/LVDS/PLL POWER
+1.5V_GPU
Discrete enable
+1V
+1V
DP/PEG POWER
PG_1V_EN
Discrete enable

PROJECT : ZR7B
Size
Document Number
PWR Status & GPU PWR CRL & THRM

Date:
1
Sheet
2
8
of
50
Rev
1A
150mA(30mil)
L53
+1.5V
+1.5V_CLK
595@PBY160808T-181Y-N/2A/180ohm_6
+VDDIO_CLK
C723
.1u/16V_4
C724
.1u/16V_4
20mil
L54
C750
C477
C745
4.7u/10V_8
.1u/16V_4
.1u/16V_4
R508
<10> CLK_ICH_14M
C734
C728
C720
C725
.1u/16V_4
.1u/16V_4
10u/Y5V_8
10u/Y5V_8
U35
1
17
24
5
29
VDD_DOT
VDD_SRC
VDD_CPU
VDD_27
VDD_REF
CLK_SDATA
CLK_SCLK
31
32
SDA
SCL
33_4
CPU_SEL
30
REF_0/CPU_SEL
XTAL_IN
28
XTAL_IN
Y5
14.318MHz
C727
XTAL_OUT
27
XTAL_OUT
VDD_SRC_I/O
VDD_CPU_I/O
33p/50V_4
33p/50V_4
2
8
9
12
21
26
33
IDT:
AL003197001 (ICS9LVS3197AKLFT)
Realtek: AL000890000 (RTM890N-632-GRT)
Silego: AL000595000 (SLG8LV595VTR)
CPU_CLK select
PBY160808T/2A/180ohm_6+1.05V
C721
.1u/16V_4
+3V_CLK
BLM18AG601SN1D/200mA/600ohm_6
L49
C744
R527
*585@0_6
+3V
80mA(20mil)
VSS_DOT
VSS_27
VSS_SATA
VSS_SRC
VSS_CPU
VSS_REF
GND
Place each 0.1uF cap as close as

possible to each VDD IO pin. Place
the 10uF caps on the VDD_IO plane.
15
18
DOT_96
DOT_96#
3
4
27M
27M_SS
6
7
SRC_1/SATA
SRC_1#/SATA#
SRC_2
SRC_2#
10
11
13
14
*CPU_STOP#
16
CPU_1
CPU_1#
CPU_0
CPU_0#
20
19
23
22
CKPWRGD/PD#
25
CLK_BUF_DREFCLK <10>
CLK_BUF_DREFCLK# <10>
R609
SW@33_4
R506
*SW@33_4
C742 *SW@10p/50V_4
TP12
CLK_VGA_27M_SS
R491
27M_CLK <17>
CLK_27M_SS <17>
CLK_BUF_PCIE_3GPLL <10>
CLK_BUF_PCIE_3GPLL# <10>
CLK_BUF_DREFSSCLK <10>
CLK_BUF_DREFSSCLK# <10>
+3V
10K_4
TP9
TP8
CLK_BUF_BCLK <10>
CLK_BUF_BCLK# <10>
CK_PWRGD_R
SLG8LV595V
+3V
SMBus
CLK Enable
+1.05V
+3V
R325
R509
*10K_4
<10> ICH_SMBDATA
R513
C747
10K_4
*10p/50V/COG_4
CLK_SDATA
CPU_SEL
R489
1K/F_4
2.2K_4
CLK_SDATA <14,15,28>
CK_PWRGD_R
3
Q18
2N7002K
+3V
R551
0
A
CPU_SEL CPU0/1=133MHz
(default)
2.2K_4
1
<10> ICH_SMBCLK
R488
100K/F_4
<40> VR_PWRGD_CK505#
Q37
2N7002K
CLK_SCLK
CLK_SCLK <14,15,28>
Q38
2N7002K
CPU0/1=100MHz

PROJECT : ZR7B
Size
Document Number
Rev
1A
Clock Generator
Date:
5
Sheet
1
of
50
AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI)
AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)

Processor Compensation Signals
<8>
<8>
<8>
<8>
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
D24
G24
F23
H23
<8>
<8>
<8>
<8>
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
D25
F24
E23
G23
E22
D21
D19
D18
G21
E19
F21
G18
<8>
<8>
<8>
<8>
<8>
<8>
<8>
<8>
FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7
D22
C21
D20
C18
G22
E20
F20
G19
<8> FDI_FSYNC0
<8> FDI_FSYNC1
F17
E17
<8>
FDI_INT
C17
<8> FDI_LSYNC0
<8> FDI_LSYNC1
F18
D17
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
FDI_TX#[0]
FDI_TX#[1]
FDI_TX#[2]
FDI_TX#[3]
FDI_TX#[4]
FDI_TX#[5]
FDI_TX#[6]
FDI_TX#[7]
FDI_TX[0]
FDI_TX[1]
FDI_TX[2]
FDI_TX[3]
FDI_TX[4]
FDI_TX[5]
FDI_TX[6]
FDI_TX[7]
FDI_FSYNC[0]
FDI_FSYNC[1]
FDI_INT
FDI_LSYNC[0]
FDI_LSYNC[1]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31
H_COMP3
AT23
20/F_4
H_COMP2
AT24
R128
49.9/F_4 H_COMP1
G16
R459
49.9/F_4 H_COMP0
750/F_4
PEG_RXN[0..15] <16>
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
Use reverse type

(at GPU side)
<11>
AT26
T52
AH24
H_CATERR#
AK14
AT15
H_PECI
H_PROCHOT#
<40> H_PROCHOT#
AN26
PEG_RXP[0..15] <16>
J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26
CPEG_TXN0
CPEG_TXN1
CPEG_TXN2
CPEG_TXN3
CPEG_TXN4
CPEG_TXN5
CPEG_TXN6
CPEG_TXN7
CPEG_TXN8
CPEG_TXN9
CPEG_TXN10
CPEG_TXN11
CPEG_TXN12
CPEG_TXN13
CPEG_TXN14
CPEG_TXN15
C300
C659
C304
C286
C288
C285
C289
C281
C644
C634
C636
C624
C638
C626
C640
C628
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25
CPEG_TXP0
CPEG_TXP1
CPEG_TXP2
CPEG_TXP3
CPEG_TXP4
CPEG_TXP5
CPEG_TXP6
CPEG_TXP7
CPEG_TXP8
CPEG_TXP9
CPEG_TXP10
CPEG_TXP11
CPEG_TXP12
CPEG_TXP13
CPEG_TXP14
CPEG_TXP15
C292
C658
C308
C284
C290
C282
C287
C280
C645
C635
C637
C625
C639
C627
C641
C629
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
AK15
<11> PM_THRMTRIP#
COMP3
COMP2
COMP1
BCLK
BCLK#
COMP0
SKTOCC#
CATERR#
PECI
PROCHOT#
THERMTRIP#
BCLK_ITP
BCLK_ITP#
PEG_CLK
PEG_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
PM_EXT_TS#[0]
PM_EXT_TS#[1]
PRDY#
PREQ#
H_CPURST#
<8>
AP26
AL15
PM_SYNC
PEG_TXN[0..15] <16>
AN14
AN27
<11> H_PWRGOOD
AK13
<8,36> PM_DRAM_PWRGD
<10,11,26,28,32,37> PLTRST#
PEG_TXP[0..15] <16>
R185
H_VTTPWRGD
AM15
T42
AM26
1.5K/F_4 CPU_PLTRST# AL14
RESET_OBS#
PWR MANAGEMENT
FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
Intel(R) FDI
<8>
<8>
<8>
<8>
<8>
<8>
<8>
<8>
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
20/F_4
R461
CLOCKS
B24
D23
B23
A22
R435
R462
PM_SYNC
VCCPWRGOOD_1
VCCPWRGOOD_0
SM_DRAMPWROK
VTTPWRGOOD
TAPPWRGOOD
TCK
TMS
TRST#
JTAG & BPM
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
PCI EXPRESS -- GRAPHICS
<8>
<8>
<8>
<8>
U33B
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
49.9/F_4
THERMAL
A24
C23
B22
A21
DMI
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
R434
B26
A26
B27
A25
MISC
<8>
<8>
<8>
<8>
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS
DDR3
MISC
U33A
TDI
TDO
TDI_M
TDO_M
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
T38
T37
A16
B16
AR30
AT30
CLK_CPU_BCLK <11>
CLK_CPU_BCLK# <11>
T44
T48
D
E16
D16
CLK_PCIE_3GPLL <10>
CLK_PCIE_3GPLL# <10>
A18
A17
DPLL_REF_SSCLK <10>
DPLL_REF_SSCLK# <10>
F6
AL1
AM1
AN1
CPU_DDR3_DRAMRST#
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
AN15
AP15
R161
R163
R170
100/F_4
24.9/F_4
130/F_4
R188
R179
XDP_PREQ#
T41
T67
AN28
AP28
AT27
XDP_TCLK
XDP_TMS
XDP_TRST#
T45
T49
T68
AT29
AR27
AR29
AP29
XDP_TDI_R
XDP_TDO_R
XDP_TDI_M
XDP_TDO_M
T73
T71
T72
T74
AN25
H_DBR#_R
AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23
XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7
R190
Layout Note: Place

these resistors
near Processor
PM_EXTTS#0 <14>
10K_4
10K_4
AT28
AP27
<36>
+1.1V_VTT
PM_EXTTS#1 <15>
*Short_4
XDP_DBRST# <8>
T40
T43
T39
T46
T51
T47
T50
T53
RSTIN#
R180
750/F_4
Clarksfield/Auburndale
Processor pull-up
Thermaltrip protect
JTAG MAPPING
VTT PWR_Good
XDP_TDI_R
XDP_TDI
+1.1V_VTT
R476
0_4
R475
*0_4
XDP_TDO_M
XDP_TDO
H_CATERR#
H_PROCHOT#
H_CPURST#
XDP_TMS
XDP_TDI_R
XDP_PREQ#
XDP_TCLK
XDP_TRST#
+1.1V_VTT
+3V
<8,40> DELAY_VR_PWRGOOD
Q15
FDV301N
R468
R157
R460
R193
R192
R479
R466
R183
R463
51/F_4
49.9/F_4
68_4
*68_4
*51_4
*51_4
*51_4
*51_4
51/F_4
<37>
MPWROK
R187
*0_4
R467
0_4
+1.5V_CPUVDDQ
2
Q14
3 MMBT3904
U15
R178
1K_4
TC7SH08FU
SYS_SHDN#
Scan Chain
(Default)
STUFF -> R469, R491, R507

NO STUFF -> R489, R490
CPU Only
STUFF -> R490, R491

NO STUFF -> R469, R489, R507
GMCH Only
STUFF -> R489, R507

NO STUFF -> R491, R490, R469
H_VTTPWRGD
4
2K/F_4
PM_THRMTRIP# 1
R473
XDP_TDO_R
0.1u/10V_4
<11> PM_THRMTRIP#
0_4
XDP_TDI_M
C398
R189
1K_4
XDP_TDO
R474
R182
1.1K/F_4
<39,48>
R181
3K/F_4
Use a voltage divider with VDDQ

(1.5V) rail (ON in S3) and
resistor combination of 4.75K (to
PM_DRAM_PWRGD VDDQ)/12K(to GND) to generate the
required voltage.
Note: CRB uses a 3.3V (always ON)
rail with 2K and 1K combination.

PROJECT : ZR7B
Size
Document Number
Rev
1A
AUBURNDA 1/4
Date:
5
Sheet
1
of
50
AUBURNDALE/CLARKSFIELD PROCESSOR (DDR3)
U33D
U33C
SB_CK[0]
SB_CK#[0]
SB_CKE[0]
W8
W9
M3
M_B_CLK0 <15>
M_B_CLK0# <15>
M_B_CKE0 <15>
SB_CK[1]
SB_CK#[1]
SB_CKE[1]
V7
V6
M2
M_B_CLK1 <15>
M_B_CLK1# <15>
M_B_CKE1 <15>
SB_CS#[0]
SB_CS#[1]
AB8
AD6
M_B_CS#0 <15>
M_B_CS#1 <15>
SB_ODT[0]
SB_ODT[1]
AC7
AD1
M_B_ODT0 <15>
M_B_ODT1 <15>
SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]
D4
E1
H3
K1
AH1
AL2
AR4
AT8
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
D5
F4
J4
L4
AH2
AL4
AR5
AR8
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
C5
E3
H4
M5
AG2
AL5
AP5
AR7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
<14> M_A_DQ[63:0]
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
A10
C10
C7
A7
B10
D10
E10
A8
D8
F10
E6
F7
E9
B7
E7
C6
H10
G8
K7
J8
G7
G10
J7
J10
L7
M6
M8
L9
L6
K8
N8
P9
AH5
AF5
AK6
AK7
AF6
AG5
AJ7
AJ6
AJ10
AJ9
AL10
AK12
AK8
AL7
AK11
AL8
AN8
AM10
AR11
AL11
AM9
AN9
AT11
AP12
AM12
AN12
AM13
AT14
AT12
AL13
AR14
AP14
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
<14> M_A_BS#0
<14> M_A_BS#1
<14> M_A_BS#2
AC3
AB2
U7
SA_BS[0]
SA_BS[1]
SA_BS[2]
<14> M_A_CAS#
<14> M_A_RAS#
<14> M_A_WE#
AE1
AB3
AE9
SA_CAS#
SA_RAS#
SA_WE#
SA_CK[0]
SA_CK#[0]
SA_CKE[0]
AA6
AA7
P7
M_A_CLK0 <14>
M_A_CLK0# <14>
M_A_CKE0 <14>
SA_CK[1]
SA_CK#[1]
SA_CKE[1]
Y6
Y5
P6
M_A_CLK1 <14>
M_A_CLK1# <14>
M_A_CKE1 <14>
AE2
AE8
M_A_CS#0 <14>
M_A_CS#1 <14>
AD8
AF9
M_A_ODT0 <14>
M_A_ODT1 <14>
SA_CS#[0]
SA_CS#[1]
SA_ODT[0]
SA_ODT[1]
SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]
DDR SYSTEM MEMORY A
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_A_DM[7:0] <14>
B9
D7
H7
M7
AG6
AM7
AN10
AN13
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
C9
F8
J9
N9
AH7
AK9
AP11
AT13
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS#[7:0] <14>
C8
F9
H9
M9
AH8
AK10
AN11
AR13
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS[7:0] <14>
Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_A[15:0] <14>
B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3
G4
H6
G2
J6
J3
G1
G5
J2
J1
J5
K2
L3
M1
K5
K4
M4
N5
AF3
AG1
AJ3
AK1
AG4
AG3
AJ4
AH4
AK3
AK4
AM6
AN2
AK5
AK2
AM4
AM3
AP3
AN5
AT4
AN6
AN4
AN3
AT5
AT6
AN7
AP6
AP8
AT9
AT7
AP9
AR10
AT10
<15> M_B_BS#0
<15> M_B_BS#1
<15> M_B_BS#2
AB1
W5
R7
<15> M_B_CAS#
<15> M_B_RAS#
<15> M_B_WE#
AC5
Y7
AC6
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
DDR SYSTEM MEMORY - B
<15> M_B_DQ[63:0]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
M_B_DM[7:0] <15>
M_B_DQS#[7:0] <15>
M_B_DQS[7:0] <15>
M_B_A[15:0] <15>
Channel A DQ[15,32,48,54], DM[5]

Requires minimum 12mils spacing
with all other signals, including data signals.
Channel B DQ[16,18,36,42,56,57,60,61,62]
Requires minimum 12mils spacing
with all other signals, including data signals.

PROJECT : ZR7B
Size
Document Number
Rev
1A
AUBURNDA 2/4
Date:
5
Sheet
1
of
50
18A
U33G
C692
330U/2V_7343
C359
22u/6.3V_8
C691
330U/2V_7343
C360
10u/6.3V_8
C358
22u/6.3V_8
C306
330u/2V_7343
+
C361
10u/6.3V_8
+1.1V_VTT
AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15
C294
22U/6.3V_8
C295
22U/6.3V_8
J24
J23
H25
C297
22u/6.3V_8
POWER
CPU VIDS
VTT_SELECT
AN33
H_PSI#
H_PSI#
AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
H_DPRSLPVR
H_VID0 <40>
H_VID1 <40>
H_VID2 <40>
H_VID3 <40>
H_VID4 <40>
H_VID5 <40>
H_VID6 <40>
H_DPRSLPVR
G15
H_VTTVID1
C345
22u/6.3V_8
<40>
C673
22u/6.3V_8
SENSE LINES
VCC_SENSE
VSS_SENSE
VTT_SENSE
VSS_SENSE_VTT
C296
22u/6.3V_8
C335
22u/6.3V_8
K26
J27
J26
J25
H27
G28
G27
G26
F26
E26
E25
VTT1_48
VTT1_49
VTT1_50
VTT1_51
VTT1_52
VTT1_53
VTT1_54
VTT1_55
VTT1_56
VTT1_57
VTT1_58
VCC_AXG_SENSE
VSS_AXG_SENSE
AM22
AP22
AN22
AP23
AM23
AP24
AN24
GFX_VID0
GFX_VID1
GFX_VID2
GFX_VID3
GFX_VID4
GFX_VID5
GFX_VID6
AR25
AT25
AM24
GFX_ON <46>
GFX_DPRSLPVR <46>
GFX_IMON <46>
VTT1_63
VTT1_64
VTT1_65
VTT1_66
VTT1_67
VTT1_68
AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1
<46>
<46>
<46>
<46>
<46>
<46>
<46>
+1.5V_CPUVDDQ
P10
N10
L10
K10
C301
C307
C373
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
C372
C363
C312
1U/6.3V_4
22U/6.3V_8
22U/6.3V_8
+ C310
330U/2V_7343
+1.1V_VTT
C665
C667
J22
J20
J18
H21
H20
H19
10U/6.3V_8
10U/6.3V_8
22U/6.3V_8
22U/6.3V_8
C660
C661
0.6A
VCCPLL1
VCCPLL2
VCCPLL3
L26
L27
M26
+1.8V
22U/6.3V_8
4.7U/6.3V_6
2.2U/6.3V_6
1U/6.3V_4
1U/6.3V_4
C298
C299
C272
C274
C273
<40>
+VCC_CORE
VCCSENSE <40>
VSSSENSE <40>
R160
100/F_4
VTT_SENSE
VSS_SENSE_VTT
T65
T64
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
H_VID5
H_VID6
H_DPRSLPVR
H_PSI#
R478
R477
R481
R480
R197
R196
R472
R471
R195
R194
R465
R458
R470
R469
R202
R201
R464
R457
1K_4
*1K/F_4
1K_4
*1K/F_4
1K_4
*1K/F_4
*1K/F_4
1K_4
*1K/F_4
1K_4
1K_4
*1K/F_4
*1K/F_4
1K_4
1K_4
*1K/F_4
*1K/F_4
1K_4
Note:
For Validating IMVP VR R6451 should be STUFF
and R2N1 NO_STUFF
AUBURNDALE/CLARKSFIELD PROCESSOR (POWER)
+1.1V_VTT

HFM_VID : Max 1.4V
LFM_VID : Min 0.65V
PROJECT : ZR7B
Size
Document Number
Rev
1A
AUBURNDA 3/4 (PWR)

Date:
C368
<46>
<46>
ARD:3A
CFD:6A
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VTT0_59
VTT0_60
VTT0_61
VTT0_62
<40>
I_MON
100/F_4
AJ34
AJ35
B15
A15
GFX_VR_EN
GFX_DPRSLPVR
GFX_IMON
T69
T70
AR22
AT22
T36
AN35
R159
GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]
C670
22u/6.3V_8
H_VTTVID1=Low, 1.1V
H_VTTVID1=High, 1.05V
ISENSE
VTT1_45
VTT1_46
VTT1_47
PEG & DMI
PSI#
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
PROC_DPRSLPVR
SENSE
LINES
+1.1V_VTT
VAXG_SENSE
VSSAXG_SENSE
1.8V
VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
GRAPHICS VIDs
AT21
AT19
AT18
AT16
AR21
AR19
AR18
AR16
AP21
AP19
AP18
AP16
AN21
AN19
AN18
AN16
AM21
AM19
AM18
AM16
AL21
AL19
AL18
AL16
AK21
AK19
AK18
AK16
AJ21
AJ19
AJ18
AJ16
AH21
AH19
AH18
AH16
- 1.5V RAILS
22A
+VGFX_AXG
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
DDR3
+1.1V_VTT
C679
C676
C662
C362
C683
C664
C663
C685
C633
C326
1.1V
AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
POWER
1.1V RAIL POWER
VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8
VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32
FDI
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100
GRAPHICS
330u/2V_7343
AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26
CPU CORE SUPPLY
330u/2V_7343
C339
C313
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
10U/6.3V_8
0.1u/10V_4_X7R
0.1u/10V_4_X7R
AUBURNDALE/CLARKSFIELD PROCESSOR (GRAPHICS POWER)
VTT Rail Values are

Auburndal VTT=1.05V
Clarksfield VTT=1.1V
+VCC_CORE
C346
C684
C350
C303
C672
C677
C674
C384
C354
C668
C311
C366
C334
C336
C322
C675
C666
C682
C678
C388
C669
C356
C357
C320
C671
C323
C314
C681
C344
C309
U33F
CPU Core Power

ARD:48A
CFD:52A
Sheet
1
of
50
U33I
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W 35
W 34
W 33
W 32
W 31
W 30
W 29
W 28
W 27
W 26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30
K27
K9
K6
K3
J32
J30
J21
J19
H35
H32
H28
H26
H24
H22
H18
H15
H13
H11
H8
H5
H2
G34
G31
G20
G9
G6
G3
F30
F27
F25
F22
F19
F16
E35
E32
E29
E24
E21
E18
E13
E11
E8
E5
E2
D33
D30
D26
D9
D6
D3
C34
C32
C29
C28
C24
C22
C20
C19
C16
B31
B25
B21
B18
B17
B13
B11
B8
B6
B4
A29
A27
A23
A9
U33E
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
AP25
AL25
AL24
AL22
AJ33
AG9
M27
L28
J17
H17
G25
G17
E31
E30
<14,36> VREF_DQ_DIMM0
CFG0
CFG3
CFG4
CFG7
VSS
NCTF
U33H
AT20
AT17
AR31
AR28
AR26
AR24
AR23
AR20
AR17
AR15
AR12
AR9
AR6
AR3
AP20
AP17
AP13
AP10
AP7
AP4
AP2
AN34
AN31
AN23
AN20
AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11
AM8
AM5
AM2
AL34
AL31
AL23
AL20
AL17
AL12
AL9
AL6
AL3
AK29
AK27
AK25
AK20
AK17
AJ31
AJ23
AJ20
AJ17
AJ14
AJ11
AJ8
AJ5
AJ2
AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13
AH9
AH6
AH3
AG10
AF8
AF4
AF2
AE35
AUBURNDALE/CLARKSFIELD PROCESSOR( RESERVED, CFG)
VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7
AT35
AT1
AR34
B34
B2
B1
A35
TP5
TP2
TP3
TP33
TP34
AM30
AM28
AP31
AL32
AL30
AM31
AN29
AM32
AK32
AK31
AK28
AJ28
AN30
AN32
AJ32
AJ29
AJ30
AK30
H16
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
SA_DIMM_VREF
SB_DIMM_VREF
RSVD11
RSVD12
RSVD13
RSVD14
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
RSVD_TP_86
B19
A19
RSVD15
RSVD16
A20
B20
RSVD17
RSVD18
U9
T9
RSVD19
RSVD20
AC9
AB9
RSVD21
RSVD22
C1
A3
RSVD_NCTF_23
RSVD_NCTF_24
J29
J28
RSVD26
RSVD27
A34
A33
RSVD_NCTF_28
RSVD_NCTF_29
C35
B35
RSVD_NCTF_30
RSVD_NCTF_31
RESERVED
AUBURNDALE/CLARKSFIELD PROCESSOR (GND)
RSVD32
RSVD33
AJ13
AJ12
RSVD34
RSVD35
AH25
AK26
RSVD36
RSVD_NCTF_37
AL26
AR2
RSVD38
RSVD39
AJ26
AJ27
RSVD_NCTF_40
RSVD_NCTF_41
AP1
AT2
RSVD_NCTF_42
RSVD_NCTF_43
AT3
AR1
RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53
RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57
RSVD58
AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32
RSVD_TP_59
RSVD_TP_60
KEY
RSVD62
RSVD63
RSVD64
RSVD65
E15
F15
A2
D15
C15
AJ15
AH15
RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75
AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3
RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85
V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9
VSS
TP6
TP7
AP34
TP4
AP34 can be NC on CRB; EDS/DG suggestion to GND

Processor Strapping
1
CFG0
(PCI-Epress
Configuration Select)
Single PEG
CFG3
(PCI-Epress Static
Lane Reversal)
Normal Operation
Ts
hI
p
ea
n
ec
n
t
c
Co
d
e
i
lm
l
f
ap
B
i
ro
G
r
c
kn
A
e
CFG4
Disabled; No Physical Display Port
(Embended
Display Port Presence) attached to Embedded Diplay Port
DEFAULT
0
Bifurcation enabled
Lane Numbers Reversed
Enabled; An external Display port
device is connected to the Embedded
Display port
CFG0 R186
*3.01K_NC
CFG3 R169
3.01K/F_4
CFG4 R162
*3.01K
CFG7 R172
*3.01K/F_4

PROJECT : ZR7B
Size
Document Number
Rev
1A
AUBURNDA 4/4
Date:
4
Sheet
1
of
50
IBEX PEAK-M (DMI,FDI,GPIO)

IBEX PEAK-M (LVDS,DDI)
U36C
BE22
BF21
BD20
BE18
DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3
BD22
BH21
BC20
BD18
BH25
+1.05V
R483
49.9/F_4
BF25
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
DMI_ZCOMP
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
DMI_IRCOMP
FDI_LSYNC0
FDI_LSYNC1
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12
FDI_TXP0
FDI_TXP1
FDI_TXP2
FDI_TXP3
FDI_TXP4
FDI_TXP5
FDI_TXP6
FDI_TXP7
<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>
BJ14
FDI_INT
<4>
U36D
SYS_PWROK
T6
M6
B17
K5
RSV_ICH_LAN_RST# A10
D9
<4,36> PM_DRAM_PWRGD
C16
<37> ICH_RSMRST#
SUS_PWR_ACK_R
M1
P5
<37> DNBSWON#
<37>
R269
PCH_ACIN
*0_4 ACIN_R
P7
PM_BATLOW#
A6
PM_RI#
F14
SYS_RESET#
WAKE#
SYS_PWROK
PWROK
MEPWROK
LAN_RST#
DRAMPWROK
RSMRST#
CLKRUN# / GPIO32
System Power Management
XDP_DBRST#
FDI_FSYNC1
<4>
BJ12
FDI_LSYNC0
<4>
BG14
FDI_LSYNC1
<4>
SUS_STAT# / GPIO61
SUSCLK / GPIO62
SLP_S5# / GPIO63
SLP_S4#
SUS_PWR_DN_ACK / GPIO30
PWRBTN#
ACPRESENT / GPIO31
SLP_S3#
SLP_M#
TP23
BATLOW# / GPIO72
RI#
PMSYNCH
SLP_LAN# / GPIO29
P8
F3
E4
CLKRUN#
SUS_STAT#
R401
2.37K/F_4
AP39
AP41
INT_TXLCLKOUT- AV53
INT_TXLCLKOUT+ AV51
<24> INT_TXLCLKOUT<24> INT_TXLCLKOUT+
<4>
<24> INT_TXLOUT0<24> INT_TXLOUT1<24> INT_TXLOUT2<24> INT_TXLOUT0+

<24> INT_TXLOUT1+
<24> INT_TXLOUT2+
INT_TXLOUT0INT_TXLOUT1INT_TXLOUT2-
BB47
BA52
AY48
AV47
INT_TXLOUT0+
INT_TXLOUT1+
INT_TXLOUT2+
BB48
BA50
AY49
AV48
AP48
AP47
<26,28>
AY53
AT49
AU52
AT53
AY51
AT48
AU50
AT51
TP14
*Short_4
SLP_S5#_R
ICH_SUSCLK
INT_CRT_BLU
INT_CRT_GRN
INT_CRT_RED
<24> INT_CRT_BLU
<24> INT_CRT_GRN
<24> INT_CRT_RED
SUSC#
<37>
SUSB#
<37>
R278
N2
Y53
Y51
<24> INT_HSYNC
<24> INT_VSYNC
*0_4
DAC_IREF
TP23
BJ10
PM_SYNC
PM_SLP_LAN#
AA52
AB53
AD53
V51
V53
<24> INT_CRT_DDCCLK
<24> INT_CRT_DDCDAT
SLP_M#
L_BKLTEN
L_VDD_EN
SDVO_TVCLKINN
SDVO_TVCLKINP
L_BKLTCTL
SDVO_STALLN
SDVO_STALLP
L_DDC_CLK
L_DDC_DATA
SDVO_INTN
SDVO_INTP
R243
1K/F_4
<4>
AD48
AB51
BJ46
BG46
BJ48
BG48
BF45
BH45
L_CTRL_CLK
L_CTRL_DATA
LVD_IBG
LVD_VBG
SDVO_CTRLCLK
SDVO_CTRLDATA
LVD_VREFH
LVD_VREFL
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
LVDSA_CLK#
LVDSA_CLK
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
LVDSB_CLK#
LVDSB_CLK
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
<37>
TP27
P12
F6
AB46
V48
<37>
H7
K8
10K_4
10K_4
AT43
AT42
BH13
Y1
R254
R258
R233
FDI_FSYNC0
PCIE_WAKE#
AB48
Y45
<24> INT_LVDS_EDIDCLK
<24> INT_LVDS_EDIDDATA
+3V
BF13
J12
Y48
<24> INT_LVDS_BRIGHT
<4> XDP_DBRST#
T48
T47
<24> INT_LVDS_BLON
<24> INT_LVDS_DIGON
Digital Display Interface
DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
FDI_TXN0
FDI_TXN1
FDI_TXN2
FDI_TXN3
FDI_TXN4
FDI_TXN5
FDI_TXN6
FDI_TXN7
LVDS
<4>
<4>
<4>
<4>
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3
BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12
CRT_BLUE
CRT_GREEN
CRT_RED
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
CRT_DDC_CLK
CRT_DDC_DATA
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN
T51
T53
SDVO_CTRLCLK <25>
SDVO_CTRLDAT <25>
BG44
BJ44
AU38
TP36
TP35
BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38
INT_HDMITX2N_R
INT_HDMITX2P_R
INT_HDMITX1N_R
INT_HDMITX1P_R
INT_HDMITX0N_R
INT_HDMITX0P_R
INT_HDMICLK-_R
INT_HDMICLK+_R
INT_HDMI_HPD
C411
C412
C414
C413
C442
C443
C432
C431
0.1u/10V_4_X7R
0.1u/10V_4_X7R
0.1u/10V_4_X7R
0.1u/10V_4_X7R
0.1u/10V_4_X7R
0.1u/10V_4_X7R
0.1u/10V_4_X7R
0.1u/10V_4_X7R
INT_HDMITX2N
INT_HDMITX2P
INT_HDMITX1N
INT_HDMITX1P
INT_HDMITX0N
INT_HDMITX0P
INT_HDMICLKINT_HDMICLK+
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
C
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPD_CTRLCLK
DDPD_CTRLDATA
CRT
<4>
<4>
<4>
<4>
BD24
BG22
BA20
BG20
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
FDI
<4>
<4>
<4>
<4>
BC24
BJ22
AW20
BJ20
DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3
DMI
<4>
<4>
<4>
<4>
Y49
AB49
BE44
BD44
AV40
BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36
U50
U52
BC46
BD46
AT38
R place close to PCH
BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36
R507
150_4
INT_CRT_BLU
R499
150_4
INT_CRT_GRN
R495
150_4
INT_CRT_RED
IbexPeak-M_R1P0
TP29
IbexPeak-M_R1P0
PCH Pull-high/low
+3V_S5
System PWR_OK
+3V
XDP_DBRST#
R275
PM_RI#
R296
10K_4
PM_BATLOW#
R541
10K_4
+3V_S5
8.2K_4
1K_4
C805
PCIE_WAKE#
R287
1K_4
ICH_RSMRST#
R560
10K_4
PM_SLP_LAN#
R292
*10K_4
RSV_ICH_LAN_RST#
R572
10K_4
SUS_PWR_ACK_R
R530
10K_4
SYS_PWROK
R582
10K_4
ACIN_R
R270
10K_4
DELAY_VR_PWRGOOD need PU 2K to +3V.

PU at power side
*.1u_4
R498
1
SYS_PWROK
DELAY_VR_PWRGOOD
4
2
U41
CLKRUN#
R605
PWROK_EC
<4,40>
<37>
100K_4
TC7SH08FU
PROJECT : ZR7B
Size
Document Number
Rev
1A
IBEX PEAK-M 1/6

Date:
5
Sheet
1
of
50
RTC Circuitry
C786
2
1
15p/50V_4
+VCCRTC
Y6
1
C796
1u/10V_4
R592
1K_4
RTC_RST#
C14
SRTC_RST#
D17
R573
+VCCRTC
C781
1u/10V_4
1M_4
SM_INTRUDER#
A16
PCH_INVRMEN
J2
*SHORT_ PAD1
A14
RTCX1
RTCX2
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
RTCRST#
FWH4 / LFRAME#
SRTCRST#
INTRUDER#
LDRQ0#
LDRQ1# / GPIO23
INTVRMEN
SERIRQ
D33
B33
C32
A32
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
C34
LPC_LFRAME#
<28,37>
<28,37>
<28,37>
<28,37>
<28,37>
D
A34
F34
R253
10K_4
AB9
+3V
IRQ_SERIRQ
<37>
C798
1u/10V_4
B13
D13
SRTC_RST#
20K/F_4
1
R326
U36A
RTC_X1
RTC_X2
15p/50V_4
J1
*SHORT_ PAD1
2
BAT54C
R557
10M_4
32.768KHZ
C785
LPC
RTC_RST#
20K/F_4
3
4
R586
RTC
CR1
+3VPCU
VCCRTC_1
3 RTC_N01
*22K_6
Q44
R600
ACZ_BIT_CLK
Internal weak pull-down

VCCVRM=>+1.8V (default)
external pull-up
VCCVRM=>+1.5V
ACZ_SYNC
SPKR
P1
ACZ_RST#
C30
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
HDA_SYNC
SPKR
<30> PCH_AZ_CODEC_SDIN0
HDA_RST#
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
F30
1
2
R591
E32
*150K/F_6
F32
+3V_S5
HDA Bus
R562
*10K_4
ACZ_SDOUT
B29
PCH_GPIO33
H32
TP20
PCH_GPIO13
<25> HDMI_HPD_PCH#
J30
M3
K3
<30> PCH_AZ_CODEC_SYNC
R563
33_4
ACZ_SYNC
R569
33_4
ACZ_RST#
R568
33_4
ACZ_SDOUT
K1
<30> PCH_AZ_CODEC_RST#
J2
J4
<30> PCH_AZ_CODEC_SDOUT
R564
<30> PCH_AZ_CODEC_BITCLK
33_4
SPI_CLK_R
BA2
SPI_CS0#_R
AV3
SPI_CS1#
AY3
ACZ_BIT_CLK
+3VPCU
C787
*27p_4
R485
*10K_4
SPI_SI_R
AY1
SPI_SO_R
AV1
HDA_SDIN0
HDA_SDIN1
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
IHDA
G30
RTC_CONN
HDA_BCLK
*68.1K/F_4
RTC_N03
BT1
<30>
A30
D29
SPKR
HDA_SDIN2
HDA_SDIN3
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
HDA_SDO
HDA_DOCK_EN# / GPIO33
HDA_DOCK_RST# / GPIO13
SATA
*MMBT3904
1
2
+5V_S5
HDA_SYNC (PCH strap pin)
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
JTAG_TCK
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
JTAG_TMS
JTAG_TDI
JTAG
R601
JTAG_TDO
TRST#
SATAICOMPO
SATAICOMPI
AK7
AK6
AK11
AK9
SATA_RXN0_C
SATA_RXP0_C
SATA_RXN0_C <29>
SATA_RXP0_C <29>
SATA_TXN0 <29>
SATA_TXP0 <29>
AH6
AH5
AH9
AH8
SATA_RXN1_C
SATA_RXP1_C
SATA_RXN1_C <29>
SATA_RXP1_C <29>
SATA_TXN1 <29>
SATA_TXP1 <29>
AF11
AF9
AF7
AF6
Note:
SATA port2/3 may not be available on all PCH sku
(HM55 support 3 port only)
AH3
AH1
AF3
AF1
AD9
AD8
AD6
AD5
AD3
AD1
AB3
AB1
AF16
R245
AF15
37.4/F_4
+1.05V
SPI_CLK
SATA_ACT# <33>
SPI_CS0#
SPI_CS1#
SATALED#
SPI_MOSI
SATA0GP / GPIO21
SPI
VCCRTC_2
SPI_MISO
SATA1GP / GPIO19
T3
PCH_ODD_EN
Y9
R263
43K/F_4
+3V
V1
R505
43K/F_4
+3V
<29>
IbexPeak-M_R1P0
PCH Strap Pin Configuration Table-1

INTVRMEN Integrated 1.05V VRM Enable /
Disable
1 = Integrated VRM is enabled

0 = Integrated VRM is disabled
+VCCRTC
R593
330K_6
PCH_INVRMEN
SPI_MOSI
TPM Functionality
Disable
1 = Enabled
0 = Disable
+3V
R529
*1K_4
SPI_SI_R
SPKR
Reboot option at power-up
0 = Default Mode (Internal weak Pull-down)

1 = No Reboot Mode with TCO Disabled
+3V
R522
PCH SPI
B
HDA_DOCK_EN Flash Descriptor

Security Override
#/GPIO33
0 = Flash Descriptor Security will be overridden

1 = Security measure defined in the Flash
Descriptor will be enabled.
GNT0#,
GNT1#
(0,0) = LPC
(1,0) = PCI
*1K/F_4 SPKR
B
PCH_GPIO33
R286
R293
*1K/F_4
*10K_4
+3V
+3V
U37
SPI_CS0#_R
SPI_CLK_R
SPI_SI_R
SPI_SO_R
1
6
5
2
3
CE#
SCK
SI
SO
VDD
HOLD#
WP#
VSS
W25Q32BVSSIG
+3V
R518
R455
R612
R282
R285
8
7 R523
3.3K/F_4
GNT2#/
GPIO53
4
C741
.1u/10V_4
GNT3#/
GPIO55
3.3K/F_4
NV_ALE
NV_CLE
GPIO8
Boot BIOS Strap
(0,1) = Reserved NAND

<10>
(1,1) = SPI
PCI_GNT0#
<10> PCI_GNT1#
ESI compatible mode is for server

platforms only
ESI Strap
(Server Only)
R289
<10,24> PWM_SELECT#
GPIO15
GPIO27
+3V
*1K/F_4
Top-Block
Swap Override
IntelR Anti-Theft Technology
HDD Data Protection
(Intel AT-d) Enable
0 = Top Block Swap Mode

1 = Default Mode (Internal pull-up)
1 = Enabled
0 = Disabled (Default)
<10>
NV_ALE
R225
*1K/F_4
+1.8V
DMI Termination
Voltage
DMI termination voltage. Weak

internal pull-up. Do not pull low.
<10>
NV_CLE
R224
*1K/F_4
+1.8V
Reserved
<10> PCI_GNT3#
This signal has a weak internal pull up.

NOTE: This signal should not be pulled low<11>
RSV_GPIO8
R528
R302
R295
1K_4
1K_4
*1K_4
*1K_4
Reserved
On-Die PLL Voltage

Regulator
<internal weak pull-up>
0 = Intel ME Crypto Transport Layer Security

(TLS) cipher suite with no confidentiality
1 = Intel ME Crypto Transport Layer Security<11>
(TLS) cipher suite with confidentiality
0 = Disables the VccVRM.
1 = Enables the internal VccVRM to have
a clean supply for analog rails.
CR_WAKE#
<11> PCH_GPIO27
*10K/F_4
10K_4
+3V_S5
*1K_4
R266
1K_4
R247
*10K_4
+3V_S5

PROJECT : ZR7B
Size
Document Number
Rev
1A
IBEX PEAK-M 2/6

Date:
5
Sheet
1
of
50
U36B
U36E
PCI_GNT0#
PCI_GNT1#
PWM_SELECT#
PCI_GNT3#
<28>
PCI_GNT0#
PCI_GNT1#
PWM_SELECT#
PCI_GNT3#
F48
K45
F36
H53
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
B41
K53
A36
A48
PCI_RST#
PCI_RST#
K6
PCI_SERR#
PCI_PERR#
TP25
TP21
E44
E50
PCI_IRDY#
PCI_PAR
PCI_DEVSEL#
PCI_FRAME#
A42
H44
F46
C46
PCI_PLOCK#
D49
PCI_STOP#
PCI_TRDY#
D41
C48
ICH_PME#
M7
PCI_PLTRST#
R516
<28> CLK_LPC_DEBUG
B
TP22
R281
CLK_PCI_FB R277
<37> CLK_PCI_775
22_4
22_4
22_4
CLK_LPC_DEBUG_C
CLK_PCI_PCCARD
CLK_PCI_775_C
CLK_PCI_FB_C
D5
N52
P53
P46
P51
P48
NV_WE#_CK0
NV_WE#_CK1
PIRQA#
PIRQB#
PIRQC#
PIRQD#
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
REQ0#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
GNT0#
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
PCIRST#
SERR#
PERR#
IRDY#
PAR
DEVSEL#
FRAME#
PLOCK#
USBRBIAS#
STOP#
TRDY#
USBRBIAS
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
BF33
BH33
BG32
BJ32
NV_ALE
NV_CLE
BD3
AY6
NV_ALE <9>
NV_CLE <9>
AU2 NV_RCOMP R486
<28>
<28>
<28>
<28>
*32.4/F_4
PCIE_RX6PCIE_RX6+
PCIE_TX6PCIE_TX6+
C441
C440
0.1u/10V_4_X7R PCIE_TXN6_C
0.1u/10V_4_X7R PCIE_TXP6_C
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
BA34
AW34
BC34
BD34
AT34
AU34
AU36
AV36
AV7
AY8
AY5
BG34
BJ34
BG36
BJ36
AV11
BF5
H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24
TP31
TP19
USBP1USBP1+
<34>
<34>
USBP3USBP3+
USBP4USBP4+
USBP5USBP5+
<34>
<34>
<34>
<34>
<28>
<28>
AK48
AK47
MB USB
CLK_PCIE_REQ0#
TP15
TP13
USB/B-USB1-3
BLUETOOTH
EHCI1
<28> CLKREQ_3G#
USBP8USBP8+
USBP9USBP9+
USBP10USBP10+
USBP11USBP11+
USBP12USBP12+
USBP13USBP13+
<24>
<24>
<34>
<34>
<28>
<28>
<34>
<34>
<32>
<32>
<28>
<28>
R503
*Short_4
CLK_PCIE_REQ1#_R
<28> PCIE_CLK_REQ2#
R526
*Short_4 CLK_PCIE_REQ2#_R
USB/B-USB1-2
Mini Card (3G)
USB/B-USB1-1
U4
AM47
AM48
<28> CLK_PCH_SRC2#
<28> CLK_PCH_SRC2
Camera
P9
AM43
AM45
<28> CLK_PCH_SRC1#
<28> CLK_PCH_SRC1
USB port6/7 may not be available on all PCH sku

(HM55 support 12port only)
N4
AH42
AH41
CLK_PCIE_REQ3#
EHCI2
A8
Card Reader
AM51
AM53
Mini Card (WLAN)
CLK_PCIE_REQ4#
M9
D25
TP26
TP16
TP30
TP17
USB_OC0# <34>
USB_OC1# <34>
USB_OC4_5# <34>
H6
AK53
AK51
<26> CLK_PCIE_LOM#
<26> CLK_PCIE_LOM
<26> CLK_PCIE_LAN_REQ#
USB_OC6#
USB_OC7#
SML0CLK
PERN4
PERP4
PETN4
PETP4
SML0DATA
SML1ALERT# / GPIO74
SML1CLK / GPIO58
PERN5
PERP5
PETN5
PETP5
PERN6
PERP6
PETN6
PETP6
SML1DATA / GPIO75
CL_CLK1
CL_DATA1
CL_RST1#
PEG_A_CLKRQ# / GPIO47
PERN7
PERP7
PETN7
PETP7
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
PERN8
PERP8
PETN8
PETP8
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P
CLKOUT_PCIE0N
CLKOUT_PCIE0P
PCIECLKRQ0# / GPIO73
CLKOUT_PCIE1N
CLKOUT_PCIE1P
CLKOUT_PCIE2N
CLKOUT_PCIE2P
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_BCLK_N
CLKIN_BCLK_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P
CLKOUT_PCIE3N
CLKOUT_PCIE3P
REFCLK14IN
B9
RSV_SMBALERT#
H14
ICH_SMBCLK
C8
ICH_SMBDATA
J14
RSV_SML0ALERT#
C6
SMB_CLK_ME0
G8
SMB_DATA_ME0
M14
RSV_SML1ALERT# R261
E10
SMB_CLK_ME1
G12
SMB_DATA_ME1
ICH_SMBCLK <3>
ICH_SMBDATA <3>
SMB_CLK_ME0 <26>
SMB_DATA_ME0 <26>
T13
CL_CLK1
T11
CL_DATA1
T9
CL_RST1#
H1
PEG_CLKREQ#_R R531
*0_4
SML1ALERT# <11,35,37>
CL_CLK1 <28>
CL_DATA1 <28>
CL_RST1# <28>
*0_4
PEG_CLKREQ# <17>
AD43
AD45
CLK_PCIE_VGA# <16>
CLK_PCIE_VGA <16>
AN4
AN2
CLK_PCIE_3GPLL# <4>
CLK_PCIE_3GPLL <4>
AT1
AT3
DPLL_REF_SSCLK# <4>
DPLL_REF_SSCLK <4>
AW24
BA24
CLK_BUF_PCIE_3GPLL# <3>
CLK_BUF_PCIE_3GPLL <3>
AP3
AP1
CLK_BUF_BCLK# <3>
CLK_BUF_BCLK <3>
F18
E18
CLK_BUF_DREFCLK# <3>
CLK_BUF_DREFCLK <3>
AH13
AH12
CLK_BUF_DREFSSCLK# <3>
CLK_BUF_DREFSSCLK <3>
P41
CLK_ICH_14M <3>
C722
CLKIN_PCILOOPBACK
J42
CLK_PCI_FB
AH51
AH53
XTAL25_IN
XTAL25_OUT
18p/50V_4
CLKOUT_PCIE4N
CLKOUT_PCIE4P
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
R492
1M_4
AF38 XCLK_RCOMP R238
90.9/F_4
Y4
25MHz
C726
+1.05V
18p/50V_4
22.6/F_4
AJ50
AJ52
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4_5#
PERN3
PERP3
PETN3
PETP3
Port1 and port9 can be used on debug mode
B25 USB_BIAS R561
N16
J16
F16
L16
E14
G16
F12
T15
SML0ALERT# / GPIO60
SMBus
BA32
BB32
BD32
BE32
SMBDATA
PERN2
PERP2
PETN2
PETP2
Link
AU30
AT30
AU32
AV32
SMBCLK
Controller
CLK_PCIE_REQ5#
PME#
PLTRST#
C439
C438
AW30
BA30
BC30
BD30
SMBALERT# / GPIO11
PCI-E*
NVRAM
NV_RB#
AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6
PCIE_RX2PCIE_RX2+
PCIE_TX2PCIE_TX2+
PERN1
PERP1
PETN1
PETP1
PEG
F51
A46
B45
M53
NV_RCOMP
NV_WR#0_RE#
NV_WR#1_RE#
<28>
<28>
<28>
<28>
<9>
<9>
<9,24>
<9>
PCI_REQ0#
PCI_REQ1#
dGPU_SELECT#
PCI_REQ3#
NV_ALE
NV_CLE
AV9
BG8
C704
C705
BG30
BJ30
BF29
BH29
<24> dGPU_SELECT#
G38
H51
B37
A44
NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15
<26> PCIE_RX1<26> PCIE_RX1+

<26> PCIE_TX1<26> PCIE_TX1+
From CLK BUFFER
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
NV_DQS0
NV_DQS1
AY9
BD1
AP15
BD8
R501
*Short_4 PCIE_CLK_REQB#
P13
TP28
TP32
CLKOUT_PCIE5N
CLKOUT_PCIE5P
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
PEG_B_CLKRQ# / GPIO56
CLKOUTFLEX0 / GPIO64
Clock Flex
J50
G42
H47
G34
NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3
PCI
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
USB
H40
N34
C44
A38
C36
J34
A40
D45
E36
H48
E40
C40
M48
M45
F53
M40
M43
J36
K48
F40
C42
K46
M51
J52
K51
L34
F42
J40
G46
F44
M47
H36
IbexPeak-M_R1P0
T45
BOARD_ID1
P43
BOARD_ID2
T42
BOARD_ID3
N50
dGPU_EDIDSEL# <24>
R271
10K_4
+3V
IbexPeak-M_R1P0
+3V
+3V_S5
+3V_S5
+3V_S5
+3V_S5
6
7
8
9
10
5
4
3
2
1
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
8.2K_10P8R
CLK_PCIE_REQ0#
10K_4
CLK_PCIE_REQ3#
10K_4
CLK_PCIE_REQ4#
10K_4
CLK_PCIE_REQ5#
10K_4
PCIE_CLK_REQB#
10K_4
IV@10K_4 PEG_CLKREQ#_R
R504
10K_4
5
PCI_PLTRST#
2
4
PLTRST# <4,11,26,28,32,37>
+3V
3
U18
TC7SH08FU
6
7
8
9
10
R313
*10K_4
R631
*10K_4 BOARD_ID2 R632
*10K_4
R633
*10K_4
R310
<37> 2ND_MBCLK
CLK_PCIE_REQ1#_R
High = JV41_CP(ZQ1)
PCI_REQ3#
PCI_PIRQB#
PCI_REQ0#
PCI_PIRQH#
SMB_CLK_ME1
+3V_S5
Low = JM41_CP(ZQ1B)
+3V
5
4
3
2
1
2.2K_4
3
Q19
2N7002K
BOARD_ID1
+3V
RP4
PCI_PIRQD#
PCI_REQ1#
PCI_FRAME#
PCI_TRDY#
+3V
C507
.1u/10V_4
R629
High = 80port output to LPC

BOARD_ID2
8.2K_10P8R
dGPU_SELECT#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCIE_CLK_REQ2#
R294
R304
R272
R580
R576
10K_4
8.2K_4
8.2K_4
8.2K_4
10K_4
R533
SW@10K/F_4 PEG_CLKREQ#_R
R311
Low = 80port output to PCI
USB_OC7#
USB_OC6#
USB_OC4_5#
R276
R543
R280
R283
R510
R535
+3V_S5
RP1
BOARD_ID3
Low = Reserved (Default)
<37> 2ND_MBDATA
100K_4
+3V
2.2K_4
High = Reserved
1
3
Q20
2N7002K
SMB_DATA_ME1
RP5
R312
PCI_PIRQC#
PCI_PIRQA#
PCI_STOP#
PCI_IRDY#
*0_4
+3V
6
7
8
9
10
5
4
3
2
1
PCI_PERR#
PCI_PLOCK#
PCI_DEVSEL#
PCI_SERR#
+3V_S5
R559
R308
R265
R303
R327
R536
R298
8.2K_10P8R
10K_4
10K_4
10K_4
2.2K_4
2.2K_4
2.2K_4
2.2K_4
RSV_SMBALERT#
RSV_SML0ALERT#
RSV_SML1ALERT#
ICH_SMBCLK
ICH_SMBDATA
SMB_CLK_ME0
SMB_DATA_ME0

PROJECT : ZR7B
Size
Rev
1A
IBEX PEAK-M 3/6

Date:
Document Number
1
Sheet
10
of
50
GPU RST#
+3V
IBEX PEAK-M (GPIO,VSS_NCTF,RSVD)
C609
*.1u_4
<37> SIO_EXT_SCI#
SIO_EXT_SCI#
D37
TACH2 / GPIO6
BOARD_ID0
J32
TACH3 / GPIO7
RSV_GPIO8
F10
GPIO8
TP18
<9>
CR_WAKE#
K9
CR_WAKE#
T7
dGPU_HOLD_RST#
<21> dGPU_PWROK
GPIO22
<9>
PCH_GPIO27
PCH_GPIO27
dGPU_PWR_EN# should be stable

before dGPU_VRON enable
TP10
SAVE_LED#
R256
EC suggestion use GPIO49 for FAN control
*Short_4
CLK_CPU_BCLK# <4>
AM1
CLK_CPU_BCLK <4>
BG10
H_PECI <4>
T1
SIO_RCIN#
BE10
H_PWRGOOD <4>
Y7
AB12
AB7
AB13
V3
P3
GPIO45
H3
F1
SV_SET_UP
AB6
SATA5GP
AA4
SATA5GP / GPIO49 / TEMP_ALERT# is used to

alert for EC when CPU or Graph/Memory
controllers' temperature go out of limit.
So connecting GPIO49 to EC and avoid this
pin to be used for other purpose
MISC
AM3
SAVE_LED#
GPIO57
SIO_A20GATE <37>
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
V6
<36> RST_GATE#
U2
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
V13
GPIO38
A20GATE
F8
A4
A49
A5
A50
A52
A53
B2
B4
B52
B53
BE1
BE53
BF1
BF53
BH1
BH2
BH52
BH53
BJ1
BJ2
BJ4
BJ49
BJ5
BJ50
BJ52
BJ53
D1
D2
D53
E1
E53
PLTRST# <4,10,26,28,32,37>
GPU_RST#
dGPU_HOLD_RST#
U27
TC7SH08FU
R414
100K_4
GPIO15
TACH0 / GPIO17
M11
dGPU_PRSNT#
LAN_PHY_PWR_CTRL / GPIO12
SATA4GP / GPIO16
STP_PCI#
dGPU_PWR_EN#
AF48
AF47
F38
TP_PCH_GPIO28
<21,44> dGPU_VRON
<39> dGPU_PWR_EN#
CLKOUT_PCIE7N
CLKOUT_PCIE7P
1
<16>
AA2
H10
TP24
AH45
AH46
LAN_DISABLE#
SCLOCK / GPIO22
GPIO24
PECI
RCIN#
GPIO27
CPU
RSV_GPIO8
CLKOUT_PCIE6N
CLKOUT_PCIE6P
TACH1 / GPIO1
GPIO28
PROCPWRGD
THRMTRIP#
BD10
PCH_THRMTRIP#_R R222
STP_PCI# / GPIO34
GPIO Pull-up/Pull-down
<37>
56/F_4
R217
+3V_S5
PM_THRMTRIP# <4>
56/F_4
+1.1V_VTT
TP_PCH_GPIO28
GPIO45
RST_GATE#
GPIO57
LAN_DISABLE#
R511
R537
R322
R309
R279
10K_4
10K_4
10K_4
*10K_4
10K_4
AY45
SIO_EXT_SMI#
SIO_EXT_SCI#
R299
R570
10K_4
10K_4
AY46
dGPU_PWR_EN#
R251
10K_4
SIO_RCIN#
SIO_A20GATE
dGPU_HOLD_RST#
SATA5GP
GPIO22
R515
R514
R246
R250
R262
10K_4
10K_4
*10K_4
10K_4
10K_4
SAVE_LED#
STP_PCI#
R521
R274
10K_4
10K_4
GPIO38
R497
10K_4
BMBUSY#
R252
8.2K_4
SV_SET_UP
R257
10K_4
SATACLKREQ# / GPIO35
SATA2GP / GPIO36
TP1
SATA3GP / GPIO37
TP2
SLOAD / GPIO38
TP3
SDATAOUT0 / GPIO39
TP4
TP5
TP6
SDATAOUT1 / GPIO48
TP7
SATA5GP / GPIO49
TP8
GPIO57
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
TP9
RSVD
<9>
BMBUSY# / GPIO0
C38
TP38
<10,35,37> SML1ALERT#
Y3
SIO_EXT_SMI#
GPIO
BMBUSY#
<37> SIO_EXT_SMI#
NCTF
TP37
U36F
BA22
AW22
AV43
AF13
M18
N18
TP11
AJ24
TP13
TP14
TP15
TP16
TP17
TP18
TP19
NC_1
AK41
AK42
N32
GPIO57 stuff PD and not stuff PU for Intel suggestion at 6/1
H12
GPIO57
AA23
R301
10K_4
AB45
AB42
TP24
1-X High = Strong (Default)
N30
AB38
INIT3_3V#
SV_SET_UP
M30
NC_3
NC_5
M32
NC_2
NC_4
+3V
AV45
TP10
TP12
+3V
BB22
+3V
AB41
R575
*10K_4
R239
IV@10K_4dGPU_PRSNT# R240
BOARD_ID0
R579
10K_4
SW@10K_4
dGPU always exist
T39
TP_INT3_3V
P6
TP11
High = JV41/JM41
BOARD_ID0
C10
Low = JM51
IbexPeak-M_R1P0
High = Disable
RSV_GPIO8
Low = Enable

PROJECT : ZR7B
Size
Document Number
Date:
Rev
1A
IBEX PEAK-M 4/6

5
Sheet
1
11
of
50
AB24
AB26
AB28
AD26
AD28
AF26
AF28
AF30
AF31
AH26
AH28
AH30
AH31
AJ30
AJ31
C479
10u/6.3V_8
1u/6.3V_4
VCCCORE(+1.05V) = 1.432A(80mils)
D
VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
AE50
VCCADAC[1]
+VCCA_DAC_1_2
L52
PBY160808T/2A/180ohm_6
+3V
AE52
VCCADAC[2]
C732
C739
C733
.01u/25V_4
10u/10V_6
0.1u/10V_4_X7R
AF53
VSSA_DAC[1]
U36J
VCCALVDS= 1mA
VCCALVDS
R248
*Short_4
+3V
*10uh_8 +V1.1LAN_VCCA_CLK
C717
*10u/6.3V_6
C718
*1u/6.3V_4
L48
+1.05V
AH38
VCCALVDS
+1.05V
R244
+1.05V_VCCAUX
*0_6
*1uh_6
BJ24
C482
1U/6.3V_4
C467
C446
C458
C478
C452
10U/6.3V_8
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
AN30
AN31
R232
*short_6
+3V_VCCA3GBG
R234
*short_6
+VCCAFDI_VRM
L29
*1uH_6
BJ18
+1.05V_VCCDPLL_FDI
AM23
VCCVRM[1]
VCCFDIPLL
VCCIO[1]
C436
*10u/6.3V_6
.01u/25V_4
22u/6.3V_8
TP_PCH_VCCDSW
C487
1u/6.3V_4
Y20
AD38
AD39
AD41
VCC3_3 = 357mA(30mils)
+3V_VCC_GIO
R264
AF43
*short_6 +3V
VCCME(+1.05V) = 1.849A(100mils)
+1.05V
.1u/16V_4
R249
*SHORT0805
R260
*SHORT0805
AF41
+1.05V_VCCEPW
AF42
V39
C485
22U/6.3V_8
V42
C491
22U/6.3V_8
Y39
C488
1U/6.3V_4
Y41
C490
1U/6.3V_4
Y42
VCCVRM= 196mA(15mils)
VCC3_3[1]
AT22
+V1.1LAN_VCCAPLL_FDI
.01u/25V_4
0.1UH_8/250mA +1.8V
C483
AT24
AT16
VCCDMI[1]
+VCCVRM
R235
+VCCDMI
R231
*short_6
*Short_4
+V1.5S_1.8S
+1.1V_VTT
VCCACLK[1]
VCCDMI= 61mA(15mils)
C463
1u/10V_4
AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15
VCCPNAND[1]
VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]
VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]
+VCCRTCEXT
0.1u/10V_4_X7R
C492
R221
*SHORT0805
+1.8V
+V1.1LAN_VCCA_A_DPL
68mA(15mils)
.1u/16V_4
+V1.1LAN_VCCA_B_DPL
69mA(15mils)
C475
C473
C474
VCCME3_3= 85mA(15mils)
+3V_VCCME_SPIR236
BD51
BD53
AH23
AJ35
AH35
VCCIO = 3.062A(150mils)
AM8
AM9
AP11
AP9
BB51
BB53
C476
+1.05V
VCCME3_3[1]
VCCME3_3[2]
VCCME3_3[3]
VCCME3_3[4]
V9
AU24
+V1.5S_1.8S
VCCPNAND= 156mA(15mils)
VCCPNAND
VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]
VCCACLK[2]
VCCLAN[1]
VCCLAN[2]
DCPSUSBYP
VCCME[1]
VCCME[2]
VCCME[3]
VCCME[4]
VCCME[5]
VCCME[6]
VCCME[7]
VCCME[8]
VCCME[9]
VCCME[10]
VCCME[11]
VCCME[12]
AU16
VCCDMI[2]
FDI
+V1.5S_1.8S
AD35
VCC3_3[4]
VCCVRM[2]
37mA(15mils)
+1.05V
C470
V41
VCCIO[54]
VCCIO[55]
AN35
L33
C469
AB35
VCC3_3[3]
HVCMOS
+1.05V
VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]
VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]
VCCIO[50]
VCCIO[51]
VCCIO[52]
VCCIO[53]
VCCTX_LVDS
C468
AB34
VCC3_3[2]
AN20
AN22
AN23
AN24
AN26
AN28
BJ26
BJ28
AT26
AT28
AU26
AU28
AV26
AV28
AW26
AW28
BA26
BA28
BB26
BB28
BC26
BC28
BD26
BD28
BE26
BE28
BG26
BG28
BH27
AF23
C482 change to 0 ohm resistor.
VCCAPLLEXP
*10u/6.3V_6
+3V
AP43
AP45
AT46
AT45
VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]
DMI
C437
+V1.1LAN_VCCAPLL_EXP
VCCIO[24]
PCI E*
L30
+1.05V
AK24
LVDS
*short_6 +1.05V_PCH_VCCDPLL_EXP
NAND / SPI
40mA(15mils)
R218
AP53
AF24
VCCTX_LVDS= 59mA(15mils)
+1.05V
AP51
VCCLAN = 320mA(30mils)
AH39
VSSA_LVDS
POWER
VCCACLK= 52mA(15mils)
AF51
VSSA_DAC[2]
*short_6 +3V
1U/6.3V_4
1U/6.3V_4
1U/6.3V_4
C472
AF34
AH34
AF32
.1u/16V_4
V12
C493
+VCCSST
0.1u/10V_4_X7R
+V1.1LAN_INT_VCCSUS
0.1u/10V_4_X7R
Y22
C484
USB
*SHORT0805
C481
DCPRTC
VCCVRM[3]
VCCADPLLA[1]
VCCADPLLA[2]
Clock and Miscellaneous
*SHORT0805
+1.05V_VCCCORE_ICH
R241
VCCADAC= 69mA(15mils)
CRT
R242
VCC CORE
+1.05V
POWER
U36G
VCCADPLLB[1]
VCCADPLLB[2]
VCCIO[21]
VCCIO[22]
VCCIO[23]
VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCSUS3_3[21]
VCCSUS3_3[22]
VCCSUS3_3[23]
VCCSUS3_3[24]
VCCSUS3_3[25]
VCCSUS3_3[26]
VCCSUS3_3[27]
VCCSUS3_3[28]
VCCIO[56]
V5REF_SUS
V5REF
PCI/GPIO/LPC
IBEX PEAK-M (POWER)
VCC3_3[8]
VCC3_3[9]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCCIO[2]
VCC3_3[14]
V24
V26
Y24
Y26
+1.05V
C489
+3V_S5_VCCPUSB
V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26
C496
C497
C501
R267
+3V_S5
+1.05V
V5REF_SUS< 1mA
R574
D18
C788
100/F_4
+5V_S5
RB500V-40
+3V_S5
1U/6.3V_4
V5REF< 1mA
U23
R288
100/F_4
+5V
RB500V-40
+3V
V23
D14
V5REF_SUS
F24
C499
K49
V5REF
J38
+3V_VCCPPCI
R284
*short_6
1U/6.3V_4
+3V
VCC3_3 = 0.357A(30mils)
L38
C500
0.1u/10V_4_X7R
C498
0.1u/10V_4_X7R
M36
N36
P36
U35
AD13
31mA(15mils)
VCCIO[4]
VCCSATAPLL[1]
VCCSATAPLL[2]
DCPSST
+V1.1LAN_VCCAPLL
AK3
AK1
L50
C730
*1u/6.3V_4
*10uh_8
+1.05V
C729
*10u/6.3V_6
DCPSUS
VCCIO[9]
*short_6
AH22
+V1.1LAN_VCC_SATA
AT20
+V1.5S_1.8S
R259
*SHORT1206+1.05V
B
R219
*short_6
+V1.5S_1.8S
C445
.1u/16V_4
C444
.1u/16V_4
+3V_S5
R307
*short_6
Internal weak pull-down

VCCVRM=>+1.8V (default)
external pull-up
VCCVRM=>+1.5V
+3V_S5_VCCPSUS
U19
U20
C494
VRM enable by strap pin GPIO27

which supply clean 1.05V for
[VCCACLK,VCCAPLLEXP,VCCFDIPLL,VCCSATAPLL]
0.1u/10V_4_X7R U22
VCCSUS3_3[29]
VCCSUS3_3[30]
VCCSUS3_3[31]
VCCSUS3_3[32]
VCC3_3 = 0.357A(30mils)
+3V
R255
*short_6
+3V_VCCPCORE
V15
V16
C486
+1.05V
L47
0.1u/10V_4_X7R Y16
VCC3_3[5]
VCC3_3[6]
VCC3_3[7]
VCCVRM[4]
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
V_CPU_IO >1mA(15mils)
C713
220u_3528
L46
+
C708
1u/10V_4
10uh_8
+1.1V_VTT
R484
*0_8
R228
+V1.1LAN_VCCA_B_DPL
+
C703
220u_3528
*short_6
+VTT_VCCPCPU
C459
C461
C462
4.7U/6.3V_6
0.1u/10V_4_X7R
0.1u/10V_4_X7R
C782
C771
0.1u/10V_4_X7R
0.1u/10V_4_X7R
AT18
AU18
V_CPU_IO[1]
V_CPU_IO[2]
VCCRTC= 2mA(15mils)
C696
1u/10V_4
A12
+VCCRTC
VCCRTC
IbexPeak-M_R1P0
VCCIO[11]
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
+V1.1LAN_VCCA_A_DPL
10uh_8
VCCIO[10]
VCCIO[12]
VCCME[13]
VCCME[14]
VCCME[15]
VCCME[16]
HDA
+1.8V
HDA_SYNC (PCH strap pin)
SATA
VCCSUS3_3 = 163mA(20mils)
VCCVRM=196mA(15mils)
PCI/GPIO/LPC
P18
CPU
R237
*SHORT0805
*short_6
VCCIO[3]
RTC
+1.05V
R305
0.1u/10V_4_X7R
0.1u/10V_4_X7R
0.022U/16V_4
VCCSUS3_3 = 0.163A(20mils)
IbexPeak-M_R1P0
1U/6.3V_4
VCCSUSHDA
C480
1u/10V_4
AH19
AD20
AF22
AD19
AF20
AF19
AH20
AB19
AB20
AB22
AD22
VCCME = 1.849A(100mils)
+1.05V_VCCEPW
AA34
Y34
Y35
AA35
L30
+V3.3A_1.5A_HDA_IO
R273
*Short_4
+3V_S5
VCCSUSHDA= 6mA(15mils)
C502
1u/10V_4

PROJECT : ZR7B
Size
Document Number
Rev
1A
IBEX PEAK-M 5/6

Date:
5
Sheet
1
12
of
50
U36I
IBEX PEAK-M (GND)

D
U36H
AB16
VSS[0]
AA19
AA20
AA22
AM19
AA24
AA26
AA28
AA30
AA31
AA32
AB11
AB15
AB23
AB30
AB31
AB32
AB39
AB43
AB47
AB5
AB8
AC2
AC52
AD11
AD12
AD16
AD23
AD30
AD31
AD32
AD34
AU22
AD42
AD46
AD49
AD7
AE2
AE4
AF12
Y13
AH49
AU4
AF35
AP13
AN34
AF45
AF46
AF49
AF5
AF8
AG2
AG52
AH11
AH15
AH16
AH24
AH32
AV18
AH43
AH47
AH7
AJ19
AJ2
AJ20
AJ22
AJ23
AJ26
AJ28
AJ32
AJ34
AT5
AJ4
AK12
AM41
AN19
AK26
AK22
AK23
AK28
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
IbexPeak-M_R1P0
A
AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47
AY7
B11
B15
B19
B23
B31
B35
B39
B43
B47
B7
BG12
BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49
BB5
BC10
BC14
BC18
BC2
BC22
BC32
BC36
BC40
BC44
BC52
BH9
BD48
BD49
BD5
BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50
BE6
BE8
BF3
BF49
BF51
BG18
BG24
BG4
BG50
BH11
BH15
BH19
BH23
BH31
BH35
BH39
BH43
BH47
BH7
C12
C50
D51
E12
E16
E20
E24
E30
E34
E38
E42
E46
E48
E6
E8
F49
F5
G10
G14
G18
G2
G22
G32
G36
G40
G44
G52
AF39
H16
H20
H30
H34
H38
H42
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[326]
VSS[327]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[332]
VSS[333]
VSS[334]
VSS[335]
VSS[336]
VSS[337]
VSS[338]
VSS[339]
VSS[340]
VSS[341]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[366]
H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14
IbexPeak-M_R1P0

PROJECT : ZR7B
Size
Document Number
Rev
1A
IBEX PEAK-M 6/6

Date:
5
Sheet
1
13
of
50
+1.5V_SUS
M_A_DQ[63:0] <5>
R215
R216
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
10K_4
10K_4
M_A_BS#0
M_A_BS#1
M_A_BS#2
M_A_CS#0
M_A_CS#1
M_A_CLK0
M_A_CLK0#
M_A_CLK1
M_A_CLK1#
M_A_CKE0
M_A_CKE1
M_A_CAS#
M_A_RAS#
M_A_WE#
<3,15,28> CLK_SCLK
<3,15,28> CLK_SDATA
<5> M_A_ODT0
<5> M_A_ODT1
<5> M_A_DM[7:0]
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15
DIMM0_SA0
DIMM0_SA1
CLK_SCLK
CLK_SDATA
109
108
79
114
121
101
103
102
104
73
74
115
110
113
197
201
202
200
BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA
116
120
ODT0
ODT1
11
28
46
63
136
153
170
187
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
12
29
47
64
137
154
171
188
10
27
45
62
135
152
169
186
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
<5> M_A_DQS[7:0]
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
<5> M_A_DQS#[7:0]
PC2100 DDR3 SDRAM SO-DIMM

(204P)
JDIM1A
<5> M_A_A[15:0]
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
2.48A
+3V
<4> PM_EXTTS#0
<15,36> DDR3_DRAMRST#
+SMDDR_VREF
R129
M1@0_6
R131
*M3@0_6
JDIM1B
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
199
VDDSPD
77
122
125
NC1
NC2
NCTEST
198
30
EVENT#
RESET#
+SMDDR_VREF_DQ0
1
+SMDDR_VREF_DIMM 126
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
<36> +SMDDR_VREF_DQ0
+1.5V_SUS
R120
*10K_4
VREF_DQ
VREF_CA
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15

(204P)
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
VTT1
VTT2
203
204
GND
GND
205
206
+0.75V_DDR_VTT
DDR3-DIMM0_H=5.2_Standard
+SMDDR_VREF
R122
*short_6
+SMDDR_VREF_DIMM
R121
*10K_4
C269
470p/X7R_4
DDR3-DIMM0_H=5.2_Standard
Place these Caps near So-Dimm0.

+1.5V_SUS
+SMDDR_VREF_DIMM
C371
10u/6.3V_6
C365
10u/6.3V_6
C386
10u/6.3V_6
C342
.1u/16V_4
+ C329
C391
330u/2V_7343
.1u/16V_4
C331
10u/6.3V_6
C349
10u/6.3V_6
C332
10u/6.3V_6
+3V
C351
.1u/16V_4
+SMDDR_VREF_DQ0
C337
.1u/16V_4
C375
.1u/16V_4
C341
.1u/16V_4
C392
C266
C268
.1u/16V_4
2.2u/6.3V_6
2.2u/6.3V_6
+0.75V_DDR_VTT
C409
2.2u/6.3V_6
C410
.1u/16V_4
C424
1U/6.3V_4
C415
1U/6.3V_4
C426
1U/6.3V_4
C425
1U/6.3V_4
C423
C421
C419
10u/6.3V_6 10u/6.3V_6 10u/6.3V_6
PROJECT : ZR7B
Size
Document Number
Rev
1A
DDRIII SO-DIMM-0
Date:
5
Sheet
1
14
of
50
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
10K_4
10K_4
R204
R214
+3V
M_B_BS#0
M_B_BS#1
M_B_BS#2
M_B_CS#0
M_B_CS#1
M_B_CLK0
M_B_CLK0#
M_B_CLK1
M_B_CLK1#
M_B_CKE0
M_B_CKE1
M_B_CAS#
M_B_RAS#
M_B_WE#
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15
109
108
79
114
121
101
103
102
104
73
74
115
110
113
197
201
202
200
BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA
116
120
ODT0
ODT1
M_B_DM0
M_B_DM1
M_B_DM2
M_B_DM3
M_B_DM4
M_B_DM5
M_B_DM6
M_B_DM7
11
28
46
63
136
153
170
187
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
12
29
47
64
137
154
171
188
10
27
45
62
135
152
169
186
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
DIMM1_SA0
DIMM1_SA1
<3,14,28> CLK_SCLK
<3,14,28> CLK_SDATA
<5> M_B_ODT0
<5> M_B_ODT1
<5> M_B_DM[7:0]
<5> M_B_DQS[7:0]
<5> M_B_DQS#[7:0]

(204P)
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
+1.5V_SUS
M_B_DQ[63:0] <5>
JDIM2A
<5> M_B_A[15:0]
2.48A
+3V
<4> PM_EXTTS#1
<14,36> DDR3_DRAMRST#
<36> +SMDDR_VREF_DQ1
+SMDDR_VREF_DIMM
+SMDDR_VREF_DQ1
R116
R127
M1@0_6
*M3@0_6
+SMDDR_VREF_DIMM
JDIM2B
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
199
VDDSPD
77
122
125
NC1
NC2
NCTEST
198
30
EVENT#
RESET#
1
126
VREF_DQ
VREF_CA
2
3
8
9
13
14
19
20
25
26
31
32
37
38
43
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15

(204P)
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
VTT1
VTT2
203
204
GND
GND
205
206
+0.75V_DDR_VTT
DDR3-DIMM1_H=5.2_Reverse
DDR3-DIMM1_H=5.2_Reverse
+1.5V_SUS
Place these Caps near So-Dimm1.

+SMDDR_VREF_DIMM
C376
10u/6.3V_6
C328
10u/6.3V_6
C364
10u/6.3V_6
C377
.1u/16V_4
+ C348
C394
330u/2V_7343
.1u/16V_4
C387
10u/6.3V_6
C343
10u/6.3V_6
C389
10u/6.3V_6
+3V
C353
.1u/16V_4
+SMDDR_VREF_DQ1
C370
.1u/16V_4
C338
.1u/16V_4
C385
.1u/16V_4
C393
C267 C265
.1u/16V_4
2.2u/6.3V_6
2.2u/6.3V_6
+0.75V_DDR_VTT
C404
2.2u/6.3V_6
C417
.1u/16V_4
C416
1U/6.3V_4
C429
1U/6.3V_4
C427
1U/6.3V_4
C428
1U/6.3V_4
C418
C422
10u/6.3V_6 10u/6.3V_6
C420
10u/6.3V_6

PROJECT : ZR7B
Size
Document Number
Rev
1A
DDRIII SO-DIMM-1
Date:
5
Sheet
1
15
of
50
U24A
<4>
<4>
PEG_TXP15
PEG_TXN15
AA38
Y37
PCIE_RX0P
PCIE_RX0N
PCIE_TX0P
PCIE_TX0N
Y33
Y32
CPEG_RXP15
CPEG_RXN15
C176
C166
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
<4>
<4>
PEG_TXP14
PEG_TXN14
Y35
W36
PCIE_RX1P
PCIE_RX1N
PCIE_TX1P
PCIE_TX1N
W33
W32
CPEG_RXP14
CPEG_RXN14
C163
C148
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
<4>
<4>
PEG_TXP13
PEG_TXN13
W38
V37
PCIE_RX2P
PCIE_RX2N
PCIE_TX2P
PCIE_TX2N
U33
U32
CPEG_RXP13
CPEG_RXN13
C153
C137
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
<4>
<4>
PEG_TXP12
PEG_TXN12
V35
U36
PCIE_RX3P
PCIE_RX3N
PCIE_TX3P
PCIE_TX3N
U30
U29
CPEG_RXP12
CPEG_RXN12
C132
C136
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
<4>
<4>
PEG_TXP11
PEG_TXN11
U38
T37
PCIE_RX4P
PCIE_RX4N
PCIE_TX4P
PCIE_TX4N
T33
T32
CPEG_RXP11
CPEG_RXN11
C121
C113
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
<4>
<4>
PEG_TXP10
PEG_TXN10
T35
R36
PCIE_RX5P
PCIE_RX5N
PCIE_TX5P
PCIE_TX5N
T30
T29
CPEG_RXP10
CPEG_RXN10
C123
C131
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
<4>
<4>
PEG_TXP9
PEG_TXN9
R38
P37
PCIE_RX6P
PCIE_RX6N
PCIE_TX6P
PCIE_TX6N
P33
P32
CPEG_RXP9
CPEG_RXN9
C107
C99
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
<4>
<4>
PEG_TXP8
PEG_TXN8
P35
N36
PCIE_RX7P
PCIE_RX7N
PCIE_TX7P
PCIE_TX7N
P30
P29
CPEG_RXP8
CPEG_RXN8
C85
C96
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
<4>
<4>
PEG_TXP7
PEG_TXN7
N38
M37
PCIE_RX8P
PCIE_RX8N
PCIE_TX8P
PCIE_TX8N
N33
N32
CPEG_RXP7
CPEG_RXN7
C83
C73
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
<4>
<4>
PEG_TXP6
PEG_TXN6
M35
L36
PCIE_RX9P
PCIE_RX9N
PCIE_TX9P
PCIE_TX9N
N30
N29
CPEG_RXP6
CPEG_RXN6
C62
C67
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
PCIE_TX10P
PCIE_TX10N
L33
L32
CPEG_RXP5
CPEG_RXN5
C61
C60
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
PCIE_TX11P
PCIE_TX11N
L30
L29
CPEG_RXP4
CPEG_RXN4
C58
C56
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
PCIE_TX12P
PCIE_TX12N
K33
K32
CPEG_RXP3
CPEG_RXN3
C48
C44
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
PEG_RXP15 <4>
PEG_RXN15 <4>
PCI EXPRESS INTERFACE
PEG_RXP14 <4>
PEG_RXN14 <4>
PEG_RXP13 <4>
PEG_RXN13 <4>
PEG_RXP12 <4>
PEG_RXN12 <4>
PEG_RXP11 <4>
PEG_RXN11 <4>
PEG_RXP10 <4>
PEG_RXN10 <4>
PEG_RXP9 <4>
PEG_RXN9 <4>
C
<4>
<4>
PEG_TXP5
PEG_TXN5
L38
K37
PCIE_RX10P
PCIE_RX10N
<4>
<4>
PEG_TXP4
PEG_TXN4
K35
J36
PCIE_RX11P
PCIE_RX11N
<4>
<4>
PEG_TXP3
PEG_TXN3
J38
H37
PCIE_RX12P
PCIE_RX12N
<4>
<4>
PEG_TXP2
PEG_TXN2
H35
G36
PCIE_RX13P
PCIE_RX13N
PCIE_TX13P
PCIE_TX13N
J33
J32
CPEG_RXP2
CPEG_RXN2
C43
C41
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
<4>
<4>
PEG_TXP1
PEG_TXN1
G38
F37
PCIE_RX14P
PCIE_RX14N
PCIE_TX14P
PCIE_TX14N
K30
K29
CPEG_RXP1
CPEG_RXN1
C39
C37
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
<4>
<4>
PEG_TXP0
PEG_TXN0
F35
E37
PCIE_RX15P
PCIE_RX15N
PCIE_TX15P
PCIE_TX15N
H33
H32
CPEG_RXP0
CPEG_RXN0
C36
C32
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
PCIE_CALRP
Y30
R33
SW@1.27K/F_4
PCIE_CALRN
Y29
R30
SW@2K/F_4 +1V
PEG_RXP8 <4>
PEG_RXN8 <4>
PEG_RXP7 <4>
PEG_RXN7 <4>
PEG_RXP6 <4>
PEG_RXN6 <4>
PEG_RXP5 <4>
PEG_RXN5 <4>
PEG_RXP4 <4>
PEG_RXN4 <4>
PEG_RXP3 <4>
PEG_RXN3 <4>
PEG_RXP2 <4>
PEG_RXN2 <4>
PEG_RXP1 <4>
PEG_RXN1 <4>
PEG_RXP0 <4>
PEG_RXN0 <4>
CLOCK
<10> CLK_PCIE_VGA
<10> CLK_PCIE_VGA#
For Broadway, Madison and Park

the PWRGOOD ball must be conneccted to ground
R44
SW@10K_4
AB35
AA36
PCIE_REFCLKP
PCIE_REFCLKN
AJ21
AK21
AH16
NC#1
NC#2
PWRGOOD
CALIBRATION
<11> GPU_RST#
GPU_RST#
AA30
+1.0V
For M97, Broadway, Madison and Park PCIE_VDDC is 1.0V
PERSTB
SW@Madison/Broadway_M2
PROJECT : ZR7B
Size
Document Number
Madison/Broadway-PCIE I/F
Date:
5
Sheet
1
16
of
50
Rev
1A
GPU Power-on sequence
U24B
1 => +3V_D
2 => +VGPU_CORE
3 => +VGPU_IO
4 => +1V
5 => +1.5V_GPU
6 => +1.8V_GPU
7 => dGPU_PWROK
U24G
TXCAP_DPA3P
TXCAM_DPA3N
TX0P_DPA2P
TX0M_DPA2N
MUTI GFX
DPA
TX1P_DPA1P
TX1M_DPA1N
NC on Park
<23> RAM_STRAP0
<23> RAM_STRAP1
<23> RAM_STRAP2
T34
1.8V GPIO
NC on Park
+3V_D
AR8
AU8
AP8
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12
DVPCNTL_MVP_0
DVPCNTL_MVP_1
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23
TX2P_DPA0P
TX2M_DPA0N
TXCBP_DPB3P
TXCBM_DPB3N
TX3P_DPB2P
TX3M_DPB2N
DPB
TX4P_DPB1P
TX4M_DPB1N
TX5P_DPB0P
TX5M_DPB0N
TXCCP_DPC3P
TXCCM_DPC3N
TX0P_DPC2P
TX0M_DPC2N
DPC
TX1P_DPC1P
TX1M_DPC1N
TX2P_DPC0P
TX2M_DPC0N
TXCDP_DPD3P
TXCDM_DPD3N
TX3P_DPD2P
TX3M_DPD2N
DPD
R58
SW@10K/F_4
R67
SW@10K/F_4
TX4P_DPD1P
TX4M_DPD1N
I2C
AK26
AJ26
TX5P_DPD0P
TX5M_DPD0N
AH20
AH18
AN16
AH23
AJ23
AH17
T11
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
T23
AM13
AK14
AG30
AN14
T27
AM17
AL13
AJ14
T14
AK13
AN13
GPIO24_TRSTB AM23
SW@10K/F_4
*SW@10K/F_4
T24
AN23
27M_CLK
AK23
SW@10K/F_4
AL24
T28
AM24
SW@10K/F_4
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24
<45>
IO_VID0
<24> EV_LVDS_BLON
<23> SOUT_GPIO8
<23> SIN_GPIO9
<23> SCLK_GPIO10
<23> GPU_GPIO11
<23> GPU_GPIO12
<23> GPU_GPIO13
+3V_D
R68
SW@10K_4
3.3V GPIO
<44> VCORE1.2ID0
<23> ALT#_GPIO17
<44> VCORE1.2ID1
+3V_D
R74
*SW@10K/F_4
<23> SCS#_GPIO22
R106
*SW@10K/F_4
+3V_D
<3>
27M_CLK
R98
+3V_D
<10> PEG_CLKREQ#
R386
10/5 modify
R105
*SW@10K/F_4
R50
R382
GenericF/G is NC on PARK
+1.8V_GPU
AK24
<25> HDMI_HP_EV
GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16_SSIN
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
GENERICF
GENERICG
G
GB
B
BB
DAC1
HSYNC
VSYNC
RSET
AVDD
AVSSQ
VDD1DI
VSS1DI
R2
R2B
G2
G2B
B2
B2B
C
Y
COMP
HPD1
A2VDDQ
VREFG
A2VSSQ
C232
SW@249/F_4
SW@0.1u/10V_4_X7R
AU26
AV25
HDMITX1P <25>
HDMITX1N <25>
TXCLK_UP_DPF3P
TXCLK_UN_DPF3N
AT27
AR26
HDMITX2P <25>
HDMITX2N <25>
TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N
VARY_BL
DIGON
L15
SW@BLM15AG121SS1/0.5A/120ohm_4
AR30
AT29
TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N
AV31
AU30
TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N
AR32
AT31
TXOUT_U3P
TXOUT_U3N
AT33
AU32
C211
DPLL_PVDD
DDC/AUX
DPLL_PVDD
SW@10u/6.3V_6
SW@0.1u/10V_4_X7R
SW@1u/6.3V_4
R410
<3> CLK_27M_SS
C611
L19
C242
C228
DPLL_VDDC
Y3
C223
SW@10u/6.3V_6
SW@0.1u/10V_4_X7R
SW@1u/6.3V_4
C610
R409
SW@1M_4
SW@27MHZ
<23>
<23>
+1.8V(5mA)
L6
AN31
XTALI_27M
XTALO_27M
AV33
AU34
TS_VDD
C218
SW@10u/6.3V_6
SW@0.1u/10V_4_X7R
AUX1P
AUX1N
DPLL_VDDC
DDC2CLK
DDC2DATA
XTALIN
XTALOUT
AUX2P
AUX2N
DDCCLK_AUX3P
DDCDATA_AUX3N
AF29
AG29
GPU_D+
GPU_DT19
TS_VDD
C219
DDC1CLK
DDC1DATA
DPLL_PVDD
DPLL_PVSS
SW@27p/50V_4
+1.8V_GPU
DPLL_VDDC
SW@27p/50V_4
+1V
AM32
AN32
*SW@0_4
+1.0V(125mA)
*SW@10K_4
*SW@10K_4
AK35
AL36
AJ38
AK37
AH35
AJ36
AG38
AH37
AF35
AG36
LVTMDP
AU14
AV13
TXCLK_LP_DPE3P
TXCLK_LN_DPE3N
AT15
AR14
TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N
AU16
AV15
TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N
AT17
AR16
TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N
AU20
AT19
TXOUT_L3P
TXOUT_L3N
AP34
AR34
EV_TXLCLKOUT+ <24>
EV_TXLCLKOUT- <24>
AW37
AU35
EV_TXLOUT0+ <24>
EV_TXLOUT0- <24>
AR37
AU39
EV_TXLOUT1+ <24>
EV_TXLOUT1- <24>
AP35
AR35
EV_TXLOUT2+ <24>
EV_TXLOUT2- <24>
AN36
AP37
AT21
AR20
DP Channel D is NC on PARK
AU22
AV21
AT23
AR22
AD39
AD37
EV_CRT_RED
AE36
AD35
EV_CRT_GRN
<24>
AF37
AE38
EV_CRT_BLU
<24>
AC36
AC38
AB34
EV_HSYNC
EV_VSYNC
R36
<23,24>
<23,24>
R383
R379
SW@150/F_4
SW@150/F_4
<24>
R375
SW@150/F_4
SW@499/F_4
AD34
AE34
AVDD
AC33
AC34
VDD1DI
+1.8V_GPU
(1.8V@70mA AVDD)
AVDD
L42
C593
C592
C591
SW@0.1u/10V_4_X7R
SW@10u/6.3V_6
SW@1u/6.3V_4
AC30
AC31
AD30
AD31
(1.8V@100mA VDD1DI)
VDD1DI
AF30
AF31
DAC2 will be NC on future ASIC

AC32
AD32
AF32
L5
C195
C196
C198
SW@0.1u/10V_4_X7R
SW@10u/6.3V_6
SW@1u/6.3V_4
T8
AD29
AC29
AG31
AG32
V2SYNC
<23>
VDD1DI
+3V_D
(3.3V@130mA A2VDD)
AG33
AD33
A2VDDQ
C174
SW@0.1u/10V_4_X7R
AF33
AA29
R37
SW@715/F_4
(1.8V@2mA A2VDDQ)
A2VDDQ
C207
<24>
<24>
+1.8V_GPU
R2SET
PLL/CLOCK
C249
EV_LVDS_BRIGHT
EV_LVDS_VDDEN
R61
R66
+1.8V(75mA)
+1.8V_GPU
AK27
AJ27
H2SYNC
V2SYNC
A2VDD
R89
HDMITX0P <25>
HDMITX0N <25>
DAC2
R88
SW@499/F_4
AH13
HDMICLK+ <25>
HDMICLK- <25>
AT25
AR24
R
RB
VDD2DI
VSS2DI
VREFG
LVDS CONTROL
AU24
AV23
SCL
SDA
GENERAL PURPOSE I/O
<23> GPU_GPIO0
<23> GPU_GPIO1
<23> GPU_GPIO2
<23> GPIO3_SMBDAT
<23> GPIO4_SMBCLK
AK32
AJ32
AJ33
DPLUS
DMINUS
THERMAL
DDCCLK_AUX4P
DDCDATA_AUX4N
DDCCLK_AUX5P
DDCDATA_AUX5N
TS_FDO
TSVDD
TSVSS
DDC6CLK
DDC6DATA
NC_DDCCLK_AUX7P
NC_DDCDATA_AUX7N
AM26
AN26
AM27
AL27
AM19
AL19
AN20
AM20
AL30
AM30
AL29
AM29
MXM_DDCCK <25>
MXM_DDCDAT <25>
C588
C587
SW@0.1u/10V_4_X7R
SW@1u/6.3V_4
T33
T31
T26
T17
T21
T18
T15
T35
T25
T30
AN21
AM21
DDCxx_AUX4x is NC on PARK
EV_LVDS_DDCCLK
EV_LVDS_DDCDAT
AJ30
AJ31
AK30
AK29
HDMI
L41
EV_CRTDCLK
EV_CRTDDAT
T29
T20
<24>
<24>
<24>
<24>
LVDS
CRT
DDCxx_AUX7x is NC on M9x and PARK

PROJECT : ZR7B
Size
Document Number
Rev
1A
Madison/Broadway-HOST I/F
Date:
5
Sheet
1
17
of
50
<19> VMA_WDQS[7..0]
VMA_DQ[63..0]
<20> VMB_DQ[63..0]
VMA_DM[7..0]
<19>
<19>
<19>
VMA_BA0
VMA_BA1
VMA_BA2
VMA_RDQS[7..0]
VMA_WDQS[7..0]
VMA_MA[13..0]
VMA_BA0
VMA_BA1
VMA_BA2
+1.5V_GPU
R353
SW@40.2/F_4
R354
+1.5V_GPU
C548
SW@0.1u/10V_4_X7R
VMA_DQ0
VMA_DQ1
VMA_DQ2
VMA_DQ3
VMA_DQ4
VMA_DQ5
VMA_DQ6
VMA_DQ7
VMA_DQ8
VMA_DQ9
VMA_DQ10
VMA_DQ11
VMA_DQ12
VMA_DQ13
VMA_DQ14
VMA_DQ15
VMA_DQ16
VMA_DQ17
VMA_DQ18
VMA_DQ19
VMA_DQ20
VMA_DQ21
VMA_DQ22
VMA_DQ23
VMA_DQ24
VMA_DQ25
VMA_DQ26
VMA_DQ27
VMA_DQ28
VMA_DQ29
VMA_DQ30
VMA_DQ31
VMA_DQ32
VMA_DQ33
VMA_DQ34
VMA_DQ35
VMA_DQ36
VMA_DQ37
VMA_DQ38
VMA_DQ39
VMA_DQ40
VMA_DQ41
VMA_DQ42
VMA_DQ43
VMA_DQ44
VMA_DQ45
VMA_DQ46
VMA_DQ47
VMA_DQ48
VMA_DQ49
VMA_DQ50
VMA_DQ51
VMA_DQ52
VMA_DQ53
VMA_DQ54
VMA_DQ55
VMA_DQ56
VMA_DQ57
VMA_DQ58
VMA_DQ59
VMA_DQ60
VMA_DQ61
VMA_DQ62
VMA_DQ63
C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5
MVREFDA
MVREFSA
L18
L20
R23
R27
R47
MP@243/F_4
L27
MP@243/F_4
N12
MP@243/F_4 AG12
R25
R22
R65
MP@243/F_4
M12
MP@243/F_4
M27
MP@243/F_4 AH12
SW@100/F_4
<20> VMB_DM[7..0]
U24C
DDR2
GDDR3/GDDR5
DDR3
<19> VMA_MA[13..0]
DQA0_0/DQA_0
DQA0_1/DQA_1
DQA0_2/DQA_2
DQA0_3/DQA_3
DQA0_4/DQA_4
DQA0_5/DQA_5
DQA0_6/DQA_6
DQA0_7/DQA_7
DQA0_8/DQA_8
DQA0_9/DQA_9
DQA0_10/DQA_10
DQA0_11/DQA_11
DQA0_12/DQA_12
DQA0_13/DQA_13
DQA0_14/DQA_14
DQA0_15/DQA_15
DQA0_16/DQA_16
DQA0_17/DQA_17
DQA0_18/DQA_18
DQA0_19/DQA_19
DQA0_20/DQA_20
DQA0_21/DQA_21
DQA0_22/DQA_22
DQA0_23/DQA_23
DQA0_24/DQA_24
DQA0_25/DQA_25
DQA0_26/DQA_26
DQA0_27/DQA_27
DQA0_28/DQA_28
DQA0_29/DQA_29
DQA0_30/DQA_30
DQA0_31/DQA_31
DQA1_0/DQA_32
DQA1_1/DQA_33
DQA1_2/DQA_34
DQA1_3/DQA_35
DQA1_4/DQA_36
DQA1_5/DQA_37
DQA1_6/DQA_38
DQA1_7/DQA_39
DQA1_8/DQA_40
DQA1_9/DQA_41
DQA1_10/DQA_42
DQA1_11/DQA_43
DQA1_12/DQA_44
DQA1_13/DQA_45
DQA1_14/DQA_46
DQA1_15/DQA_47
DQA1_16/DQA_48
DQA1_17/DQA_49
DQA1_18/DQA_50
DQA1_19/DQA_51
DQA1_20/DQA_52
DQA1_21/DQA_53
DQA1_22/DQA_54
DQA1_23/DQA_55
DQA1_24/DQA_56
DQA1_25/DQA_57
DQA1_26/DQA_58
DQA1_27/DQA_59
DQA1_28/DQA_60
DQA1_29/DQA_61
DQA1_30/DQA_62
DQA1_31/DQA_63
DDR2
GDDR5/GDDR3
DDR3
MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
MAA1_5/MAA_13_BA2
MAA1_6/MAA_14_BA0
MAA1_7/MAA_A15_BA1
WCKA0_0/DQMA_0
WCKA0B_0/DQMA_1
WCKA0_1/DQMA_2
WCKA0B_1/DQMA_3
WCKA1_0/DQMA_4
WCKA1B_0/DQMA_5
WCKA1_1/DQMA_6
WCKA1B_1/DQMA_7
GDDR5/DDR2/GDDR3
EDCA0_0/QSA_0/RDQSA_0
DDBIA0_0/QSA_0B/WDQSA_0
ADBIA0/ODTA0
ADBIA1/ODTA1
CLKA0
CLKA0B
CLKA1
CLKA1B
RASA0B
RASA1B
CASA0B
CASA1B
CSA0B_0
CSA0B_1
CSA1B_0
CSA1B_1
MVREFDA
MVREFSA
CKEA0
CKEA1
MEM_CALRN0
MEM_CALRN1
MEM_CALRN2
WEA0B
WEA1B
MEM_CALRP1
MEM_CALRP0
MEM_CALRP2
MAA0_8
MAA1_8
<20> VMB_RDQS[7..0]
G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17
VMA_MA0
VMA_MA1
VMA_MA2
VMA_MA3
VMA_MA4
VMA_MA5
VMA_MA6
VMA_MA7
VMA_MA8
VMA_MA9
VMA_MA10
VMA_MA11
VMA_MA12
VMA_BA2
VMA_BA0
VMA_BA1
A32
C32
D23
E22
C14
A14
E10
D9
VMA_DM0
VMA_DM1
VMA_DM2
VMA_DM3
VMA_DM4
VMA_DM5
VMA_DM6
VMA_DM7
C34
D29
D25
E20
E16
E12
J10
D7
VMA_RDQS0
VMA_RDQS1
VMA_RDQS2
VMA_RDQS3
VMA_RDQS4
VMA_RDQS5
VMA_RDQS6
VMA_RDQS7
A34
E30
E26
C20
C16
C12
J11
F8
VMA_WDQS0
VMA_WDQS1
VMA_WDQS2
VMA_WDQS3
VMA_WDQS4
VMA_WDQS5
VMA_WDQS6
VMA_WDQS7
J21
G19
VMA_ODT0
VMA_ODT1
H27
G27
VMA_CLK0
VMA_CLK0#
J14
H14
VMA_CLK1
VMA_CLK1#
K23
K19
VMA_RAS0#
VMA_RAS1#
K20
K17
VMA_CAS0#
VMA_CAS1#
K24
K27
VMA_CS0#
M13
K16
VMA_CS1#
K21
J20
VMA_CKE0
VMA_CKE1
K26
L15
VMA_WE0#
VMA_WE1#
H23
J19
VMA_MA13
<20> VMB_WDQS[7..0]
<20> VMB_MA[13..0]
<20>
<20>
<20>
VMB_BA0
VMB_BA1
VMB_BA2
VMB_DQ[63..0]
VMB_DM[7..0]
U24D
DDR2
GDDR3/GDDR5
DDR3
VMB_RDQS[7..0]
VMB_WDQS[7..0]
VMB_DQ0
VMB_DQ1
VMB_DQ2
VMB_DQ3
VMB_DQ4
VMB_DQ5
VMB_DQ6
VMB_DQ7
VMB_DQ8
VMB_DQ9
VMB_DQ10
VMB_DQ11
VMB_DQ12
VMB_DQ13
VMB_DQ14
VMB_DQ15
VMB_DQ16
VMB_DQ17
VMB_DQ18
VMB_DQ19
VMB_DQ20
VMB_DQ21
VMB_DQ22
VMB_DQ23
VMB_DQ24
VMB_DQ25
VMB_DQ26
VMB_DQ27
VMB_DQ28
VMB_DQ29
VMB_DQ30
VMB_DQ31
VMB_DQ32
VMB_DQ33
VMB_DQ34
VMB_DQ35
VMB_DQ36
VMB_DQ37
VMB_DQ38
VMB_DQ39
VMB_DQ40
VMB_DQ41
VMB_DQ42
VMB_DQ43
VMB_DQ44
VMB_DQ45
VMB_DQ46
VMB_DQ47
VMB_DQ48
VMB_DQ49
VMB_DQ50
VMB_DQ51
VMB_DQ52
VMB_DQ53
VMB_DQ54
VMB_DQ55
VMB_DQ56
VMB_DQ57
VMB_DQ58
VMB_DQ59
VMB_DQ60
VMB_DQ61
VMB_DQ62
VMB_DQ63
VMB_MA[13..0]
VMB_BA0
VMB_BA1
VMB_BA2
VMA_ODT0 <19>
VMA_ODT1 <19>
VMA_CLK0 <19>
VMA_CLK0# <19>
VMA_CLK1 <19>
VMA_CLK1# <19>
VMA_RAS0#
VMA_RAS1#
<19>
<19>
VMA_CAS0#
VMA_CAS1#
<19>
<19>
+1.5V_GPU
VMA_CS0# <19>
VMA_CS1# <19>
R34
SW@40.2/F_4
VMA_CKE0 <19>
VMA_CKE1 <19>
VMA_WE0#
VMA_WE1#
<19>
<19>
MVREFDB
MVREFSB
R31
C128
+3V_D
SW@0.1u/10V_4_X7R
SW@100/F_4
R377
SW@10K/F_4
R39
*SW@1K_4 TESTEN
C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5
Y12
AA12
DDR2
GDDR5/GDDR3
DDR3
DQB0_0/DQB_0
DQB0_1/DQB_1
DQB0_2/DQB_2
DQB0_3/DQB_3
DQB0_4/DQB_4
DQB0_5/DQB_5
DQB0_6/DQB_6
DQB0_7/DQB_7
DQB0_8/DQB_8
DQB0_9/DQB_9
DQB0_10/DQB_10
DQB0_11/DQB_11
DQB0_12/DQB_12
DQB0_13/DQB_13
DQB0_14/DQB_14
DQB0_15/DQB_15
DQB0_16/DQB_16
DQB0_17/DQB_17
DQB0_18/DQB_18
DQB0_19/DQB_19
DQB0_20/DQB_20
DQB0_21/DQB_21
DQB0_22/DQB_22
DQB0_23/DQB_23
DQB0_24/DQB_24
DQB0_25/DQB_25
DQB0_26/DQB_26
DQB0_27/DQB_27
DQB0_28/DQB_28
DQB0_29/DQB_29
DQB0_30/DQB_30
DQB0_31/DQB_31
DQB1_0/DQB_32
DQB1_1/DQB_33
DQB1_2/DQB_34
DQB1_3/DQB_35
DQB1_4/DQB_36
DQB1_5/DQB_37
DQB1_6/DQB_38
DQB1_7/DQB_39
DQB1_8/DQB_40
DQB1_9/DQB_41
DQB1_10/DQB_42
DQB1_11/DQB_43
DQB1_12/DQB_44
DQB1_13/DQB_45
DQB1_14/DQB_46
DQB1_15/DQB_47
DQB1_16/DQB_48
DQB1_17/DQB_49
DQB1_18/DQB_50
DQB1_19/DQB_51
DQB1_20/DQB_52
DQB1_21/DQB_53
DQB1_22/DQB_54
DQB1_23/DQB_55
DQB1_24/DQB_56
DQB1_25/DQB_57
DQB1_26/DQB_58
DQB1_27/DQB_59
DQB1_28/DQB_60
DQB1_29/DQB_61
DQB1_30/DQB_62
DQB1_31/DQB_63
MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1
WCKB0_0/DQMB_0
WCKB0B_0/DQMB_1
WCKB0_1/DQMB_2
WCKB0B_1/DQMB_3
WCKB1_0/DQMB_4
WCKB1B_0/DQMB_5
WCKB1_1/DQMB_6
WCKB1B_1/DQMB_7
GDDR5/DDR2/GDDR3
EDCB0_0/QSB_0/RDQSB_0
DDBIB0_0/QSB_0B/WDQSB_0
ADBIB0/ODTB0
ADBIB1/ODTB1
CLKB0
CLKB0B
CLKB1
CLKB1B
RASB0B
RASB1B
CASB0B
CASB1B
CSB0B_0
CSB0B_1
CSB1B_0
CSB1B_1
CKEB0
CKEB1
MVREFDB
MVREFSB
WEB0B
WEB1B
AD28
AK10
AL10
+1.5V_GPU
GDDR5
<19> VMA_RDQS[7..0]
GDDR5
<19> VMA_DM[7..0]
MEMORY INTERFACE A
<19> VMA_DQ[63..0]
MEMORY INTERFACE B
TESTEN
CLKTESTA
CLKTESTB
MAB0_8
MAB1_8
DRAM_RST
P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9
VMB_MA0
VMB_MA1
VMB_MA2
VMB_MA3
VMB_MA4
VMB_MA5
VMB_MA6
VMB_MA7
VMB_MA8
VMB_MA9
VMB_MA10
VMB_MA11
VMB_MA12
VMB_BA2
VMB_BA0
VMB_BA1
H3
H1
T3
T5
AE4
AF5
AK6
AK5
VMB_DM0
VMB_DM1
VMB_DM2
VMB_DM3
VMB_DM4
VMB_DM5
VMB_DM6
VMB_DM7
F6
K3
P3
V5
AB5
AH1
AJ9
AM5
VMB_RDQS0
VMB_RDQS1
VMB_RDQS2
VMB_RDQS3
VMB_RDQS4
VMB_RDQS5
VMB_RDQS6
VMB_RDQS7
G7
K1
P1
W4
AC4
AH3
AJ8
AM3
VMB_WDQS0
VMB_WDQS1
VMB_WDQS2
VMB_WDQS3
VMB_WDQS4
VMB_WDQS5
VMB_WDQS6
VMB_WDQS7
T7
W7
VMB_ODT0
VMB_ODT1
L9
L8
VMB_CLK0
VMB_CLK0#
AD8
AD7
VMB_CLK1
VMB_CLK1#
T10
Y10
VMB_RAS0#
VMB_RAS1#
W10
AA10
VMB_CAS0#
VMB_CAS1#
P10
L10
VMB_CS0#
AD10
AC10
VMB_CS1#
U10
AA11
VMB_CKE0
VMB_CKE1
N10
AB11
VMB_WE0#
VMB_WE1#
T8
W8
VMB_MA13
AH11
R419
VMB_ODT0 <20>
VMB_ODT1 <20>
VMB_CLK0 <20>
VMB_CLK0# <20>
VMB_CLK1 <20>
VMB_CLK1# <20>
VMB_RAS0#
VMB_RAS1#
<20>
<20>
VMB_CAS0#
VMB_CAS1#
<20>
<20>
VMB_CS0#
<20>
VMB_CS1#
<20>
VMB_CKE0
VMB_CKE1
<20>
<20>
VMB_WE0#
VMB_WE1#
<20>
<20>
R361
*SW@4.7K_4
SW@51_4
+1.5V_GPU
MEM_RST# <19,20>
B
+1.5V_GPU
TP1
Madison
Park
R23, R47,
R22, R65
R27, R25
R21
SW@40.2/F_4
R20
AL31
R80
*0_4
RSVD
R86
*0_4
C565
R92
SW@68p/50V_4
SW@10K_4
R40
SW@40.2/F_4
C63
SW@0.1u/10V_4_X7R
R35
C164
SW@0.1u/10V_4_X7R
SW@100/F_4
SW@100/F_4

PROJECT : ZR7B
Size
Document Number
Date:
Madison/Broadway-MEM I/F
5
Sheet
1
18
of
50
Rev
1A
<18> VMA_DQ[63..0]
<18> VMA_DM[7..0]
<18> VMA_RDQS[7..0]
<18> VMA_WDQS[7..0]
VMA_DQ[63..0]
VMA_RDQS[7..0]
QSA[7..0]
VMA_WDQS[7..0]
QSA#[7..0]
U20
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
VMA_MA0
VMA_MA1
VMA_MA2
VMA_MA3
VMA_MA4
VMA_MA5
VMA_MA6
VMA_MA7
VMA_MA8
VMA_MA9
VMA_MA10
VMA_MA11
VMA_MA12
VMA_MA13
<18>
<18>
<18>
VMA_BA0
VMA_BA1
VMA_BA2
<18> VMA_CLK0
<18> VMA_CLK0#
<18> VMA_CKE0
<18>
<18>
<18>
<18>
<18>
VMA_ODT0
VMA_CS0#
VMA_RAS0#
VMA_CAS0#
VMA_WE0#
VREFC_VMA1
VREFD_VMA1
M8
H1
VMA_MA0
VMA_MA1
VMA_MA2
VMA_MA3
VMA_MA4
VMA_MA5
VMA_MA6
VMA_MA7
VMA_MA8
VMA_MA9
VMA_MA10
VMA_MA11
VMA_MA12
VMA_MA13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
VMA_BA0
VMA_BA1
VMA_BA2
M2
N8
M3
VMA_CLK0
VMA_CLK0#
VMA_CKE0
J7
K7
K9
VMA_ODT0
VMA_CS0#
VMA_RAS0#
VMA_CAS0#
VMA_WE0#
K1
L2
J3
K3
L3
VMA_RDQS1
VMA_RDQS2
F3
C7
VMA_DM1
VMA_DM2
E7
D3
VMA_WDQS1
VMA_WDQS2
G3
B7
MEM_RST#
T2
<18,20> MEM_RST#
VMA_ZQ1
L8
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
DML
DMU
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
DQSL
DQSU
RESET
ZQ
NC#J1
NC#L1
NC#J9
NC#L9
VMA_DQ10
VMA_DQ11
VMA_DQ9
VMA_DQ12
VMA_DQ13
VMA_DQ15
VMA_DQ8
VMA_DQ14
E3
F7
F2
F8
H3
H8
G2
H7
VMA_DQ20
VMA_DQ19
VMA_DQ23
VMA_DQ18
VMA_DQ22
VMA_DQ16
VMA_DQ21
VMA_DQ17
D7
C3
C8
C2
A7
A2
B8
A3
VREFC_VMA2
VREFD_VMA2
M8
H1
VMA_MA0
VMA_MA1
VMA_MA2
VMA_MA3
VMA_MA4
VMA_MA5
VMA_MA6
VMA_MA7
VMA_MA8
VMA_MA9
VMA_MA10
VMA_MA11
VMA_MA12
VMA_MA13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
VMA_BA0
VMA_BA1
VMA_BA2
M2
N8
M3
VMA_CLK0
VMA_CLK0#
VMA_CKE0
J7
K7
K9
+1.5V_GPU
BA0
BA1
BA2
R349
MP@240/F_4
J1
L1
J9
L9
U1
VREFCA
VREFDQ
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5V_GPU
A1
A8
C1
C9
D2
E9
F1
H2
H9
VMA_ODT0
VMA_CS0#
VMA_RAS0#
VMA_CAS0#
VMA_WE0#
K1
L2
J3
K3
L3
VMA_RDQS0
VMA_RDQS3
F3
C7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VMA_DM0
VMA_DM3
E7
D3
VMA_WDQS0
VMA_WDQS3
G3
B7
MEM_RST#
T2
VMA_ZQ2
B1
B9
D1
D8
E2
E8
F9
G1
G9
L8
100-BALL
SDRAM DDR3
MP@VRAM _DDR3
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15
CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU
RESET
ZQ
R3
MP@240/F_4
J1
L1
J9
L9
U21
VREFCA
VREFDQ
BA0
BA1
BA2
NC#J1
NC#L1
NC#J9
NC#L9
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
VMA_DQ6
VMA_DQ0
VMA_DQ7
VMA_DQ1
VMA_DQ4
VMA_DQ2
VMA_DQ5
VMA_DQ3
D7
C3
C8
C2
A7
A2
B8
A3
VMA_DQ25
VMA_DQ31
VMA_DQ27
VMA_DQ28
VMA_DQ24
VMA_DQ30
VMA_DQ26
VMA_DQ29
0
3
VREFC_VMA3
VREFD_VMA3
M8
H1
VMA_MA0
VMA_MA1
VMA_MA2
VMA_MA3
VMA_MA4
VMA_MA5
VMA_MA6
VMA_MA7
VMA_MA8
VMA_MA9
VMA_MA10
VMA_MA11
VMA_MA12
VMA_MA13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9
B2
D9
G7
K2
K8
N1
N9
R1
R9
VMA_BA0
VMA_BA1
VMA_BA2
M2
N8
M3
+1.5V_GPU
A1
A8
C1
C9
D2
E9
F1
H2
H9
<18> VMA_CLK1
<18> VMA_CLK1#
<18> VMA_CKE1
VMA_CLK1
VMA_CLK1#
VMA_CKE1
J7
K7
K9
<18>
<18>
<18>
<18>
<18>
VMA_ODT1
VMA_CS1#
VMA_RAS1#
VMA_CAS1#
VMA_WE1#
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VMA_ODT1
VMA_CS1#
VMA_RAS1#
VMA_CAS1#
VMA_WE1#
K1
L2
J3
K3
L3
VMA_RDQS6
VMA_RDQS7
F3
C7
VMA_DM6
VMA_DM7
E7
D3
VMA_WDQS6
VMA_WDQS7
G3
B7
MEM_RST#
T2
VMA_ZQ3
B1
B9
D1
D8
E2
E8
F9
G1
G9
BA0
BA1
BA2
CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU
RESET
L8
ZQ
J1
L1
J9
L9
BOT Left
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15
R344
MP@240/F_4
Group-A0 VREF
U2
VREFCA
VREFDQ
+1.5V_GPU
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
100-BALL
SDRAM DDR3
MP@VRAM _DDR3
TOP Left
Park, M92M Use Channel B Memory Interface Only
CHANNEL A: 512MB DDR3 (64M*16*4pcs)
VMA_DM[7..0]
NC#J1
NC#L1
NC#J9
NC#L9
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
VMA_DQ54
VMA_DQ53
VMA_DQ55
VMA_DQ50
VMA_DQ49
VMA_DQ48
VMA_DQ52
VMA_DQ51
VREFC_VMA4
VREFD_VMA4
M8
H1
VMA_MA0
VMA_MA1
VMA_MA2
VMA_MA3
VMA_MA4
VMA_MA5
VMA_MA6
VMA_MA7
VMA_MA8
VMA_MA9
VMA_MA10
VMA_MA11
VMA_MA12
VMA_MA13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
D7
C3
C8
C2
A7
A2
B8
A3
VMA_DQ63
VMA_DQ56
VMA_DQ62
VMA_DQ59
VMA_DQ60
VMA_DQ58
VMA_DQ61
VMA_DQ57
VMA_BA0
VMA_BA1
VMA_BA2
M2
N8
M3
VMA_CLK1
VMA_CLK1#
VMA_CKE1
J7
K7
K9
A1
A8
C1
C9
D2
E9
F1
H2
H9
VMA_ODT1
VMA_CS1#
VMA_RAS1#
VMA_CAS1#
VMA_WE1#
K1
L2
J3
K3
L3
VMA_RDQS5
VMA_RDQS4
F3
C7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VMA_DM5
VMA_DM4
E7
D3
VMA_WDQS5
VMA_WDQS4
G3
B7
MEM_RST#
T2
6
7
+1.5V_GPU
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9
B2
D9
G7
K2
K8
N1
N9
R1
R9
+1.5V_GPU
VMA_ZQ4
B1
B9
D1
D8
E2
E8
F9
G1
G9
L8
VREFCA
VREFDQ
BA0
BA1
BA2
CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU
RESET
ZQ
R6
MP@240/F_4
J1
L1
J9
L9
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15
NC#J1
NC#L1
NC#J9
NC#L9
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
VMA_DQ40
VMA_DQ44
VMA_DQ45
VMA_DQ42
VMA_DQ46
VMA_DQ41
VMA_DQ47
VMA_DQ43
D7
C3
C8
C2
A7
A2
B8
A3
VMA_DQ32
VMA_DQ36
VMA_DQ33
VMA_DQ39
VMA_DQ35
VMA_DQ37
VMA_DQ34
VMA_DQ38
5
D
+1.5V_GPU
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
+1.5V_GPU
A1
A8
C1
C9
D2
E9
F1
H2
H9
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9
100-BALL
SDRAM DDR3
MP@VRAM _DDR3
100-BALL
SDRAM DDR3
MP@VRAM _DDR3
BOT Right
TOP Right
Group-A1 VREF
+1.5V_GPU
+1.5V_GPU
+1.5V_GPU
+1.5V_GPU
+1.5V_GPU
+1.5V_GPU
+1.5V_GPU
+1.5V_GPU
R352
MP@4.99K/F_4
R336
MP@4.99K/F_4
VREFC_VMA1
R351
C545
MP@0.1u/10V_4_X7R
MP@4.99K/F_4
R337
MP@4.99K/F_4
VREFD_VMA1
R340
R8
MP@4.99K/F_4
VREFC_VMA2
C533
MP@0.1u/10V_4_X7R
MP@4.99K/F_4
R341
C534
MP@0.1u/10V_4_X7R
MP@4.99K/F_4
R338
MP@4.99K/F_4
VREFD_VMA2
VREFC_VMA3
R7
C26
MP@0.1u/10V_4_X7R
MP@4.99K/F_4
Group-A0 decoupling CAP
MEM_A0 CLK
R348
MP@4.99K/F_4
R342
C535
MP@0.1u/10V_4_X7R
MP@4.99K/F_4
R4
MP@4.99K/F_4
VREFD_VMA3
R350
C544
MP@0.1u/10V_4_X7R
MP@4.99K/F_4
Group-A1 decoupling CAP
R339
MP@4.99K/F_4
VREFC_VMA4
VREFD_VMA4
R5
C23
MP@0.1u/10V_4_X7R
MP@4.99K/F_4
R343
C536
MP@0.1u/10V_4_X7R
MP@4.99K/F_4
MEM_A1 CLK
+1.5V_GPU
+1.5V_GPU
VMA_CLK1
VMA_CLK0
VMA_CLK1#
VMA_CLK0#
C532
C13
R2
R1
MP@56.2/F_4
MP@1u/6.3V_4
C530
C19
C15
C526
C24
C25
C22
MP@1u/6.3V_4
MP@1u/6.3V_4
MP@1u/6.3V_4
MP@1u/6.3V_4
MP@1u/6.3V_4
MP@1u/6.3V_4
MP@1u/6.3V_4
MP@1u/6.3V_4
C27
C528
C523
C11
C28
C10
C529
MP@1u/6.3V_4
MP@1u/6.3V_4
MP@1u/6.3V_4
MP@1u/6.3V_4
MP@1u/6.3V_4
MP@1u/6.3V_4
MP@1u/6.3V_4
R345
R346
MP@56.2/F_4
MP@56.2/F_4
MP@56.2/F_4
+1.5V_GPU
+1.5V_GPU
C2
MP@0.01u/25V_4
A
C519
MP@0.01u/25V_4
C518
C546
C16
C531
C527
C17
C542
C517
MP@1u/6.3V_4
MP@1u/6.3V_4
MP@1u/6.3V_4
MP@1u/6.3V_4
MP@1u/6.3V_4
MP@1u/6.3V_4
MP@1u/6.3V_4
MP@1u/6.3V_4
C12
C9
C6
C524
C21
C525
C8
C7
MP@1u/6.3V_4
MP@1u/6.3V_4
MP@1u/6.3V_4
MP@1u/6.3V_4
MP@1u/6.3V_4
MP@1u/6.3V_4
MP@1u/6.3V_4
MP@1u/6.3V_4
+1.5V_GPU
+1.5V_GPU
C540
C20
MP@10u/6.3V_6
C3
C18
C520
C547
MP@10u/6.3V_6
MP@10u/6.3V_6
MP@10u/6.3V_6
MP@10u/6.3V_6
MP@10u/6.3V_6
C539
C522
C5
C521
MP@10u/6.3V_6
MP@10u/6.3V_6
MP@10u/6.3V_6
MP@10u/6.3V_6

PROJECT : ZR7B
Size
Document Number
Date:
Rev
1A
MEMORY 1 channel A
5
Sheet
1
19
of
50
CHANNEL B: 512MB DDR3 (64M*16*4pcs)
VMB_DQ[63..0]
<18> VMB_DQ[63..0]
VMB_DM[7..0]
<18> VMB_DM[7..0]
<18> VMB_RDQS[7..0]
<18> VMB_WDQS[7..0]
VMB_RDQS[7..0]
QSA[7..0]
VMB_WDQS[7..0]
QSA#[7..0]
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
VMB_MA0
VMB_MA1
VMB_MA2
VMB_MA3
VMB_MA4
VMB_MA5
VMB_MA6
VMB_MA7
VMB_MA8
VMB_MA9
VMB_MA10
VMB_MA11
VMB_MA12
VMB_MA13
<18>
<18>
<18>
VMB_BA0
VMB_BA1
VMB_BA2
<18> VMB_CLK0
<18> VMB_CLK0#
<18> VMB_CKE0
<18>
<18>
<18>
<18>
<18>
VMB_ODT0
VMB_CS0#
VMB_RAS0#
VMB_CAS0#
VMB_WE0#
U3
VREFC_VMB1
VREFD_VMB1
M8
H1
VMB_MA0
VMB_MA1
VMB_MA2
VMB_MA3
VMB_MA4
VMB_MA5
VMB_MA6
VMB_MA7
VMB_MA8
VMB_MA9
VMB_MA10
VMB_MA11
VMB_MA12
VMB_MA13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
VMB_BA0
VMB_BA1
VMB_BA2
M2
N8
M3
VMB_CLK0
VMB_CLK0#
VMB_CKE0
J7
K7
K9
VMB_ODT0
VMB_CS0#
VMB_RAS0#
VMB_CAS0#
VMB_WE0#
K1
L2
J3
K3
L3
VMB_RDQS0
VMB_RDQS3
F3
C7
VMB_DM0
VMB_DM3
E7
D3
VMB_WDQS0
VMB_WDQS3
G3
B7
MEM_RST#
T2
<18,19> MEM_RST#
VMB_ZQ1
L8
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15
BA0
BA1
BA2
CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU
RESET
ZQ
R26
SW@240/F_4
J1
L1
J9
L9
U23
VREFCA
VREFDQ
NC#J1
NC#L1
NC#J9
NC#L9
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
VMB_DQ6
VMB_DQ3
VMB_DQ5
VMB_DQ1
VMB_DQ7
VMB_DQ0
VMB_DQ4
VMB_DQ2
D7
C3
C8
C2
A7
A2
B8
A3
VMB_DQ24
VMB_DQ31
VMB_DQ28
VMB_DQ30
VMB_DQ26
VMB_DQ27
VMB_DQ25
VMB_DQ29
0
3
VREFC_VMB2
VREFD_VMB2
M8
H1
VMB_MA0
VMB_MA1
VMB_MA2
VMB_MA3
VMB_MA4
VMB_MA5
VMB_MA6
VMB_MA7
VMB_MA8
VMB_MA9
VMB_MA10
VMB_MA11
VMB_MA12
VMB_MA13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9
B2
D9
G7
K2
K8
N1
N9
R1
R9
VMB_BA0
VMB_BA1
VMB_BA2
M2
N8
M3
VMB_CLK0
VMB_CLK0#
VMB_CKE0
J7
K7
K9
VMB_ODT0
VMB_CS0#
VMB_RAS0#
VMB_CAS0#
VMB_WE0#
K1
L2
J3
K3
L3
VMB_RDQS2
VMB_RDQS1
F3
C7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VMB_DM2
VMB_DM1
E7
D3
VMB_WDQS2
VMB_WDQS1
G3
B7
MEM_RST#
T2
VMB_ZQ2
B1
B9
D1
D8
E2
E8
F9
G1
G9
ODT
CS
RAS
CAS
WE
DQSL
DQSU
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
DML
DMU
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
DQSL
DQSU
RESET
L8
ZQ
J1
L1
J9
L9
NC#J1
NC#L1
NC#J9
NC#L9
E3
F7
F2
F8
H3
H8
G2
H7
VMB_DQ17
VMB_DQ23
VMB_DQ18
VMB_DQ16
VMB_DQ20
VMB_DQ22
VMB_DQ19
VMB_DQ21
D7
C3
C8
C2
A7
A2
B8
A3
VMB_DQ15
VMB_DQ10
VMB_DQ14
VMB_DQ11
VMB_DQ12
VMB_DQ9
VMB_DQ13
VMB_DQ8
2
1
VREFC_VMB3
VREFD_VMB3
M8
H1
VMB_MA0
VMB_MA1
VMB_MA2
VMB_MA3
VMB_MA4
VMB_MA5
VMB_MA6
VMB_MA7
VMB_MA8
VMB_MA9
VMB_MA10
VMB_MA11
VMB_MA12
VMB_MA13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
VMB_BA0
VMB_BA1
VMB_BA2
M2
N8
M3
VMB_CLK1
VMB_CLK1#
VMB_CKE1
J7
K7
K9
+1.5V_GPU
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
CK
CK
CKE
R360
SW@240/F_4
100-BALL
SDRAM DDR3
SW@VRAM _DDR3
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
BA0
BA1
BA2
+1.5V_GPU
A1
A8
C1
C9
D2
E9
F1
H2
H9
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15
+1.5V_GPU
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
U26
VREFCA
VREFDQ
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9
B2
D9
G7
K2
K8
N1
N9
R1
R9
<18> VMB_CLK1
<18> VMB_CLK1#
<18> VMB_CKE1
+1.5V_GPU
A1
A8
C1
C9
D2
E9
F1
H2
H9
<18>
<18>
<18>
<18>
<18>
VMB_ODT1
VMB_CS1#
VMB_RAS1#
VMB_CAS1#
VMB_WE1#
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VMB_ODT1
VMB_CS1#
VMB_RAS1#
VMB_CAS1#
VMB_WE1#
K1
L2
J3
K3
L3
VMB_RDQS4
VMB_RDQS7
F3
C7
VMB_DM4
VMB_DM7
E7
D3
VMB_WDQS4
VMB_WDQS7
G3
B7
MEM_RST#
T2
VMB_ZQ3
B1
B9
D1
D8
E2
E8
F9
G1
G9
J1
L1
J9
L9
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15
BA0
BA1
BA2
CK
CK
CKE
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU
RESET
ZQ
R384
SW@240/F_4
100-BALL
SDRAM DDR3
SW@VRAM _DDR3
BOT Down
L8
U5
VREFCA
VREFDQ
NC#J1
NC#L1
NC#J9
NC#L9
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
VMB_DQ36
VMB_DQ39
VMB_DQ33
VMB_DQ34
VMB_DQ37
VMB_DQ32
VMB_DQ38
VMB_DQ35
VREFC_VMB4
VREFD_VMB4
M8
H1
VMB_MA0
VMB_MA1
VMB_MA2
VMB_MA3
VMB_MA4
VMB_MA5
VMB_MA6
VMB_MA7
VMB_MA8
VMB_MA9
VMB_MA10
VMB_MA11
VMB_MA12
VMB_MA13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
D7
C3
C8
C2
A7
A2
B8
A3
VMB_DQ62
VMB_DQ56
VMB_DQ63
VMB_DQ58
VMB_DQ61
VMB_DQ57
VMB_DQ60
VMB_DQ59
VMB_BA0
VMB_BA1
VMB_BA2
M2
N8
M3
VMB_CLK1
VMB_CLK1#
VMB_CKE1
J7
K7
K9
A1
A8
C1
C9
D2
E9
F1
H2
H9
VMB_ODT1
VMB_CS1#
VMB_RAS1#
VMB_CAS1#
VMB_WE1#
K1
L2
J3
K3
L3
VMB_RDQS6
VMB_RDQS5
F3
C7
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VMB_DM6
VMB_DM5
E7
D3
VMB_WDQS6
VMB_WDQS5
G3
B7
MEM_RST#
T2
4
7
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9
B2
D9
G7
K2
K8
N1
N9
R1
R9
BA0
BA1
BA2
CK
CK
CKE
+1.5V_GPU
VMB_ZQ4
B1
B9
D1
D8
E2
E8
F9
G1
G9
ODT
CS
RAS
CAS
WE
DQSL
DQSU
DML
DMU
DQSL
DQSU
RESET
L8
ZQ
R59
SW@240/F_4
J1
L1
J9
L9
NC#J1
NC#L1
NC#J9
NC#L9
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
E3
F7
F2
F8
H3
H8
G2
H7
VMB_DQ54
VMB_DQ51
VMB_DQ53
VMB_DQ50
VMB_DQ52
VMB_DQ48
VMB_DQ55
VMB_DQ49
D7
C3
C8
C2
A7
A2
B8
A3
VMB_DQ41
VMB_DQ46
VMB_DQ40
VMB_DQ42
VMB_DQ44
VMB_DQ45
VMB_DQ43
VMB_DQ47
6
D
+1.5V_GPU
B2
D9
G7
K2
K8
N1
N9
R1
R9
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
+1.5V_GPU
A1
A8
C1
C9
D2
E9
F1
H2
H9
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9
100-BALL
SDRAM DDR3
SW@VRAM _DDR3
TOP Up
Group-B0 VREF
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15
+1.5V_GPU
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
100-BALL
SDRAM DDR3
SW@VRAM _DDR3
TOP Down
VREFCA
VREFDQ
BOT Up
Group-B1 VREF
+1.5V_GPU
+1.5V_GPU
R355
SW@4.99K/F_4
R16
SW@4.99K/F_4
VREFC_VMB1
R24
+1.5V_GPU
R367
SW@4.99K/F_4
VREFD_VMB1
C65
SW@0.1u/10V_4_X7R
SW@4.99K/F_4
+1.5V_GPU
R357
SW@4.99K/F_4
VREFC_VMB2
R19
C51
SW@0.1u/10V_4_X7R
SW@4.99K/F_4
R365
C569
SW@0.1u/10V_4_X7R
SW@4.99K/F_4
+1.5V_GPU
R390
SW@4.99K/F_4
VREFD_VMB2
R356
C559
SW@0.1u/10V_4_X7R
SW@4.99K/F_4
R389
C594
SW@0.1u/10V_4_X7R
SW@4.99K/F_4
+1.5V_GPU
R392
SW@4.99K/F_4
VREFC_VMB3
Group-B0 decoupling CAP
MEM_B0 CLK
+1.5V_GPU
R45
SW@4.99K/F_4
VREFD_VMB3
R391
C589
SW@0.1u/10V_4_X7R
SW@4.99K/F_4
+1.5V_GPU
R64
SW@4.99K/F_4
VREFC_VMB4
VREFD_VMB4
R53
C183
SW@0.1u/10V_4_X7R
SW@4.99K/F_4
Group-B1 decoupling CAP
+1.5V_GPU
R63
C190
SW@0.1u/10V_4_X7R
SW@4.99K/F_4
MEM_B1 CLK
+1.5V_GPU
VMB_CLK1
VMB_CLK0
VMB_CLK1#
C86
C614
C553
C564
C554
C45
C154
C552
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
VMB_CLK0#
R18
R17
SW@56.2/F_4
C192
C217
C224
C181
C583
C193
C201
C585
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
R71
R76
SW@56.2/F_4
SW@56.2/F_4
+1.5V_GPU
+1.5V_GPU
SW@56.2/F_4
C203
SW@0.01u/25V_4
C600
C556
SW@0.01u/25V_4
C165
C40
C47
C602
C566
C42
C142
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
+1.5V_GPU
C69
SW@10u/6.3V_6
C571
C604
C14
C209
C186
C575
C581
C601
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
+1.5V_GPU
C33
C570
C613
C557
SW@10u/6.3V_6
SW@10u/6.3V_6
SW@10u/6.3V_6
SW@10u/6.3V_6
C252
SW@10u/6.3V_6
C168
C579
C4
C577
SW@10u/6.3V_6
SW@10u/6.3V_6
SW@10u/6.3V_6
SW@10u/6.3V_6
PROJECT : ZR7B
Size
Document Number
Date:
Rev
1A
MEMORY 2 channel B
5
Sheet
1
20
of
50
U24F
U24E
For DDR3, MVDDQ = 1.5V (7.5A)
MEM I/O
+1.5V_GPU
+1.8V_GPU
PCIE
C77
C49
C551
C90
C555
SW@10u/6.3V_6
SW@10u/6.3V_6
SW@10u/6.3V_6
SW@10u/6.3V_6
SW@10u/6.3V_6
C155
C89
C54
C126
C122
C55
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
C187
C172
C64
C100
C59
C175
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
C157
C76
C53
C52
C194
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@1u/6.3V_4
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
VDDC_CT
C180
C178
C169
SW@1u/6.3V_4
SW@10u/6.3V_6
SW@0.1u/10V_4_X7R
AF26
AF27
AG26
AG27
+3V_D
C255
C179
C170
C173
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@10u/6.3V_6
SW@1u/6.3V_4
+1.8V_GPU
PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12
VDDR4
AF23
AF24
AG23
AG24
AF13
AF15
AG13
AG15
C230
C231
AD12
SW@0.1u/10V_4_X7R AF11
SW@1u/6.3V_4
AF12
AG11
T2
T1
M20
M21
T5
T4
V12
U12
VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4
VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4
VDDR4#4
VDDR4#5
VDDR4#7
VDDR4#8
VDDR4#1
VDDR4#2
VDDR4#3
VDDR4#6
NC_VDDRHA
NC_VSSRHA
NC_VDDRHB
NC_VSSRHB
(For M97, Broadway, Madison and Park SPV10 = 1.0V)

+1.8V_GPU
PLL
(1.8V@40mA PCIE_PVDD)
L40
PCIE_PVDD
MPV18
C572
C573
C574
SW@1u/6.3V_4
SW@10u/6.3V_6
SW@0.1u/10V_4_X7R
(1.8V@75mA/Park & 150mA/Madison MPV18)
L1
AM10
SPV10
H7
H8
AN9
AN10
C46
C50
C66
SW@1u/6.3V_4
SW@10u/6.3V_6
SW@0.1u/10V_4_X7R
+1.8V_GPU
PCIE_PVDD
MPV18#1
MPV18#2
SPVSS
C206
SW@0.1u/10V_4_X7R
SW@10u/6.3V_6
(1.0V@120mA SPV10)
L7
L4
180 ohm/1.5A
SW@HCB1608KF-181T15/180ohm/1.5A_6
AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39
C125
C145
C129
C143
C177
C144
C124
C185
SW@0.1u/10V_4_X7R
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@10u/6.3V_6
SW@0.1u/10V_4_X7R
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
+1V
(1.0V@1.1A PCIE_VDDC)
C71
C68
C74
C98
C87
C80
C108
C57
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@10u/6.3V_6
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
AH27
AH28
M26
N24
N27
R18
R21
R23
R26
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28
+VGPU_CORE
C109
C127
C91
C140
C104
C149
C151
C93
C117
C111
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
T9
AF28
T10
AG28
T12
AH29
FB_VDDC
FB_VDDCI
FB_GND
C215
C205
SW@0.1u/10V_4_X7R
SW@10u/6.3V_6
AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13
C150
C158
C120
C105
C75
C118
C94
C112
C103
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
U13
V13
C159
C92
C160
C110
C138
C102
C141
C119
C171
C152
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
C156
C130
C88
C114
C135
C133
SW@10u/6.3V_6
SW@10u/6.3V_6
SW@10u/6.3V_6
SW@10u/6.3V_6
SW@10u/6.3V_6
SW@10u/6.3V_6
BIF_VDDC should be connected to VDDC if BACO feature not used.

For BACO, refer to the databook
+VGPU_CORE
R28
SW@0_4
C95
C115
SW@1u/6.3V_4
SW@1u/6.3V_4
+VGPU_CORE
+VGPU_IO
VDDCI and VDDC should have seperate regulators with a merge option on PCB
For Madison and Park, VDDCI and VDDC can share one common regulator
C72
C147
C161
C106
C101
C162
C146
C81
C78
C79
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
SW@1u/6.3V_4
PIN different between Broadway and Madison

C70
C134
C82
SW@10u/6.3V_6
SW@10u/6.3V_6
SW@10u/6.3V_6
Pin
Broadway
Madison
N27
T27
VDDC
BIF_VDDC
AL31
TS_A
NC_TS_A
AL21
GND
PX_EN
VDDC_SENSE/VSS_SENSE and VDDCI_SENSE/VSS_SENSE route as differetial pair

+3V
+3V
+3V
+3V
GPU all PWROK

1
GPU +3V power
+3V_S5
R109
SW@10K_4
R110
*SW@0_6
dGPU_VRON_N2
*SW@0_4
C254
R101
SW@1u/6.3V_4
R78
*10K_4
R75
*SW@0_4
A39
AW1
AW39
dGPU_PWROK <11>
Q10
SW@2N7002E
0.5A
+3V_D
C615
C620
+3V_D_S
C621
C943
*SHORT0402
SW@1u/6.3V_4
SW@10u/6.3V_6
SW@0.1u/10V_4_X7R
C944
C945
SW@10u/6.3V_6
SW@.1u/10V_4
SW@1u/10V_4
+1.8V_GPU
PROJECT : ZR7B
Q8
SW@PDTC143TT
Size
Document Number
Rev
1A
Madison/Broadway (PWR/GND)
Date:
+3V_D
<11,44> dGPU_VRON
PowerXpress control signal for Madsion and Park only

If not used, can be disconnected.
PX_EN = LOW, turn on
PX_EN = HIGH, turn off
PX_EN is used to turn ON/OFF some
regulators for PowerXpress mode. An
output high 3.3V will turn the regulators
OFF. An output low 0V will turn the
regulators ON. PX_EN outputs low (0V)
by default.
If this signal is unused, it can be NC (not
connected) or connected to ground.
R768
*SW@0_6
SW@AO3413
Q5
SW@PDTC143TT
R100
VSS_MECH#1
VSS_MECH#2
VSS_MECH#3
A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
AG22
AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AL21
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
AW34
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13
+1.5V_GPU
Q55
0.5A
SW@AO3413
Q7
GND
GND#100
GND#101
GND#102
GND#103
GND#104
GND#105
GND#106
GND#107
GND#108
GND#109
GND#110
GND#111
GND#112
GND#113
GND#114
GND#115
GND#116
GND#117
GND#118
GND#119
GND#120
GND#121
GND#122
GND#123
GND#124
GND#125
GND#126
GND#127
GND#128
GND#129
GND#130
GND#131
GND#132
GND#133
GND#134
GND#135
GND#136
GND#137
GND#138
GND#139
GND#140
GND#141
GND#142
GND#143
GND#144
GND#145
GND#146
GND#147
GND#148
GND#149
GND#150
GND#151
GND#153
GND#154
GND#155
GND#156
GND#157
GND#158
GND#159
GND#160
GND#161
GND#163
GND#164
GND#165
GND#166
GND#167
GND#168
GND#169
GND#170
GND#171
GND#172
GND#173
GND#174
GND#175
GND#152
GND#162
GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
GND#8
GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#56
GND#57
GND#58
GND#59
GND#60
GND#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#85
GND#86
GND#87
GND#88
GND#89
GND#90
GND#91
GND#92
GND#93
GND#94
GND#95
GND#96
GND#97
GND#98
GND#99
dGPU_VRON_N
R123
SW@10K_4
R111
SW@4.7K_4
PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31
PCIE_VSS#32
PCIE_VSS#33
PCIE_VSS#34
PCIE_VSS#35
C139
(DDR3 1.12V@4A VDDCI) or more

VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8
VDDCI#9
VDDCI#10
VDDCI#11
VDDCI#12
VDDCI#13
VDDCI#14
ISOLATED VDDCI#15
CORE I/O VDDCI#16
VDDCI#17
VDDCI#18
VDDCI#19
VDDCI#20
VDDCI#21
VDDCI#22
SPV10
C214
+1V
VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDC#26
VDDC#27
VDDC#28
VDDC#29
VDDC#30
VDDC#31
VDDC#32
VDDC#33
VDDC#34
VDDC#35
VDDC#36
VDDC#37
VDDC#38
VDDC#39
VDDC#40
VDDC#41
VDDC#42
VDDC#43
VDDC#44
VDDC#45
VDDC#46
VDDC#47
VDDC#48
VDDC#49
VDDC#50
VDDC#51
VDDC#52
VDDC#53
VDDC#54
VDDC#55
VDDC#56
VDDC#57
VDDC#58
SPV18
VOLTAGE
SENESE
(1.8V@75mA SPV18)
L12
G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28
(1.8V@400mA PCIE_VDDR)
PCIE_VDDR
+VGPU_IO
SPV18
+1.8V_GPU
AB37
AA31
AA32
AA33
AA34
V28
W29
W30
Y31
(30A or more)
CORE
I/O
(3.3V@60mA))
L11
PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8
LEVEL
TRANSLATION
(1.8V@110mA VDD_CT)
L2
VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17
VDDR1#18
VDDR1#19
VDDR1#20
VDDR1#21
VDDR1#22
VDDR1#23
VDDR1#24
VDDR1#25
VDDR1#26
VDDR1#27
VDDR1#28
VDDR1#29
VDDR1#30
VDDR1#31
VDDR1#32
VDDR1#33
VDDR1#34
POWER
+1.8V_GPU
AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7

1
Sheet
21
of
50
+1.8V_GPU
+1V
U24H
(1.8V@130mA DPA_VDD18)
L10
DPA_VDD10
DPA_VDD18
DP C/D POWER
AP20
AP21
DPC_VDD18#1
DPC_VDD18#2
DPA_VDD18#1
DPA_VDD18#2
AN24
AP24
DPA_VDD18
DPA_VDD10
AP13
AT13
DPC_VDD10#1
DPC_VDD10#2
DPA_VDD10#1
DPA_VDD10#2
AP31
AP32
DPA_VDD10
AN17
AP16
AP17
AW14
AW16
DPC_VSSR#1
DPC_VSSR#2
DPC_VSSR#3
DPC_VSSR#4
DPC_VSSR#5
DPA_VSSR#1
DPA_VSSR#2
DPA_VSSR#3
DPA_VSSR#4
DPA_VSSR#5
AN27
AP27
AP28
AW24
AW26
DPA_VDD18
AP22
AP23
DPD_VDD18#1
DPD_VDD18#2
DPB_VDD18#1
DPB_VDD18#2
AP25
AP26
DPA_VDD18
DPA_VDD10
AP14
AP15
DPD_VDD10#1
DPD_VDD10#2
DPB_VDD10#1
DPB_VDD10#2
AN33
AP33
DPA_VDD10
AN19
AP18
AP19
AW20
AW22
DPD_VSSR#1
DPD_VSSR#2
DPD_VSSR#3
DPD_VSSR#4
DPD_VSSR#5
DPB_VSSR#1
DPB_VSSR#2
DPB_VSSR#3
DPB_VSSR#4
DPB_VSSR#5
AN29
AP29
AP30
AW30
AW32
AW18
DPCD_CALR
DPAB_CALR
AW28
C220
C212
SW@1u/6.3V_4
SW@10u/6.3V_6
SW@0.1u/10V_4_X7R
C216
C197
C213
SW@1u/6.3V_4
SW@10u/6.3V_6
SW@0.1u/10V_4_X7R
SW@150/F_4
DPCD_CALR
DPAB_CALR
R408
SW@150/F_4
L3
DPE_VDD18
AH34
AJ34
DPE_VDD10
AL33
AM33
(1.8V@400mA DPE/F_VDD18)
DPE_VDD10#1
DPE_VDD10#2
DP PLL POWER
DPA_PVDD
DPA_PVSS
AU28
AV27
DPB_PVDD
DPB_PVSS
AV29
AR28
DPC_PVDD
DPC_PVSS
AU18
AV17
DPE_VSSR#1
DPE_VSSR#2
DPE_VSSR#3
DPE_VSSR#4
DPE_VSSR#5
(1.8V@20mA DPB_PVDD) L16
C237
C238
SW@1u/6.3V_4
SW@10u/6.3V_6
SW@0.1u/10V_4_X7R
DPB_PVDD
+1.8V_GPU
C236
C235
SW@1u/6.3V_4
SW@10u/6.3V_6
SW@0.1u/10V_4_X7R
AF34
AG34
DPE_VDD18
(1.0V@400mA DPE/F_VDD10)
DPF_VDD18#1
DPF_VDD18#2
SW@BLM15AG121SS1/0.5A/120ohm_4 DPE_VDD10
AK33
AK34
DPE_VDD10
C226
C221
C210
SW@1u/6.3V_4
SW@0.1u/10V_4_X7R
SW@10u/6.3V_6
DPF_VSSR#1
DPF_VSSR#2
DPF_VSSR#3
DPF_VSSR#4
DPF_VSSR#5
AM39
DPEF_CALR
L14
L18
L43
C246
C234
C240
SW@1u/6.3V_4
SW@10u/6.3V_6
SW@0.1u/10V_4_X7R
AV19
AR18
+1.8V_GPU
DPD_PVDD
DPE_PVDD
DPE_PVSS
AM37
AN38
NC_DPF_PVDD
NC_DPF_PVSS
AL38
AM35
DPF_VDD10#1
DPF_VDD10#2
AF39
AH39
AK39
AL34
AM34
+1.8V_GPU
DPC_PVDD
(1.8V@20mA DPC_PVDD)
DPD_PVDD
DPD_PVSS
L9
C243
AN34
AP39
AR39
AU37
AW35
C182
C184
SW@1u/6.3V_4
SW@0.1u/10V_4_X7R
SW@10u/6.3V_6
+1V
L17
C244
SW@BLM15AG121SS1/0.5A/120ohm_4DPE_VDD18
C167
DP E/F POWER
DPE_VDD18#1
DPE_VDD18#2
+1.8V_GPU
(1.8V@20mA DPA_PVDD)
DPA_PVDD
+1.8V_GPU
R104
L8
DP A/B POWER
DPA_VDD18
C222
(1.0V@110mA DPA_VDD10)
(1.8V@20mA DPD_PVDD)
C245
C233
C239
SW@1u/6.3V_4
SW@10u/6.3V_6
SW@0.1u/10V_4_X7R
+1.8V_GPU
(1.8V@40mA DPE/F_PVDD)
DPE_PVDD
C595
R70
SW@150/F_4
DPEF_CALR
C599
C598
SW@1u/6.3V_4
SW@10u/6.3V_6
SW@0.1u/10V_4_X7R

PROJECT : ZR7B
Size
Document Number
Rev
1A
Madison/Broadway (DP_PWR/GND)
Date:
5
Sheet
1
22
of
50
PIN STRAPS
CONFIGURATION STRAPS
<17> GPU_GPIO0
<17> GPU_GPIO1
R57
*SW@10K/F_4
R52
*SW@10K/F_4
000
<17> GPIO3_SMBDAT
<17> GPIO4_SMBCLK
*SW@10K/F_4
R48
*SW@10K/F_4
SCS#_GPIO22 R418
<17> GPU_GPIO13
<17> GPU_GPIO12
<17> GPU_GPIO11
<17,24> EV_HSYNC
<17,24> EV_VSYNC
SIN_GPIO9
V2SYNC
PIN
DESCRIPTION OF DEFAULT SETTINGS
TX_PWRS_ENB
GPIO0
0 = 50% TX OUTPUT SWING

1 = FULL TX OUTPUT SWING
TX_DEEMPH_EN
GPIO1
PCIE TRANSMITTER DE-EMPHASIS ENABLED

0 = TX DE-EMPHASIS DISABLED
1 = TX DE-EMPHASIS ENABLED
ENABLE EXTERNAL BIOS ROM
0 = DISABLE
1 = ENABLE
128MB
001
256MB
010
64MB
BIOS_ROM_EN
011
32MB
ROMIDCFG(2:0)
GPIO[13:11]
BIF_GEN2_EN_A
GPIO2
GPIO_8_ROMSO
H2SYNC
GPIO_21_BB_EN
GPIO8
H2SYNC
GPIO21
GPIO_22_ROMCSB
REMARK
DEFAULT
*SW@10K/F_4
R81
*SW@10K/F_4
R69
*SW@10K/F_4
R79
*SW@10K/F_4
R82
<17> GPU_GPIO2
STRAPS
GPIO[13:11] Size
R51
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
THEY MUST NOT CONFLICT DURING RESET
Memory Aperture size
+3V_D
<17>
*SW@10K/F_4
R42
SW@10K/F_4
R43
SW@10K/F_4
R96
*SW@10K/F_4
R38
*SW@10K/F_4
ROM Table
EXT_HSYNC
EXT_VSYNC
0
0
1
1
Discription
AUD[1]
HSYNC
AUD[0]
VSYNC
SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT

NUMONYX M25P10A : 101
0 = PCIE DEVICE AS 2.5GT/S CAPABLE
1 = PCIE DEVICE AS 5GT/S CAPABLE
Reserved Only
AUD[1:0]
00: NO AUDIO FUNCTION.
01: AUDIO FOR DISPLAYPORT AND HDMI IF
ADAPTER IS DETECTED.
10: AUDIO FOR DISPLAYPORT ONLY.
No Audio
0
1
0
1
000
See Memory Aperture size
See Audio table
11
11: AUDIO FOR BOTH DISPLAYPORT AND HDMI.
Any one by dectec

GPIO_9_ROMSI
0 = VGA controller capacity enable
GPIO9
DP only
VIP_DEVICE_STRAP_ENA
V2SYNC
0 = DRIVER would ignore the value sample on VHAD_0 during RESET.
Both DP & HDMI
DDR3 Memory Aperture size
EEPROM
U29
SIN_GPIO9
<17> SIN_GPIO9
5
6
<17> SCLK_GPIO10
SCS#_GPIO22
<17> SCS#_GPIO22
1
7
+3V_D_S
R424
*SW@10K_4
3
8
R428
*SW@10K_4C619
SOUT_GPIO8
DDR3 Memory Aperture size
SOUT_GPIO8 <17>
C
S
Vendor
Vendor P/N
STN B/S P/N
Size
HOLD
W
VCC
VSS
*SW@M25P10-AVMN6P
Hynix
H5TQ1G63BFR-12C
*SW@0.1u/10V_4
AKD5LZGTW04
(64M*16)
RAM_STRAP2
RAM_STRAP1
RAM_STRAP0
DVPDATA_2
DVPDATA_1
DVPDATA_0
512MB
1GB
2GB
Thermal Sensor
NS
512MB
none
WINDBOND
AL83L771K02
GMT
AL000780003
K4W1G1646E-HC12
AKD5LGGT506
(64M*16)
1GB
K4W2G1646B-HC12
AKD5MGGT500
2GB
23EY2387MA12-SZ
AKD5LGGT700
1GB
0
0
0
1
1
0
Samsung
AMD
+3V_D_S
+3V_D_S
R430
SW@10K_4
R423
SW@10K_4
C623
+1.8V_GPU
SW@0.1u/10V_4_X7R
<17> RAM_STRAP2
U31
A
<37> MXM_SMCLK12
<37> MXM_SMDATA12
7
<17> ALT#_GPIO17
<37> VGA_THERM#
SCLK
VCC
SDA
DXP
ALERT#
DXN
OVERT#
GND
GPU_D+
C617
SW@2200p/50V_4
*VRAM@10K/F_4
VRAM@10K/F_4
R427
*VRAM@10K/F_4
R426
VRAM@10K/F_4
R416
*VRAM@10K/F_4
R415
VRAM@10K/F_4
<17>
<17> RAM_STRAP1
GPU_D-
R422
R421
RAM_STRAP2 SET DDR3 Vendor

RAM_STRAP[1:0] SET SIZE.
<17>
SW@G780-1P81U(MSOP)
<17> RAM_STRAP0
ADDRESS: 9AH

PROJECT : ZR7B
Size
Document Number
Rev
1A
Strip/Thermal
Date:
5
Sheet

1
23
of
50
CRT Switch
CRT
updatefootprint 12/11
+5V
C257
3.3V or 5V level?
C277
16
VCC
2
5
11
14
<17> EV_CRT_BLU
<17> EV_CRT_GRN
<17> EV_CRT_RED
A
IA0
IB0
IC0
ID0
3
6
10
13
YA
YB
IA1
IB1
IC1
ID1
YC
OE
VGA_BLU
VGA_GRN
VGA_RED
<17> EV_CRTDCLK
<17> EV_CRTDDAT
<17> EV_LVDS_DDCDAT
<17> EV_LVDS_DDCCLK
<8> INT_CRT_DDCCLK
<8> INT_CRT_DDCDAT
<8> INT_LVDS_EDIDDATA
<8> INT_LVDS_EDIDCLK
12
YD
16
EV_CRTDCLK
EV_CRTDDAT
EV_LVDS_DDCDAT
EV_LVDS_DDCCLK
2
5
11
14
INT_CRT_DDCCLK
INT_CRT_DDCDAT
INT_LVDS_EDIDDATA
INT_LVDS_EDIDCLK
3
6
10
13
D10
SSM22LLPT
CRTVDD5
SMD1206P110TFT
VCC
GND
IA0
IB0
IC0
ID0
YA
YB
IA1
IB1
IC1
ID1
YC
OE
YD
CRTDCLK
CRTDDATA
LCD_EDIDDATA
VGA_RED
L22
BLM18BA750SN1D/0.3A/75ohm_6
CRT_R1
VGA_GRN
L21
CRT_G1
L20
VGA_BLU
12 LCD_EDIDCLK
CN13
CRT
6
1
7
2
8
3
9
4
10
5
CRT_B1
R134
R132
R115
C279
C275
C263
C270
C271
C276
150/F_4
150/F_4
150/F_4
10p/50V_4
10p/50V_4
10p/50V_4
10p/50V_4
10p/50V_4
10p/50V_4
11
CRT_11
12
DDCDAT_1
13
CRTHSYNC
14
CRTVSYNC
15
DDCCLK_1
T66
17
<8> INT_CRT_BLU
<8> INT_CRT_GRN
<8> INT_CRT_RED
GND
U8
SW@0.22u/6.3V_4
+5V
C250
U9
SW@0.22u/6.3V_4
0.1u/10V_4_X7R
F1
16
+5V
IV@
SW@
dGPU_SELECT#
15
<10> dGPU_EDIDSEL#
SW@SN74CBT3257CPWR
Yn
EV
IV
C278
U10
SW@0.22u/6.3V_4
16
<17> EV_LVDS_BLON
<17> EV_LVDS_VDDEN
<17,23> EV_HSYNC
<17,23> EV_VSYNC
2
5
11
14
<8> INT_LVDS_BLON
<8> INT_LVDS_DIGON
<8> INT_HSYNC
<8> INT_VSYNC
3
6
10
13
dGPU_SELECT#
VCC
IA0
IB0
IC0
ID0
IA1
IB1
IC1
ID1
Output
EV_LVDS
INT_LVDS
INT_CRT_RED
INT_CRT_GRN
INT_CRT_BLU
INT_VSYNC
INT_HSYNC
INT_CRT_DDCDAT
INT_CRT_DDCCLK
INT_LVDS_EDIDDATA
INT_LVDS_EDIDCLK
GND
LVDS_BLON
YA
LVDS_VDDEN
YB
YC
R133
R112
R113
R130
R125
R93
R103
R114
R102
IV@0_4
IV@0_4
IV@0_4
IV@0_4
IV@0_4
IV@0_4
IV@0_4
IV@0_4
IV@0_4
VGA_RED
VGA_GRN
VGA_BLU
VSYNC
HSYNC
CRTDDATA
CRTDCLK
LCD_EDIDDATA
LCD_EDIDCLK
+3V
C642
INT_LVDS_DIGON RN5
INT_LVDS_BLON
1
3
U32
CRTVDD5
CRT_BYP
7
8
0.1u/10V_4_X7R
C632
.22u/25V_6
+3V
HSYNC
12 VSYNC
YD
15
SW@SN74CBT3257CPWR
dGPU_SELECT#
+5V
2 IV@0_4P2RLVDS_VDDEN
LVDS_BLON
4
16
14
CRT_VSYNC2
CRT_HSYNC2
R437
R438
VSYNC
HSYNC
15
13
CRTVSYNC
CRTHSYNC
*Short_4
*Short_4
CRTVDD5
+3V
C643
CRT_R1
CRT_G1
CRT_B1
0.1u/10V_4_X7R
15
OE
VCC_SYNC SYNC_OUT2
SYNC_OUT1
VCC_DDC
BYP
SYNC_IN2
VCC_VIDEO
SYNC_IN1
3
4
5
6
SW@SN74CBT3257CPWR
VIDEO_1
VIDEO_2
VIDEO_3
DDC_IN1
DDC_IN2
DDC_OUT1
DDC_OUT2
GND
10
11
CRTDCLK
CRTDDATA
9
12
DDCCLK_1
DDCDAT_1
R432
R433
2.7K_4
2.7K_4
R431
R436
2.7K_4
2.7K_4
C646
*.1u/10V_4
CRTVDD5
C648
*10p/50V_4
CRTVSYNC
C649
*10p/50V_4
CRTHSYNC
C631
10p/50V_4
DDCCLK_1
C647
10p/50V_4
DDCDAT_1
CM2009-02QR
LVDS
LVDS Switch
LCD Power
+3V
VIN
U6
+3V
A0P
A0N
15
16
TXLOUT1+
TXLOUT1-
C116
TXLOUT0+
TXLOUT0-
18
19
CCLKP
CCLKN
<8> INT_TXLOUT2+
<8> INT_TXLOUT2-
33
32
<8> INT_TXLOUT1+
<8> INT_TXLOUT1-
30
29
<8> INT_TXLOUT0+
<8> INT_TXLOUT0-
C248
C202
C229
C225
C253
C251
28
27
+1.8V
SW@1000p/50V_4
SW@1000p/50V_4
SW@0.22u/6.3V_4
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
SW@2.2u/6.3V_6
48
36
25
23
21
12
4
2
B2P
B2N
dGPU_SELECT#
IN_B
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
CN5
+3V
LCDVCC
R95
R94
SW@100K_4
Yn
EV
IV
<37> PANEL_COLOR
SW@TS3DV421DGVR
VIN
dGPU_SELECT#
L
RN1
1
3
1
3
1
3
1
3
RN4
RN3
RN2
2
4
2
4
2
4
2
4
IN
OUT
IN
GND
ON/OFF
GND
IV@0_4P2R TXLCLKOUTTXLCLKOUT+
IV@0_4P2R TXLOUT0TXLOUT0+
Output
<37> PANEL_ENG
R29
R32
0.8A
*SHORT0805
*SHORT0805
EV_LVDS
1
2
3
G_1
4
5
6
7
TXLOUT08
TXLOUT0+
9
10
TXLOUT111
TXLOUT1+
12
13
TXLOUT214
TXLOUT2+
15
G_2
16
TXLCLKOUT17
TXLCLKOUT+
18
19
20
21
22
23
LVDS_BRIGHT
R614
24
BL_ON BLM15AG121SS1/0.5A/120ohm_4
25
26
27
28
G_4
29
INVCC0
30
2.2K_4
2.2K_4
DMIC_CLK_1
DMIC0_1
<17> EV_LVDS_BRIGHT
*0_4
3
1
<8> INT_LVDS_BRIGHT
B0
YA
B1
GND
<34,37>
D3
BAS316
R55
10
9
R41
<10>
<10>
USBP8USBP8+
2
3
2
3
10K_4
BL_ON
10K_4
2
2
Q2
2N7002K
EC_FPBACK#
<37>
Q1
DTC144EUA
*0_4
L13
<9,10>
LVDS_BRIGHT
22u/6.3V_8
R46
1
4
1
4
USBP8-_R
USBP8+_R
100K_4
Q3
2N7002K
R56
PWM_SELECT#
C258
LID591#
BL#
R91
6
0.1u/10V_4_X7R.01u/25V_4
+3V
LVDS_BLON
U4
S
*2.2u/10V_8
LID591#,EC intrnal PU
SW@0.22u/6.3V_4
VCC
*.1u/10V_4
8P CON
C261
Backlight Control
C188
*SHORT0402
C260
CN4
8
7
6
5
4
3
2
1
+3V
<30> DMIC_CLK_1
<30>
DMIC0_1
R49
C259
INT_LVDS
+3V
<37> CONTRAST
C262
100K_4
LVD-A30SFYG+
R97
LCD_EDIDCLK
LCD_EDIDDATA
USBP8-_R
USBP8+_R
LCDVCC
INT_TXLCLKOUTINT_TXLCLKOUT+
INT_TXLOUT0INT_TXLOUT0+
AAT4280-4
R99
1
3
5
8
11
14
17
20
22
24
26
31
37
42
47
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
BCLKP
BCLKN
U7
1000p/50V_4
<10>
dGPU_SELECT_R
13
SEL
B1P
B1N
B0P
B0N
4.7u/25V_8
LVDS_VDDEN
2
1
35
34
C247
Q6
SW@2N7002K
<8> INT_TXLCLKOUT+
<8> INT_TXLCLKOUT-
C97
1U/6.3V_4
C0P
C0N
ACLKP
ACLKN
9
10
C256
0.1u/10V_4_X7R
1000p/50V_4
C1P
C1N
OUT_C
C241
+1.8V
39
38
IN_A
TXLOUT2+
TXLOUT2-
<17> EV_TXLOUT0+
<17> EV_TXLOUT0-
A1P
A1N
TXLCLKOUT+
TXLCLKOUT-
<17> EV_TXLOUT1+
<17> EV_TXLOUT1-
41
40
6
7
G_0
44
43
C2P
C2N
G_3
<17> EV_TXLOUT2+
<17> EV_TXLOUT2-
A2P
A2N
46
45
<17> EV_TXLCLKOUT+
<17> EV_TXLCLKOUT-
RFCMF1632100M3T/200mA/90ohm
R90
*0_4
2
SW@74LVC1G3157GW
R62
IV@0_4
PROJECT : ZR7B
Size
Document Number
Date:
Rev
1A
CRT/LVDS/CAMERA/LID
1
24
Sheet
8
of
50
SW@HDMI-detect
+3V
I@ HDMI LEVEL SHIFTER

R639
<9> HDMI_HPD_PCH#
To MXM
R441
10K_4
+3V
SW@
C687
C327
C680
IV@2.2u/6.3V_6
IV@.1u/10V_4
IV@.1u/10V_4
IV@.1u/10V_4
IV@.1u/10V_4
R164
+3V
*4.7K_4
DDCBUF_EN
CFG
+3V
HDMI_HPD_EC#
<37> HDMI_HPD_EC#
+5V
R138
*10K_4
Q34
SW@2N7002E
close to pin2/11/15/21/26/33/40/46
from PCH
36
35
34
33
32
31
30
29
28
27
26
25
37
38
39
40
41
42
43
44
45
46
47
48
49
<8> INT_HDMITX0N
<8> INT_HDMITX0P
+3V
<8> INT_HDMITX2N
<8> INT_HDMITX2P
<8> INT_HDMITX1P
<8> INT_HDMITX1N
+3V
GND
OUT_D1OUT_D1+
VCC
OUT_D2OUT_D2+
GND
OUT_D3OUT_D3+
VCC
OUT_D4OUT_D4+
1
2
3
4
5
6
7
8
9
10
11
12
<8> INT_HDMICLK+
<8> INT_HDMICLK-
GND
IN_D1IN_D1+
VCC
IN_D2IN_D2+
GND
IN_D3IN_D3+
VCC
IN_D4IN_D4+
GND
+3V
4.7K_4
*4.7K_4
PC0
R141
*4.7K_4
PC1
R166
R165
*4.7K_4
*4.7K_4
DDCBUF_EN
R167
R168
*4.7K_4
*4.7K_4
CFG
+3V
24
23
22
21
20
19
18
17
16
15
14
13
PC0
PC1
from PCH
R151
Q33
2N7002E
MB_HDMITX0N
MB_HDMITX0P
+3V
MB_HDMITX2N
MB_HDMITX2P
MB_HDMITX1P
MB_HDMITX1N
+3V
I2C
MB_HDMICLK+
MB_HDMICLKD12 2
+5V
1RB501V-40
+5V
R443
SW@1.5K/F_4
IV@PS8101
Q45
LS_REXT
R142
R143
*IV@.1u/10V_4
HDMI_MB_HP
*IV@.1u/10V_4
GND
CCT2
CCT1
VCC
DDC_EN
GND
HPD_SINK
SDA_SINK
SCL_SINK
GND
VCC
OE#
U13
C688
+3V
C686
<17>
+3V
Active Buffer
SP@
HDMI_HP_EV
C383
GND
VCC
TRIM
HPDEN
GND
REXT
HPD_S
SDA_S
SCL_S
NC
VCC
GND
C325
R442
SW@10K_4
IV@
HDMI_MB_HP
MB_HDMI_DDCDATA
MB_HDMI_DDCCLK
HDMI_HPD_EC#
+3V
*0_4
R147
1.5K/F_4
SW@BSN20
NV suggestion near
HDMI connector
+3V
<17> MXM_DDCCK
3
C
IV@499/F_4
MB_HDMI_DDCCLK R610
IV@0_4
HDMI_DDCCLK_MB
Control by pin4 HPDEN_R

D11 2
+5V
1RB501V-40
C324
<8> INT_HDMI_HPD
*.1u/10V_4
<8> SDVO_CTRLDAT
<8> SDVO_CTRLCLK
Equalization Control
PC1 PC0
PIN4 PIN3 EQ Control
L
L
H
H
L
H
L
H
8dB
4dB
12dB
0dB
PC0
internal PD
PC1
internal PD
DDCBUF_EN
internal PD
CFG
internal PD
DDC_EN
internal PU
IV@0_4 HDMI_DDCDATA_SW
R149
IV@0_4
R444
SW@1.5K/F_4
Q46
HDMI_DDCCLK_SW
+3V
R140
1.5K/F_4
SW@BSN20
<17> MXM_DDCDAT
R145
R146
+5V
R150
IV@2.2K_4
IV@2.2K_4
MB_HDMI_DDCDATA
R611
IV@0_4
HDMI_DDCDATA_MB
C317
*.1u/10V_4
Switchable Graphic HDMI source
ESD Protect
EMI
HDMI connector
MB_HDMITX2P
<17> HDMITX0N
<17> HDMITX0P
To MXM
<17> HDMITX2N
<17> HDMITX2P
C374
C369
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
MB_HDMITX0N
MB_HDMITX0P
C367
C355
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
MB_HDMITX2N
MB_HDMITX2P
C352
C347
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
MB_HDMITX1P
MB_HDMITX1N
C340
C333
SW@0.1u/10V_4_X7R
SW@0.1u/10V_4_X7R
MB_HDMICLK+
MB_HDMICLK-
R156
CN15
*100/F_4
MB_HDMITX2P
MB_HDMITX2N
MB_HDMITX2N
MB_HDMITX1P
MB_HDMITX1P
<17> HDMITX1P
<17> HDMITX1N
<17> HDMICLK+
<17> HDMICLK-
R155
MB_HDMITX1N
MB_HDMITX0P
*100/F_4
MB_HDMITX1N
MB_HDMITX0N
MB_HDMICLK+
MB_HDMITX0P
R445
R446
R447
R449
R450
R451
R452
R453
SW@499/F_4
SW@499/F_4
SW@499/F_4
SW@499/F_4
SW@499/F_4
SW@499/F_4
SW@499/F_4
SW@499/F_4
R158
+5V
*100/F_4
F2
SMD1206P110TFT
2
1
MB_HDMITX0N
MB_HDMICLK+
R153
MB_HDMICLK-
*100/F_4
D17
HDMI_DDCCLK_MB
HDMI_DDCDATA_MB
SSM22LLPT
HDMI_MB_HP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Q35
R448
SW@100K_4
MB_HDMICLK-
R137
20
23
22
21
HDMI
100K_4
SW@2N7002E
+5V
SHELL1
D2+
D2 Shield
D2D1+
D1 Shield
D1D0+
D0 Shield
D0GND
CK+
CK Shield GND
CKCE Remote
NC
DDC CLK
DDC DATA
GND
+5V
HP DET
SHELL2

PROJECT : ZR7B
Size
Document Number
Date:
Rev
1A
HDMI (PS8101)
5
Sheet
1
25
of
50
Giga-LAN AR8151
+3V_S5
+3V_LAN
R226
+3V_LAN
*short_6
C448
C447
C450
C451
C449
10u/6.3V_8
10u/6.3V_8
1u/6.3V_4
0.1u/10V_4
*1000p/50V_4
U16
<4,10,11,28,32,37> PLTRST#
<8,28> PCIE_WAKE#
*Short_4 BCM_CLKREQ#
R220
<10> CLK_PCIE_LAN_REQ#
WAKEn
CLKREQn
VDDCT
AR8151
5X5mm
1u/6.3V_4
AVDDL
AVDDL_REG
C707
0.1u/10V_4
XTLO
XTLO
XTLI
AVDDH
C700
1u/6.3V_4
C701
0.1u/10V_4
R205
2.37K/F_4
RBIAS
10
XTLI
AVDDH_REG
RBIAS
C430
0.1u/10V_4
24
DVDDL
C434
0.1u/10V_4
SMCLK
25
SMCLK_8151
R227
*0_4
SMDATA
26
SMDATA_8151
R223
*0_4
TESTMODE
27
TEST_RST
28
TX_N
29
PCIE_RXN1_LAN_R
0.1u/10V_4_X7R
C465
TX_P
30
PCIE_RXP1_LAN_R
0.1u/10V_4_X7R
C466
AVDDL
31
22
23
DVDDL
TRXN0
REFCLK_P
33
13
NC/AVDDL
AVDDL
34
<27> LAN_TRD1P
14
TRXP1
RX_P
35
<27> LAN_TRD1N
15
TRXN1
RX_N
36
16
NC/AVDDH
DVDDL_REG
37
DVDDL
17
NC/TRXP2
LED0
38
LAN_ACTLED
18
NC/TRXN2
LED1
39
LAN_LINKLED#
LX
0.1u/10V_4 AVDDH
<27> LAN_TRD2P
<27> LAN_TRD2N
XTLI
33p/50V_4
0.1u/10V_4 AVDDL
C697
19
NC/AVDDL
LX
40
<27> LAN_TRD3P
20
NC/TRXP3
GND
41
<27> LAN_TRD3N
21
NC/TRXN3
SMB_CLK_ME0 <10>
SMB_DATA_ME0 <10>
AVDDH
PCIE_RX1- <10>
PCIE_RX1+ <10>
0.1u/10V_4
C
12
0.1u/10V_4 AVDDL
1
2
C433
C453
REFCLK_N
C698
Y1
25MHz
AVDDL
*0_4
TRXP0
C699
1.2H
R613
32
<27> LAN_TRD0N
XTLO
40-Pin QFN
AVDDH
AVDDH
CLKREQn/LED2
11
<27> LAN_TRD0P
33p/50V_4
PERSTn
C710
C435
VDD33
0.1u/10V_4 +VDDCT
C714
CLK_PCIE_LOM# <10>
CLK_PCIE_LOM <10>
AVDDL
C454
0.1u/10V_4
PCIE_TX1+ <10>
PCIE_TX1- <10>
L31
LAN_ACTLED <27>
C455
1u/6.3V_4
C456
0.1u/10V_4
LAN_LINKLED# <27>
4.7uH/1A_2X2
+VDDCT
C457
C460
C464
10u/6.3V_8
0.1u/10V_4
*1000p/50V_4
AR8151
LAN_TRD3N
LAN_TRD3P
LAN_TRD2N
LAN_TRD2P
LAN_TRD1N
LAN_TRD0N
LAN_TRD1P
LAN_TRD0P
R209
R208
R207
R206
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
LAN_N4
R210
49.9/F_4
LAN_N3
R211
49.9/F_4
LAN_N2
R212
49.9/F_4
LAN_N1
R213
C408
C407
C406
C405
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4

PROJECT : ZR7B
Size
Document Number
Rev
1A
GLAN BCM57780
Date:
5
Sheet
1
26
of
50
L28
PBY160808T-181Y-N/2A/180ohm_6
C399
C395
C396
C397
0.1u/10V_4_X7R
0.1u/10V_4_X7R
0.1u/10V_4_X7R
0.1u/10V_4_X7R
C403
1U/10V_4
CN16
R456
<26> LAN_ACTLED
220_8
R454
LAN_ACT_LED_PWR
9
10
X-TX0P
X-TX0N
X-TX1P
X-TX2P
X-TX2N
X-TX1N
X-TX3P
X-TX3N
1
2
3
4
5
6
7
8
<26> LAN_TRD1P
<26> LAN_TRD1N
<26> LAN_TRD2P
<26> LAN_TRD2N
B
LAN_TRD0P
LAN_TRD0N
1
2
3
TCT1
TD1+
TD1-
MCT1
MX1+
MX1-
24
23
22
X-TX0P
X-TX0N
LAN_TRD1P
LAN_TRD1N
4
5
6
TCT2
TD2+
TD2-
MCT2
MX2+
MX2-
21
20
19
X-TX1P
X-TX1N
LAN_TRD2P
LAN_TRD2N
7
8
9
TCT3
TD3+
TD3-
MCT3
MX3+
MX3-
18
17
16
X-TX2P
X-TX2N
10
11
12
TCT4
TD4+
TD4-
MCT4
MX4+
MX4-
15
14
13
X-TX3P
X-TX3N
LAN_TRD3P
LAN_TRD3N
<26> LAN_TRD3P
<26> LAN_TRD3N
<26> LAN_LINKLED#
+3V_LAN
LAN_LINKLED#
LAN_LNK_LED_PWR
11
12
YELLOW_N
YELLOW_P
5.1K_4
U34
<26> LAN_TRD0P
<26> LAN_TRD0N
+VDDCT
TRANSFORMER
Close to Transformer pin 1,4,7,10
R487
220_8
GND2
GND1
0+
01+
2+
213+
3-
14
13
R203
R171
*0_6
*0_6
GREEN_N
GREEN_P
RJ45
B
LFE9276A-R
LAN_ACT_LED_PWR
R177
75/F_8
Delta
LFE9276C-R (DB0ZR1LAN00)
FCE
NS892407
Bothhand GST5009B
R184
75/F_8
R191
75/F_8
R200
75/F_8
LAN_LINKLED#
(DB0LL1LAN00)
C378
(DB0Z06LAN00)
C716
*0.1u//50V_8
*0.1u//50V_8
C390
1500p/3KV_18

PROJECT : ZR7B
Size
Document Number
Rev
1A
LAN Transformer and RJ45

Date:
1

7
Sheet
27
of
8
50
MINI-CARD WLAN(MPC)
Check LED signal. (active high or low)

*Short_4 CL_DATA1_WLAN
*Short_4 CL_CLK1_WLAN
*0_4
*0_4
*0_4
CL_RST1#_WLAN
CL_DATA1_WLAN
CL_CLK1_WLAN
+WL_VDD
A
<10>
<10>
PCIE_TX6+
PCIE_TX6-
<10>
<10>
PCIE_RX6+
PCIE_RX6-
<10> CLK_PCH_SRC2
<10> CLK_PCH_SRC2#
<10> PCIE_CLK_REQ2#
PCIE_WAKE#_R
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GND
PETp0
PETn0
GND
GND
PERp0
PERn0
GND
UIM_C4
UIM_C8
15
13
11
9
7
5
3
1
GND
REFCLK+
REFCLKGND
CLKREQ#
Reserved
Reserved
WAKE#
+WL_VDD
R544
*SHORT0805 +WL_VDD
+3.3V
GND
+1.5V
LED_WPAN#
LED_WLAN#
LED_WWAN#
GND
USB_D+
USB_DGND
SMB_DATA
SMB_CLK
+1.5V
GND
+3.3Vaux
PERST#
W_DISABLE#
GND
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
+WL_VDD
UIM_VPP
UIM_RST
UIM_CLK
UIM_DATA
UIM_PWR
+1.5V
GND
+3.3V
16
14
12
10
8
6
4
2
A_LFRAME#_R
A_LAD3_R
A_LAD2_R
A_LAD1_R
A_LAD0_R
C776
10u/10V_8
+1.5V
RF_LED#
C778
0.1u/10V_4
C772
*0.1u/10V_4
C774
*0.1u/10V_4
RF_LED# <33,37>
USBP13+
USBP13-
<10>
<10>
CLK_SDATA <3,14,15>
CLK_SCLK <3,14,15>
+1.5V
+1.5V
+WL_VDD
PLTRST#
RF_EN
R552
R553
R554
R555
R556
<37>
Debug
*0_4
*0_4
*0_4
*0_4
*0_4
LPC_LFRAME# <9,37>
LPC_LAD3 <9,37>
LPC_LAD2 <9,37>
LPC_LAD1 <9,37>
LPC_LAD0 <9,37>
C773
1000p/50V_4
C775
0.1u/10V_4
C770
10u/6.3V_8
+1.5V
+WL_VDD
53
+WL_VDD
LTS_AAA-PCI-046-K01
GND
R585
R589
R594
CL_RST1#
CL_DATA1
CL_CLK1
+3V
H=5.6mm
CN21
GND
R590
R606
<10>
PCI_RST#
<10> CLK_LPC_DEBUG
<10>
<10>
<10>
54
+3.3V: 1000mA
+3.3Vaux:330mA
+1.5V:500mA
<8,26> PCIE_WAKE#
modify 10/19
MINI-CARD 3G(MNC)Reserve for JV41-CP
<10> CLK_PCH_SRC1
<10> CLK_PCH_SRC1#
<10> CLKREQ_3G#
C
3G_WAKE_2_R
15
13
11
9
7
5
3
1
53
GND
REFCLK+
REFCLKGND
CLKREQ#
Reserved
Reserved
WAKE#
+1.5V
UIM_VPP
UIM_RST
UIM_CLK
UIM_DATA
UIM_PWR
+1.5V
GND
+3.3V
3G_LED#
R397
R394
*0_4
*Short_4
USBP10+
USBP10-
*Short_4
R396
*0_4
+1.5V_Mini2_VDD
Active Low
R398
+3V_Mini2_VDD
*0_8
1
R393
*10K_4
3G_MINI_LED#
3G_MINI_LED# <33>
C563
*0.1u/10V_4
RF_LED#
R395
+3V
C582
*0.47u/10V_6
C605
C204
C208
*10u/6.3V_8
3G@0.1u/10V_4
*10u/6.3V_8
<10>
<10>
3G_SMDATA
3G_SMCLK
7/15 modify
PLTRST#
+3V
PLTRST# <4,10,11,26,32,37>
R369
*Short_4
R368
3G_EN
*0_4
UIM_VPP
UIM_RST
UIM_CLK
UIM_DATA
UIM_PWR
16
14
12
10
8
6
4
2
+3V_Mini2_VDD
<37>
R77
*0_8
R411
3G@0_8
RF_EN
<10> PCIE_RX2+
<10> PCIE_RX2-
+3V_Mini2_VDD
+3VSUS
C612
3G@10u/6.3V_8
C607
3G@0.1u/10V_4
C576
3G@0.1u/10V_4
C562
C578
3G@0.1u/10V_4
<10> PCIE_TX2+
<10> PCIE_TX2-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
GND
PETp0
PETn0
GND
GND
PERp0
PERn0
GND
UIM_C4
UIM_C8
GND
3G_WAKE_1_R
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
3G@LTS_AAA-PCI-049-K01
+3.3V 52
GND 50
+1.5V 48
LED_WPAN# 46
44
LED_WLAN#
LED_WWAN# 42
GND 40
USB_D+ 38
USB_D- 36
GND 34
SMB_DATA 32
SMB_CLK 30
+1.5V 28
GND 26
24
+3.3Vaux
PERST# 22
W_DISABLE# 20
GND 18
GND
CN12
T3
+1.5V_Mini2_VDD
H=7.0mm
+3V_Mini2_VDD
T32
C558
3G@0.47u/10V_6 3G@10p/50V_4
A:(10/17)FAE confirm:
3G module need +3VSUS and no need +1.5V and no need SMBUS
54
Q41
*DTC144EUA
PCIE_WAKE#_R
1
+3V_Mini2_VDD
modify 10/19
ESD1
*CM1293-04SO
1
CH1
+3V_Mini2_VDD
6
CH4
+3V_Mini2_VDD
UIM_VPP
4
2
UIM_RST_C
VP
RP3
4
CH3
UIM_DATA_C
C30
3G@10p/50V_4
C38
3G@33p/50V_4
<3,14,15> CLK_SDATA
R385
JSIM1
*Short_4 UIM_CLK_C 6
*0_4
USBP5-_R 7
*0_4
USBP5+_R 8
9
10
+3V_Mini2_VDD
CLK(C3)
N/A(C8)
N/A(C4)
CT
CD
GND(C5)
VCC(C1)
VPP(C6)
RST(C2)
DATA(C7)
12
14
3G@SIM-Conn
13
11
3G_SMDATA
*0_4
SIM CARD SIGNALS

ROUTE PARALLEL
1
2
3
4
5
UIM_PWR
UIM_VPP
UIM_RST_C
UIM_DATA_C
R15
R12
R13
GND
GND
USBP5USBP5+
R10
R11
*Short_4
*Short_4
UIM_RST
UIM_DATA
UIM_PWR
C29
2
C31
The value of the capacitor is suggest by Siemens HQ expert.
For against 900MHz RF interference. The value of capacitor is 27pF.
For against 1800MHz RF interference. The value of capacitor is 10pF.
1nF/10nF value capacitor use for against ESD purpose.
Q26
*2N7002E
3G@27p/50V_4
<3,14,15> CLK_SCLK
GND
GND
UIM_CLK
<10>
<10>
*4.7K_4P2R
Q27
*2N7002E
3
1
CH2
VN
2
1
SIM CARD(RFM)Reserve for JV41-CP
2
UIM_CLK_C
1
3G@1u/10V_6
R373
3G_SMCLK
D
*0_4
7/15 modify
UIM_DATA
C35
3G@10p/50V_4
UIM_RST
C34
3G@27p/50V_4

PROJECT : ZR7B
Closed JSIM1
1
Size
Document Number
Date:
Rev
1A
MINI PCI-E card/TV

6
Sheet
28
8
of
50
EE RETURN-PATH CAPACITORS
MAIN SATA HDD
+5V
CN18
GND23
23
GND1
RXP
RXN
GND2
TXN
TXP
GND3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
GND24
24
SATA_TXP0_C
SATA_TXN0_C
C748
C743
.01u/25V_4
.01u/25V_4
SATA_RXN0
SATA_RXP0
C737
C736
.01u/25V_4
.01u/25V_4
C516
*.01u/25V_4
C630
*.01u/25V_4
VIN
+5V
SATA_TXP0 <9>
SATA_TXN0 <9>
C506
+3V
SATA_RXN0_C <9>
SATA_RXP0_C <9>
+5V_S5
*.01u/25V_4
VIN
+5V
+5V
R482
*SHORT0805+5V_HDD
C695
C702
C712
C711
C709
C706
0.1u/25V_4_X5R
C541
0.1u/25V_4_X5R
C503
*.1u/10V_4
C622
0.1u/25V_4_X5R
C756
*.1u/10V_4
C618
0.1u/25V_4_X5R
C512
*.1u/10V_4
C693
*.1u/10V_4
C537
0.1u/25V_4_X5R
C511
*.01u/25V_4
C657
*.1u/10V_4
C538
0.1u/25V_4_X5R
C504
*.1u/10V_4
C690
0.1u/25V_4_X5R
C651
*.1u/10V_4
C543
0.1u/25V_4_X5R
C694
*.1u/10V_4
C689
0.1u/25V_4_X5R
C757
*.1u/10V_4
C84
0.1u/25V_4_X5R
100u/6.3V_3528
10u/10V_6
*.1u/16V_4
*.1u/16V_4
.01u/25V_4
.01u/25V_4
C754
*.01u/25V_4
+3V
C495
*.1u/10V_4
+3V
ODD POWER(ODD)
.01u/25V_4
.01u/25V_4
.01u/25V_4
*.1u/16V_4
*.1u/16V_4
C656
10u/10V_6
C650
<9> PCH_ODD_EN
*Short_4 ODD_EN
*0_4
R362
*100K_4
100u/6.3V_3528
3
3
1
R363
R358
C655
Q24
DMN601K-7
.01u/25V_4
C652
<37> ODD_POWER
C653
C264
0.1u/25V_6
Q25
DMN601K-7
1K_4
C654
MOD_EN_5V
+5V_ODD
SATA_DPR440
100K_4
Connect to PCH(GPIO21) pin Y9

and EC pin28(GPIO53)
SATA_RXN1_C <9>
SATA_RXP1_C <9>
C305
C302
SATA_TXP1 <9>
SATA_TXN1 <9>
*0_8
R119
2
+15V
.01u/25V_4
.01u/25V_4
GND15
15
SATA_RXN1
SATA_RXP1
C318
C315
DP
5V
5V
MD
GND
GND
8
9
10
11
12
13
SATA_TXP1_C
SATA_TXN1_C
R439
6
5
2
1
R359
100K_4
14
1
2
3
4
5
6
7
+5V
+5V_ODD
+3VPCU
CN14
GND
A+
AGND
BB+
GND
Q32
AO6402A
+5V
ODD (SATA)
GND14
C1
+5V_HDD
MAIN_SATA
VIN
3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
RSVD
GND
12V
12V
12V
SATA_ODD
D

PROJECT : ZR7B
Size
Document Number
SATA-HDD/ODD/USB-ESATA
Date:
1
Sheet
4
29
of
50
Rev
1A
Mute(ADO)
HP
<31>
HP-L
<31>
HP-R
+3V
reverse R441
R539
*0_4
R532
*Short_4
ADOGND
MIC1-VREFO-L
MIC1-VREFO-L <31>
MIC1-VREFO-R
+5VA
R615
R599
*10K_4
1K_4
PD#
R538
*0_4
C760
Codec(ADO)
*BAS316
D20
BAS316
D21
MIC1-VREFO-L
10u/6.3V_6
EAPD#
MIC1-VREFO-R <31>
ADOGND
BAS316
ADOGND
D22
AMP_MUTE# <37>
PCH_AZ_CODEC_RST#
C761
Place next to pin 27

+
2.2u/6.3V_6
C759
ADOGND
C762
C768
+5VA
10u/6.3V_6 0.1u/10V_4
+5VA
46
EAPD#
C792
C793
C790
47
C789
48
10u/6.3V_6 0.1u/10V_4
10u/6.3V_6
0.1u/10V_4
49
26
27
28
29
30
31
32
33
25
AVDD1
AVSS1
VREF
LDO-CAP
MIC2-VREFO
MIC1-VREFO-R
MIC1-VREFO-L
HP-OUT-L
34
MIC2-L
PVDD2
LINE2-R
SPDIFO2/EAPD
SPDIFO
PGND
Spilt by DGND
HP-OUT-R
MIC2-R
SPK-R+
ADOGND
22
21
MIC1-L
MIC1-R
<31>
MIC1-L
<31>
MIC
R566
20K/F_4
ADOGND
18
17
16
15
14
LINE2-L
SENSEA
13
Sense A
PCBEEP
+5VPVDD2
SPK-R-
12
45
RESET#
44
R_SPK+
11
R_SPK-
R_SPK+
10u/6.3V_6
T79
MIC1-R
19
JDREF
Sense-B
SYNC
*short_6
R_SPK-
<31>
(Vista Premium Version)
PVSS2
10
R581
+5V
<31>
PVSS1
DVDD-IO
43
C508
0.1u/10V_4
20
MONO-OUT
42
MIC1-L
SDATA-IN
GND_EARTH
MIC1-R
SPK-L+
SPK-L-
C509
T77
23
LINE1-L
10u/6.3V_6
24
LINE1-R
PVDD1
DVSS2
41
L_SPK-
BIT-CLK
40
L_SPK-
SDATA-OUT
L_SPK+
<31>
0.1u/10V_4
10u/6.3V_6 0.1u/10V_4
39
C779
<31>
L_SPK+
C783
PD#
C780
C784
AVDD2
+5V
AVSS2
GPIO1/DMIC-CLK
38
37
+5VPVDD1
*short_6
GPIO0/DMIC-DATA
Spilt by AGND
R558
CBN
ADOGND
ANALOG
DVDD1
ADOGND
CBP
U39
CPVEE
36
C766
0.1u/10V_4
C764
10u/6.3V_6
35
2.2u/6.3V_6
R578
39.2K/F_4
LINEOUT_JD
R583
20K/F_4
MIC1_JD
LINEOUT_JD <31>
MIC1_JD
ANALOG
<31>
ALC271X
PCBEEP dont coupling any signals if possible

8/17 separate PCBEEP to Digital from Realtek suggestion
DIGITAL
1.6Vrms
<31> SPDIF_OUT
+3V
PCBEEP
C800
1u/10V_6 BEEP_1
R597
C807
C799
0.1u/10V_4
C806
10u/6.3V_6
47K/F_4
SPKR
<9>
R596
4.7K_4
100p/50V_4
Place next to pin 1
R587
<24>
L58
SBK160808T-301Y-N/0.2A/300ohm_6
L57
SBK160808T-301Y-N/0.2A/300ohm_6
DMIC0_1
<24> DMIC_CLK_1
C810
*33p/50V_4
C809
*33p/50V_4
DMIC0
DMIC_CLK
PCH_AZ_CODEC_RST#
EMI request
ACZ_SDIN0_R R598
22_4
PD#
0V : Power down Class D SPK amplifer

3.3V : Power up Class D SPK amplifer
C808
ANALOG
L56
<9>
PCH_AZ_CODEC_SDIN0
<9>
PCH_AZ_CODEC_SDOUT
<9>
PCH_AZ_CODEC_BITCLK
<9>
<9>
C802
C801
0.1u/10V_4
10u/6.3V_6
C795
*100p/50V_4
Place next to pin 9
*22p/50V_4
Power (ADO)
DIGITAL
+5V
PCH_AZ_CODEC_SYNC
*short_6 +3V
UPB201209T-310Y-N/6A/31ohm_8
R595
*0_6
R603
*0_6
R493
*short_6
R502
R602
R490
R517
*0_6
*0_6
*0_6
*0_6
+5VA
GND_EARTH don't coupling AGND and SPK signals
U38
3
IN
2
A
OUT
GND
SHDN
SET
R540
*29.4K/F_4
GND_EARTH
R577
*short_6
R565
R571
*0_6
*0_6
*G923-330T1UF
R534
*10K/F_4
C755
C767
C765
10u/10V_3216
0.1u/10V_4
C751
C752
R317
R519
+
0.1u/10V_4
C763
*1000p/50V_4
*1000p/50V_4
*short_6
**0_4
10u/10V_3216
PROJECT : ZR7B
ADOGND
Size
ADOGND
ADOGND
Document Number
Rev
1A
REALTEK ALC663&888/MDC
C730, C787 close U37 pin3 and L65
Date:
4
Sheet

1
30
of
50
MIC
MIC1-VREFO-R
MIC1-VREFO-L
<30> MIC1-VREFO-R
<30> MIC1-VREFO-L
Internal Speaker
R500
4.7K/F_4
CN19
<30>
<30>
Normal OPEN Jack

R525
4.7K/F_4
MIC1-L
C753
4.7u/6.3V_6
MIC1_L2
R524
1K/F_4
MIC1_L3
MIC1-R
C746
4.7u/6.3V_6
MIC1_R2
R512
1K/F_4
MIC1_R3
<30>
L55
BLM15AG121SS1/0.5A/120ohm_4
L51
1
2
6
3
4
MIC1_L
MIC1_R
MIC1_JD
PINK
7
CN7
<30>
<30>
<30>
<30>
MIC1_JD
R_SPKR_SPK+
L_SPKL_SPK+
R_SPK-R176
R_SPK+
R175
L_SPK-R174
L_SPK+
R173
R_SPK-_1
R_SPK+_1
L_SPK-_1
L_SPK+_1
*short_6
*short_6
*short_6
*short_6
1
25
36
4
MIC
C731
470p/50V_4
Max. 100mVrms input for Mic-IN
C758
470p/50V_4
MIC1_JD
C381
C382
C380
C379
*0.22u/25V_6 *0.22u/25V_6 *0.22u/25V_6 *0.22u/25V_6
SPEAKER-CONN
ADOGND
ADOGND
D13
*VPORT_6
ADOGND
C
HP/SPDIF
CN20
HP_JD
<30>
<30>
HP-L
HP-R
HP-L R291
HP-R R315
56/F_4
56/F_4
HPL-1
HPR-1
BLM15AG121SS1/0.5A/120ohm_4 HPL_SYS
BLM15AG121SS1/0.5A/120ohm_4 HPR_SYS
L34
L37
3
4
5
ADOGND
C505
R319
R290
C515
*1K_4
*1K_4
2200p/50V_4 2200p/50V_4
1
2
7
8
6
+3V_SPD
Drive
IC
LED
SPDIF_BLACK
ADOGND
B
<30>
SPDIF_OUT
SPDIF_OUT
L39
SPDIF_OUT_R
+5VA
+3V_SPD
LINEOUT_JD
3
R300
+5VA
C510
10K_4
HP_JD
0.22u/6.3V_4
LINE_JD#
2
Q40
R320
ADOGND
2N7002ESPT
D19
20K_4
HP_JD
LINEOUT_JD <30>
Q43
ME2347
+3V
Q42
ADOGND
ADOGND
2N7002ESPT
*VPORT_6
PROJECT : ZR7B
ADOGND
Size
Document Number
Rev
1A
AMP /AUDIO JACK CONN

Date:
5
Sheet
1
31
of
50
4 IN 1 CARD READER (MMC)

CN9
XD_RDY
XD_RE#
XD_CE#
XD_CLE
XD_ALE
XD_WE#
XD_WP#
XD_D0
XD_D1
SD_DAT2
SD_DAT3
SD_CMD
CARD READER Controller

4
VCC_XD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
MS_SCLK
MS_DATA3
MS_INS#
MS_DATA2
MS_DATA0
XD-R/B
XD-RE
XD-CE
XD-CLE
XD-ALE
XD-WE
XD-WP
XD-D0
XD-D1
SD-DAT2
SD-DAT3
SD-CMD
4IN1-GND1
MS-VCC
MS-SCLK
MS-DATA3
MS-INS
MS-DATA2
MS-DATA0
MS-DATA1
MS-BS
4IN1-GND2
SD-VCC
SD-CLK
SD-DAT0
XD-D2
XD-D3
XD-D4
SD-DAT1
XD-D5
XD-D6
XD-D7
XD-VCC
XD-CD-SW
SD-WP-SW
SD-CD-SW
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
SHIELD1-GND
SHIELD2-GND
SHIELD3-GND
37
38
41
XD_CD#
SD_WP
SD_CD#
R496
C738
*5.1K_4
T76
T78
Clock input selection

'1' for 48MHz input [Default]
'0' for 12MHz input
C513
C514
0.1u/16V_4
0.1u/16V_4
Main
SD_DAT0
DFHD36MS006
DATA0
Second
XD_D0
SD_DAT1
48
47
46
45
44
43
42
41
40
39
38
37
U40
C777 *0.47u/10V_6
+3V
R545
*short_6
+3V_VDD
C769
4.7u/10V_6
R567 330_4
<10>
<10>
USBP12+
USBP12C791
C794
*5p/50V_4
*5p/50V_4
XI
XO
+1.8V_VDD
1
2
3
4
5
6
7
8
9
10
11
12
8/14 C707 close PIN11, 12
DATA1
GPON7
EXT48IN
RSTN
REXT
VD33P
DP
DM
VS33P
XI
XO
VDD
VDD
36
35
34
33
32
31
30
29
28
27
26
25
CTRL0
DATA5
CTRL2
GPI4
DATA4
DATA3
DATA2
XD_WP#
GPI2
XD_CE#
EEPDATA
GPI1
XD_D1
SD_DAT2
DATA2
MS_DATA2
XD_D2
T80
SD_DAT3
DATA3
MS_DATA3
XD_D3
T81
T82
T83
Close to connector
CTRL0
R494
SD_CLK
XD_ALE
13
14
15
16
17
18
19
20
21
22
23
24
CTRL0
DATA5
CTRL2
GPI4
DATA4
DATA3
DATA2
XDWPN
GPI2
XDCEN
EEPDATA
GPI1
AU6437-GBL
MS_DATA1
CTRL0, CRTL 1 trace length shorter ,

and surround with GND.
VDDHM
GND
VDD
XTALSEL
TRIST
NBMD
CTRL1
CTRL3
DATA1
DATA0
DATA7
DATA6
*Short_4
+3V_VDD
V18
CF_V33
VCC33
AGND5V
V33
VDDHM
GND
VDD
CTRL4
XDCDN
SDWPEN
EEPCLK
R550
<4,10,11,26,28,37> PLTRST#
MS_DATA0
DFHD36MS012
8/14 ZH7 remove R136, R591 and C775

*100K_4
0.1u/16V_4
C708 close PIN48, 47
XTALSEL
R549
C740
4.7u/10V_6
Close to CN14 pin 14 & pin23

4.7u CAP close to pin23
XTALSEL
CRMD_N
NBMD
CTRL1
CTRL3
DATA1
DATA0
DATA7
DATA6
*Short_4
VCC_XD
modify for ESD
C743 close PIN46, 47
+3V_VDD
R548
VCC_XD
SD_CLK
SD_DAT0
XD_D2
XD_D3
DATA4
SD_DAT1
DATA5
DATA6
DATA7
VCC_XD
CONN_CARDREADER
+1.8V_VDD
MS_DATA1
MS_BS
C735
*10p/50V_4
MS_BS
crystal trace width needs at least 10 mils.

EEPCLK
18p/50V_4
C804
XI
4.7u/10V_6
C803
18p/50V_4
SD_WP
CTRL1
R584
270K_4
XO
XD_CLE
R520
MS_SCLK
SD_CMD
*0_4
VCC_XD
Y7
12MHz
T84
VCC_XD
8/14 pin13 output 20mils

C797
XD_CD#
CTRL4
+1.8V_VDD
+3V_VDD
+3V_VDD
C811
C812
4.7u/10V_6
0.1u/16V_4
R604
CTRL2
SD write protect
1:decided by SDWP[Default]
0:letting SD always
write-able
C749
*10p/50V_4
XD_RDY
SD_CD#
CTRL3
XD_WE#
MS_INS#
CTRL4
XD_RE#

PROJECT : ZR7B
Size
Document Number
Rev
1A
AU6433 CardReader
Date:
A
Sheet
E
32
of
50
LED
POWER BOARD CONN(UIF)
+3V_S5
POWER
<37>
SUSLED#
<37>
PWRLED#
PWRLED#
LED1
<37>
+3V_S5
SUSLED#
R329
90.9/F_4
R328
37.4/F_4
<37> PWRLED#
+3VPCU
Amber
+3V_S5
2
1
LED_A/B
Blue
2
1
R347
SUSLED# 2
Q23
*BSS84
ACPRN
D2
NUMLED#
CAPSLED#
*1M_4
+3VPCU
+3VPCU
PWR_LED
SUS_LED
PIPE_LED
<37>
<37>
*1M_4
R333
Amber
POWER/B
Q21
*BSS84
<37> NBSWON#
R332
Battery
+3V
<37>
*100K/F_6
Q22
BSS84
BAS316
SATA_LED#_R
+3V
12
11
10
9
8
7
6
5
4
3
2
1
LED2
<37> BATLED1#
14
13
<37> BATLED0#
R331
90.9/F_4
R330
37.4/F_4
2
1
Blue
RF_LED_EN#
CN1
LED3
SATA_LED#_R
R642
<37> RF_LED_EN#
SATA_ACT#
1
BSS84
Amber
<28,37> RF_LED#
4
<9>
+3V
Q47
R9
10K/F_4 1
LED_A/B
PIPE LED will flash while

battery insert at C-test
U22
*TC7SH08FU
*0_4
<28> 3G_MINI_LED#
R335
90.9/F_4
R334
37.4/F_4
R643
*0_4
LED_A/B
R14
*Short_4
Blue
SW /B
+3V
+3V
CN3
<37> P_SAVE_LED#
Q4
BSS84
R87
1
2
3
4
5
6
P_SAVE_LED
330_4
<37> ODD_EJ
<37> POWER_SAVE
R607
R608
1
2
3
4
5
6
+3V
C227
7
8
7
8
0.1u/10V_4
A
SW/LED
100K_4
100K_4

PROJECT : ZR7B
11/3 modify
Size
Document Number
Rev
1A
POWER/MMB/LAUNCH/LED
Date:
5
Sheet
33
1
of
50
USB
+5V_S5
C471
U17
1U/6.3V_4
D
<37>
USBON#
2
3
IN1
IN2
4
1
EN#
GND
OUT3
OUT2
OUT1
8
7
6
OC#
USBPWR1
C719
+
BLUETOOTH CONNECTOR
C715
11/13 modify
1000p/50V_4
330u/6.3V_6X5.7
CN8
G547F2P81U
+3V_S5
2
CN17
1
2
3
4
USBP1-_R
USBP1+_R
R230
1
2
3
4
8
7
6
5
8
7
6
5
R199
USBP1-_R
USBP1+_R
<10>
<10>
DLW21HN900SQ2L/300mA/90ohm
R229
*0_4
BT_LED
7
6
*Short_4
C401
*.01u/16V_4
L27
3
2
USBP4+
USBP4-
1
4
3
2
4
1
4
1
USBP4+_R
USBP4-_R
*RFCMF1632100M3T/200mA/90ohm
R198
*Short_4
RV2
RV1
*EGA-0402
*EGA-0402
1
4
T54
BT_CONN
USB_MB_Turbo
*0_4
2
3
C402
1000p/50V_4
<37> BT_POWERON#
L32
2
3
USBP1USBP1+
AO3413
+ C400
2.2u/6.3V_6
5
4
3
2
1
USBP4+_R
USBP4-_R
Q13
<10> USB_OC0#
<10>
<10>
BT_POWER
USB/B
R321
+5V_S5
*0_4
L38
<10>
<10>
USBP3USBP3+
2
3
2
3
1
4
1
4
USBP3-_R
USBP3+_R
R324
*0_4
R316
*0_4
L36
<10>
<10>
USBP9USBP9+
2
3
2
3
1
4
1
4
USBP9-_R
USBP9+_R
<37> USBON#
<10> USB_OC1#
<10> USB_OC4_5#
+3VPCU
<24,37> LID591#
R314
*0_4
R306
USBP3-_R
USBP3+_R
USBP9-_R
USBP9+_R
*0_4
L35
<10>
<10>
USBP11USBP11+
2
3
2
3
1
4
1
4
USBP11-_R
USBP11+_R
USBP11-_R
USBP11+_R
CN10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
R297
*0_4
Aces 88501-240N
R230, R229, R321, R324, R316, R314, R306, R297

A

PROJECT : ZR7B
Size
Document Number
Rev
1A
USB/ BT
Date:
5
Sheet
1
34
of
50
K/B
MY7
MY6
MY5
MY4
MY11
MY10
MY9
MY8
MY15
MY14
MY13
MY12
MX4
MX5
MX6
MX7
+5V
+3V
+5V
+3V
R378
R374
R370
R371
10K_4
10K_4
10K_4
10K_4
R372
FAN_PWM_E
*10K_4
<37>
CN11
FANSIG
Q29
MMBT3904
1
2
3
4
<10,11,37> SML1ALERT#
27
28
<37>
FAN_PWM_CN
3
Q28
MMBT3904
FAN
30mil
CPUFAN#
KB
+3VPCU
MX1
MX0
+3V
MY3
MY2
MY1
MY0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
MX6
MX7
MY17
MY16
MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
MY16
MY17
MX7
MX6
MX5
MX4
MX3
MX2
MX1
MX0
MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
MY16
MY17
MX7
MX6
MX5
MX4
MX3
MX2
MX1
MX0
<37>
<37>
<37>
<37>
<37>
<37>
<37>
<37>
<37>
<37>
<37>
<37>
<37>
<37>
<37>
<37>
<37>
<37>
<37>
<37>
<37>
<37>
<37>
<37>
<37>
<37>
MX2
MX3
MX4
MX5
CPU FAN
CN2
7
8
5
6
3
4
1
2
CP6
*100p/50Vx4
7
8
5
6
3
4
1
2
CP5
*100p/50Vx4
7
8
5
6
3
4
1
2
CP1
*100p/50Vx4
7
8
5
6
3
4
1
2
CP2
*100p/50Vx4
7
8
5
6
3
4
1
2
CP3
*100p/50Vx4
7
8
5
6
3
4
1
2
CP4
*100p/50Vx4
C549 *100p/50V_4
C550 *100p/50V_4
RP2
10
9
8
7
6
TOUCHPAD & Switch CONN.
10K_10P8R
1 MX3
2 MX2
3 MX1
4 MX0
5
+5V
+5V
L24
+TPVDD
*SHORT0805
C283
H-C157D63PT
R136
10K_4
R135
10K_4
0.1u/10V_4_X7R
HOLE22
*h-c157d102pt
CN6
<37>
TPDATA
<37>
TPCLK
L25
*short_6
L23
*short_6
1
2
3
4
5
6
7
8
9
10
11
12
TPDATA_R
TPCLK_R
C293
HOLE28
*h-c157d79pt
1
2
3
6
5
4
HOLE31
*Hg-c276d110p2
7
6
8
5
9
4
HOLE30
*H-C91D91N
1
2
3
HOLE7
*O-ZR7-1
7
8
9
1
2
3
HOLE1
*HG-C315D110P2
7
6
8
5
9
4
1
2
3
HOLE2
*HG-C315D110P2
7
6
8
5
9
4
C291
RIGHT#
*.01u/25V_4
*.01u/25V_4
HOLE3
*HG-C315D110P2
7
6
8
5
9
4
HOLE20
*hg-c315d110p2
7
6
8
5
9
4
HOLE19
*H-C91D91N
LEFT#
1
2
3
RIGHT#
H-C197D122PB
HOLE6
*h-c276d110p2
HOLE23
*H-C236D161PB
HOLE9
*h-c236d142pb
SW3
3
1
LEFT#
2
4
SW2
3
1
2
4
SWITCH_1.5
HOLE18
*H-C236D161PB
HOLE27
*h-c236d161pb
SWITCH_1.5
1
2
3
HOLE26
*hg-c394d110p2
7
6
8
5
9
4
h-c236d118p2
HOLE4
HOLE5
HOLE8
*H-C197D122PB *H-C197D122PB *H-C197D122PB
H-C236D142PB
HOLE14
*H-C236D142PB
HOLE13
*H-C236D142PB
HOLE10
*H-C236D142PB
HOLE11
*H-C236D142PB

1
HOLE12
*hg-c355d110p2
7
6
8
5
9
4
1
2
3
1
2
3
HOLE29
*hg-c236d110p2
7
6
8
5
9
4
HOLE15
*H-C236D157PB
Aces 88501-120N
H-C236D157PB
HOLE16
*H-C236D157PB
13
14
1
2
3
HOLE25
*HG-C315D110P2
7
6
8
5
9
4
1
2
3
HOLE24
*HG-C315D110P2
7
6
8
5
9
4
1
2
3
HOLE21
*HG-C315D110P2
7
6
8
5
9
4
1
2
3
HOLE17
*h-c236d142p2
7
6
8
5
9
4
1
2
3
PROJECT : ZR7B
Size
Document Number
Rev
1A
KB/FAN/TP+FP
Date:
5
Sheet
1
35
of
50
EMI decoupling
VIN_SRC
<38>
C813
10u/25V_1206
C814
C815
C821
C817
10u/25V_1206 *10u/25V_1206*10u/25V_1206 *10u/25V_1206
2200p/50V_4
C825
C826
C827
*1u/25V_6 *1u/25V_6 *1u/25V_6
<47> MAINON_DIS_G
VDC
EC1
EC2
C818
22u/25V_1210 22u/25V_1210 10u/25V_1206
C819
10u/25V_1206
C820
10u/25V_1206
<47> MAINON_DIS_G
PQ21
DMN601K-7
PQ20
DMN601K-7
<38>
PR86
220_8
C822
10u/25V_1206
3
C824
*1u/25V_6
PR85
22_8
+3V
C828
C823
*1u/25V_6
+1.5V_CPUVDDQ
+0.75V_DDR_VTT
CSOP_1
VIN
C816
10u/25V_1206
+1.5V_SUS
C330
*.1u_4
C321
*.1u_4
C319
*.1u_4
C316
*.1u_4
+1.5V_CPUVDDQ
+3V_S5
+3V_S5
+1.5V_SUS
R108
U19
*1K_4
R546
PM_DRAM_PWRGD <4,8>
*TC7SH08FU
R547
*750/F_4
<11> RST_GATE#
*BSS138
1
R107
*Short_4
Q16
*PDTC143TT
<14,15>
Q9
*1.5K/F_4
3
Q17
*2N7002E
+1.5V_CPUVDDQ
DDR3_DRAMRST#
2
3
R318
*10K/F_4
R323
*10K/F_4
PWRGD_1.5VCPU
<4> CPU_DDR3_DRAMRST#
<43>
+1.5V_SUS
+1.5V_SUS
+1.5V_SUS
R126
*1K/F_4
R118
*1K/F_4
1
2
5
6
PQ12
+SMDDR_VREF_DQ1
Q12
Q11
R124
*1K/F_4
<39,43,47> MAIND
RST_GATE#_R
*AO6402A
3
R117
*1K/F_4
*SHORT1206
*SHORT1206
+1.5V_CPUVDDQ
6A/maximum
R152
*A03402
*A03402
R154
RST_GATE#_R
<15>
<14>
+SMDDR_VREF_DQ0

PROJECT : ZR7B
Size
Document Number
Rev
1A
S3 power saving
Date:
1

7
Sheet
of
36
8
50
EC(KBC)
L45
PBY160808T-250Y-N/3A/25ohm_6
I/O ADDRESS SETTING(KBC)
+A3VPCU
+3V
C596
30mil
C597
0.1u/10V_4_X7R
10u/10V_6
+3VPCU
R54
1
E775AGND
2.2_6
2
D15
0.03A(30mils)
+3VPCU_EC
0.1u/10V_4_X7R
*.1u/16V_4
0.1u/10V_4_X7R U25
C560
C561
4.7U/6.3V_6
0.1u/10V_4_X7R
0.1u/10V_4_X7R
*.1u/16V_4
C567
VDD
4.7U/6.3V_6
C584
102
C200
AVCC
C199
VCC1
VCC2
VCC3
VCC4
VCC5
C586
19
46
76
88
115
BAS316
C590
C606
E775AGND
10u/6.3V_8 ICMNT
C603
D16
<11> SIO_EXT_SCI#
C568
*10p/50V_4
BAS316
PLTRST#
<34> USBON#
<9> IRQ_SERIRQ
6
NOCIR#
T7
<4,10,11,26,28,32>
29
EC_FPBACK#
<24> EC_FPBACK#
124
PLTRST#
USBON#
123
IRQ_SERIRQ
125
9
<11> SIO_EXT_SMI#
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
<35>
MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
MY16
MY17
<38>
MBCLK
<38>
MBDATA
<10> 2ND_MBCLK
<10> 2ND_MBDATA
<35>
TPCLK
<35>
TPDATA
<8> PCH_ACIN
<34> BT_POWERON#
<41,42,43,47> MAINON
T62
R400
<8> ICH_SUSCLK
MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7
54
55
56
57
58
59
60
61
MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
MY16
MY17
53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33
MBCLK
MBDATA
2ND_MBCLK
2ND_MBDATA
70
69
67
68
TPCLK
TPDATA
PCH_ACIN
72
71
10
11
12
13
MAINOND
*Short_4
E775_32KX1
R399
*20M_6
E775_32KX2
R412
Y2
77
79
GPIO94/DA0
GPI95/DA1
GPI96/DA2
GPI97
101
105
106
107
POWER_SAVE <33>
64
95
93
94
119
109
120
65
66
15
16
17
20
21
22
23
24
25
26
27
28
91
110
112
80
ACIN
<38>
NBSWON# <33>
LID591# <24,34>
SUSB# <8>
MXM_SMCLK12 <23>
ACPRN <33>
MXM_SMDATA12 <23>
BATLED0# <33>
BATLED1# <33>
VRON <40>
SUSLED# <33>
GPIO11/CLKRUN
GPIO85/GA20
D/A
KBRST/GPIO86
LPC
ECSCI/GPIO54
GPIO24/LDRQ
GPIO10/LPCPD
LREST
GPIO67/PWUREQ
SERIRQ
GPIO65/SMI
GPIO
KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7
KBSOUT0/JENK
KBSOUT1/TCK
KBSOUT2/TMS
KBSOUT3/TDI
KB
KBSOUT4/JEN0
KBSOUT5/TDO
KBSOUT6/RDY
KBSOUT7
KBSOUT8
KBSOUT9/SDP_VIS
KBSOUT10/P80_CLK
KBSOUT11/P80_DAT
KBSOUT12/GPIO64
KBSOUT13/GPIO63
KBSOUT14/GPIO62
KBSOUT15/GPIO61/XOR_OUT
GPIO60/KBSOUT16
GPIO57/KBSOUT17
GPIO17/SCL1
GPIO22/SDA1
GPIO73/SCL2
GPIO74/SDA2
PS/2
TIMER
GPIO72/IRRX1/SIN2
GPIO70/IRRX2_IRSL0
GPIO71/IRTX/SOUT2
GPIO87/CIRRXM/SIN_CR
GPIO34/CIRRXL
GPIO16/CIRTX
GPO83/SOUT_CR/XORTR
F_SDI
F_SDO
F_CS0
F_SCK
FIU
GPIO55/CLKOUT/IOX_DIN
GPIO02
4
L44
GPIO15/A_PWM
GPIO21/B_PWM
GPIO13/C_PWM
GPIO66/G_PWM
GPIO77/SPI_DI
GPO76/SPI_DO/SHBM
GPIO75/SPI_SCK
SPI
GPIO00/32KCLKIN
NPCE781
GPIO01/TB2
GPIO03
GPIO06/IOX_DOUT
GPIO07
GPIO23/SCL3
GPIO30/CIRTX2
GPIO31/SDA3
GPIO32/D_PWM
GPIO33/H_PWM
GPIO36
GPIO40/F_PWM
GPIO42/TCK
GPIO43/TMS
GPIO44/TDI
GPIO45/E_PWM
GPIO46/CIRRXM/TRST
GPO47/SCL4
GPIO50/TDO
GPIO51
GPIO52/CIRTX2/RDY
GPIO53/SDA4
GPIO81
GPO82/TEST
GPO84/TRIST
GPIO41
GPIO56/TA1
GPIO20/TA2/IOX_DIN
GPIO14/TB1
SMB IR
GPIO37/PSCLK1
GPIO35/PSDAT1
GPIO26/PSCLK2
GPIO27PSDAT2
GPIO25/PSCLK3
GPIO12/PSDAT3
*33K/F_4
C608
*32.768KHz
*15p/50V_4
97
98
99
100
108
96
PBY160808T-250Y-N/3A/25ohm_6
C616
*15p/50V_4
VCC_POR
VCORF
<11> SIO_RCIN#
122
AGND
121
SHBM=0: Enable shared memory with host BIOS
GPIO90/AD0
GPIO91/AD1
GPIO92/AD2
GPIO93/AD3
GPIO05
GPIO04
VREF
WL_SW
T22
*0_4
AC_OFF
T60
3G_SW
10K_4
1/13 Comfirm by vendor mail :

Disabled ('1') if using FWH device on LPC.
Enabled ('0') if using SPI flash for both system BIOS and EC firmware
VGA_THERM# <23>
T6
R72
R73
10K_4
10K_4
MXM_SMCLK12
MXM_SMDATA12
R380
R376
2.2K_4
2.2K_4
ODD_EJ
2ND_MBCLK
2ND_MBDATA
R406
R85
R84
*10K_4
10K_4
10K_4
ODD_POWER
R364
10K_4
+3V
CPUFAN# <35>
PANEL_COLOR <24>
VIN_ON <38>
D/C#
<38>
S5_ON <39,48>
HDMI_HPD_EC# <25>
ODD_POWER <29>
DNBSWON# <8>
ACER ID(KBC)
T16
RF_LED_EN# <33>
PANEL_ENG <24>
10/27 modify
PANEL_ENG
ODDLED
T61
SUSON <39,43>
FANSIG <35>
32
118
62
81
84
83
82
+3VPCU
MBCLK
MBDATA
+3V_D_S
AMP_MUTE# <30>
PANEL_COLOR
CONTRAST <24>
NUMLED# <33>
PWRLED# <33>
CAPSLED# <33>
SHBM_R
RF_LED_R
R542
RSMRST#_uR
R402
*Short_4
PWROK_EC_uR
R83
*Short_4
86
87
90
92
SPI_SDI_uR
SPI_SDO_uR_R
SPI_CS0#_uR
SPI_SCK_uR_R
30
ECDB_CLOCK
T58
85
VCC_POR#
R405
104
VREF_uR
CIRR_X2
HWPG
P_SAVE_LED#
SPI FLASH(KBC)
ODD_EJ <33>
3G_EN <28>
RF_LED# <28,33>
10/27 modify
*0_4
75
73
74
113
14
114
111
+3VPCU
U28
SPI_SDI_uR R420
R425
ICH_RSMRST# <8>
SUSC# <8>
PWROK_EC <8>
RF_EN <28>
22_4 SPI_SDI_uR_R
*100K_4
7/24 modify
T59
+3VPCU
R429
10K_4
SPI_SDO_uR
SPI_SCK_uR
SPI_CS0#_uR
P_SAVE_LED# <33>
R404
22_4
SPI_SDO_uR
R403
22_4
SPI_SCK_uR
R388
47K/F_4
*Short_4
SO
VDD
SI
HOLD
SCK
WP
CE
VSS
W25X40BVSSIG
8
7
C191
0.1u/10V_4
1/13 Comfirm by vendor mail :

If the Southbridge enables 'Long Wait Abort' by
default, the flash device should be 50MHz (or faster)
+3V
HWPG(KBC)
+3VPCU
R381
+A3VPCU
10K_4
SM BUS ARRANGEMENT TABLE
<41> HWPG_VTT
<47> HWPG_1.8V
SM Bus 1
Battery
SM Bus 2
PCH
SM Bus 3
MMB3 and EEPROM
SM Bus 4
HDMI Controller, MMB1, MMB2 and VGA Thermal
<42> HWPG_1.05V
C580
<43> HWPG_1.5V
1u/6.3V_4
E775AGND
R407
SHBM_R
SHBM
SML1ALERT# <10,11,35>
ICMNT <38>
R645
SM BUS PU(KBC)
31
117
63
TEMP_MBAT <38>
VCORF_uR 44
*22_4
CLKRUN#
<11> SIO_A20GATE
A/D
103
<8>
R366
CLK_PCI_775
LFRAME
LAD0
LAD1
LAD2
LAD3
LCLK
GND1
GND2
GND3
GND4
GND5
GND6
CLK_PCI_775
3
126
127
128
1
2
5
18
45
78
89
116
<9,28> LPC_LFRAME#
<9,28> LPC_LAD0
<9,28> LPC_LAD1
<9,28> LPC_LAD2
<9,28> LPC_LAD3
<10> CLK_PCI_775
0.01u/16V_4
E775AGND
<39> SYS_HWPG
<46> HWPG_GFX
POWER-ON Switch(KBC)
D4
BAS316
D9
BAS316
D7
BAS316
D8
BAS316
D6
BAS316
D5
BAS316
HWPG
R387
*Short_4
MPWROK <4>
INTERNAL KEYBOARD STRIP SET(KBC)
+3VPCU
SW1
*MSK:NTCQ31-AB1G-A160T
NBSWON#
1
3
2
4
5
6
R60
10K_4
D1
*VPORT_6
MY0
PROJECT : ZR7B
Size
Document Number
Rev
1A
WPCE781 & FLASH

Date:
5
Sheet
1
37
of
50
PD4
SBR1045SP5-13
1
3
2
1
2
3
4
PC124
2200p/50V_6
POWER_JACK
PC117
PL5
0.1u/50V_6
UPB201212T-800Y-N/5A/80ohm_8
PC116
0.1u/50V_6
PC113
0.1u/50V_6
PD5
SMAJ20A
PR126
220K/F_6
PC15
0.1u/50V_6
PC13
2200p/50V_6
PR134
33K_6
VIN_SRC
CSIP_1
PC120
0.1u/50V_6
PD1
SW1010CPT
PR121
220K/F_6
PR137
10K_6
4
PQ30
IMD2AT108
<37>
D/C#
VIN_SRC
VIN_SRC
CSIP_1
PR39
10/F_6
PR34
4.7_6
PC34
0.1u/50V_6
CH2
CH4
VP
CH3
MBDATA
MBDATA
PR37
100K/F_6
+3VPCU
11
PR38
2.7_6
BOOT
25
SDA
UGATE
24
SCL
PHASE
23
LGATE
20
PGND
19
CSOP
18 CSOP
VDDSMB
PC29
0.1u/50V_8
PQ5
AO4468
10
ACIN
88731_LX
0.01_3720
PR138
PL6
6.8uH
BAT-V
5
6
7
8
<37>
88731_DH 4
MBCLK
MBCLK
PC129
0.1u/50V_6
PC130
2200p/50V_6
5
6
7
8
26
27
21
VDDP
VN
VCC
CH1
PD6
*RB500V-40
3
2
1
TEMP_MBAT
CSSN
PU2
CM1293A-04SO
PC24
10u/25V_1206
PC26
1u/16V_6
CSIN
NC
GND
GND
GND
GND
CSSP
+3VPCU
PC31
0.1u/50V_6
1
33
32
31
30
28
CSIP
+3VPCU
PQ36
DMN601K-7
PC32
1u/16V_6
PR40
10/F_6
BAT-V
PC123
0.1u/50V_6
PQ33
FDD6685
VIN_SRC
9/1 modify
PR130
0.01/F_7520
PQ29
FDD6685
VA1
VDC
VA
PL4
UPB201212T-800Y-N/5A/80ohm_8
<36>
PJ2
VDC
22
DCIN
PU3
ISL88731A
PR43
82.5K/F_6
2
PR42
22K/F_6
VREF
ICOMP
CSON
10/1 modify
NC
PC35
*1u/16V_6
MBDATA
<37>
BAT-V
1
2
3
BAT-V
PR12
100_4
PC232
1u/25V_6
PR17
150K_6
PR18
39K_6
<37>
PR19
100K/F_6
<37>
29
VIN
PQ26
AOL1413
reserve 0.1u cap
PR11
100_4
MBCLK
GND
ICMNT
PC38
0.01u/50V_6
+3VPCU
PR10
100_4
VBF
15
VIN_SRC
CSOP_1
PR41
2.21K/F_6
TEMP_MBAT <37>
PR13
*0_6
PC112
10u/25V_1206
BAT-V
PR33
10/F_6
PR36
SHORT_PAD_4
7
TEMP_MBAT
PC6
47p/50V_6
16
VCOMP
PD3
RB500V-40
PC5
47p/50V_6
NC
NC
PL1
UPB201212T-800Y-N/5A/80ohm_8
Batt_Conn
PC8
10u/25V_1206
10 1
2
3
4
5
6
7
9 8
17 CSON
GND
MBAT+
PC111
2200p/50V_6
12
5
UPB201212T-800Y-N/5A/80ohm_8
PL2
BAT-V
PJ1
NC
PC109
100p/50V_6
PC18
2200p/50V_6
<36>
PC27
0.1u/50V_6
14
CSOP_1
ACIN
ICM
PC110
0.1u/50V_6
1
PQ4
AO4710
CSOP_1
PC37
PC36
*0.01u/50V_6
0.01u/50V_6
<37>
VIN_ON
PR32
10/F_6
PC7
0.01u/50V_6
3
2
1
DCIN
PR21
2.2_6
88731_DL 4
PR9
*Short_6
ACOK
PC28
0.1u/50V_6
PR35
49.9/F_6
13
PQ3
DMN601K-7
PC33
3300p/50V_4
1
2
PR20
*100K/F_6
PC14
0.01u/50V_6
PROJECT : ZR7
Size
Document Number
Rev
1A
CHARGER (ISL88731)
Date:
5
Sheet

1
38
of
50
MAIND
MAIND
<36,43,47>
PR105
SHORT_PAD_4
VL
<4,48> SYS_SHDN#
VIN_SRC
D
PR243
39.2K/F_4
VIN_SRC
VL
Add 100u cap
PC214
PC102
2200p/50V_6 10u/25V_1206
PR252
SHORT_PAD_4
PC92
1u/16V_6
PC197
0.01u/16V_4
PC94
0.1u/50V_6
REF
PC204
0.1u/50V_6
PC224
PR108
*2200p/50V_6
SHORT_PAD_4
PQ71
AO4710
1
2
3
PC91
0.1u/50V_6
330u/6.3V_6X5.7
5V_DL
PD13
SX34
PR256
1/F_6
2
PR258
*0_6
PC209
0.1u/50V_6
2
PD11
CHN217UPT
+5V
PR220
+5V_GPU
PQ59
AO3413
PR110
182K/F_6
2
3V_LX
5
6
7
8
REFIN2
1
3
2
1
PL15
2.2uH_14A
change to 330u/6.3V_6x5.7
PR114
*2.2_6
SKIP
DDPWRGD_R
3V_EN
4
+
PR245
SHORT_PAD_6
PC100
*2200p/50V_6
PQ69
AO4710
PC205
0.1u/50V_6
PD10
SX34
PR255
1/F_6
PC194
330u/6.3V_6X5.7
1
PR246
1
PR249
2
*0_4
2
SHORT_PAD_4
3V_DL
PR240
SHORT_PAD_6
VL
SKIP
PR112
PR109
*0_6
OCP:8A
3
PC210
0.1u/50V_6
PR250
SHORT_PAD_6
+15V_ALWP
+15V
+3VPCU
pad 2/12 09
Iocp=8-(2.48/2)=6.67A
Vth=6.67A*15mOhm=94.714mV
R(Ilim)=(94.714mV*10)/5uA
~191K
PR264
dGPU_5V_EN 2
REF
L(ripple current) 0 ohm change to shot

=(19-3.3)*3.3/(2.2u*0.5M*19)
~2.48A
PR257
SHORT_PAD_6
PD12
CHN217UPT
*0_6
PC207
1u/16V_6
PC99
0.1u/50V_6
10K_4
+3VPCU
PU11
RT8206B
0.75A
10K_4
PR104
100K/F_4
DDPWRGD_R
SYS_HWPG <37>
PR248
22_8
32
31
30
29
28
27
26
25
REFIN2
ILIM2
OUT2
SKIP#
PGOOD2
EN2
DH2
LX2
PR211
*0_6
PC191
0.1u/50V_6
PC93
10u/25V_1206
+5VPCU
BYP
OUT1
FB1
ILIM1
PGOOD1
EN1
DH1
LX1
PAD
PAD
17
18
19
20
21
22
23
24
1
2
3
PR267
*2.2_6
PC201
9
10
11
2
12
200K/F_6 DDPWRGD_R 13
5V_EN 14
15
16
37
36
PAD
PAD
PAD
PR247
*0_4
8
7
6
5
1
PR111
OCP : 8A
PQ70
AO4468
3V_DH
3
2
1
+5VPCU
5V_LX
PC98
10u/25V_1206
PC95
2200p/50V_4
8
7
6
5
4
3
2
1
PQ68
AO4468
PL16
2.2uH_14A
PR101
150K_4
5V_DH
LDOREFIN
LDO
VIN
NC
ONLDO
VCC
TON
REF
PC101
0.1u/50V_6
BST1
DL1
PVCC
NC
GND
PGND
DL2
BST2
Iocp=10-(4.18/2)=7.91A
Vth=7.91A*14.2mOhm=112.322mV
R(Ilim)=(112.322mV*10)/5uA
~220K
PR103
35
34
33
+5VPCU
8
7
6
5
OCP: 10A
L(ripple current)
=(19-5)*5/(2.2u*0.4M*19)
~4.18A
PR106
*0_4
5
6
7
8
PC198
0.1u/50V_6
OCP:10A
PR102
390K_4
3V_EN
5V_EN
100u/25V_6X5.7
PR107
SHORT_PAD_4
PR239
SHORT_PAD_4
PR251
SHORT_PAD_4
PC223
PC199
4.7u/10V_8
3V5V_EN
PC218
10u/25V_1206
PC215
0.1u/50V_6
SHORT_PAD_4
PC221
0.1u/50V_6
PQ63
DMN601K-7
+5VPCU
+3VPCU
<11> dGPU_PWR_EN#
8/12 modify
VIN_SRC
+15V
MAIND
+3VPCU
PR212
1M_6
PR79
22_8
PR76
22_8
PR74
3G@1M_6
SUSD
PQ61
DMN601K-7
PQ62
DMN601K-7
0.23A
AO4496
2.2n/50V_4
PQ58
DMN601K-7
3
2
PR77
1M_6
PC65
PQ15
DMN601K-7
PQ16
DMN601K-7
PROJECT : ZR7
Date:
+3V
3G@DMN601K-7
Size
7/9 add +3VSUS for 3G option
+5V_S5
3.11A
+5V
+3VSUS
PQ14
2.85A
5
2A
2.17A
7/28 BOM option for 3G or WL
PQ13
2.2n/50V_4 3G@AO6402A
PQ25
L26
*3G@0_8
2
PQ17
DTC144EU
+3V_S5
3
2
1
PC185
PQ57
DTC144EU
2
2
PQ23
AO4496
4
SUSON
2
2
PR232
1M_6
+3V
PQ22
<37,43>
AO3404
S5D 2
S5D
PQ24
AO4496
3
2
1
PR223
22_8
<37,48> S5_ON
MAIND 4
+3VPCU
PR75
1M_6
3
2
1
PR215
22_8
+5VPCU
1
2
5
6
PR233
1M_6
+15V
+5V_S5
+3V_S5
+SMDDR_VREF
5
6
7
8
VIN_SRC
+1.5V_SUS
5
6
7
8
7/7 Add +5V_GPU
5
6
7
8
PQ60
DMN601K-7
Document Number
Rev
1A
SYSTEM 5V/3V (RT8206)

Sheet
1
39
of
50
[PWM]
PR71, PR72, PR73, PR74, PR75, PR76, and PR77 deleted

VR_PWRGD_CK505# <3>
VIN
1
<4,8>
1
DELAY_VR_PWRGOOD
PC61
10u/25V_1206
PC164
10u/25V_1206
+
PC59
0.1u/50V_6
PC150
100u/25V_6X7.7
PC159
2200p/50V_6
PQ44
AOL1448
8/4 EMI request

62882_DH1
4
D
1
2
3
+VCC_CORE
+3V
PL11
1
5
PQ49
AOL1718
PQ48
AOL1718
62882_LX1
PR72
SHORT_PAD_6
0.36uH
2
4
VIN
PR73
+ PC66
*2.2/F_6
330u/2V_7343
4
1
2
3
PC62
0.22u/25V_6
PR71
10_6
PC63
*1000p/50V_6
5/12 Change pr144 from 10K to 1.91K
SHORT_PAD_8
RBIAS
<4> H_PROCHOT#
19
PHASE1
VR_TT#
LGATE1a
<6>
H_VID4
<6>
H_VID5
<6>
H_VID6
H_VID1
32
H_VID2
33
VID2
H_VID3
34
VID3
H_VID4
35
H_VID5
36
VID5
37
VID6
H_VID6
<6> H_DPRSLPVR
VR_ON
38
DPRSLPVR
39
VID1
PC153
0.22u/10V_4
PC176
10u/25V_1206
PC179
100u/25V_6X7.7
VCCP
ISL62882
PR198
25
8/4 EMI request
SHORT_PAD_4 +5V_S5
PC168 1u/6.3V_4
1
2
+VCC_CORE
PC64 1u/6.3V_4
1
2
VR_ON
DPRSLPVR
UGATE2
FB
FB2
30
28
LGATE2
26
ISEN2
PQ50
AOL1718
0.36uH
2
PR83
+ PC70
4
*2.2/F_6
PC167
0.22u/25V_6
330u/2V_7343
PR161
PC73
*1000p/50V_6
27
PR167
SHORT_PAD_4
SHORT_PAD_4
B
62882_ISEN2
10
1
PC52
1
PL12
1
62882_DL2 4
PHASE2
VSSP2
62882_LX2
PQ51
AOL1718
29
PQ52
AOL1448
62882_DH2 4
VID4
PC151
22p/50V_4
PC74
10u/25V_1206
8/10 modify
BOOT2
PR54
412K/F_4
PC75
0.1u/50V_6
VSUM-
PR193
2.2_6
PR65
*10K/F_4
PC177
2200p/50V_6
62882_ISEN1
11
VID0
PR180
499/F_4
PR183
100K/F_4
22
2
ISEN1
31
H_VID3
62882_DL1B
24
<6>
10K/F_4
1
2
3
H_VID2
1/F_4
PR63
H_VID1
<6>
PR178
62882_DL1A
23
<6>
3.65K/F_4
VSUM-
PC166
0.22u/25V_6
21
VIN
LGATE1b
H_VID0
VRON
2
<37>
H_VID0
10K/F_4
PR175
NTC
VSSP1
<6>
PR59
VSUM+
2
PR190
2.2_6
PR53
*4.02K/F_4
PC56
*0.01u/16V_4
1
2
PR188
*470K_4 NTC
Close to Phase 1 Inductor
PSI#
147K/F_6
1
2
3
PR64
10K/F_4
PR164
20
BOOT1
PSI#
H_PSI#
UGATE1
1
2
3
PR165
*499/F_4
<6>
40
17
PAD
7/16 modify
PR179
SHORT_PAD_4
SHORT_PAD_4
PGOOD
41
CLK_EN#
PC60
1u/6.3V_4
+1.1V_VTT
VIN
VDD
16
PR176
PU8
PR60
PR163
1.91K/F_4
1
2
3
PR177
1.91K/F_4
+5V_S5
150p/50V_4
COMP
2
PC152
0.22u/10V_4
VSUM8/10 modify
PR52
8.06K/F_4
VW
IMON
18
PR191
9.76K/F_4
<6>
ISUM+
ISUM-
RTN
10K/F_4
PR160
3.65K/F_4
VSUM-
PR166
1/F_4
PR58
10K/F_4
VSSSENSE
5/12 Change pc92 rom 0.33u_4 to 0.22u_6

5/12 stuff pc26 0.068u_6
15
2.7K/F_4
14
12
PR55
13
VSEN
5/12 Change pr24 rom 2.87K to 2.8K
PR51
VSUM+
PC165
0.033u/16V_4
PC53
1000p/50V_4
PC162
0.22u/10V_6
PC55
390p/50V_4
PC161
0.068u/25V_6
VSUM+
PR56
562/F_4
I_MON
1
PC154
10p/50V_4
PR171
82.5/F_4
2
*27.4_4
PC57
PR57
2.61K/F_4
1
PR61
+VCC_CORE
PC160
SHORT_PAD_4
PR68
SHORT_PAD_4
330p/50V_4
PC155
330p/50V_4
Parallel
PR62
PC156
0.01u/16V_4
PC58
1
PR67
2
*27.4_4
1000p/50V_4
2700p/50V_4
<6> VSSSENSE
<6> VCCSENSE
A
PR184
11K/F_4
PR194
10K _6_NTC
PR185
SHORT_PAD_4
Panasonic
ERT-J1VR103J
VSUM-
5/12 Change pr34 rom 1K to 1.24K

PR181
1.24K/F_4
PC157
*1000p/50V_4
PR174
*100/F_4
PC158
0.1u/10V_4
Close to Phase 1 Inductor
Load Line setting to 2mV/A
PROJECT : ZR7
Size
5/12 un-stuff PC76,PR140

Date:
5
Document Number
Rev
1A
CPU Core ( ISL62882)

3
Sheet
1
40
of
50
[PWM]
VIN
+5V_S5
PD7
RB500V-40
PR45
*10K/F_6
<37> HWPG_VTT
PC40
1u/16V_6
EN/DEM
16
BOOT
13
TON
UGATE
12
VOUT
PHASE
11
VDD
OC
10
FB
PGOOD
GND
NC
14
NC
VDDP
PC141
2200p/50V_4
PQ39
AOL1448
PC143
0.1u/50V_6
PC140
PC42
0.1u/50V_6
10u/25V_1206
PC41
*10u/25V_1206
PL9
UGATE-VTT
PHASE-VTT
PR152
PGND
TPAD
17
+1.1V_VTT
3.92K/F_6
2.2uH
PL8
PC139
LGATE
2.2uH
PC45
*0.1u/50V_6
15
1.05V/15A
OCP: 18A
+
1u/16V_6 LGATE-VTT
PR147
*4.7_6
4
1
2
3
+3V
PC138
4.7u/6.3V_6
1
2
3
PR154
SHORT_PAD_6
PU6
UP6111AQDD
<37,42,43,47> MAINON
PR155
1M/F_6
PR156
SHORT_PAD_6
PR149
2.2/F_6
PR153
10_6
D
PQ38
AOL1718
PC39
330u/2V_7343
PC137
*680p/50V_6
PC43
330u/2V_7343
PC135
0.1u/50V_6
PC136
10u/10V_8
PC44
*1000p/50V_6
VOUT=(1+R1/R2)*0.75
R1
PR151
4.02K/F_6
R2
PR150
10K/F_6
PC142
*33p/50V_6
VTT_FB
PR44
SHORT_PAD_6
B
AO1718 Rdson=3~4.3mOhm
L(ripple current)
=(19-1.05)*1.05/(1u*272k*19)
~3.64A
TON=3.85p*RTON*Vout/(Vin-0.5)
Frequency=Vout/(Vin*TON)
9/4 modify
TON=3.85p*1M*1/(Vin-0.5)
4.3m*18=RILIM*20uA
RILIM=3.87K --- 3.92K
Frequency=1/(0.0036767)=272K
A

PROJECT : ZR7
Size
Document Number
Rev
1A
+VTT (UP6111A)
Date:
5
Sheet
1
41
of
50
VIN
+5V_S5
PD14
RB500V-40
PU13
UP6111AQDD
+3V
PC219
*0.1u/50V_6
EN/DEM
16
1
PR271
*10K/F_6
1
2
TON
UGATE
12
VOUT
PHASE
11
OC
10
VDD
FB
PC106
1u/16V_6
13
<37> HWPG_1.05V
BOOT
PGOOD
VDDP
LGATE
GND
PGND
NC
TPAD
17
14
NC
5
6
7
8
PQ72
AO4468
PC222
0.1u/50V_6
3
2
1
15
1.05V/8A
OCP: 10A
4
PC105
2200p/50V_4
PC225
0.1u/50V_6
PC227
10u/25V_1206
PL18
2.2uH_8A
UGATE-1.05V
PHASE-1.05V
PR117
+1.05V
3.9K/F_6
8/24 modify
5
6
7
8
MAINON
PC230
4.7u/6.3V_6
PC228
1u/16V_6
LGATE-1.05V
PR273
*4.7_6
Rds*OCP=RILIM*20uA
PQ73
AO4710
PC231
*680p/50V_6
3
2
1
PR115
SHORT_PAD_6
<37,41,43,47>
PR266
SHORT_PAD_6
PR272
2.2/F_6
PR265
1M_6
PR116
10/F_6
PC104
10u/10V_8
PC220
*1000p/50V_6
PC103
0.1u/50V_6
PC229
560u/2.5V_6X5.7
R1
PR268
4.02K/F_6
1.05V_FB
PC226
*33p/50V_6
VOUT=(1+R1/R2)*0.75
R2
PR269
10K/F_6
PR270
SHORT_PAD_6
TON=3.85p*RTON*Vout/(Vin-0.5)
Frequency=Vout/(Vin*TON)
A
TON=3.85p*1M*1/(Vin-0.5)
Frequency=1/(0.0036767)=272K
AO4710 Rdson=11.7~14.2mOhm
L(ripple current)
=(19-1.05)*1.05/(1u*272k*19)
~3.646A
14.2m*10=RILIM*20uA
RILIM=7.1K--- 7.15K
PROJECT : ZR7
Size
Rev
1A
VCCP 1.05V(UP6111A)
Date:
Document Number
Sheet
1
42
of
50
[PWM]
36
PC174
10u/10V_8
PR206
SHORT_PAD_6
PC175
0.1u/50V_6
+0.75V_DDR_VTT
VIN
8207_DH
PC173
10u/10V_8
8207_LX
5
PC172
10u/10V_8
2A
8207_DL
VTTGND
1
2
3
19
DRVL
20
LL
21
DRVH
22
VBST
CS_GND
17
16
V5IN
15
FOR DDR III
V5FILT
14
PGOOD
13
1
2
3
1
2
PC69
1u/6.3V_4
100K/F_6
VIN
+3VPCU
(For RT8207A
PR199
SHORT_PAD_6SUSON
PR200
PR78
PR202
*0/F_6
PC77
*680p/50V_6
PC170
1u/6.3V_4
PC171
560u/2.5V_6x5.7
+5V_S5
Add it for S3 leakage circuit

7/23 modify
4.6m*12=RILIM*10uA
RILIM=5.62K
PR81
SHORT_PAD_6
PC67
*33p/50V_6
PR203
10K/F_4
PC72
10u/10V_8
AO1412 Rdson=3.8~4.6mOhm
OCP=12.21+0.5A
L(ripple current)
=(19-1.5)*1.5/(2.2u*400k*19)
~1.57A
400KHZ )
<37,39>
SHORT_PAD_6
MAINON <37,41,42,47>
*0/F_6
PWRGD_1.5VCPU <36>
PC169
*560u/2.5V_6x5.7
HWPG_1.5V <37>
S5_1.8V
S3_1.8V
PQ54
AOL1718
1
2
PR204
PR201
620K/F_4
PR84
*4.7_6
4
PR205
5.1/F_6
NC
S5
COMP
+5V_S5
PR82
4.99K/F_6
12
VTTREF
NC
11
+5V_S5
PC71
0.033u/50V_6
S3
0.003A
VDDQSET
+SMDDR_VREF
12A
18
CS
MODE
+1.5V_SUS 4
10
RT8207A
PU9
GND
VDDQSNS
PC180
10u/25V_1206
PL13
1.5uH
+1.5V_SUS
PGND
VTTSNS
PC178
PC76
2200p/50V_6 10u/25V_1206
PQ53
AOL1448
VLDOIN
23
24
GND
VTT
25
(10u*PR35)/Rdson+Delta_I/2=Iocp
Vout = (PR150/PR149) X 0.75 + 0.75
+1.5V_SUS
PC68
*0.033u/50V_6
PR80
10K/F_4
<36,39,47> MAIND
+1.5V_SUS
VIN
MAIND
SW@
2
PQ18
AO3404
+15V
+1.5V
5
6
7
8
PR69
SW@1M/F_6
PR50
SW@1M/F_6
2.03A
PR66
SW@1M/F_6
2
PC49
*SW@2.2n/50V_4
3
2
1
<47> PG_1.5V_EN
PQ9
SW@AO4496
PQ10
SW@DMN601K-7
1
PQ11
PR70
SW@DTC144EUA
*SW@100K_4
+1.5V_GPU
3.94A
PROJECT : ZR7
Size
Document Number
Rev
1A
DDR III 1.5V(TPS51116)

Date:
5
Sheet

1
43
of
50
+5V_GPU
VIN
PC121
SW @10u/25V_1206
8792VCC
SW @1u/10V_6
8792PGD
<45> PG_GPUIO_EN
8792EN
<11,21> dGPU_VRON
PR119
*SW @0_4
14
1
PR8
TON
DH
8792TON
8792DH
8792BST
BST
PC20
SW @2200p/50V_4
LX
8792LX
DL
8792DL
FB
ILIM
PR15
SW @1_6
PC12
SW @0.22u/25V_6
8792SKIP# 12
SKIP#
8792REFIN 10
REFIN
PC122
SW @10u/25V_1206
PL7
SW @0.36uH
PU1
EN
+VGPU_CORE
PQ37
SW @AOL1448
PGOOD
*SW @0_4
PR120
SW @SHORT_PAD_4
PR118
VCC
MAX8792ETD+T
change net name

PC1
SW @0.1u/10V_4
+3V_D_S
13
VDD
OCP=35A
PC21
SW @10u/25V_1206
PC2
1
2
3
SW @1u/10V_6
PC4
PR4
SW @100K_4
PC19
SW @0.1u/50V_6
PR16
SW @200K/F_4
A
29A
PR125
*SW @0_4
+3V_D_S
PR22
SW @1_8
4
REF-2V
8792ILIM
PC30
*SW @330u/2V
1
2
3
REF
PC17
SW @1000p/50V_4
EP
11
1
2
3
8792REF
SW @100K_4
15
PR127
SW @44.2K/F_4
PR128
SW @62K/F_4
PR1
SHORT_PAD_6
PC16
*SW @4700P/25V_4
PQ35
SW @AOL1718
PQ34
SW @AOL1718
PC133
SW @0.1u/50V_6
PC134
SW @330u/2V
PC25
SW @330u/2V
Place near GND pin15
PR123
SW @470K/F_4
PC11
SW @1000P/50V_4
PR14
SW @100K_4
VID1
PQ27
SW @2N7002E
<17> VCORE1.2ID0
Frequency(PR220=200K)
300K
Madison VID Table
PR129
SW @49.9K/F_4
PR122
SW @100K_4
VID1
VID2
changed value on 09/17
VCORE1.2ID0
PC108
SW @0.01u/16V_4
changed to vga_gnd
PR5
SW @220K/F_4
VID2
LOW (0)
LOW (0)
1.05V
HIGH (1)
LOW (0)
1.0V
LOW (0)
HIGH (1)
0.95V
HIGH (1)
HIGH (1)
0.90V
=
=
=
=
44.2K
49.9K
470K
220K
PARK VID Table

VID1
PR3
SW @100K_4
VCORE1.2ID0
C
PR127
PR129
PR123
PR5
+VCC_GFX_CORE
PQ1
SW @2N7002E
<17> VCORE1.2ID1
VCORE1.2ID1
PC3
SW @0.01u/16V_4
PR127
PR129
PR123
PR5
VID2
VCORE1.2ID1
+VCC_GFX_CORE
LOW (0)
LOW (0)
1.12V
HIGH (1)
LOW (0)
1.05V
LOW (0)
HIGH (1)
0.95V
HIGH (1)
HIGH (1)
0.90V
=
=
=
=
39.2K
49.9K
332K
130K
CS33922FB15
CS43322FB15
CS41302FB00
C
VIN_SRC
+VGPU_CORE
PR2
SW @22_8
PR7
SW @1M_6
change net name
8792EN
PQ28
SW @DTC144EU
PR6
SW @1M_6
PQ2
SW @MF2N7002E-G
take out PR318, PQ79, PC258, and PR320
take out PR322

PROJECT : ZR7
Size
Document Number
Rev
1A
GPU CORE(MAX8792)
Date:
1
Sheet
5
44
of
50
[PWM]
+5V_GPU
PC119
SW@10u/10V_8
PR131
SW@0_6
62872_PVCC2
PR132
SW@2.2_6
VIN
D
IO_VID1_R
PR144
EN
VID1
*0_4
IO_VID0
IO_VID0_R
VID0
62872_SREF
PU5
SW@ISL62872
5
6
7
8
20
BOOT
18
UGATE
17
PR135
SW@2.2_6
PHASE
16
NC
15
SREF
OCSET
14
SET0
VO
13
SET1
FB
12
82872_AGND
2
PC115
SW@2.2n/50V_4
PC126
SW@0.22u/25V_6
62872_DH
PC114
SW@10u/25V_1206
PC9
PC10
SW@0.1u/50V_6
SW@10u/25V_1206
PQ32
SW@AO4468
10
82872_AGND
8/24 modify
PR124
*4.7_6
PR23
SW@0_4
PR26
SW@0_4
62872_FB
3
2
1
PGOOD
62872_OCSET
PC107
*680p/50V_6
PQ31
SW@AO4710
PC132
PC127
PC125
SW@560u/2.5V_6X5.7SW@10u/10V_8 SW@0.1u/50V_6
11
SET2
1
2
PR28
SW@26.7K/F_6
4.5A
DCR(max)=20mohm
PL3
SW@2.2uH_8A
1
2
PC23
SW@47n/16V_6
JP4
SHORT PAD
62872_LX
PR29
SW@15.8K/F_6
19
5
6
7
8
<17>
GND
4
VCC
*SW@0_4
<44> PG_GPUIO_EN
C
+VGPU_IO
PR136
PGND
PC22
SW@0.1u/50V_6
3
2
1
82872_AGND
62872_DL
PC118
SW@10u/10V_8
PVCC2
PR133
SW@0_6
LGATE
PC131
SW@2700p/50V_4
2
PR25
SW@17.4K/F_6
2
1
PR30
SW@100/F_6
PG_1V_EN_1
PC128
SW@0.1u/25V_4
PR143
SW@11.5K/F_6
+3VPCU
PR27
SW@249K/F_6
PR145
SW@28K/F_6
8/10 modify
1
PR31
SW@24K/F_6
PR142
SW@17.4K/F_6
2
1
82872_AGND
8/24 modify
PR141
*10K/F_4
PR24
*10K/F_4
+3V_D_S
IO_VID0_R
IO_VID1_R
change to "stuff"
PR275
PR140
SW@10K/F_4
PR139
SW@10K/F_4
PR146
SW@10K/F_6
PG_1V_EN_1
PR274
<47> PG_1V_EN
SW@0_4
*SW@0_4
PG_GPUIO_EN
PROJECT : ZR7
PG_GPUIO_EN
Size
<44>
Rev
1A
+VGPU_IO(ISL62872)
Date:
Document Number
Sheet
1
45
of
50
Int_VGA
[PWM]
<6> GFX_VID0
<6> GFX_VID1
+1.1V_VTT
+1.1V_VTT
<6> GFX_VID2
<6> GFX_VID3
1
PR98
*0_6
<6> GFX_VID4
PR97
*0_6
PR217
*0_6
PR96
*0_6
PR93
*0_6
PR88
*0_6
PR87
*0_6
<6> GFX_VID5
<6> GFX_VID6
GFX_VID6
62881_GND
GFX_ON
SHORT_PAD_4
PR227
SHORT_PAD_4
GFX_VID6
GFX_VID5
GFX_VID4
GFX_VID3
GFX_VID2
25
24
23
22
47K/F_4
PR235
8.06K/F_4
VID2
VID3
VID4
VID5
VID6
VID1
21
62881RBIAS
62881VW
RBIAS
VID0
VW
VCCP
PU4
20
19
ISL62881HRZ-T
PHASE
PC87
16 62881PHASE
BOOT
15 62881UGATE
4
14
IMON
13
VIN
12
VDD
11
PR90
62881BOOT
62881VIN
62881VDD
10
ISUM-
62881ISUM+
62881RTN
PC86
330p/50V_4
62881ISUM-
PC90
330p/50V_4
ISUM+
VSEN
RTN
UGATE
17
FB
PQ55
AOL1718
PC81
PQ19
AOL1718
PR95
2.61K/F_4
0.22u/25V_6
PR89
*19.1K/F_4
PC192
560u/2.5V_6X5.7
PR92
11K/F_4
PC187
0.15u/10V_4
PC85
0.1u/10V_4
PC190
47n/10V_4
+5V_S5
62881_GND
0616 change to 2.49k
PR216
PC189
VIN
PC186
0.22u/25V_6
62881_GND
PC82
10u/6.3V_8
PC83
*0.022u/25V_4
62881_GND
PR214
SHORT_PAD_4
PC184
560u/2.5V_6X5.7
DCR=1.6~1.8mOhm
Load Line=7mV/A
1.6m*0.6168=0.986m
0.986m/.49K=396p
392p*2*8.87K=7.03m
OCP
20u/2*2.49K=24.9m
24.9m/0.6168=40.3m
40.3m/1.6m=25.2A
GFX_IMON <6>
VSS_AXG_SENSE
PR209
10K _6_NTC
PC181
*680p/50V_6
GFX_IMON
1000p/50V_4
PR91
3.65K/F_4
PR207
*4.7_6
1_6
62881_GND
+VGFX_AXG
PL14
0.56uH
1
2
3
VSSP
6
PC89
150p/25V_4
22A
18 62881LGATE
0616 change to 22pF
0616 change to 8.87k

PR100
8.87K/F_4
62881VSEN
0616 change to 150pF
LGATE
COMP
17.8K/F_4
0616 change to 0.56uH
62881COMP 5
62881FB
PC196
100p/50V_4
PC183
2.2n/50V_4
PQ56
AOL1448
PC80
PC195
22p/50V_4
PC182
10u/25V_1206
4.7u/6.3V_6
1000p/50V_4
PR236
PC79
10u/25V_1206
0.1u/50V_6
+5V_S5
PC88
PR237
820K/F_4
GFX_VID0
5
PGOOD
1
2
3
PR225
GFX_VID1
62881VR_ON
26
VR_ON
CLK_EN#
GFX_VID0
1
2
3
62881_GND
PR226
*150K/F_4
62881_GND
GFX_VID2
PC78
GFX_VID1
62881PGOOD
DPRSLPVR
1
SHORT_PAD_4
GND
PR234
1.91K/F_4
PR99
27
62881_GND
29
+3V
<37> HWPG_GFX
GFX_VID3
VIN
62881_GND
GFX_VID4
short
62881DPRSLPVR
PR219
PR222
28
<6>
<6> GFX_DPRSLPVR
GFX_VID5
PC193
*0.01u/25V_4
2
1
PC188
*180p/50V_4
PR224
2.49K/F_4
10_6
1u/6.3V_4
PR221
*100/F_4
62881_GND
PR94
82.5/F_4
Parallel
PR228
PR229
PC84
2
1
0616 un-mount
0.01u/25V_4
10/F_4
SHORT_PAD_4
VSS_AXG_SENSE <6>
PR231
PR230
10/F_4
SHORT_PAD_4
VCC_AXG_SENSE <6>

PROJECT : ZR7
Size
1.Level 1 Environment-related Substances Should NEVER be Used.
2.Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as Green Partners.
A
Document Number
Rev
1A
+VGFX_AXG (ISL62881)
Date:
Sheet
46
H
of
50
1.76A
+3VPCU
+1.8V
PC97
0.1u/25V_4
PC212
10u/10V_8
PU12
16
PR113
SHORT_PAD_4
MAINON
VIN
PH
11
VIN
PH
12
BOOT
13
15
54418-1.8_VFB
PC203
1000p/50V_4
PWRGD
COMP
GND
RT/CLK
SS
PR261
182K/F_4
PC216
*100P/50V_4
VSNS
PL17
1.0uH/11A_7X7X3
D
PR254
SHORT_PAD_6
PC206 0.1u/50V_6
14
PR263
51.1/F_4
GND
AGND
R1
HWPG_1.8V <37>
PR253
100K/F_4
PC213
0.01u/25V_4
MAINON <37,41,42,43>
PR262
100K/F_4
+3VSUS
22
21
20
19
18
17
PR259
15K/F_4
MAINON
EN
DCR(max)=10mohm
10
PH
PAD
PAD
PAD
PAD
PAD
PAD
HPA00835RTER
VIN
PC208
0.1u/25V_4
PC96
10u/10V_8
PC211
10u/10V_8
54418-1.8_VFB
PC217
1200p/50V_4
V0=0.8*(R1+R2)/R2
PR260
78.7K/F_4
R2
+3VPCU
C
SW@
2A
+1V
PC149
SW@0.1u/25V_4
PU7
1
PR159
SW@SHORT_PAD_4
2
15
<45> PG_1V_EN
54418-1_VFB
PC144
SW@1000p/50V_4
7
8
9
PR168
SW@182K/F_4
PC51
*SW@100P/50V_4
VIN
PH
VIN
PH
EN
BOOT
VSNS
PWRGD
COMP
GND
RT/CLK
SS
GND
AGND
DCR(max)=10mohm
PL10
SW@1.0uH/11A_7X7X3
11
12
PR157
13
SW@SHORT_PAD_6
PC147
SW@0.1u/50V_6
14
PR173
SW@51.1/F_4
R1
4
PG_1.5V_EN <43>
PR158
SW@10K/F_4
PR170
SW@20K/F_4
+3VSUS
22
21
20
19
18
17
PR169
SW@8.06K/F_4
SW@HPA00835RTER
PH 10
VIN
PAD
PAD
PAD
PAD
PAD
PAD
16
PC145
PC146
PC48
SW@0.1u/25V_4
SW@10u/10V_8
SW@10u/10V_8
PC50
SW@0.01u/25V_4
54418-1_VFB
PC54
SW@1200p/50V_4
PR162
SW@78.7K/F_4
R2
+1.8V
V0=0.8*(R1+R2)/R2
VIN_SRC
+15V
PR49
SW@1M/F_6
SW@
PR46
SW@1M/F_6
1
2
5
6
PC148
SW@10u/10V_8
change p/n
PQ6
SW@SWAO6402A
Add it for S3 leakage circuit
PR187
22_8
2
PR48
SW@1M/F_6
+1.05V
PR172
22_8
+1.5V
PR182
22_8
+15V
7/9 change power enable

net name to +1.5V_GPU
(ZY9B solution)
PR196
22_8
PR197
22_8
PQ8
PC46
SW@DMN601K-7 *SW@2.2n/50V_4
PQ7
SW@PDTC143TT
+1.8V_GPU
1.41A
+1.1V_VTT
PR192
1M/F_6
<36> MAINON_DIS_G
+5V
+3V
VIN_SRC
PR47
SW@SHORT_PAD_4
+1.5V_GPU
PC47
SW@1u/10V_4
PR189
1M/F_6
7/23 modify
MAINON_G
MAIND
MAIND
<36,39,43>
PQ40
DMN601K-7
PC163
*2.2n/50V_4
7/7 modify
PQ45
DMN601K-7
DMN601K-7
PQ46
DMN601K-7
PROJECT : ZR7
PQ43
DMN601K-7
PQ42
DMN601K-7
2
PQ41
1
PQ47
DTC144EUA
2
2
PR195
*100K_4
PR186
1M/F_6
<37,41,42,43> MAINON
Size
Document Number
Rev
1A
Discharge/1.8V)
Date:
5
Sheet

1
47
of
50
VIN_SRC
A
PR241
1M_6
PD9
SW1010CPT
PQ65
AO3409
TH_ON 2
VL
2
PQ66
DTC144EUA
VL
Thermal protection
S5_ON
S5_ON
<37,39> S5_ON
SYS_SHDN# <4,39>
PR218
1K_4
PR242
200K/F_4
PR244
200K_6
PC200
0.1u/50V_6
2.469V
NTC
2
PQ67
DMN601K-7
PU10A
LM393
PC202
0.1u/50V_6
PR238
200K/F_4
+3VPCU
PR148
10K _6_NTC
VL
S5_ON
2
PR208
100K/F_6
PQ64
DMN601K-7
PR210
10K/F_6
5
4.95V
PD8
+
NC_TEMP
T75
PU10B
LM393
RB500V-40
For EC control thermal protection (output 3.3V)
PR213
1M/F_6

PROJECT : ZR7
Size
Document Number
Rev
1A
Thermal Protection
Date:
1
Sheet
5
48
of
50
300 mil
ISL62882 1800 mil
1800 mil
U3031
200 mil
AO6402A
200 mil
D
520 mil
+5V
PQ35
+5VPCU
AO4496
+5V_TMA
AO6402A
U50
CN27
U6
U22
U33
CN1
CN2
CN34
CN36
CN30
CN15
20 mil
40 mil
40 mil
20 mil
20 mil
20 mil
30 mil
20 mil
80 mil
80 mil
80 mil
20 mil
CN19
CN20
CN10
CN43
CN12
CN16
CN41
U2
20 mil
20 mil
20 mil
20 mil
20 mil
20 mil
20 mil
20 mil
280 mil
40 mil
+5V_S5
PQ38
200 mil
System
Charger
ISL6251A
U3035
40 mil
CN9
280 mil
PQ82
ISL6237
PU4
40 mil
AC
U38
280 mil
400 mil
CPU
VCC_CORE
PU7
+5VPCU
U3035
PU7
PU8
PU9
PU10
PU6
PU11
20 mil
20 mil
20 mil
20 mil
20 mil
20 mil
20 mil
R330
R3691
U45
ESD1
U23
CN15
CN14
20 mil
10 mil
20 mil
30 mil
20 mil
20 mil
20 mil
CN39
CN6
U4
U19
U14
CN5
R428
20 mil
10 mil
70 mil
10 mil
70 mil
130 mil 20 mil
VIN
DC
PU2
40 mil
+3VPCU
D30
MR1
CN14
U16
U8
R429
PU12
20 mil
15 mil
20 mil
30 mil
20 mil
20 mil
20 mil
R164
15 mil
R586
R437
L22
U9
PU2
20 mil
10 mil
10 mil
20 mil
10 mil
+3VPCU
250 mil
AO4496
PQ25
150 mil
AO6402A
250 mil
+3V
150 mil
U15
10 mil
R3343
20 mil
R649
20 mil
R462
30 mil
L3035
15 mil
R184
30 mil
U5
Q6
U33
U27
U18
U44
R655
20 mil
65 mil
15 mil
20 mil
20 mil
20 mil
20 mil
R327
CN12
CN18
U29
U13
CN5
R158
30 mil
20 mil
20 mil
100 mil 20 mil
20 mil
20 mil
G973
30 mil
+3V_S5
PQ7
L26
20 mil
120 mil
U3031
R3301
R3268
30 mil
15 mil
15 mil
R198
U21
U3017
U29
20 mil
15 mil
20 mil
30 mil
40 mil
+1.8V
PU11
R654
Q22
20 mil
120 mil 30 mil
CN17
R3234
R34
15 mil
15 mil
R3587
15 mil
R619
20 mil
R36
20 mil
L25
15 mil
R17
20 mil
R167
10 mil
R192
30 mil
R195
30 mil
U3010
10 mil
CN27
80 mil
R710
L57
CN11
R496
R499
20 mil
20 mil
40 mil
120 mil 30 mil
R11
R29
CN3
R3289
R3292
20 mil
20 mil
20 mil
40 mil
20 mil
R711
L28
R3291
40 mil
25 mil
20 mil
U3044
U11
R151
20 mil
15 mil
30 mil
20 mil
G909
20 mil
+1.5V_S5
PU12
200 mil
250 mil
UP6111A
PU10
400 mil
UP6111A
PU9
600 mil
R3340
R448
R165
L3055
R3570
20 mil
80 mil
20 mil
15 mil
150 mil 15 mil
L3047
R185
R3644
L3058
R195
15 mil
30 mil
60 mil
15 mil
30 mil
+SMDDR_VTERM
TPS51116
JDIM3001
JDIM3002
40 mil
40 mil
20 mil
600 mil
A
300 mil
+1.5VSUS
AO4496
PU8
R3304
15 mil
L3046
L3048
R186
R454
R455
15 mil
15 mil
40 mil
50 mil
50 mil
400 mil
+VAXG
Q39
U3031
10 mil
600 mil 15 mil
R3243
R195
15 mil
300 mil
JDIM3001
100 mil
R3302
CN17
CN9
15 mil
30 mil
180 mil 20 mil
U18
R69
R668
U29
30 mil
30 mil
60 mil
R676
A
+1.5V
PQ23
400 mil
ISL62881
15 mil
R3326
20 mil
+SMDDR_VREF
PU6
200 mil
R180
+VTT
80 mil
200 mil
R3056
+1.05V
JDIM3002
100 mil
30 mil
U3031
350 mil
U3031
350 mil
PROJECT : ZR7B
Size
Document Number
Date:
Rev
1A
POWER MANAGEMENT
5
Sheet
49
of
50
MODEL
Model
CHANGE LIST
REV
1A
ZR7
FRO M
10/6 1. Change Hole13,14,15,16,18,19,20,21,27 for layout requirement__P35

2. Rename__All
ZR7B MB
To
1A
1A
1A
3. Unstuff R203, R171__P27
10/12 1. PQ6 and +1V power system add SW@ for power design change__P47
2. Swap VCORE1.2ID1 to pin AL13__P17
1A
B 2A
1A
B 2A
1A
1A
B 2A
1A
B 2A
2. Del R358 for ODD power control__P29

3. Unstuff R588,R268, Stuff R587,R273 for Speaker issue__P12, P30
4. Power design change
4. Change Net RF_LED_R and RF_LED# for BT and WLAN LED control__P37
5. Change CN4 P/N and footprint to 8pin for cost down__P24
6. Add R607, R608 for SW/B signal__P33
7. SMT product issues_All
* CN12,CN21 change footprint__P28
* PU4 change footprint__P46

* Q36,Q40,Q42 change P/N__P31
* U34 change footprint__P27
9. Add R609 for vender suggest__P3
B 2A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
12. PC25, PC30, PC134 change value to 330u/2V_P44
2. Change Bead from CX05T121000 to CX5AG121001 for vender cost down requirement__All
3. CN8 change P/N and footprint for ME design change__P34
6. Change HOLE18, 23, 6, 9, 27, 22, 17 and add HOLE30, 31
B 2A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
4. Add Q45, Q46, R610, R611, del R443, R444 for HDMI issue__P34
5. Change PJ1 for ME design change__P38
for machenical change_P35
7. Add R444, R443 1.5K for HDMI test__P25

8. Stuff L32, L35, L36, L38, Unstuff R230, R229, R321, R324, R316, R314, R306, R297 for EMI requirement __P34
9. Change R494, R520 from 0ohm to bead for EMI requirement __P34
10. Change R419 from 680ohm to 51ohm for ATI design change __P18
11/17 1. Remove 3G@, Add MP@ for separate different parts between Madison and Park__All
2. Remove Power Short Pad__All
3. Add PC232 for power design change__P38
4. Add Q47,R642 ,R542 for WiFi LED__P33
5. Change U16 P/N for update LAN chip version__P33
6. Change PJ1, CN8, CN4, BT1, CN14 for ODD, RTC, Battery connector change__All
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
B 2A
1A
11/18 1. Swap L38 for layout requirement__P34
B 2A
1A
2. Change CN9 P/N and footprint for ME issue__P32
B 2A
1A
3. Change HOLE18, 23, 6, 9, 27, 22, 17 for layout requirement_P35

4. Power design change
B 2A
B 2A
* PR128, PR102, PR101, PR158, PR110, PR111, PR151, PL8, PL9, PR117, PL13, PR82 change P/N for power design change_All
C 3A
B 2A
* Del PC68 for power design change_All

* Add PC190 for power design change_All
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
12/9 1. Change PR17, PR18, PC232 for Power design change__P38
C 3A
B 2A
2. Del Q36, R455 and R441, Q33 change mark__P25

3. R22,R23,R25,R27,R47,R65 change mark to MP@__P18
4. Change R92, C565 location for ATI design change__P18
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
5. Reserve R639 and add HDMI_HPD_PCH# for EC requirement__P9,P25
C 3A
B 2A
12/18 1. Add R455,R612 PCH strap pin __P9

2. Del 0ohm_0402: R10,R11,R15,R14,R83,R402,R388,R90,R91,R107,R144,
R190,R199,R198,R220,R231,R248,R256,R273,R363,
R369,R393,R394,R387,R437,R438,R400,R401,R501,
R503,R526,R532,R548,R550,R552,R553,R554,R555, R556,R590,R606__All
3. Del 0ohm_0603:
R493,R122,R139,R148,R173,R174,R175,R176,R218,
R219,R226,R228,R255,R232,R234,R235,R236,R237,
R244,R264,R267,R284,R307,R545,R558,R581,R587__All
4. U16 change footprint for PM requirement__P26
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
5. Del R268,R588 for Audio I/O power level__P31
C 3A
B 2A
6. Add R590 for LAN design change__P26

7. Add R643 for W/L LED design change__P33
8. SMTPE requirement
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
*JSIM1 change footprint
C 3A
B 2A
*PU3 change footprint
C 3A
B 2A
*PR130 change footprint

12/22 1. Cahnge Hole18, Hole23 for layout modify__P35
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
1. R455 & R612 reconnect_P9
C 3A
B 2A
2. R552/R553/R554/R555/R556 change back to 0 ohm for black screen issue verify_P28
C 3A
B 2A
3. CN9 footprint change footprint_P32

4. Update VRAM table and add VRAM@ mark_P23
5. EMI solution
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
* R90 & R91 change to unstuff , L13 stuff._P24
C 3A
B 2A
* Add R614 on LVDS_BRIGHT_P24
C 3A
B 2A
* Adding C813 for VIN

* Adding C814,C815,C816,C817,C818,C819,C820,C821 for VIN_SRC
* Adding C822 for CSOP_1,PC102 change to stuff
C 3A
B 2A
C 3A
B 2A
C 3A
B 2A
* Adding C823,C824,C825,C826,C827 for VIN_SRC
C 3A
B 2A
* Add C828 to +3V
C 3A
B 2A
* Change R614 to bead_P24
C 3A
B 2A
6. Add F1 & F2 for safety.
C 3A
B 2A
7. Add JP4 and delete JP5 for for change VGPU_IO source
C 3A
B 2A
8. Change PR55 to 2.7K for Power change design_P40

9. Add 3G@ for 3G function_All
C 3A
B 2A
C 3A
B 2A
C 3A
C
1. U28 change to 512K, U37 change to 4M for BIOS design change_P9,P37

2. Change
B 2A
1A
1A
1A
10. Add R610,R611,Q45,Q46, del R444, R443 for HDMI test__P25

11. Add R291,R315 for Acer requirement__P31
11/12 1. Change bead from CX08T121000 to CX5AG121001 for vender cost down requirement__All
4A
B 2A
B 2A
B 2A
1A
1A
1A
* PL10,PL17 change footprint__P47

12/31
B 2A
B 2A
1A
1A
1A
2. Mark +1V power system with sw@__P47
B 2A
B 2A
1A
1A
1A
3. Mark +1.8V_GPU power system with sw@__P47
12/24
1A
1A
1A
* PC223 change to use CC71004MZ01

* PL11,PL12 change to use CV+18V0MZ04
* PC136, PC104, PC172, PC173, PC174,PC72 change to use CH6102K9A19
* PC68 change to use CH33306K915
* PR127 change to use CS34422FB00
* PC121 change to use CH61004M291
* PC21 change to use CH61004M291
* PL7 change to use CV+18V0MZ04
* PC25,PC134,PC30 change to use CH733RY8802
* PC118,PC119,PC127 change to use CH6102K9A19
* PC10,PC114 change to use CH61004M291
* PC211,PC212, PC96,PC148,PC146,PC48 change to use CH6102K9A19
10/28 1. R380,R376 PH with +3VPCU__P37
3A
B 2A
6. Change U37 to 2M size__P9

7. Change PU7,PU12 for power design change__P47
10/19 1. Change U36 P/N for PCH version update__P8~P13
B 2A
B 2A
3. Change PR5, PR123, PR127, PR129 for power design change__P44

4. Unstuff PC68 for power design change__P43
5. Change Net name RST_GATE#_R to RST_GATE#__P36
2A
1A
1A
R328,R329,R330,R331,R334,R335 value for LED Brightness fine turn_P33
3. Stuff PR274,unstuff PR136, PR275 for change VGPU_IO source_P45
1/5
1. Reserve Board_ID PAD and unstuff R629,R630,R631,R632,R633,R634 _P10

2. Remove R417,R413,Q30,Q31 for costdown_P23,P37
3. Add trace VGA_THERM#_P23,P37
4. NONE
5. D10, F1 replace location_P24
6. Stuff R99, Change Q6<P/N modify> location for dGPU_SELECT_R control design change_P24
2010/01/11
2010/01/18
2.
PR1
SHORT0603
PR44
SHORT0603
PR36
SHORT0402
1. unstuff R486
2. R244 change from shortpad to RC0603 and unstuff.
3. C482 change from cap to 0 ohm resistor.
1. delete PAD of U11/U12/U14
3. PD# PU change from +3V to +5VA
& R599 change to 1K ohm resistor.
2010/01/19
1. PQ7 changes to BA001430Z49
2. PR1
SHORT0603
3. remove shortpad R139/R148/R144
PR44
SHORT0603
4. R152/R154/R259 change to SHORTPAD

5. R78 connect from +3V to +3V_D and R75 change to Unstuff.
6. F1/F2 update P/N.
PR72
SHORT0603
PR36
SHORT0402
PR62
SHORT0402
PR72
SHORT0603
PR81
SHORT0603
PR62
SHORT0402
2010/01/20
PR68
SHORT0402
PR81
SHORT0603
PR115
SHORT0603
PR68
SHORT0402
PR99
SHORT0402
PR115
SHORT0603
PR154
SHORT0603
PR99
SHORT0402
PR105
SHORT0402
PR154
SHORT0603
PR156
SHORT0603
PR105
SHORT0402
2010/01/21
2010/01/22
2010/02/03
2010/02/04
PR107
SHORT0402
PR156
SHORT0603
PR206
SHORT0603
PR107
SHORT0402
PR108
SHORT0402
PR206
SHORT0603
PR240
SHORT0603
PR108
SHORT0402
PR113
SHORT0402
PR240
SHORT0603
PR245
SHORT0603
PR113
SHORT0402
PR161
SHORT0402
PR245
SHORT0603
PR250
SHORT0603
PR161
SHORT0402
PR167
SHORT0402
PR250
SHORT0603
PR254
SHORT0603
PR167
SHORT0402
PR176
SHORT0402
PR254
SHORT0603
PR257
SHORT0603
PR176
SHORT0402
PR179
SHORT0402
PR257
SHORT0603
PR266
SHORT0603
PR179
SHORT0402
PR185
SHORT0402
PR266
SHORT0603
PR270
SHORT0603
PR185
SHORT0402
PR198
SHORT0402
PR270
SHORT0603
PR60
SHORT0805
PR198
SHORT0402
PR214
SHORT0402
PR60
SHORT0805
PR120
SHORT0402
PR214
SHORT0402
PR222
SHORT0402
PR120
SHORT0402
PR199
SHORT0603
PR222
SHORT0402
PR227
SHORT0402
PR199
SHORT0603
PR200
SHORT0603
PR227
SHORT0402
PR228
SHORT0402
2010/03/05
1. Unstuff R552/R553/R554/R555/R556
2. L23/L24/L25/R221/R249/R260/R305/R241/R242/R29/R32/R482/R544/ change to SHORTPAD
3. BOM for Board-ID,check again.
1. add C829/EC1/EC2
2. Delete U30/C189
3. Delete D21/D22 , ADD Q36/Q39
4. Change PR21 to CS-2203J913
5. Change PC18 to CH22206K917
6. Unstuff<C815/C816/C817/C818/C820/C821/C823/C824/C825/C826/C827>
1. R49/R101 change to SHORTPAD
2. Delete C829
3. C816/C818/C819/C820 change net and stuff.
4. Q36/Q39 should be always @ NOT SW@
1. C777/PC190/PC1 update P/N & description.
2. PR222 Value change back to 0_4
1. PR222 change to SHORTPAD
2. delete Q36/Q39 , add D21/D22, and reserve PAD of R615
1. Delete PD2
2. PR101 & PR102 change P/N.
PR200
SHORT0603
PR228
SHORT0402
PR230
SHORT0402
PR157
SHORT0603
PR230
SHORT0402
PR239
SHORT0402
PR159
SHORT0402
PR239
SHORT0402
PR248
SHORT0402

Document Number
Date:
PR47
SHORT0402
PR248
DOC NO.
SHORT0402
PROJECT : ZR7
Size
Rev
1A
Change list2
Sheet
50
PROJECT MODEL :
ZR7B
PART NUMBER:
PR249
of
50
SHORT0402
APPROVED BY:
DATE:
DRAWING BY:
REVISON:
2009/12/24
C3A
PR249
SHORT0402
PR251
SHORT0402
PR251
SHORT0402
PR252
SHORT0402
PR252
SHORT0402

ACER Aspire TimelineX 5820TG

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ACER Aspire TimelineX 5820TG

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5

ZR7B SYSTEM BLOCK DIAGRAM

ZR7B MB(UMA,BT)W/O CPU

ZR7B MB(SG,MADS,SAM,BT,3G)W/O CPU

P8, 9, 10, 11, 12, 13

SIM Card FFC

BOM Option Table

for Switchable Graphic only SKU

for Madison & Park different parts

for different VRAM parts

Quanta Computer Inc.

Friday, March 05, 2010

GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)

+1V (DP PLL PWR)

G9334ADJ & MOS

GPU PWR CTRL Option 2 (VDDR3 after VDDR1)

+1V (DP PLL PWR)

G9334ADJ & MOS

Thermal Follow Chart

CHARGE PUMP POWER

PCH/GPU/Peripheral component POWER

CPU/SODIMM CORE POWER

SODIMM Termination POWER

Internal GPU POWER

MINI CARD/NEW CARD POWER

CPU VTT POWER

PCH CORE POWER

CPU CORE POWER

SWITCHABLE PWM IC POWER

GPU CORE POWER

GPU I/O POWER

VRAM CORE POWER

Quanta Computer Inc.

PWR Status & GPU PWR CRL & THRM

Friday, March 05, 2010

Place each 0.1uF cap as close as

Quanta Computer Inc.

Friday, March 05, 2010

AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI)

AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)

Use reverse type

1.5K/F_4 CPU_PLTRST# AL14

JTAG & BPM

PCI EXPRESS -- GRAPHICS

Layout Note: Place

STUFF -> R469, R491, R507

STUFF -> R490, R491

STUFF -> R489, R507

Use a voltage divider with VDDQ

Quanta Computer Inc.

Friday, March 05, 2010

AUBURNDALE/CLARKSFIELD PROCESSOR (DDR3)

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY - B

Channel A DQ[15,32,48,54], DM[5]

Quanta Computer Inc.

Friday, March 05, 2010

AUBURNDALE/CLARKSFIELD PROCESSOR (POWER)

Quanta Computer Inc.

AUBURNDA 3/4 (PWR)

PEG & DMI

1.1V RAIL POWER

CPU CORE SUPPLY

AUBURNDALE/CLARKSFIELD PROCESSOR (GRAPHICS POWER)