FPGA BASED AUTOMATIC MICROWAVE DISH ALIGNMENT SYSTEM B.S.

TELECOM ENGINEERING, BATCH 2008 Internal Advisor

Waseem Ahmed Siddiqui Assistant Professor Department of Telecommunication SSUET, Karachi Submitted by
AsmaSehar SadiaAzam Tehseen Ul Hassan Tabish Ur Rehman 2008-TE-013 2008-TE-057 2008-TE-089 2008-TE-103

DEPARTMENT OF TELECOMMUNICATION ENGINEERING

SIR SYED UNIVERSITY OF ENGINEERING & TECHNOLOGY, KARACHI
JANUARY 2012

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FPGA BASED AUTOMATIC MICROWAVE DISH ALIGNMENT SYSTEM

BY

AsmaSehar SadiaAzam Tehseen Ul Hassan Tabish Ur Rehman

2008-TE-013 2008-TE-057 2008-TE-089 2008-TE-103

Report submitted in partial fulfillment of the requirements for the degree of Bachelor of Science inTelecommunication Engineering

DEPARTMENT OF TELECOMMUNICATION ENGINEERING SIR SYED UNIVERSITY OF ENGINEERING AND TECHNOLOGY, KARACHI JANUARY 2012 ACKNOWLEDGEMENT

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We would like to thank those who helped during our final year project. Without their support, we could have never accomplished this work. We take this special occasion to thanks our parents. We dedicate this work to our parents. It would have been simply impossible to start, continue and complete without the support of our parents who, unconditionally provided the resources to us. We are eternally indebted to our internal advisor MrWaseem Ahmed Siddique for all the help, invaluable guidance and generous support throughout our final year project. We have been very fortunate to be associated with such a kind and good person and it would take more than a few words to express our sincere gratitude. We also like to thanks our external advisor Engr.Sami urRehmanfor enlightening suggestions and advices. His professionalism, guidance, energy, humour, thoroughness, dedication and inspirations will always serve to us as an example in our professional life.

Finally, we would like to thanks FINERS Engineering Systems for providing us Alignment system guideline AsmaSehar SadiaAzam Tehseen Ul Hassan TabishurRehman 2008-TE-013 2008-TE-057 2008-TE-089 2008-TE-103

January 2012

TABLE OF CONTENTS Page ACKNOWLEDGEMENT

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TABLE OF CONTENTS LIST OF TABLES LIST OF FIGURES ABSTRACT CHAPTER ONE: INTRODUCTION& BACKGROUND 1.0 Introduction 1.1 Pre-Alignment

iii v vi vii

1 2 3

Polarization Pre-alignment
1 1 Azimuth Pre-Alignment Elevation (Tilt) Pre- Alignment

1.2 1.3

Final Alignment Conclusion

CHAPTER TWO : SUBMISSION OF THE REPORT 2.0 2.1 2.2 Introduction Submission of soft cover report Submission of hard cover report 2 2 2

CHAPTER THREE : SPECIFICATIONS OF THE REPORT 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 Length of report Language of report Cover and binding Front cover and title page 3.3.1 Front cover 3.3.2 Title of report Text, font size and spacing Subdivision Margins Paper and printing Pagination Corrections Tables Figures 3 3 3 3 3 4 4 5 5 5 5 6 6 6
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3.12 3.13 3.14

Notes and Footnotes Usage of Colour in report Softcopy of the FYP report

7 7 7

CHAPTER FOUR : FORMAT OF THE REPORT 4.0 Introduction 8

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LIST OF TABLES
age
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3.1 4.1 4.2

Comparison of different grades in last one year Comparison of different grades in last two year Comparison of different grades in last three year

LIST OF FIGURES

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1.1 1.2 1.3 1.4 1.5 1.6 1.7

Antenna, top-down perspective Use of level to establish vertical plumb Calculating required tilt angle Antenna tilt adjustment Sample RSL Chart Side lobe pattern Using side lobes to combat interference

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FPGA BASED AUTOMATIC MICROWAVE DISH ALLIGNMENT SYSTEM

ABSTRACT
Our project is an alignment tool for the micro wave dish assembly, which can be used on telecom towers for the intra network communication. Through our project the BTS cell sites micro wave dishes can easily aligned automatically to far end. We have used Field Programmable Gate Array (FPGA) based intelligent alignment system which aligns antenna automatically and an antenna can be positioned according to the received
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signal strength.The individual signals that are obtained from the detector, after converted into their digital domain using Analog to Digital Converter (ADC), is fed into the FPGA. The signals are then compared and the point at which the maximum signal is noted. Finally it guides the antenna in the direction of the maximum signal received. For this each axis will be controlled by separate servo to move the dish along the axis at certain detected degrees by using two different servomotors. When it will reach at the set point the servo will be stopped and locked. Then dish screws can be tightening as manually. Once the LOS is adjusted then fine tuning done through the signal strength. The experimental results are found to be positive and effective. The proposed system has been realized using ALTERA MAX II EPM2210F324 FPGA device.We can reconfigure the FPGA at any time in our project, even in the field, to meet changing market requirements. A design based on a single FPGA platform offers increased flexibility. We can integrate all our motor control functions on one device, allowing us to enhance drive performance, improve network communications, implement embedded processors, and meet custom logic requirements.

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CHAPTER 1

INTRODUCTION&BACKGROUND

INTRODUCTION
One of the most important elements of a wireless backhaul deployment is the antenna system. Proper alignment of that antenna system is critical to the performance of any backhaul radio system, as it is fundamental to the high link availability that is the ultimate goal when designing high-performance wireless systems.Our project is an alignment tool for the micro wave dish assembly, which used on telecom towers for the intra network communication. Through our project the BTS cell sites micro wave dishes can easily aligned automatically to far end using FPGA.
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The received signals from the far end MV dish will be fed into FPGA board through interface circuit. The received signals then processed and executed on board ports to provide the appropriate signals for the servos which will be operated for the alignment mechanism on the tower. For this each axis will be controlled by separate servo to move the dish along the axis at certain detected degrees by using two different servomotors. When it will reach at the set point the servo will be stopped and locked. Then dish screws can be tightening as manually. When the LOS maintained then fine tuning done through the signal strength. Engineering a wireless link for the highest achievable system gain while minimizing or eliminating the potential for interference will help reach the goal of high availability. This paper will address in a generalized fashion the steps required to align an antenna pair for a terrestrial microwave radio system. There are two fundamental phases to this process: 1) Pre-alignment or coarse-tuning; and 2) Final alignment or fine-tuning.

1 Pre-alignment
The pre-alignment phase involves settings on the antenna prior to installation and/or turn-on of the radio electronics. The final alignment includes all steps taken after the radio electronics have been installed and turned on. Most antennas have three adjustments for alignment: 1.1Polarization 1.2Azimuth (left and right) 1.3Elevation (up and down) Coarse-tuning the antenna at time of antenna installation will ensure that adequate signal is available for the fine tuning phase of the installation.
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1 Polarization Pre-alignment
The polarization of an antenna is defined as the orientation of the "E" field of the RF beam. If the "E" field is vertical, the antenna is said to be vertically polarized and, conversely, if the "E" field is horizontal the polarization is said to be horizontal. On most solid reflector and panel antennas, the polarization can be identified by the orientation of the feed horn or panel assembly. On grid antennas, polarization is easily identified by the grid pattern. For example, if a grid antenna is mounted with the reflecting elements oriented vertically it will produce a vertically polarized signal. Most antenna vendors clearly mark their antennas and feed assemblies for easy setting of the desired polarization. It will be necessary to consult the installation instructions for the specific antenna under alignment to determine how polarization is indicated. Prior to raising the antenna to the tower or rooftop mounting position, the polarization should be verified and adjusted to correspond to the antenna data sheets.

1 Azimuth Pre-alignment
Once the antenna is securely mounted at its permanent location on the rooftop or tower, coarsetuning the azimuth is required so that sufficient signal is present for fine tuning. If the path length is short enough and conditions are clear, the distant end may be seen with a pair of binoculars or a spotting scope. Figure 1.1 shows the top view of the mounted antenna. The binocular or spotting scope is held against the top rim of the antenna and the antenna is adjusted in azimuth so that the distant antenna is centered in the field of view of the binocular. Once the antenna is coarse tuned for azimuth, proceed to the elevation pre-alignment.

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Figure 1.1 Antenna, top-down perspective If path analysis documentation is available at the time of installation and the distant end antenna location is not easily seen, a compass can be used for azimuth pre-alignment. Most microwave link analysis documents will contain specific information regarding the antennas height, polarization and azimuth (compass heading). After determining the azimuth of the antenna from the link analysis documentation, Understanding how to use a compass is important when determining the direction an antenna should be aimed.

1 Elevation (Tilt) Pre-Alignment

Elevation (Tilt) Pre-Alignment In most cases, adjusting the antenna for vertical plumb (0 degrees elevation) is recommended for coarse-tuning the elevation adjustment. Figure 1.2 shows the use of a level to plumb the antenna. The use of the level requires that the level reach from top rim to lower rim. If the level is too short it can be attached to a straightedge that is long enough for this purpose.

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Figure 1.2 Use of level to establish vertical plumb While a 0 degree pre-alignment elevation setting is suitable for most paths, it may be necessary to calculate the tilt angle if significant differences exist between the two antenna heights. Figure 1.3 shows the parameters for calculating the angle for the difference in elevation of two antennas.

Figure 1.3 Calculating required tilt angle Vertical angle calculations: Tan =X/D, Where: X = Antenna Height Difference, in Feet D = Path Length, in Feet 2 = Antenna 3 dB Beam width = Angle to Lower Antenna, Therefore:

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=Tan-1(X/D) Once the angle is calculated, mechanical elevation can be set. Simply set the elevation according to the installation instructions included with the antenna mounting hardware. If no such scale exists, Figure1.4 shows the parameters required to calculate the amount of tilt required. R Tan = Y R = Radius of Antenna, in Inches 2Y = Distance between bottom of antenna and plumb bob (in)

Figure 1.4 Antenna tilt adjustment If the above procedures are followed, the required final antenna adjustment will be minimal and the possibility of peaking on a side-lobe will be minimized. These coarse-tune adjustments can be conducted prior to the installation of the electronics. When the electronics are installed and turned on, the final adjustment of the antenna is made.

1.2Antenna Final Adjustments

Prior to the final adjustment of the antenna, some preliminary measurements can be made. Decide which method is to be used to indicate when the antenna is adjusted to peak power. Two methods are usually available, DC voltage at the RSL (receive signal level) test point and RSL indication in software/firmware. The first method is recommended as this is typically a near-realtime reading. Changes in signal strength are immediately conveyed to the installer by variations

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in the DC voltage present at the RSL test point on the face plate of the radio. This type of reading allows for precise positioning of the antenna. As an alternative to the voltmeter, most radio systems have RSL information available through an integrated management interface. This may be an internal http server, telnet, serial or proprietary interface. Many of these types of interfaces offer only snapshots of current performance data while others may only refresh at factory set time intervals. Using these types of interfaces for antenna alignment should be considered only as a last resort. Time delays in relaying signal strength information to personnel aligning the antennas can cause misalignment and lengthen the duration of the alignment procedure. Since the antennas at both ends of the links have been coarse-tuned for azimuth, elevation and polarization, sufficient signal should be present to commence with the fine-tuning of the antennas. While monitoring the receive signal level with a voltmeter or through the management interface, fine tune the azimuth, elevation and polarization for maximum receive signal. Perform the final tuning adjustments one end at a time. It is necessary for one antenna to be stationary while the other is being adjusted. Figure 1.5 shows a sample of an RSL chart from Exalt Communications. Note that as voltage decreases, signal strength increases. This relationship will vary by model and manufacturer so consult the radio documentation so that there is clear understanding of the relationship between the RSL test voltage and signal strength. If the peak of the antenna pattern is broad and hard to find, then the antenna can be swung for equal signal strength drop off in each direction. The distance between these points can be measured in number of turns or distance. The final adjustment can be set to the half-way point between these two points.

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Figure 1.5 Sample RSL Chart The polarization is adjusted in the same manner as azimuth and tilt. If the antenna structure is not perfectly vertical, polarization adjustment may be necessary. Once the antenna is set at peak level, tighten all adjustments and mounting hardware. Continue to monitor the RSL while doing this to ensure final tightening of the hardware has little to no effect on RSL. The calculated receive signal strength should always be attained or exceeded. Repeat the procedure at both ends of the link until the calculated RSL is achieved. If the RSL is worse than the calculated value after the above procedures, rotate one feed assembly or panel 90 degrees. The RSL should drop by greater than 20 dB. A lower than expected RSL that is attained with good cross-polarization discrimination (>20dB) is indicative of a faulty antenna feed system, a defective transmission line or an obstructed path. Verify that calculated insertion loss through the transmission line is within limits and replace antennas or transmission system elements with known good devices until the fault is found. Antenna Adjustment for Minimum Interference

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So far, we have discussed how to adjust the antenna for maximum receive power. If it is determined that interference is present, then the antenna can be adjusted to minimize the interference. The antenna data sheets will specify the antenna polarization. It should be determined if there was a reason for selecting a certain polarization during the link design process. The possible sources of interference are: a.Interference from other sources (out of your control); b.Interference from sources within your control, such as adjoining radios in a backbone or hub. There are various methods for determining the presence of interference. A simple method is to use a DC voltmeter connected to the RSL test point on the radio that indicates receive level. When the receiver's distant transmitter is turned off, the receive level meter may still indicate a received carrier. If the level is high enough, threshold degradation may occur. This will be evidenced by a high bit error rate or complete loss of synchronization from the far end. The absence of an indication of signal level above the receivers threshold is not necessarily an indication that interference does not exist. RF levels below the receivers threshold may be difficult to detect at the RSL test point. Radio systems operating at complex orders of modulation can still be affected by co-channel interference well below threshold. A better method is to connect a spectrum analyzer to the antenna to measure the level and frequency of the interference. More advanced radio systems offer integral spectrum analyzers that are useful in analyzing the properties of signals present at the antenna. If it is determined that interference exists, many techniques can be used to avoid the identified interferer. Some of these techniques use the unique properties of the antenna to suppress the interfering signal.

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The antenna has characteristics that can be used for reducing interference. The first characteristic is polarization discrimination. If two antennas are opposite in polarization, there will be 20 to 30 dB of isolation between them. Rotating an antenna or antenna feed assembly 90 degrees can be an effective countermeasure to interference. While observing the interference at the receive signal level test point or on a spectrum analyzer, the polarization can be adjusted for minimum interference rather than peak power. Make sure that whatever adjustments are made to polarization on one end of the link are duplicated at the other end. There is another adjustment of the antenna that can be used to minimize interference. Figure 1.6 shows the side lobe pattern of a typical antenna. The plot is a polar plot that shows sharp drops in power response between the lobes of the antenna.

Figure 1.6 Side lobe pattern Figure 7 shows what can be done to combat an interfering source. Since the antenna has valleys between the side-lobes and a relatively broad power response at the peak, it can be seen that a slight rotation or tilt of the antenna can make a significant difference in the power level of the interfering signal. This can be used to reduce interference without significant loss in power of the

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intended signal. This adjustment will help only if there is an angle between the two antennas relative to the angle of the interference source.

Figure 1.7 Using side lobes to combat interference

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Conclusion
The importance of proper antenna alignment cannot be overstated. Any misalignment results in lower system gain which directly affects the availability of the microwave link. Always consider using a professional services organization with a proven track record of successful point-to-point microwave system installations. Finally, schedule annual maintenance on the antenna system to ensure all mechanical connections remain secure and have not shifted.

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CHAPTER 2

PROJECT OVERVIEW

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2.1BLOCK DIAGRAM
Figure shows the complete block diagram of the FPGA based Automatic microwave dish alignment System. The system align the microwave dish through received power from far end the received signal is fed into the FPGA KIT which generate appropriate signal to servo motor to align dishes correctly

Figure 2.1 System Block Diagram

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2.2DESCRIPTION OF PROJECT
Proper alignment of that antenna system is critical to the performance of any backhaul radio system. FPGA based Automatic microwave dish alignment System is an alignment tool for communication system which align the microwave dishes, through received power from other communicating end, accurately and quickly and help to enhance the performance of

communication system. Our project FPGA based Automatic microwave dish alignment System consists of following main parts:

FPGA Kit (Altera MAX II EPM2210F324) RF Transceivers IR sensors IR driver Servomotors Serial ports Microwave Dishes

2.3SUMMARIZE OVERVIEW
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Working of each main part is described as below:

2.3.1FPGA

kit

FPGA kit Altera MAX II EPM2210F324 used as blaster mode which receive signal from IR receiver and processed it and provide an appropriate signal to servomotor where dish has to be aligned. It also manages the received data from other side as well.

2.3.2RF TRANSCEIVERS
HM-TR series transparent wireless data link module have high data rate, longer transmission distance. Connect the RS232 connector with PC and transmits the data. Transmitter / Receiver mode select as per required

2.2.3IR SENSORS
IR sensor in used as finger prints in project. The IR receiver knows that the particular transmitted frequency from IR transmitter has to receive. When IR receiver recognizes the particular frequency and received. The received signal is fed into the FPGA kit for further process.

2.2.4SERVOMOTORS
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The FPGA processed the signal received from IR receiver to generate a pulse width dependent signal for servomotor. A position demand signal is detected by the control electronics. This signal represents a required position for the motor shaft to be in. . If there is a difference between the actual position and the demand position, then the electronics drives the motor in the appropriate direction to reduce that difference.

2.2.5SERIAL PORTS
Serial port is used to carry data from PC to transceiver to transmit the data.The MAX232 is an integrated circuit that converts signals from an RS-232 serial port to signals suitable for use in TTL compatible digital logic circuits. The MAX232 is a dual driver/receiver and typically converts the RX, TX, CTS and RTS signals.

2.3CONCLUSION
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In this chapter we discussed the brief overview of project and the components and the importance of each component in project. The explanation of the project and detailed description of hardware components will be explained in the next chapter.

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CHAPTER 3

SYSTEM METHODOLYGY

3.1INTRODUCTION
Our methodology depends upon the electrical and mechanical setup. Since it has to meet the requirements of practical implementation and has to be very flexible in order to meet & fulfill the scenario and conditions. The mechanical
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part consists of several motors to rotate the arm in the desired direction and also it has to react and response quickly in accordance with the signal received from far end. The electronic part composed of sensors HMI and PLC in order to give the right instructions to perform & act accordingly. The pulse dependent signal generated from FPGA will drive the servomotor in right direction. The transceivers transmit and receive the data as desired.

D nP a esig h se

Im lem n tio p e ta n Pa h se

T estin P a g h se

3.2DESIGN PHASE
Our system design includes a mechanical setup. There are different precise step regarding dish alignment, we want to align dishes through received signal power from other end because microwave
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communication require adjustment of LOS and it is very difficult to adjust LOS in long distance. To achieve this purpose we include IR transmitter and receiver in our design which helps to adjust LOS. Since the system design is based in FPGA, the use of FPGA was another problem, what kind of FPGA we have to use. At last we design system with ALTERA MAX II MICRO, which functions properly and it fitful our requirements in projects to achieve the correct & desired result. It can perform tasks which can be controlled through a PLC therefore we require best programs. The design of software has strong impact on our project which provides the complete controlling and assessment of our tasks.

3.3IMPLEMENTATION PHASE
The mechanical and electrical setup consists of fix body structure. The IR transmitter and receiver place parallel to the RF transceiver. The temperature of microwave dishes increases during the transmission therefore we place IR Transmitter a little distance from the dish. A serial port used to connect PC to the transceiver. The most difficult and important task is the implementation of FPGA. As the we have designed that the signal from IR receivers used as input and the output signals is fed into the servomotor which depends on the pulse width i.e. time dependent, rotates the servos in desired direction. The implementation of software on FPGA helps us to operate our device properly.

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Figure- 3.1 Circuit design of FPGA based Automatic Microwave Dish Alignment System

3.4TESTING PHASE
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This is the most interesting phase of our project. It is important for any system that the system should work properly what the designer want.
It is very important that our system function properly which match with the standards and it has been tested for many conditions as possible and we will keep testing and improving as new challenges will be faced by this system. We are testing the system in different ways to find either it has any malfunction therefore we implement the testing phase more & more to improve the performance.

3.5CONCLUSION
In this chapter, we have the methodology of the FPGA Based Automatic Microwave Dish Alignment system. The system was implemented and in three phases and discussed briefly. The details of the hardware components & about software of the device will be presented in later chapters.

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CHAPTER 4

SYSTEM PROCESS FLOW

4.1INTRODUCTION
In this section, we have discussed the overall process of our project step by step. This would include both the hardware and
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software part of the system. After going through this section, the user would know how the system is working. How dishes align automatically and quickly through received signal power from other end? Why we use IR transceiver and receiver in the system? How system working and execute proper functions as desired?

4.2PROJECT FLOW
The design of our system is composed of both the electrical and mechanical setup working with proper software to perform tasks according to our desire and in the case of our system we require a higher level accuracy so that our system not only work better to enhance the performance of the communication system but also the align dished very quickly and accurately. The most important part of the project is the software will be discussed in next chapter. Complete basic process flow of the project is shown in figure 5.1.

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Figure 5.1: Process Flow Diagram

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4.3EXPALNATION OF PROCESS FLOW

From the Basic process flow diagram, we can observe that the continuous process can be divided into several steps that will help the user to understand the system much comprehensively.

4.3.1PHASE"ONE"
The first phase of the project is pre-alignment phase where microwave dishes adjust the LOS through IR sensors, we use IR sensor because IR sensor doesnt required the adjustment of LOS. IR transmitter start transmission with a particular frequency and IR receiver recognize the frequency and Fed into the FPGA. There are two IR transmitters as well as two IR receivers used, one for X-axis and other for Y-axis.At the time of IR transmission and reception the RF transmitter and receiver both are in OFF state.

4.3.2PHASE"TWO"
The second phase in which the signal from IR receiver fed into the FPGA, the FPGA process the Receive signal and generate appropriate signal dependent on pulse width to servomotors to align dishes in the desired direction.

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First the signal from x-axis IR sensor is processed which align the x-axis of dish through servomotor while the signal from y-axis align Y-axis of dish.

4.3.3PHASE"THREE"
When the dishes align i.e. the LOS is adjusted then the transmitter and receiver turn on and starts transmission and reception in other end.

4.3.4PHASE"FOUR"
This phase is also known as fine tuning where we align dishes through received power of RF signal called final alignment. Through software we monitor that where we achieve maximum SNR. We lock the dish in position where we got maximum signal to noise ratio (SNR).

4.3.5PHASE"FIVE"
After final alignment i.e. fine tuning data transmission start from far end while other side receives and hence communication established through FPGA based Automatic Microwave Dish Alignment.

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4.1CONCLUSION
In this chapter, we have discussed the overall process of our project step by step. How system start it working through a procedure.After going through this chapter, the readers would know how the system is working.

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CHAPTER 5

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ALTERA MAX II MICRO

5.1 INTRODUCTION

TO

FIELD-PROGRAMMABLE

GATE ARRAY
A field-programmable gate array (FPGA) is an integrated

circuit designed to be configured by the customer or designer after manufacturinghence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL). FPGAs can be used to implement any logical function that an ASIC could perform. FPGAs contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together"somewhat like many logic gates that can be inter-wired in (many) different configurations. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND & XOR. In most FPGAs, the logic blocks also include memory elements, which may be simple flipflops or more complete blocks of memory.

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In addition to digital functions, some FPGAs have analog features. The most common analog feature is programmable slew rate and drive strength on each output pin, allowing the engineer to set slow rates on lightly loaded pins that would otherwise ring unacceptably, and to set stronger, faster rates on heavily loaded pins on high-speed channels that would otherwise run too slow. A few "mixed signal FPGAs" have integrated peripheral Analog-to-Digital Converters (ADCs) and Digitalto-Analog Converters (DACs) with analog signal conditioning blocks allowing them to operate as a system-on-a-chip.

5.2HISTORY
The FPGA industry sprouted from programmable read-only

memory (PROM) and programmable logic devices (PLDs). PROMs and PLDs both had the option of being programmed in batches in a factory or in the field (field programmable), however programmable logic was hard-wired between logic gates. Some of the industrys foundational concepts and technologies for programmable logic arrays, gates, and logic blocks are founded in patents awarded to David W. Page and LuVerne R. Peterson in 1985. Xilinx Co-Founders, Ross Freeman and Bernard Vonderschmitt,

invented the first commercially viable field programmable gate array in

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1985 the XC2064. The XC2064 boasted a mere 64 configurable logic blocks (CLBs), with two 3-input lookup tables (LUTs). In the early 1990s, FPGAs were primarily used in telecommunications and networking. By the end of the decade, FPGAs found their way into consumer, automotive, and industrial applications. FPGAs got a glimpse of fame in 1997, when Adrian Thompson, a researcher working at the University of Sussex, merged genetic algorithm technology and FPGAs to create a sound recognition device. Thomsons algorithm configured an array of 10 x 10 cells in a Xilinx FPGA chip to discriminate between two tones, utilizing analogue features of the digital chip. The application of genetic algorithms to the configuration of devices like FPGAs is now referred to as Evolvable hardware.

5.3MODERN DEVELOPMENTS
A recent trend has been to take the coarse-grained architectural approach a step further by combining the logic blocks and

interconnects of traditional FPGAs with embedded microprocessors and related peripherals to form a complete "system on a programmable chip", that work was done in 1982. Examples of such hybrid technologies can be found in the Xilinx Virtex-II PRO and Virtex-4 devices, which include one or more PowerPC processors embedded within the FPGA's logic fabric.
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In 2010, an extensible processing platform was introduced for FPGAs that fused features of an ARM high-end microcontroller (hard-core implementations of a 32-bit processor, memory, & I/O) with an FPGA fabric to make FPGAs easier for embedded designers to use. An alternate approach to using hard-macro processors is to make use of soft processor cores that are implemented within the FPGA logic Micro Blaze and Nios II are examples of popular soft-core processors. As previously mentioned, many modern FPGAs have the ability to be reprogrammed at "run time," and this is leading to the idea of reconfigurable computing or reconfigurable systems CPUs that

reconfigure themselves to suit the task at hand. However, it does not support dynamic reconfiguration at runtime, but instead adapts itself to a specific program. Additionally, the new, non-FPGA architectures are beginning to emerge. Software configurable microprocessors such as the Stretch S5000 adopt a hybrid approach by providing an array of processor cores and FPGA-like programmable cores on the same chip.

5.4MAJOR MANUFACTURERS
Xilinx and Altera are the current FPGA market leaders and long-time industry rivals. Together, they control over 80 percent of the market, with Xilinx alone cover 58 percent. Both Xilinx and Altera provide free Windows and Linux design software which provides limited set of devices.
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Figure 5.1 - The Programmable Marketplace In March 2010, Tabula announced their new FPGA technology that uses time-multiplexed logic and interconnect for greater potential cost savings for high-density applications.

5.5GATES
1987: 9,000 gates, Xilinx 1992: 600,000, Naval Surface Warfare Department Early 2000s: Millions

5.1MARKET SIZE
1985: First commercial FPGA technology invented by Xilinx 1987: $14 million ~1993: >$385 million 2005: $1.9 billion

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2010 estimates: $2.75 billion

5.1APPLICATIONS
Applications of FPGAs include Digital Signal Processing Software-Defined Radio Aerospace And Defense Systems Asics Prototyping Medical Imaging, Computer Vision Speech Recognition Cryptography Bioinformatics Computer Hardware Emulation

5.1ARCHITECTURE
The most common FPGA architecture consists of an array of logic blocks (called Configurable Logic Block, CLB, or Logic Array Block, LAB, depending on vendor), I/O pads, and routing channels. Generally, all the routing channels have the same width (number of wires). Multiple I/O pads may fit into the height of one row or the width of one column in the array.

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An application circuit must be mapped into an FPGA with adequate resources. While the number of CLBs/LABs and I/Os required is easily determined from the design, the number of routing tracks needed may vary considerably even among designs with the same amount of logic. Since unused routing tracks increase the cost (and decrease the performance) of the part without providing any benefit, FPGA manufacturers try to provide just enough tracks so that most designs that will fit in terms of LUTs and IOs can be routed. This is determined by estimates such as those derived from Rent's rule or by experiments with existing designs.

Figure 5.2 -Generic FPGA architecture: In general, a logic block (CLB or LAB) consists of a few logical cells (called ALM, LE, Slice etc.). A typical cell consists of a 4-input Lookup table (LUT), a Full adder (FA) and a D-type flip-flop, as shown below. The LUTs are in this figure split into two 3-input LUTs. In normal mode those are combined into a 4-input LUT through the left mux.
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In arithmetic mode, their outputs are fed to the FA. The selection of mode is programmed into the middle multiplexer. The output can be either synchronous or asynchronous, depending on the programming of the mux to the right. ALMs and Slices usually contain 2 or 4 structures similar to the example figure, with some shared signals. CLBs/LABs typically contain a few ALMs/LEs/Slices. In recent years, manufacturers have started moving to 6-input LUTs in their high performance parts, claiming increased performance.

Figure 5.3 - Structure of configurable logic blocks (CLB) Generally, the FPGA routing is un-segmented. That is, each wiring segment spans only one logic block before it terminates in a switch box. By turning on some of the programmable switches within a switch
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box, longer paths can be constructed. For higher speed interconnect, some FPGA architectures use longer routing lines that span multiple logic blocks.

Figure 5.4 - Switch box topology FPGAs are also widely used for systems validation including pre-silicon validation, post-silicon validation, and firmware development. This allows chip companies to validate their design before the chip is produced in the factory, reducing the time-to-market. To shrink the size and power consumption of FPGAs, vendors such as Tabula and Xilinx have introduced new 3D or stacked

architectures. Following the introduction of its 28 nm 7-series

5.2FPGA DESIGN AND PROGRAMMING

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To define the behavior of the FPGA, the user provides a HDL or a schematic design. The HDL form is more suited to work with large structures because it's possible to just specify them numerically rather than having to draw every piece by hand. However, schematic entry can allow for easier visualization of a design. The most common HDLs are VHDL and Verilog, although in an attempt to reduce the complexity of designing in HDLs, which have been compared to the equivalent of assembly languages, there are moves to raise the abstraction level through the introduction of languages. To simplify the design of complex systems in FPGAs, there exist libraries of predefined complex functions and circuits that have been tested and optimized to speed up the design process. These predefined circuits are commonly called IP cores, and are available from FPGA vendors and third-party IP suppliers (rarely free and typically released under proprietary licenses). In a typical design flow, an FPGA application developer will simulate the design at multiple stages throughout the design process. Initially the RTL description in VHDL or Verilog is simulated by creating test benches to simulate the system and observe results. Then, after the synthesis engine has mapped the design to a netlist, the netlist is translated to a gate level description where simulation is repeated to confirm the synthesis proceeded without errors. Finally the design is

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laid out in the FPGA at which point propagation delays can be added and the simulation run again with these values back-annotated onto the netlist.
5.3 ALTERA

MAX II MICRO BOARD

The FPGA kit used in the project isAltera MAX II EPM2210F324. Which filful the requirements of project and other FPGA kits are more expensive as compare to ALTERA MAX II MICRO. A photograph of the MAX II Micro board is shown in Figure 5.1. It depicts the layout of the board and indicates the location of the connectors and key

components.

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Figure 5.5 - The MAX II Micro board.

5.4Layout and Components of MAX II board

The following hardware is provided on the MAX II Micro board: Altera MAX II EPM2210F324 FPGA device USB Blaster (on board) for programming; MAX II Micro can be used as a USB Blaster,and programming mode supported depends on the configuration device of Altera board connected to MAX II Micro. Only JTAG programming mode is supported to configure MAX II Micro. 4 pushbutton switches
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1 DIP switch 2 red user LEDs 2 yellow user LEDs 2 green user LEDs 2 blue user LEDs 50-MHz oscillator for clock sources Powered by a USB cable (Type-A-Male to Type-A-Female)

5.1BLOCK DIAGRAM OF THE MAX II MICRO BOARD

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Figure 5.6 - Block diagram of the MAX II Micro board.

5.12.1MAX II 2210 FPGA

2,210 Les 272 user I/O pins Fine Line BGA 324-pin package
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5.12.1USB BLASTER CIRCUIT

On-board USB Blaster for programming Only JTAG programming mode is supported to configure MAX II Micro or when MAX II Micro is used as a USB Blaster cable.

5.12.1PUSHBUTTON SWITCHES
4 pushbutton switches Debounced by a Schmitt trigger circuit Normally high; generates one active-low pulse when the switch is pressed.

5.12.1CLOCK INPUTS
50-MHz oscillator

5.12.1PROTOTYPING AREAS
A 40-pin expansion port area compatible with Altera DE2/DE1 expansion ports.

Prototyping Area A with 68 GPIO, 6 3.3V, 2 5V and 8 GND pins Prototyping Area B with 20 GPIO, 2 3.3V, and 2 GND pins

5.1SCHEMATIC OF THE MAX II MICRO BOARD

The complete schematic can be found in the Schematic folder of MAX II Micro System CD-ROM. The following sections describe the major parts of the schematic in detail.
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5.13.16BLEDS,

SWITCHES, AND CLOCK INPUTS

The MAX II Micro board provides four pushbutton switches. Each of these switches is debounced using a Schmitt Trigger circuit, as indicated in Figure 2.3. The four outputs called KEY0, ,KEY3 of the Schmitt Trigger device are connected directly to the MAX II CPLD. Each switch provides a high logic level (3.3 volts) when it is not pressed, and provides a low logic level (0 volts) when depressed. Since the pushbutton switches are debounced, they are appropriate for use as clock or reset inputs in a circuit.

Figure 5.7 Switch debouncing. There are 8 user-controllable LEDs on the MAX II Micro board. Each LED is driven directly by a pin on the MAX II CPLD; driving its associated pin to a high logic level turns the LED on, and driving the pin low turns it off.

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A list of the pin names on the MAX II CPLD that are connected to the LEDs, pushbuttons, and clock inputs is given in Table 2.1.

Table 5.1 - Pin assignments for the LEDs, Buttons, and Clock inputs.

Figure 5.8 - Schematic diagrams of the LEDs, pushbuttons, and clock circuit.

5.13.2EXPANSION PORT AND PROTOTYPING AREA

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The MAX II Micro board provides users two prototyping area: PROTO_A and PROTO_B, as shown in Figure 2.1. The schematics are shown in Figure 2.5 and Figure 2.6.To help users locate the corresponding GPIOs, we provide a detailed I/O map shown in Figure 2.7.

Figure 5.9 - Schematic of the prototyping area.

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Figure 5.10 - Schematic of the prototyping area. Prototyping Area A and Prototyping Area B

Figure 5.11 - The detailed I/O map of prototyping area A and B.

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5.1POWER-UP THE MAX II MICRO BOARD

The MAX II Micro board comes with a pre-loaded configuration bit stream to demonstrate various LED modes. This bit stream also allows users to see quickly if the board is working properly. For

communication between the host and the MAX II Micro board, it is necessary to install the Altera USB Blaster driver software. The driver only supports Windows OS, and if it is not already installed on the host computer, it can be installed as explained in the Altera website: For XP: HUhttp://www.altera.com/support/software/drivers/usb-blaster/dri-usbblaster-xp.htmlU For 2000:

HUhttp://www.altera.com/support/software/drivers/usb-blaster/dri-usb blaster-2000.htmlU At this point you should observe LEDs turn ON/OFF in sequence there are 2 different modes. Pre-loaded and it can be changed by pressing Button1. Each mode can be reset by pressing corresponding Button3 and Button4.

5.2METHODS TO CONFIGURE THE MAX II MICRO BOARD

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The MAX II Micro board provides two modes, JTAG Mode and USB Blaster Mode, which allows users to use the MAX II Micro board as a CPLD development board or as a USB Blaster cable respectively.

5.15.1CONFIGURE THE MAX II MICRO BOARD IN JTAG MODE

Users should use JTAG mode in normal operation. Set Swtich1 to UP position and set Switch2 to DOWN position as shown in Figure 2.8.

Figure 5.12 - Set Switch1 to UP position and Switch2to DOWN Position in normal operation (JTAG mode)

5.15.2USE MAX II MICRO AS A USB BLASTER CABLE

This section describes how to use MAX II Micro as a USB Blaster Cable. Simply follow the instructions below to finish the setting. Before using

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MAX II Micro board as a USB Blaster, you need to solder a 10-pin header onto the board as show in Figure 2.9. Note: The USB blaster cable function only supports JTAG programming mode.

Figure 5.13 - Solder a 10-pin header onto the MAX II Micro board Connect the USB cable to the USB port on your PC and to the USB-Blaster port of MAX II Micro board.

Set the both dip switches on the Max II Micro board to UP location, as shown in Figure 2.10.

Connect the USB-Blaster download cable to the 10-pin header (J3) on the device board and MAX II Micro board. Figure 2.11 shows how to use the MAX II Micro Board to configure an Altera NIOS II Kit.

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Figure 5.14 set both switches to UP position to set up the MAX II Micro board as a USB Blaster.

Figure 2.11 Use MAX II Micro as a USB Blaster cable and Connect to another Altera board (NIOS II Kit in this case).

5.15.1MAX II CPLD POWER OFF MODE

The MAX II Micro board provides a Power OFF switch mode to completely shut down the MAX II CPLD by setting Switch1 to DOWN position as show in Figure 2.12.

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Figure 2.12 -Set Switch1 to DOWN position to Turn off the power supply to MAX II CPLD

5.1MAX 11 MICRO BOARD CONTOL PANEL

The MAX II Micro board comes with a Control Panel facility that allows users to access various components on the board through a USB connection from a host computer. This chapter first presents how to setting up the Control Panel, then describes its structure in block diagram form, and finally describes its capabilities. To run the Control Panel application, it is first necessary to configure a corresponding circuit in the MAX II CPLD. This is done by downloading the configuration file DEN_Control_Panel.pof into the CPLD. The downloading procedure is described as followed. In addition to the DEN_Control_Panel.poffile, it is necessary to execute on the host computer the program DEN_Control_Panel.exe. Both of these files are available under the directory DEN_control_panel of the MAX II Micro system CD-ROM included. To activate the Control Panel, perform the following steps: Configure the dip switch on the MAX II Micro board as shown in Figure 2.8. Connect the USB cable to the USB port on your PC and to the USB-Blaster port of MAX II Micro board.
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Start the Quartus II software. Select Tools >Programmer to reach the window in Figure 3.1. Click on Add File and in the pop-up window that appears select the DEN_Control_Panel.poffile. Next, click on the three check boxes in the Program/Configure columns. Now, click Start to download the configuration file into the CPLD.

Once the download is finished, Plug out the USB cable from the MAX II Micro board and re-plug it in to power up and reset the MAX II CPLD device.

Start

the

executable

DEN_Control_Panel.exe

on

the

host

computer. The Control Panel user interface shown in Figure 3.2 will appear.

The Control Panel also can download the configuration file DEN_Control_Panel.pof into the CPLD by clicking the icon of Download. POF as shown in Figure 3.2.

The Control Panel is now ready for use.

The Control Panel will occupy the USB port, you cannot use Quartus II to download a configuration file into the CPLD until you close the Control Panel.

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Figure 3.1 - Quartus II Programmer window

Figure 3.2 - The MAX II Micro Board Control Panel window. The concept of the MAX II Micro Control Panel is illustrated in Figure 3.3. The IP that Performs the control functions are implemented in the CPLD device. It communicates with the Control Panel window, which is active on the

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host computer, via the USB Blaster link. The graphical interface is used to issue commands to the control circuitry. The provided IP handles all requests and performs data transfers between the computer and the MAX II Micro board.

Figure 3.3 The MAX II Micro Control Panel concepts.

5.1USING THE CONTROL PANEL

The interface of the MAX II Micro control panel window matches the real MAX II Micro board. Users can select the components they want to control directly. All configurable components are marked with blue frame in the window. The MAX II Micro Control Panel can be used to light up LEDs, detect the pressed action of pushbutton switches and configure the I/O logic level of prototyping area on the MAX II Micro board. The following sections describe how to perform these actions with the control panel already open on the host computer

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Typical design activities do not require the ability to set arbitrary values for simple display devices. However, for troubleshooting purposes, setting arbitrary values enables you to verify that the devices are operating correctly.

5.17.1LIGHT UP THE LEDS

To light up the LEDs on the MAX II Micro board, you can turn the individual LEDs on by clicking the LED icon on the control panel window as show in the Figure 3.4. The icon of the chosen LED will be marked with yellow color.

5.17.2DETECTION PUSHBUTTONS

OF

THE

ACTION

OF

THE

When users press the pushbutton switches on the MAX II Micro board, the MAX II Micro control panel window will indicate which pushbutton switches are pressed with an arrow icon

5.17.3CONFIGURE

THE

GPIOS

IN

THE

PROTOTYPING AREA
The I/O logic level of the GPIOs in the prototyping area is low (0 volts), you can change the logic level of the GPIOs to high (3.3 volts) by clicking the corresponding GPIO holes on the control panel window as show in Figure 3.6. The icon of the chosen GPIO holes will be marked with yellow colour. With
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this function you can control the other circuit easily by using the control panel and prototyping area I/Os. Corresponding holes shown in the Control Panel window section. The GPIOs colour will be marked by yellow to indicate their voltage level is HIGH (3.3V).

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