Mux-Based Latches

Negative latch (transparent when CLK= 0)

Q = Clk Q + Clk In

1 D 0

Q D

1 0

CLK = 0

CLK = 1

Mux-Based Latches
Positive latch (transparent when CLK= 1)
Q = Clk Q + Clk In

0 D 1

Q D

0 1

CLK = 0

CLK = 1

Mux-Based Latch
CLK

CLK=0
Q CLK

CLK=1
D

CLK

Mux-Based Latch
CLK

CLK=1 CLK=0

QM QM

CLK

CLK

CLK

NMOS only

Non-overlapping clocks

Master-Slave (Edge-Triggered) Register

Slave Master 0 1 D 0 QM 1 Q D QM Q CLK CLK

Two opposite latches trigger on edge Also called master-slave latch pair

Master-Slave (Edge-Triggered) Register

Slave Master 0 1 D 0 QM 1 Q D QM Q CLK CLK

CLK=0

Two opposite latches trigger on edge Also called master-slave latch pair

Master-Slave (Edge-Triggered) Register

Slave Master 0 1 D 0 QM 1 Q D QM Q CLK CLK

CLK=1 Two opposite latches trigger on edge Also called master-slave latch pair

Master-Slave Register
Multiplexer-based latch pair

I2

T2

I3 QM

I5

T4

I6

I1

T1

I4

T3

CLK

CLK = 0 T1, T4 accesi, T2, T3 spenti CLK = 1 T2, T3 accesi, T1, T4 spenti

Master-Slave Register
Multiplexer-based latch pair

I2

T2

I3 QM

I5

T4

I6

I1

T1

I4

T3

CLK

CLK = 0 T1, T4 accesi, T2, T3 spenti CLK = 1 T2, T3 accesi, T1, T4 spenti

Master-Slave Register
Multiplexer-based latch pair

I2

T2

I3 QM

I5

T4

I6

I1

T1

I4

T3

CLK

CLK = 0 T1, T4 accesi, T2, T3 spenti CLK = 1 T2, T3 accesi, T1, T4 spenti

Master-Slave Register
Multiplexer-based latch pair

I2

T2

I3 QM

I5

T4

I6

tcq
I4 T3

I1

T1

CLK

CLK = 0 T1, T4 accesi, T2, T3 spenti CLK = 1 T2, T3 accesi, T1, T4 spenti

Clk-Q Delay
2.5

CLK
CLK

1.5
Volts

tc 2

q(lh)

tc 2

q(hl)

0.5

2 - 0.5

0.5

1 1.5 time, nsec

2.5

Master-Slave Register: setup

Setup time

I2

T2

I3 QM

I5

T4

I6

I1

T1

I4

T3

CLK

il dato D deve avere il tempo di attraversare I1, T1, I3 e I2 prima che CLK passi da 0 a 1

D deve arrivare tsu=tpI1+tpT1+tpI3+tpI2 prima della transizione 0 - 1 del clock

Master-Slave Register: setup

Setup time

I2

T2

I3 QM

I5

T4

I6

I1

T1

I4

T3

CLK

il dato D deve avere il tempo di attraversare I1, T1, I3 e I2 prima che CLK passi da 0 a 1

D deve arrivare tsu=tpI1+tpT1+tpI3+tpI2 prima della transizione 0 - 1 del clock

Master-Slave Register: setup

Setup time

tsu
I2 T2 I3 QM I1 T1 I4 T3 I5 T4 I6 Q

CLK

il dato D deve avere il tempo di attraversare I1, T1, I3 e I2 prima che CLK passi da 0 a 1

D deve arrivare tsu=tpI1+tpT1+tpI3+tpI2 prima della transizione 0 - 1 del clock

Setup Time
3.0 2.5 2.0 1.5 D
Volts

3.0 Q QM CLK
Volts

2.5 2.0 1.5 D 1.0 QM 0.5 0.0 I2 2 T 2 CLK

I2 2 T 2
Q

1.0 0.5 0.0

2 0.5

0.2

0.4 0.6 time (nsec)

0.8

2 0.5

0.2

0.4 0.6 time (nsec)

0.8

(a) Tsu=0.21 ns t setup 5 0.21 nsec

(b) tsu=0.20 ns T setup 5 0.20 nsec

Cross-Coupled NAND
Cross-coupled NANDs set-reset
S

forbidden state S R 0 1 0 1 Q 1 1 0 Q Q 1 0 1 Q

S R
R Q

Q Q

0 0 1 1

Other Latches/Registers: C2MOS

VDD M2 VDD M6

CLK D CLK

M4 X M3 CL1

CLK

M8 Q CL2

CLK

M7

M1

M5

Master Stage

Other Latches/Registers: C2MOS

VDD M2 VDD M6

CLK D CLK

M4

CLK=0
X CL1

CLK

M8 Q CL2

M3

CLK

M7

M1

M5

Master Stage

Other Latches/Registers: C2MOS

VDD M2 VDD M6

CLK D CLK

M4 X M3 CL1

CLK

M8

CLK=1
Q CL2

CLK

M7

M1

M5

Master Stage

TSPC Register
VDD CLK VDD VDD Q Q CLK M8

M3

M6 Y

M9

CLK

M2

M5

M1

CLK

M4

M7

TSPC Register
1/2 N-latch
VDD CLK VDD VDD Q Q CLK M8

M3

M6 Y

M9

CLK

M2

M5

M1

CLK

M4

M7

TSPC Register
1/2 N-latch
VDD CLK VDD VDD

1/2 P-latch
Q Q

M3

M6 Y

M9

CLK

M2

M5

CLK

M8

M1

CLK

M4

M7

TSPC Register
precharge inverter 1/2 N-latch
VDD CLK VDD VDD

1/2 P-latch
Q Q

M3

M6 Y

M9

CLK

M2

M5

CLK

M8

M1

CLK

M4

M7

TSPC Register: funzionamento

VDD CLK VDD VDD Q Q CLK M8

M3

M6 Y

M9

CLK

M2

M5

M1

CLK

M4

M7

TSPC Register: funzionamento

precarica
VDD CLK VDD VDD Q Q CLK M8

M3

M6 Y

M9

CLK

M2

M5

mantiene il dato precedente

M1

CLK

M4

M7

CLK=0

TSPC Register: funzionamento

VDD CLK VDD VDD Q Q CLK M8

M3

M6 Y

M9

CLK

M2

M5

M1

CLK

CLK=1
M4 M7

valutazione