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Design 4x1 multiplexer using VHDL in dataflow model? 3. Design Full adder using two half adders? 4. Design four bit full adder using 1 bit full adder? 5. Design 4x16 decoder using two 74x138 and verify its functionality by test bench? 6. Design 5x32 decoder using one 74x139 and four 74x138 and verify its functionality by test bench?