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  • Venkatesh Prasad: Day 4 Latchup, ESD & Antenna

    Transféré par

    Kanhaiya Mishra
    31 vues13 pages
    Latchup is a failure mechanism of CMOS integrated circuits. It is characterized by excessive current drain coupled with functional failure, parametric failure and / or device destruction. The cause of the latchup exists in all junctions -isolated or bulk CMOS processes: parasitic PNPN paths.

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    Latchup is a failure mechanism of CMOS integrated circuits. It is characterized by excessive current drain coupled with functional failure, parametric failure and / or device destruction. The cause of the latchup exists in all junctions -isolated or bulk CMOS processes: parasitic PNPN paths.

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    31 vues13 pages

    Venkatesh Prasad: Day 4 Latchup, ESD & Antenna

    Transféré par

    Kanhaiya Mishra
    Latchup is a failure mechanism of CMOS integrated circuits. It is characterized by excessive current drain coupled with functional failure, parametric failure and / or device destruction. The cause of the latchup exists in all junctions -isolated or bulk CMOS processes: parasitic PNPN paths.

    Droits d'auteur :

    Attribution Non-Commercial (BY-NC)
    Téléchargez comme PDF, TXT ou lisez en ligne sur Scribd
    Signaler comme contenu inapproprié
    sur 13

    DAY4 Latchup,ESD&Antenna VENKATESHPRASAD

    01/07/09

    WhatisLatchup?
    ItisafailuremechanismofCMOSintegratedcircuitscharacterized byexcessivecurrentdraincoupledwithfunctionalfailure, parametricfailureand/ordevicedestruction. Thecauseofthelatchupexistsinalljunctionsisolatedorbulk CMOSprocesses:parasiticPNPNpaths.

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    Latchup
    in Vdd
    out
    p+ n+ n+ P+ Nwell p+ n+

    GND

    Vdd

    Rsub T1

    T1
    Rsub

    T2

    Rwell

    vsub
    Substratetap

    T2
    Well tap

    Psubstrate

    Rwell

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    Conditionwhicharenecessaryfor latchuptooccur
    Bothparasiticbipolarmustbebiasedintotheactivestate. Theproductoftheparasiticbipolartransitioncurrentgainmustbe sufficienttoallowregeneration.i.e.,greaterthanorequaltoone. Theterminalnetworkmustbecapableofsupplyingacurrentgreater thantheholdingcurrentrequiredbythePNPNpath.

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    Guidelinestoavoidlatchup
    Everywellshouldhaveatleastonetap. Allsubstrateandwelltapsshouldconnectdirectlytotheappropriate supplyinmetal. nMOStransistorsshouldbeclusteredtogethernearGNDand pMOStransistorsshouldbeclusteredtogethernearVDD,avoiding convolutedstructuresthatintertwinenMOSandpMOStransistorsin checkboardpatterns.

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    ESD
    Itcanoccurwhenthechargesstoredinmachinesorthehumanbody aredischargedtothechiponcontactorbystaticinduction. DifferentmodelsforESDtesting 1.HBMHumanBodyModel 2.MMMachineModel 3.CDMChargeDeviceModel

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    HumanBodyModelHBM
    1Mohms 1.5kohms

    Inthismethodatouchofa chargedpersonsfingeris simulatedbydischarginga 100pfcapacitorthrougha 1.5kohmsresistor. Effectiveprotectionnetworks canwithstandashighas8kV HBMESDstress.

    Vesd

    100pf

    DUT

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    MachineModelMM

    Contactwithothermachines alsocauseESDstress. Bodyresistanceisabsent, thestresscanbemore severewithhighercurrent levels.


    +

    1Mohms

    Vesd

    200pf

    DUT

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    ChargeDeviceModelCDM

    1Gohms

    DUT

    TheCDMESDtesters electricallychargeDUTand thendischargeittoground, thusprobingthehighshort durationcurrentpulsetoDUT.

    Charging supply

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    AntennaEffect
    Metallayer gate D S

    Chargescollectedonmetalcancreateasignificantelectricalfields acrossthegateoxides.Thisiscalledantennaeffect. Antennadesignrule:specifythemaximumratioofmetalareato gateareasuchthatchargeonthemetalwillnotdamagethegate.

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    10

    MetalSplittingorLayerJumping

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    MetalSplittingorLayerJumping

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    Electromigration
    Highcurrentdensitiesleadtoanelectronwindthatcauses metalatomstomigrateovertime. Electromigrationdependsonthecurrentdensity,J=I/(w.t) Theelectromigrationcurrentslimitsvarywithmaterials, processing,desiredmeantimetofailureandobtainedfromthe fabricationvendor.

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    13

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