Introduction to CMOS VLSI Design

Lecture 9: Circuit Families

David Harris

Harvey Mudd College Spring 2004

Outline
Pseudo-nMOS Logic Dynamic Logic Pass Transistor Logic

9: Circuit Families

CMOS VLSI Design

Slide 2

Introduction
What makes a circuit fast? I = C dV/dt -> tpd (C/I) V low capacitance high current 4 B small swing 4 A Logical effort is proportional to C/I 1 1 pMOS are the enemy! High capacitance for a given current Can we take the pMOS capacitance off the input? Various circuit families try to do this
CMOS VLSI Design

9: Circuit Families

Slide 3

Pseudo-nMOS
In the old days, nMOS processes had no pMOS Instead, use pull-up transistor that is always ON In CMOS, use a pMOS that is always ON Ratio issue Make pMOS about effective strength of pulldown network
1.8 1.5 1.2 P = 24 Vout 0.9

load

P/2 Ids Vout 16/2 Vin

0.6 P = 14 0.3 0 0 0.3 0.6 0.9 Vin 1.2 1.5 1.8 P=4

9: Circuit Families

CMOS VLSI Design

Slide 4

Pseudo-nMOS Gates
Design for unit current on output to compare with unit inverter. pMOS fights nMOS
Y inputs f

Inverter
gu gd gavg pu pd pavg = = = = = =

NAND2
gu g Y gd avg pu pd pavg = = = = = =

NOR2
gu gd gavg Y pu pd pavg = = = = = =
Slide 5

Y A

A B

9: Circuit Families

CMOS VLSI Design

Pseudo-nMOS Gates
Design for unit current on output to compare with unit inverter. pMOS fights nMOS
Y inputs f

Inverter
gu gd gavg pu pd pavg = = = = = =

NAND2
gu g Y gd avg 8/3 pu pd 8/3 pavg 2/3 A B = = = = = =

NOR2
gu gd gavg Y pu 4/3 pd pavg = = = = = =
Slide 6

2/3 A 4/3

2/3 A 4/3 B

9: Circuit Families

CMOS VLSI Design

Pseudo-nMOS Gates
Design for unit current on output to compare with unit inverter. pMOS fights nMOS
Y inputs f

Inverter
gu gd gavg pu pd pavg = 4/3 = 4/9 = 8/9 = = =

NAND2
gu 2/3 g Y gd avg 8/3 pu pd 8/3 pavg = 8/3 = 8/9 = 16/9 = = =

NOR2
gu gd gavg Y pu 4/3 pd pavg = 4/3 = 4/9 = 8/9 = = =
Slide 7

2/3 A 4/3

A B

2/3 A 4/3 B

9: Circuit Families

CMOS VLSI Design

Pseudo-nMOS Gates
Design for unit current on output to compare with unit inverter. pMOS fights nMOS
Y inputs f

Inverter
gu gd gavg pu pd pavg = 4/3 = 4/9 = 8/9 = 6/3 = 6/9 = 12/9

NAND2
gu g Y gd avg 8/3 pu pd 8/3 pavg 2/3 A B = 8/3 = 8/9 = 16/9 = 10/3 = 10/9 = 20/9

NOR2
gu gd gavg Y pu 4/3 pd pavg = 4/3 = 4/9 = 8/9 = 10/3 = 10/9 = 20/9
Slide 8

2/3 A 4/3

2/3 A 4/3 B

9: Circuit Families

CMOS VLSI Design

Pseudo-nMOS Design
Ex: Design a k-input AND gate using pseudo-nMOS. Estimate the delay driving a fanout of H
Pseudo-nMOS

G= F= P= N= D=

In1 Ink

1 1

Y H

9: Circuit Families

CMOS VLSI Design

Slide 9

Pseudo-nMOS Design
Ex: Design a k-input AND gate using pseudo-nMOS. Estimate the delay driving a fanout of H
Pseudo-nMOS

G = 1 * 8/9 = 8/9 F = GBH = 8H/9 P = 1 + (4+8k)/9 = (8k+13)/9 N=2 4 2 H 8k + 13 1/N + D = NF + P = 3 9

In1 Ink

1 1

Y H

9: Circuit Families

CMOS VLSI Design

Slide 10

Pseudo-nMOS Power
Pseudo-nMOS draws power whenever Y = 0 Called static power P = IVDD A few mA / gate * 1M gates would be a problem This is why nMOS went extinct! Use pseudo-nMOS sparingly for wide NORs Turn off pMOS when not in use
en Y A B C

9: Circuit Families

CMOS VLSI Design

Slide 11

Dynamic Logic
Dynamic gates uses a clocked pMOS pullup Two modes: precharge and evaluate
2 1 Static
Y

2/3 A 4/3

1 1

Pseudo-nMOS
Precharge

Dynamic
Evaluate Precharge

9: Circuit Families

CMOS VLSI Design

Slide 12

The Foot
What if pulldown network is ON during precharge? Use series evaluation transistor to prevent fight.
precharge transistor Y foot
footed unfooted inputs inputs

Y f

Y f

9: Circuit Families

CMOS VLSI Design

Slide 13

Logical Effort
Inverter NAND2
1 2 2

NOR2

unfooted

1 1

Y gd pd = =

A B

Y A

gd pd = = 1

1 B 1

Y gd pd = =

1 2 2

1 3 3 3

footed

Y gd pd = =

A B

Y A

gd pd = = 2

1 B 2 2 Y gd pd = =

9: Circuit Families

CMOS VLSI Design

Slide 14

Logical Effort
Inverter NAND2
1 2 2

NOR2

unfooted

1 1

Y gd pd = 1/3 = 2/3

A B

Y A

gd pd = 2/3 = 3/3 1

1 B 1

Y gd pd = 1/3 = 3/3

1 2 2

1 3 3 3

footed

Y gd pd = 2/3 = 3/3

A B

Y A

gd pd = 3/3 = 4/3 2

1 B 2 2 Y gd pd = 2/3 = 5/3

9: Circuit Families

CMOS VLSI Design

Slide 15

Monotonicity
Dynamic gates require monotonically rising inputs during evaluation 0 -> 0 A 0 -> 1 1 -> 1 violates monotonicity But not 1 -> 0 during evaluation
A Y Output should rise but does not Precharge Evaluate Precharge

9: Circuit Families

CMOS VLSI Design

Slide 16

Monotonicity Woes
But dynamic gates produce monotonically falling outputs during evaluation Illegal for one dynamic gate to drive another!
A=1 A X X Y Precharge Evaluate Precharge

9: Circuit Families

CMOS VLSI Design

Slide 17

Monotonicity Woes
But dynamic gates produce monotonically falling outputs during evaluation Illegal for one dynamic gate to drive another!
A=1 A X X X monotonically falls during evaluation Y Y should rise but cannot Precharge Evaluate Precharge

9: Circuit Families

CMOS VLSI Design

Slide 18

Domino Gates
Follow dynamic stage with inverting static gate Dynamic / static pair is called domino gate Produces monotonic outputs
Precharge Evaluate Precharge

domino AND

W A B

X C

X Y Z

dynamic static NAND inverter

A B

W H C X

Y H Z = A B

X C

9: Circuit Families

CMOS VLSI Design

Slide 19

Domino Optimizations
Each domino gate triggers next one, like a string of dominos toppling over Gates evaluate sequentially but precharge in parallel Thus evaluation is more critical than precharge HI-skewed static stages can perform logic
S0 D0 S1 D1 S2 D2 S3 D3 H S4 D4 S5 D5 S6 D6 S7 D7 Y

9: Circuit Families

CMOS VLSI Design

Slide 20

Dual-Rail Domino
Domino only performs noninverting functions: AND, OR but not NAND, NOR, or XOR Dual-rail domino solves this problem Takes true and complementary inputs Produces true and complementary outputs
sig_h 0 0 1 1 sig_l 0 1 0 1 Meaning Precharged 0 1 invalid
CMOS VLSI Design Slide 21
Y_l inputs f f Y_h

9: Circuit Families

Example: AND/NAND
Given A_h, A_l, B_h, B_l Compute Y_h = A * B, Y_l = ~(A * B)

9: Circuit Families

CMOS VLSI Design

Slide 22

Example: AND/NAND
Given A_h, A_l, B_h, B_l Compute Y_h = A * B, Y_l = ~(A * B) Pulldown networks are conduction complements

Y_l = A*B A_l B_l

A_h B_h

Y_h = A*B

9: Circuit Families

CMOS VLSI Design

Slide 23

Example: XOR/XNOR
Sometimes possible to share transistors

Y_l = A xnor B A_h A_l B_l

Y_h A_l B_h A_h = A xor B

9: Circuit Families

CMOS VLSI Design

Slide 24

Leakage
Dynamic node floats high during evaluation Transistors are leaky (IOFF 0) Dynamic value will leak away over time Formerly miliseconds, now nanoseconds! Use keeper to hold dynamic node Must be weak enough not to fight evaluation
weak keeper A 1 k 2 2 X H Y

9: Circuit Families

CMOS VLSI Design

Slide 25

Charge Sharing
Dynamic gates suffer from charge sharing
A B=0 x Cx Y CY

A Y

9: Circuit Families

CMOS VLSI Design

Slide 26

Charge Sharing
Dynamic gates suffer from charge sharing
A B=0 x Cx Y CY

A Y Charge sharing noise x

Vx = VY =

9: Circuit Families

CMOS VLSI Design

Slide 27

Charge Sharing
Dynamic gates suffer from charge sharing
A B=0 x Cx Y CY

A Y Charge sharing noise x

CY Vx = VY = VDD C x + CY
9: Circuit Families CMOS VLSI Design Slide 28

Secondary Precharge
Solution: add secondary precharge transistors Typically need to precharge every other node Big load capacitance CY helps as well
Y A B x secondary precharge transistor

9: Circuit Families

CMOS VLSI Design

Slide 29

Noise Sensitivity
Dynamic gates are very sensitive to noise Inputs: VIH Vtn Outputs: floating output susceptible noise Noise sources Capacitive crosstalk Charge sharing Power supply noise Feedthrough noise And more!

9: Circuit Families

CMOS VLSI Design

Slide 30

Domino Summary
Domino logic is attractive for high-speed circuits 1.5 2x faster than static CMOS But many challenges: Monotonicity Leakage Charge sharing Noise Widely used in high-performance microprocessors

9: Circuit Families

CMOS VLSI Design

Slide 31

Pass Transistor Circuits

Use pass transistors like switches to do logic Inputs drive diffusion terminals as well as gates CMOS + Transmission Gates: 2-input multiplexer Gates should be restoring
S A S B S
9: Circuit Families CMOS VLSI Design

S A Y B S
Slide 32

LEAP
LEAn integration with Pass transistors Get rid of pMOS transistors Use weak pMOS feedback to pull fully high Ratio constraint

S A S B L Y

9: Circuit Families

CMOS VLSI Design

Slide 33

CPL
Complementary Pass-transistor Logic Dual-rail form of pass transistor logic Avoids need for ratioed feedback Optional cross-coupling for rail-to-rail swing
S A S B S A S B L Y L Y

9: Circuit Families

CMOS VLSI Design

Slide 34