module clk(a,s,p,clk_0

);
input [10:0]a,s;
input [2:0]p;
output clk_0;
wire [11:0]w;
mux2_1 m1(~clk_0,a[0],s[0],w[0]);
mux2_1 m2(w[0],a[1],s[1],w[1]);
mux2_1 m3(w[1],a[2],s[2],w[2]);
mlb d0(w[0],w[1],w[2],w[3]);
mux2_1 m4(w[3],a[3],s[3],w[4]);
mux2_1 m5(w[4],a[4],s[4],w[5]);
mux2_1 m6(w[5],a[5],s[5],w[6]);
mux2_1 m7(w[6],a[6],s[6],w[7]);
mux2_1 m8(w[7],a[7],s[7],w[8]);
mux2_1 m9(w[8],a[8],s[8],w[9]);
mux2_1 m10(w[9],a[9],s[9],w[10]);
mux2_1 m11(w[10],a[10],s[10],w[11]);
mux8_1 m12(w[11:4],p[2:0],clk_0);
endmodule

module mux2_1(a,b,s,y);
input a,b,s;
output reg y;
always @ (a or b or s)
begin
if(s==0)
y=a;
else
y=b;
end
endmodule
module mux8_1(d,s,y);
input [7:0]d;
input [2:0]s;
output reg y;
always @ (d or s)
begin
if(s[2]==0 && s[1]==0 && s[0]==0)
y=d[0];
else if(s[2]==0 && s[1]==0 && s[0]==1)
y=d[1];
else if(s[2]==0 && s[1]==1 && s[0]==0)
y=d[2];
else if(s[2]==0 && s[1]==1 && s[0]==1)
y=d[3];
else if(s[2]==1 && s[1]==0 && s[0]==0)
y=d[4];
else if(s[2]==1 && s[1]==0 && s[0]==1)
y=d[5];
else if(s[2]==1 && s[1]==1 && s[0]==0)
y=d[6];
else

y=d[7];
end
endmodule
//majority logic block
module mlb (a,b,c,y);
input a;
input b;
input c;
output y;
assign y=(a&b)|(b&c)|(c&a);
endmodule