Overview

Chapter 9 Part A
Counters and Shift Registers

Counters
Types Design of State Table VHDL

Shift Registers
Types VHDL SR Based Counters
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Counters and Shift Registers

Counter: A Sequential Circuit that counts pulses. Used for Event Counting, Frequency Division, Timing, and Control Operations. Shift Register: A Sequential Circuit that moves stored data bits in a specific direction. Used in Serial Data Transfers, SIPO/PISO Conversions, Arithmetic, and Delays.

Counter Terminology 1
A Counter is a digital circuit whose outputs progress in a predictable repeating pattern. It advances on state for each clock pulse. State Diagram: A graphical diagram showing the progression of states in a sequential circuit such as a counter.
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Counter Terminology 2
Count Sequence: The specific series of output states through which a counter progresses. Modulus: The number of states a counter sequences through before repeating (mod-n). Counter directions:
UP - count high to low (MSB to LSB) DOWN - count low to high (LSB to MSB).

Counter Modulus
Modulus of a counter is the number of states through which a counter progresses. A Mod-12 UP Counter counts 12 states from 0000 (010) to 1011 (1110). The process then repeats. A Mod-12 DOWN counter counts from 1011 (1110) to 0000 (010), then repeats.

State Diagram
A diagram that shows the progressive states of a sequential circuit. The progression from one state to the next state is shown by an arrow.
(0000 0001 0010).

MOD 12 Counter State Diagram

With each clock pulse the counter progresses by one state from its present position on the state diagram to the next state in the sequence. This close system of counting and adding is known as modulo arithmetic.

Each state progression is caused by a pulse on the clock to the sequential circuit.
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MOD 12 Counter State Diagram

Truncated Counters 1
An n-bit counter that counts the maximum modulus (2n) is called a fullsequence counter such as Mod 2, Mod 4, Mod 8, etc. An n-bit counter whose modulus is less than the maximum possible is called a truncated sequence counter, such as mod 3 (n = 2), mod 12 (n = 4).
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Truncated Counters 2
A 4-bit mod 12 UP counter that counts from 0000 to 1011 is an example of a truncated counter. A 4-bit mod 16 UP counter that counts up from 0000 to 1111 is an example of a full-sequence counter.

Truncated Counters 3

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Counter Timing Diagrams 1

Shows the timing relationships between the input clock and the outputs Q3, Q2, Q1, Qn of a counter. For a 4-bit mod 16 counter, the output Q0 changes for every clock pulse, Q1 changes on every two clock pulses, Q2 on four, and Q3 on 8 clocks.
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Counter Timing Diagrams 2

The outputs (Q0 Q3) of the counter can be used as frequency dividers with Q0 = clock 2, Q1 = clock 4, Q2 = clock 8, and Q3 = clock 16. The frequency is based on T of the output, not a transition on the output. The same is true for a mod 12, except Q3 = clock 12.
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Counter Timing Diagrams 3

Counter Timing Diagrams 4

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Synchronous Counters
A counter whose flip-flops are all clocked by the same source and change state in synchronization. The memory section keeps track of the present state. The control section directs the counter to the next state using command and status lines.
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Synchronous Counters

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Analysis of Synchronous Counters 1

Set equations for the (JK, D, T) inputs in terms of the Q outputs for the counter. Set up a table similar to the one in Table 9.5 and place the first initial state in the present state column (usually all 000). Use the initial state to fill in the Inputs that will cause this state on a clock pulse.

Analysis of Synchronous Counters 2

Determine the result on each FF in the counter and place this in the next state. Enter the next state on the present state line 2 and repeat the process until you cycle back to the first initial state.

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Analysis of Synchronous Counters 3

State Table For Figure 9.11

Present State Synchronous Inputs Next State

Q2Q1Q0
000 001 010 011 100

J2K2
01 01 01 11 01 (R) (R) (R) (T) (R)

J1K1
00 11 00 11 00 (NC) (T) (NC) (T) (NC)

J0K0
11 11 11 11 01 (T) (T) (T) (T) (R)

Q2Q1Q0
001 010 011 100 000

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Basic Design Approach 1

Draw a state diagram showing state changes and inputs and outputs. Create a present/next state table. List present states in binary order and next states based on the state diagram.

Basic Design Approach 2

Use FF Excitation Tables to determine FF (JK, D, T) inputs for each present next state transition. Specify inputs equations for each input and simplify using Boolean reductions. A VHDL design for counters is done more easily and is not as time consuming.
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Basic Design Approach 3

The previous two slides describe the process for designing counters by deriving and simplifying Boolean equations for a counter (classical approach). VHDL design for counters is done more easily and is not as time consuming.
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VHDL Process Statements

Sequential counters use a process statement to control transitions to the next count state. A VHDL Attribute is used with an identifier (signal) to define clock edges. Clock uses an attribute called EVENT such as (clkEVENT AND clk=1) to define a rising edge clock event.
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VHDL UP Counter
-- simple_int_counter.vhd -- 8-bit synchronous counter with asynchronous clear. -- Uses INTEGER type for counter output. LIBRARY ieee; USE ieee.std_logic_1164.ALL;

VHDL UP Counter Entity

ENTITY simple_int_counter IS PORT( clock : IN STD_LOGIC; reset : IN STD_LOGIC; q : OUT INTEGER RANGE 0 TO 255); END simple_int_counter;

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VHDL UP Counter Architecture 1

ARCHITECTURE counter OF simple_int_counter IS BEGIN PROCESS (clock, reset) VARIABLE count : INTEGER RANGE 0 to 255; BEGIN IF (reset = 0) THEN COUNT : = 0;

VHDL UP Counter Architecture 2

ELSE IF (clock EVENT AND clock = 1) THEN count := count +1; END IF; END IF; q <= count; END PROCESS; END counter;

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VHDL UP Counter Summary

PROCESS statement monitors the two inputs clock and reset, which controls the state of the counter. A variable count holds the present value of the counter. The IF statement evaluates the clock and reset inputs to determine whether the counter should increment or clear.
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LPM Counters 1
The Altera LPM (Library of Parameterized Modules) counter can be used to create counter designs in VHDL. This is a structured design approach that uses the LPM-counter as a component in a hierarchy. The LPM counter is instantiated in the structured design.
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LPM Counters 2
The basic parameters of the LPM counter, such as width, are defined with a generic map. The port map is used to connect LPM counter I/O to the actual VHDL design entity.
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VHDL LPM Library Declaration

The Altera LPM Library must be added to the usual STD_LOGIC after the ieee library has been declared
LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY lpm; USE lpm.lpm_components.ALL;
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VHDL LPM Entity

Entity for an 8-bit mod 256 counter. LPM requires the use of STD_LOGIC data types.
ENTITY simple_lpm_counter IS PORT( clk, clear : IN STD_LOGIC; q : OUT STD_LOGIC_VECTOR (7 downto 0));

VHDL LPM Architecture

ARCHITECTURE count OF simple_lpm_counter IS SIGNAL clrn : STD_LOGIC;--internal signal for active low clr. BEGIN -- Instantiate 8-bit counter. count : lpm_counter GENERIC MAP (LPM_WIDTH => 8) PORT MAP ( clock => clk, aclr => clrn,--Intrnal clear mapped to async. clr. q => q_out (7 downto 0 )); clrn <= not clear;--Input port inverted mapped to internal clr. END count;
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END simple_lpm_counter;
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Entering Simple LPM Counters in Quartus II

Use either the MegaWizard Plug in Manager or manually enter the LPM component. Refer to Chapter 9, Entering Simple LPM Counters with the Quartus II Block Editor.

Entering Simple LPM Counters in Quartus II

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Entering Simple LPM Counters in Quartus II

LPM Counter Features 1

Parallel Load: A function (syn/asyn) that allows loading of a binary value into the counter FF. Clear: asynchronous or synchronous reset. Preset: A set (syn. Or asyn.).

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LPM Counter Features 2

Counter Enable: A control function that allows a counter to count the sequences or disable the count. Bi-Directional: A control line to switch the counter from a count up to a count down.

LPM Counter Features 3

There are other features for LPM counters that are given in the Altera Reference Data Sheets. The same holds true for other LPM functions, such as arithmetic and memory.

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4-Bit Parallel Load Counter 1

A preset counter (parallel load) has an additional input (load) that can be synchronous or asynchronous and four parallel data inputs. The load pulse selects whether the synchronous counter inputs are generated by count logic or parallel load data.
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4-Bit Parallel Load Counter 2

An asynchronous load counter uses an asynchronous clear or preset to force the counter to a known state (usually 0000 or 1111).

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4-Bit Parallel Load Counter 3

4-Bit Parallel Load Counter 4

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4-Bit Parallel Load Counter 5

4-Bit Parallel Load Counter 6

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Count Enable Logic

As shown in Figure 9.46, adding another AND gate to each FF input inhibits the count function. This has the effect of inhibiting the clock to the counter (a clock pulse has no effect). Outputs remain at the last state until the counter is enabled again.
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Bi-Directional Counter
Adds a direction Input (DIR) to the counter and the control logic for up or down counting. Basic counter element is shown in Figure 9.50. The control logic selects the up or down count logic depending on the state of DIR.
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Terminal Count Decoding 1

Uses a combinational decoder to detect when the last state of a counter is reached (terminal count). Determines a maximum count out for an UP counter and a minimum for a DOWN counter.

Terminal Count Decoding 2

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Terminal Count Decoding 3

Terminal Count Decoding 2

The terminal count decoder generates a RCO (ripple carry out) when the terminal count is reached (a high pulse for 1 clock period).

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Terminal Count Decoding 3

VHDL Counter (8-Bit) 1

-- Pre-settable_8bit_counter_sync_load -- 8-bit pre-settable counter with synchronous -- clear and load and terminal count decoding -- using STD_LOGIC types LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL;

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VHDL Counter (8-Bit) 2

ENTITY presettable_8bit_counter_sync_load IS PORT( clk, count_ena : IN STD_LOGIC; clear, load, direction : IN STD_LOGIC; p : IN STD_LOGIC_VECTOR (7 downto 0); max_min :OUT STD_LOGIC; q : BUFFER STD_LOGIC_VECTOR (7 downto 0)); END presettable_8bit_counter_sync_load;
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VHDL Counter (8-Bit) 3

ARCHITECTURE a OF presettable_8bit_counter_sync_load IS SIGNAL terminal_count : STD_LOGIC_VECTOR (8 downto 0); BEGIN PROCESS (clk) -- Since all functions are synchronous only clk is on -- the sensitivity list. BEGIN IF (CLKEVENT AND clk = 1) THEN IF (clear = 0) THEN -- Synchronous clear. q <= (others => 0); ELSIF (load = 1) THEN Synchronous load. q <= p;
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VHDL Counter (8-Bit) 3

ELSIF (count_ena = 1 and direction = 0) THEN q <= q 1; ELSIF (count_ena = 1 and direction = 1) THEN q <= q+1; END IF; END IF; END PROCESS;

Terminal Count Code

-- Terminal count decoder (combinational) Terminal_count <= direction & q; WITH terminal_count SELECT max_min <= 1 WHEN 000000000, 1 WHEN 111111111, 0 WHEN others;

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8-Bit Counter Summary 1

After the PROCESS statement. q = 0 (if clear = 0). q = p (if clear = 0 and load = 1).

8-Bit Counter Summary 2

q increments if there is a positive clk edge, count_ena = 1, and direction = 1). q decrements if there is a positive clk edge, count_ena = 1, and direction = 0). q remains the same if above conditions are not met.
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8-Bit Counter Summary 3

LPM Counter Functions

LPM counters can be used as a simple 8-bit counter. The component lpm_counter has a number of other functions that can be implemented using specific ports and parameters. These functions are indicated on Table 9.12.
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LPM Counter VHDL Code 1

-- pre_lpm8 -- 8-bit presettable counter with asynchronous clear and load, -- count enable, and a directional control port. LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY lpm; USE lpm.lpm_components.ALL;

LPM Counter VHDL Code 2

ENTITY pre_lpm8 IS PORT( clk, count_ena : IN STD_LOGIC; clear, load, direction : IN STD_LOGIC; p : IN STD_LOGIC_VECTOR (7 downto 0); q_out : IN STD_LOGIC_VECTOR (7 downto 0)); END PRE_LPM8;

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LPM Counter VHDL Code 3

ARCHITECTURE a OF pre_lpm8 IS BEGIN counter 1: lpm_counter GENERIC MAP (LPM_WIDTH => 8) PORT MAP (clock => clk, updown => direction, cnt_en => count_ena, data => p, aload => load, aclr => clear, q => q_out; END a;
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Homework
Chapter 9
4, 6 (Modulus) 12 (Synchronous Counter) 20 (T Flip-flop Synchronous Counter) 22 (VHDL for 6-Bit Counter) 32 (Down Counter) 39 (Generic Width Counter)

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ACLU #17
A counter is to count the Gray code pattern 000 001 011 010 110 111 101 100 000 etc. The inputs are Clk, ClkEn, and the counter outputs are Gray, and Cout. Write the entity statement Complete the Architecture
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