iput output blocking assignment(=) procedural sequence in order of statements nonblocking assignment(<=) RTL parallel code execution

vhdl and verilog codes ...Full View Photo for Femari Serrano From: Femari Serrano <femari89@yahoo.com> [Chat now] ... To: Clarisse Manalang <cla_wanique@yahoo.com>; Laura Marco <bestfrnd13@yahoo .com> Inline Attachment Follows: CODES.txt library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --THIS IS A VHDL CODE FOR A HALF ADDER --USING PORT TYPE STD_LOGIC entity half_adder is Port ( A,B : in std_logic; C_OUT, SUM : out std_logic); end half_adder; architecture Behavioral of half_adder is begin SUM<=A xor B; C_OUT<=A and B; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --THIS IS VHDL CODE FOR A FULL ADDER --USING PORT TYPE STD_LOGIC entity full_adder is Port ( A, B, C_IN : in std_logic; C_OUT, SUM : out std_logic); end full_adder; architecture Behavioral of full_adder is begin SUM<=(A xor B) xor C_IN;

C_OUT<=((A xor B) and C_IN) or (A and B); end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --THIS IS A VHDL CODE OF A FULL-ADDER --COMPOSED OF TWO HALF-ADDERS --PORT TYPE: STD_LOGIC entity full_adder2 is Port ( A, B, C_IN : in std_logic; C_OUT, SUM : out std_logic); end full_adder2; architecture Behavioral of full_adder2 is signal X,Y,Z : std_logic; component half_adder is port (A, B : in std_logic; C_OUT, SUM : out std_logic); end component; begin ha1: half_adder port map (A, B, Y, X); ha2: half_adder port map (X, C_IN, Z, SUM); C_OUT<= Z or Y; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --THIS VHDL CODE IS A HALF ADDER MODULE --USING PORT TYPE BIT --AND WHEN-ELSE STATEMENT. entity half_adder1 is Port ( A, B : in bit; C_OUT, SUM : out bit); end half_adder1; architecture Behavioral of half_adder1 is begin SUM<='0' when A='0' and B='0' else '0' when A='1' and B='1' else '1'; C_OUT<='1' when A='1' and B='1' else '0'; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --THIS IS A VHDL CODE OF A HALF ADDER MODULE

--USING PORT TYPE OF BIT_VECTOR --AND WHEN-ELSE STATEMENT. entity half_adder2 is Port ( A : in bit_vector(1 downto 0); B : out bit_vector(1 downto 0)); end half_adder2; --B(0)==SUM --B(1)==CARRY OUT architecture Behavioral of half_adder2 is begin B<="00" when A="00" else "10" when A="11" else "01"; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --THIS IS A VHDL CODE OF A HALF ADDER MODULE --USING PORT TYPE OF BIT --AND SEQUENTIAL STATEMENT: IF-THEN-ELSE entity half_adder3 is Port ( A, B : in bit; C_OUT, SUM : out bit); end half_adder3; architecture Behavioral of half_adder3 is begin process(A,B) begin if A='0' and B='0' then SUM<='0'; elsif A='1' and B='1' then SUM<='0'; else sum<='1'; end if; if A='1' and B='1' then C_OUT<='1'; else C_OUT<='0'; end if; end process; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --THIS IS A VHDL CODE OF A HALF ADDER MODULE --USING PORT TYPE OF BIT_VECTOR --AND SEQUENTIAL STATEMENT: IF-THEN-ELSE entity half_adder4 is Port ( A : in bit_vector(1 downto 0); B : out bit_vector(1 downto 0)); end half_adder4;

--B(0)==SUM --B(1)==CARRY OUT architecture Behavioral of half_adder4 is begin process(A) begin if A="00" then B<="00"; elsif A="11" then B<="10"; else B<="01"; end if; end process; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --THIS IS A VHDL CODE FOR A FULL ADDER --USING PORT TYPE BIT --AND CONCURRENT STATEMENT: WHEN-ELSE entity full_adder1 is Port ( A, B, C_IN : in bit; C_OUT, SUM : out bit); end full_adder1; architecture Behavioral of full_adder1 is begin SUM<='0' when A='0' and B='0' and C_IN='0' else '0' when A='0' and B='1' and C_IN='1' else '0' when A='1' and B='0' and C_IN='1' else '0' when A='1' and B='1' and C_IN='0' else '1'; C_OUT<='0' when A='0' and B='0' else '0' when A='0' and C_IN='0' else '0' when B='0' and C_IN='0' else '1'; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --THIS IS A VHDL CODE OF A FULL ADDER --USING PORT TYPE BIT_VECTOR --AND CONCURRENT STATEMENT: WHEN-ELSE entity full_adder2 is Port ( A : in bit_vector(2 downto 0); B : out bit_vector(1 downto 0)); end full_adder2; --B(0)==SUM --B(1)==CARRY OUT architecture Behavioral of full_adder2 is begin

B<="00" when A="000" else "11" when A="111" else "01" when (A="001" or A="010" or A="100") else "10"; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --THIS IS A VHDL CODE FOR A FULL ADDER --USING PORT TYPE BIT --AND SEQUENTIAL STATEMENT: IF-THEN-ELSE entity full_adder3 is Port ( A,B,C_IN : in bit; C_OUT, SUM : out bit); end full_adder3; architecture Behavioral of full_adder3 is begin process(A,B,C_IN) begin if A='0' and B='0' and C_IN='0' then SUM<='0' ; elsif A='0' and B='1' and C_IN='1' then SUM<='0'; elsif A='1' and B='0' and C_IN='1' then SUM<='0'; elsif A='1' and B='1' and C_IN='0' then SUM<='0'; else SUM<='1'; end if; if A='0' and B='0' then C_OUT<='0'; elsif A='0' and C_IN='0' then C_OUT<='0'; elsif B='0' and C_IN='0' then C_OUT<='0'; else C_OUT<='1'; end if; end process; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --THIS IS A VHDL CODE FOR A FULL ADDER --USING PORT TYPE BIT_VECTOR --AND SEQUENTIAL STATEMENT: IF-THEN-ELSE entity full_adder4 is Port ( A : in bit_vector(2 downto 0); B : out bit_vector(1 downto 0)); end full_adder4; --B(0)==SUM --B(1)==CARRY OUT architecture Behavioral of full_adder4 is begin process(A) begin if A="000" then B<="00";

elsif A="111" then B<="11"; elsif A="001" or A="010" or A="100" then B<="01"; else B<="10"; end if; end process; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity half_adder is Port ( A, B : in std_logic; C_OUT, SUM : out std_logic); end half_adder; architecture Behavioral of half_adder is begin SUM<=A xor B; C_OUT<=A and B; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity full_adder is Port ( A, B, C_IN : in std_logic; C_OUT, SUM : out std_logic); end full_adder; architecture Behavioral of full_adder is signal X, Y, Z: std_logic; component half_adder is port(A, B: in std_logic; C_OUT, SUM: out std_logic); end component; begin ha1: half_adder port map(A, B, Y, X); ha2: half_adder port map(X, C_IN, Z, SUM); C_OUT<=Y and Z; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity fa_4bit is Port ( A, B : in std_logic_vector(3 downto 0); C_IN : in std_logic; C_OUT : out std_logic; SUM : out std_logic_vector(3 downto 0)); end fa_4bit; architecture Behavioral of fa_4bit is signal X: std_logic_vector(2 downto 0); component full_adder is port(A, B, C_IN : in std_logic; C_OUT, SUM : out std_logic); end component; begin fa1: full_adder port map (A(0),B(0),C_IN,X(0),SUM(0)); fa2: full_adder port map (A(1),B(1),X(0),X(1),SUM(1)); fa3: full_adder port map (A(2),B(2),X(1),X(2),SUM(2)); fa4: full_adder port map (A(3),B(3),X(2),C_OUT,SUM(3)); end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --THIS IS A VHDL CODE FOR A BCD ADDER/SUBTRACTOR entity bcd_adder is Port ( A, B : in std_logic_vector(3 downto 0); C_IN : in std_logic; C_OUT : out std_logic; SUM : out std_logic_vector(3 downto 0)); end bcd_adder; architecture Behavioral of bcd_adder is signal INPUT,SUM1,CF : std_logic_vector(3 downto 0); signal X,Y : std_logic; component fa_4bit is port ( A, B : in std_logic_vector(3 downto 0); C_IN : in std_logic; C_OUT : out std_logic; SUM : out std_logic_vector(3 downto 0)); end component; begin INPUT(0)<=A(0) xor C_IN; INPUT(1)<=A(1) xor C_IN; INPUT(2)<=A(2) xor C_IN; INPUT(3)<=A(3) xor C_IN; fa1: fa_4bit port map(INPUT,B,C_IN,X,SUM1); Y<='0'; CF(0)<='0'; CF(1)<=((SUM1(3) and SUM1(2)) or (SUM1(3) and SUM1(1))) xor X xor C_IN; CF(2)<=((SUM1(3) and SUM1(2)) or (SUM1(3) and SUM1(1))) xor X xor C_IN; CF(3)<='0'; fa2: fa_4bit port map(SUM1,CF,Y,C_OUT,SUM);

end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity half_adder2 is Port ( A : in std_logic_vector(1 downto 0); B : out std_logic_vector(1 downto 0)); end half_adder2; architecture Behavioral of half_adder2 is begin --B[0]==sum --B[1]==carry-out B(0)<=A(1) xor A(0); B(1)<=A(1) and A(0); end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity full_adder2 is Port ( A : in std_logic_vector(2 downto 0); B : out std_logic_vector(1 downto 0)); end full_adder2; architecture Behavioral of full_adder2 is begin --B(0)==sum --B(1)==carry-out B(0)<=(A(2) xor A(1)) xor A(0); B(1)<=((A(2) xor A(1)) and A(0)) or (A(2) and A(1)); end Behavioral; Inline Attachment Follows: CODES2.txt //VERILOG CODE FOR HALF-ADDER module half_adder(A, B, C_OUT, SUM); input A, B; output C_OUT, SUM; assign SUM=A^B; //sum=a xor b assign C_OUT=A&B; //carry=a and b endmodule //VERILOG CODE FOR HALF-ADDER MODULE module half_adder2(A, B); input [1:0] A; //A is a multibit variable output [1:0] B; //B is a multibit variable //B(1)==CARRY OUT //B(0)==SUM assign B[0]=A[1]^A[0]; //sum assign B[1]=A[1]&A[0]; //carry-out endmodule

//Verilog code for full-adder module full_adder(A,B,C_IN, C_OUT,SUM); input A,B,C_IN; output C_OUT,SUM; assign SUM=A^B^C_IN; assign C_OUT=((A^B)&C_IN) (A&B); endmodule //Verilog code for full-adder module full_adder2(A, B); input [2:0] A; //A is a multibit variable output [1:0] B; //B is a multibit variable assign B[0]=A[2]^A[1]^A[0]; //sum assign B[1]=((A[2]^A[1])&A[0]) (A[2]&A[1]); endmodule //VERILOG code for a full-adder using wire module full_adder_wire(A, B, C_IN, C_OUT,SUM); input A, B, C_IN; //input declaration output C_OUT,SUM; //output declaration wire X,Y,Z; //wire declaration //using two half-adders half_adder G1(A,B,Y,X); half_adder G2(X,C_IN,Z,SUM); assign C_OUT=Z Y; endmodule //Verilog code for a four-bit full-adder module FA_4BIT(A,B, C_IN, C_OUT, SUM); input [3:0] A,B; //A and B are multibit variables input C_IN; //carry-in output C_OUT; //carry-out output [3:0] SUM; //SUM is a multibit variable wire [2:0] X; //X is a multibit variable //using four full-adders full_adder_wire G1(A[0],B[0],C_IN,X[0],SUM[0]); full_adder_wire G2(A[1],B[2],X[0],X[1],SUM[1]); full_adder_wire G3(A[2],B[2],X[1],X[2],SUM[2]); full_adder_wire G4(A[3],B[3],X[2],C_OUT,SUM[3]); endmodule //Verilog code for a BCD adder/subtractor module bcd_adder(A,B, C_IN, C_OUT, SUM); input [3:0] A,B; //A and B are multibit variables input C_IN; output C_OUT; output [3:0] SUM; //SUM is a multibit variable wire X,temp; wire Y[3:0],Z[3:0],CF[3:0]; //Y,Z and CF are multibit variables /*to pass A to the adder in either true or complement form*/ //input=A,B;carry-out=Y,sum=x //input=X,C_IN;carry-out=Z,sum=SUM //carry-out=Z or Y //carry-out

assign Y[0]=A[0]^C_IN; assign Y[1]=A[1]^C_IN; assign Y[2]=A[2]^C_IN; assign Y[3]=A[3]^C_IN; fa_4bit G1 (Y,B,C_IN,X,Z); //CF is the correcting factor assign CF[0]=0; assign temp=((Z[3]&Z[2]) (Z[3]&Z[1]))^X^C_IN; assign CF[1]=temp; assign CF[2]=temp; assign CF[3]=0; supply0 C2; //the carry-in of the second adder is connected to the ground fa_4bit G2 (Z,CF,C2,C_OUT,SUM); endmodule module half_adder3(A,B, C_OUT,SUM); input A,B; output C_OUT,SUM; reg X,Y; always@(A or B) begin if (A==1'b1 & B==1'b1) X=1'b1; else X=1'b0; if (A==1'b0 & B==1'b0) Y=1'b0; else if (A==1'b1 & B==1'b1) Y=1'b0; else Y=1'b1; end assign C_OUT=X; assign SUM=Y; endmodule module half_adder4(A, B); input [1:0] A; output [1:0] B; //B(1)==CARRY OUT //B(0)==SUM reg X,Y; always@(A) begin if (A==2'b11) X=1'b1; else X=1'b0; if (A==2'b00) Y=1'b0; else if (A==2'b11) Y=1'b0; else Y=1'b1; end assign B[1]=X; assign B[0]=Y; endmodule

module full_adder3(A,B,C_IN, C_OUT,SUM); input A,B,C_IN; output C_OUT,SUM; reg X,Y; always@(A or B) begin if (A==1'b0 & B==1'b0 & C_IN==1'b0) Y=1'b0; else if (A==1'b0 & B==1'b1 & C_IN==1'b1) Y=1'b0; else if (A==1'b1 & B==1'b0 & C_IN==1'b1) Y=1'b0; else if (A==1'b1 & B==1'b1 & C_IN==1'b0) Y=1'b0; else Y=1'b1; if (A==1'b0 & B==1'b0) X=1'b0; else if (A==1'b0 & C_IN==1'b0) X=1'b0; else if (B==1'b0 & C_IN==1'b0) X=1'b0; else X=1'b1; end assign C_OUT=X; assign SUM=Y; endmodule module full_adder4(A, B); input [2:0] A; output [1:0] B; reg [1:0] X; always@(A) begin if (A==3'b000) X=2'b00; else if (A==3'b111) X=2'b11; else if (A==3'b001 A==3'b010 X=2'b01; else X=2'b10; end assign B=A; endmodule

A==3'b100)