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Compal confidential

Schematics Document
Mobile Banias uFCBGA/uFCPGA with Intel
ODEM_MCH+ICH4-M core logic
2003-05-12
3

REV:1.0

Compal Electronics, Inc.


Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Cover Sheet
Rev
1.0

LA-1701

Date:

Monday, May 12, 2003

Sheet
E

of

49

Compal confidential
File Name : LA-1701

Fan Control

page 4

Mobile Banias
uFCBGA-479/uFCPGA-478 CPU
page 4,5

PSB

H_A#(3..31)

page 14

400MHz

ICS 950810

page 4

CRT & TV-OUT Conn.

Clock Generator

Thermal Sensor
ADM1032AR

page 12

H_D#(0..63)

Memory BUS(DDR)
DDR-SO-DIMM X2

Intel ODEM MCH-M


VGA Board Connector

uFCBGA-593

AGP BUS

page 6,7,8

page 13

BANK 0, 1, 2, 3 page 9,10,11


2.5V DDR- 200/266

USB2.0

USB conn
page 27

Audio CKT

Hub-Link

AMP & Audio Jack

AD1981B
page 23

page 24

MDC & BT Conn

Mini PCI
socket

LAN
RTL 8139CL+

page 25

Intel ICH4-M

IDSEL:AD20
(PIRQA#,GNT#2,REQ#2)

IDSEL:AD17
(PIRQB#,GNT#1,REQ#1)

IEEE 1394
VT6307S
page 20

page 28

PCI BUS

3.3V 33 MHz

CardBus Controller

page 25

page 21
IDSEL:AD16
(PIRQA#,GNT#0,REQ#0)

Primary IDE
ATA-100

HDD
Connector
page

18

CDROM
Connector
page

18

IDSEL:AD18,AD22
(PIRQC/D#,GNT#3/4,REQ#3/4)

Slot 0

RJ45/11 CONN
page 19
3

Mini-PCI solt

BGA-421
page 15,16,17

ENE CB1410

page 19

AC-LINK

page 31

Secondary IDE

page 21

ATA-100

RTC CKT.

SPR CONN.
page 33

*RJ45 CONN
*PS2 x2 CONN
*CRT CONN
*LINE IN JACK
*LINE OUT JACK
*1394 CONN
*SPDIF CONN
*DVI CONN
*DC JACK
*TVOUT CONN
*PRINTER PORT
*COM PORT
*USB CONN x2

LPC BUS

page 16

Power OK CKT.

EC NS87591L

page 32

SD Connector

page 29

SMsC LPC47N227
Super I/O

page 31

page 22

Power On/Off CKT.


page 28

Int.KBD

Touch Pad

page 28

EC I/O Buffer
DC/DC Interface CKT.

BIOS

page 30

PARALLEL

page 28

page 26

FIR

page 26

page 30

page 34
4

Power Circuit DC/DC

page
35,36,37,38,39,40,41,42

Compal Electronics, Inc.


Title

Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

LA-1701

Date:

Monday, May 12, 2003

Sheet
E

of

49

Voltage Rails

Symbol note:
:means digital ground.

Power Plane

Description

S0-S1

S3

S5

VIN

Adapter power supply (19V)

N/A

N/A

N/A

B+

AC or battery power rail for power circuit

N/A

N/A

N/A

+CPU_CORE

Core voltage for CPU

ON

OFF

OFF

+VCCP

1.05V rail for Processor I/O

ON

OFF

OFF

+1.25VS

1.25V switched power rail for DDR Vtt

ON

OFF

OFF

+1.2VS

1.2V switched power rail for MCH core power

ON

OFF

OFF

+1.5VALW

1.5V always on power rail

ON

ON

ON*

+1.5VS

1.5V switched power rail for AGP interface

ON

OFF

OFF

+1.8VS

1.8V switched power rail for CPU PLL & Hub-Link ON

OFF

OFF

+2.5V

2.5V power rail for DDR

ON

ON

OFF

+2.5VS

2.5V switched power rail

ON

OFF

OFF

+3VALW

3.3V always on power rail

ON

ON

ON*

+3V

3V power rail

ON

ON

OFF
OFF

+3VS

3.3V switched power rail

ON

OFF

+5VALW

5V always on power rail

ON

ON

ON*

+5V

5V power rail

ON

ON

OFF

+5VS

5V switched power rail

ON

OFF

OFF

+12VALW

12V always on power rail

ON

ON

ON*

+12V

12V power rail

ON

ON

OFF

+12VS

12Vswitched power rail on power rail

ON

OFF

OFF

RTCVCC

RTC power

ON

ON

ON

:means analog ground.


@ :means reserved.

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Internal PCI Devices


DEVICE

PCI Device ID

HUB

D30

USB

D29

AC97 MODEM

D31

AC97

D31

ATA 100

D31

ETHERNET

D8 (AD24)

LPC I/F

D31

SMBUS

D31

External PCI Devices


DEVICE

PCI Device ID

IDSEL #

REQ/GNT #

PIRQ

1394

D0

AD16

LAN

D1

AD17

CARD BUS

D4

AD20

Wireless LAN

D2

AD18

Mini-PCI

D6

AD22

AGP BUS

N/A

AGP_DEVSEL#

N/A

I2C / SMBUS ADDRESSING


DEVICE

HEX

ADDRESS

DDR SO-DIMM 0

A0

1010000X

DDR SO-DIMM 1

A2

1010001X

CLOCK GENERATOR (EXT.)

D2

1101001X

Compal Electronics, Inc.


Title

Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

LA-1701

Date:

Monday, May 12, 2003

Sheet

of

49

H_D#[0..63]
<6> H_A#[3..31]

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
ADSTB0#
ADSTB1#

R137

<6> H_LOCK#
<6> H_CPURST#
<6> H_RS#0
<6> H_RS#1
<6> H_RS#2
<6> H_TRDY#

+3VALW
<16> ITP_DBRESET#

R1111

<6> H_DBSY#
<7,15> H_DPSLP#
<7> H_DPWR#

1
2
R121
330_0402_5%

+VCCP
<15> H_CPUPWRGD

<15> H_CPUSLP#

R105
R107

H_CPURST#
H_RS#0
H_RS#1
H_RS#2

H1
K1
L2
M3

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3

1 R110
2
150_0402_5%
ITP_DBRESET#

H_IERR#

@1K_0402_5%
@1K_0402_5%

ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
HITM#
IERR#
LOCK#
RESET#
RS0#
RS1#
RS2#
TRDY#

C8
B8
A9
C9

BPM0#
BPM1#
BPM2#
BPM3#

2 0_0402_5% A7
M2
B7
C19
ITP_BPM#4
A10
ITP_BPM#5
B10
H_PROCHOT# B17
H_CPUPWRGD
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#

CONTROL GROUP

DBR#
DBSY#
DPSLP#
DPWR#
PRDY#
PREQ#
PROCHOT#

MISC

8
9
10
14
16
18
20
22

GND0
GND1
GND2
GND3
GND4
GND5

PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#

BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5

THERMAL
THERMDA DIODE
THERMDC
THERMTRIP#

C129
2200P_0402_25V7K

<6>
<6>
<6>
<6>

2
1

VDD

SCLK

D+

SDATA

D-

EC_SMC_2 <29>

EC_SMD_2 <29>

ALERT#

GND

THERM#

+5VS

+12VS

<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>

C140

2
2

0.1U_0402_10V6K

C6
B4

H_A20M#

H_A20M# <15>
H_FERR# <15>
H_IGNNE# <15>
H_INIT# <15>
H_INTR <15>
H_NMI <15>

H_IGNNE#
H_INIT#
H_INTR
H_NMI

O
-

D Q23

U14
FAN1_ON 3

SI3456DV-T1_TSOP6

+5VS

H_STPCLK#
H_SMI#

C427
@10000P

@2200P_0603_16V7K

H_STPCLK# <15>
H_SMI# <15>

1
R340

R341
10K_0402_5%
JP15

FAN1_VOUT

2
7.32K_0603_1%

D23
RB751V_SOD323

1
2
3

<29> FANSPEED1
C422
10U_1206_10V4Z

C439
@10000P

53398-0310

C139
1U_0603_10V6K
1
2
R108
56_0402_5%

Q20
@2SC2411K_SOT23

R101
330_0402_5%
1
2
2
B
1
2

LM321MF_SOT23-5

C448
1
2

R342
13K_0603_1%

2
1

2
1
2
330_0402_5%
MMBT3904_SOT23

Address:1001_100X

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

2
1
3

R109

H_THERMDC

ADM1032AR_SOP8

C23
K24
W25
AE24
C22
L24
W24
AE25

STPCLK#
SMI#

R102
56 _0402_1%
Q21

H_THERMDA

DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#

+VCCP

U13
@10K_0402_5%

Fan Control circuit

+VCCP

Q22

C131

R114

LEGACY CPU

1K_0402_5%

MMBT3904_SOT23

ITP_TRST#
2
680_0402_5%
ITP_TCK
2
27.4_0402_1%

1
R129
1
R154

1 0.1U_0402_10V6K

2
1

R120

2
2

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

C2
D3
A3
B5
D1
D4

W=15mil

D25
J26
T24
AD20

A20M#
FERR#
IGNNE#
INIT#
LINT0/INTR
LINT1/NMI

ITP_TDO_R

+3VS

DINV0#
DINV1#
DINV2#
DINV3#

+VCCP

<29> PROCHOT#

R153
@22.6_0402_1%

ITP_TMS
2
39.2_0603_1%
ITP_TDI
2
150_0402_1%

1
R135
1
R134

MAINPWON <35,37,42>

ITP_TDO

+VCCP

4
6

NC1
NC2

1RESETITP#

R119
22.6_0402_1%

Thermal Sensor ADM1032AR

mFCBGA479

R124
330_0402_5%

ITP_DBRESET#
@0_0402_5%

ITP_BPM#0
ITP_BPM#1
ITP_BPM#2
ITP_BPM#3
ITP_BPM#4
ITP_BPM#5

@ITP700-FLEXCON

+3VALW

BCLK#
BCLK

23
21
19
17
15
13

<29> EN_FAN1

E4
A6
A13
C12
A12
C5
F23
C11
B13

H_THERMDA
B18
H_THERMDC
A18
H_THERMTRIP# C17

FBO

R138

H_CPURST#
2

RESET#

R149
@54.9_0402_1%

2
R112
56_0402_5%

N2
L1
J3
N4
L4
H2
K3
K4
A4
J2
B11

HOST CLK

CLK_CPU_ITP#
CLK_CPU_ITP

11

R104
54.9_0402_1%

@0.1U_0402_16V7K

BCLK0
BCLK1

ITP_TCK

25
24

DBR#
DBA#

B15
B14

<12> CLK_CPU_BCLK
<12> CLK_CPU_BCLK#

<6> H_ADS#
<6> H_BNR#
<6> H_BPRI#
<6> H_BR0#
<6> H_DEFER#
<6> H_DRDY#
<6> H_HIT#
<6> H_HITM#

ITP_CLK0
ITP_CLK1

12

27
28
26

VTT0
VTT1
VTAP

+VCCP

A16
A15

RESETITP#

TDI
TMS
TCK
TDO
TRST#

CLK_CPUITP
CLK_CPUITP#

1
2
5
7
3

C145
2

U3
AE5

+VCCP

+VCCP
JP29
ITP_TDI
ITP_TMS
ITP_TCK
ITP_TDO_R
ITP_TRST#

1
2
5
6

DATA GROUP

ITP700FLEX FOR BANIAS

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

A19
A25
A22
B21
A24
B26
A21
B20
C20
B24
D24
E24
C26
B23
E23
C25
H23
G25
L23
M26
H24
F25
G24
J23
M23
J25
L26
N24
M25
H26
N25
K25
Y26
AA24
T25
U23
V23
R24
R26
R23
AA23
U26
V24
U25
V26
Y23
AA26
Y25
AB25
AC23
AB24
AC20
AC22
AC25
AD23
AE22
AF23
AD24
AF20
AE21
AD21
AF25
AF22
AF26

ADDR GROUP

D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#

Banias

R2
P3
T2
P1
T1

<6> H_ADSTB#0
<6> H_ADSTB#1
0_0402_5%
1
2
R136 1
20_0402_5%

A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A27#
A28#
A29#
A30#
A31#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

+VCCP

P4
U4
V3
R3
V2
W1
T4
W2
Y4
Y1
U1
AA3
Y3
AA2
AF4
AC4
AC7
AC3
AD3
AE4
AD2
AB4
AC6
AD5
AE2
AD6
AF3
AE1
AF1

H_REQ#[0..4]

<6> H_REQ#[0:4]

<6>

U9A
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

<12> CLK_CPU_ITP
<12> CLK_CPU_ITP#

H_D#[0..63]

H_A#[3..31]

1
R118
56_0402_5%

THRMTRIP# <16>

H_THERMTRIP#
Title

H_PROCHOT#

Compal Electronics, Inc.


INTEL CPU BANIAS (1 of 2)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003

Rev
1.0

LA-1701

Sheet
E

of

49

+CPU_CORE

+CPU_VCCA
1

1 R79

+1.8VS

F26
B1
N1
AC26

0_1206_5%

P23
W4

+VCCP

D10
D12
D14
D16
E11
E13
E15
F10
F12
F14
F16
K6
L5
L21
M6
M22
N5
N21
P6
P22
R5
R21
T6
T22
U21

D6
D8
D18
D20
D22
E5
E7
E9
E17
E19
E21
F6
F8
F18

+CPU_CORE

Resistor placed within


0.5" of CPU pin.Trace
should be at least 25
miles away from any
other toggling signal.
+VCCP

<41>
<41>
<41>
<41>
<41>
<41>

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5

VID0
VID1
VID2
VID3
VID4
VID5

AD26
E26
G1
AC1

C37
220P_0402_50V8K

COMP0
COMP1
COMP2
COMP3

R56

R296

R103

R57

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
PSI#

VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP

E2
F2
F3
G3
G4
H4

1
C34
1U_0603_10V6K

VCCQ0
VCCQ1

E1

GTL_REF0

R32
2K_0402_1%

VCCA0
VCCA1
VCCA2
VCCA3

<41> PSI#

R36
1K_0402_1%

VCCSENSE
VSSSENSE

GTLREF0
GTLREF1
GTLREF2
GTLREF3

P25
P26
AB2
AB1

COMP0
COMP1
COMP2
COMP3

B2
AF7
C14
C3

RSVD
RSVD
RSVD
RSVD

C16

TEST3

@1K_0402_5%

Banias

POWER, GROUNG, RESERVED SIGNALS AND NC

@54.9_0402_1%
VCCSENSE AE7
2
VSSSENSE AF6
2
@54.9_0402_1%

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A2
A5
A8
A11
A14
A17
A20
A23
A26
B3
B6
B9
B12
B16
B19
B22
B25
C1
C4
C7
C10
C13
C15
C18
C21
C24
D2
D5
D7
D9
D11
D13
D15
D17
D19
D21
D23
D26
E3
E6
E8
E10
E12
E14
E16
E18
E20
E22
E25
F1
F4
F5
F7
F9
F11
F13
F15
F17
F19
F21
F24
G2
G6
G22
G23
G26
H3
H5
H21
H25
J1
J4
J6
J22
J24
K2
K5
K21
K23
K26
L3
L6
L22
L25
M1

1
+

C281
220U_D2_2VM

1
+

C110
220U_D2_2VM

10U_1206_6.3V7K

C62
220U_D2_2VM

C67

10U_1206_6.3V7K
1
1

1
C68

C69

2
2
10U_1206_6.3V7K

C70

2
2
10U_1206_6.3V7K

10U_1206_6.3V7K
1
1

C71

C82

2
2
10U_1206_6.3V7K

C88
10U_1206_6.3V7K

+CPU_CORE
10U_1206_6.3V7K
1
1

1
C105

C104

2
2
10U_1206_6.3V7K

10U_1206_6.3V7K

10U_1206_6.3V7K
1
1

C103

C102

2
2
10U_1206_6.3V7K

C101

1
C81

2
2
10U_1206_6.3V7K

C87
10U_1206_6.3V7K

+CPU_CORE
10U_1206_6.3V7K

1
C328

10U_1206_6.3V7K

1
C327

2
2
10U_1206_6.3V7K

1
C326

10U_1206_6.3V7K

1
C325

2
2
10U_1206_6.3V7K

1
C324

1
C351

2
2
10U_1206_6.3V7K

C364
10U_1206_6.3V7K

+CPU_CORE
10U_1206_6.3V7K

1
C385

10U_1206_6.3V7K

1
C386

2
2
10U_1206_6.3V7K

1
C387

10U_1206_6.3V7K

1
C388

2
2
10U_1206_6.3V7K

1
C389

1
C365

2
2
10U_1206_6.3V7K

C352
10U_1206_6.3V7K

+CPU_CORE
10U_1206_6.3V7K

1
C121

10U_1206_6.3V7K

10U_1206_6.3V7K

1
C117

2
2
10U_1206_6.3V7K

1
C50

1
C350

2
2
10U_1206_6.3V7K

1
C349

F20
F22
G5
G21
H6
H22
J5
J21
K22
U5
V6
V22
W5
W21
Y6
Y22
AA5
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AA21
AB6
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC9
AC11
AC13
AC15
AC17
AC19
AD8
AD10
AD12
AD14
AD16
AD18
AE9
AE11
AE13
AE15
AE17
AE19
AF8
AF10
AF12
AF14
AF16
AF18

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

M4
M5
M21
M24
N3
N6
N22
N23
N26
P2
P5
P21
P24
R1
R4
R6
R22
R25
T3
T5
T21
T23

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

1
C122

2
2
10U_1206_6.3V7K

Vcc-core
Decoupling
SPCAP,Polymer

C,uF

ESR, mohm

ESL,nH

4X220uF

12m ohm/4

3.5nH/4

MLCC 0805 X5R

35X10uF

5m ohm/35

0.6nH/35

10U_1206_6.3V7K

1
C126

1
C356

10U_1206_6.3V7K

10U_1206_6.3V7K

1
C362

1
C127

0.01U_0402_16V7K

1
C98

C72

0.01U_0402_16V7K

Banias

POWER, GROUND

C49
10U_1206_6.3V7K

+CPU_VCCA

C64
0.01U_0402_16V7K

54.9_0402_1%

27.4_0402_1%

+CPU_CORE

R293

54.9_0402_1%

1
C280
220U_D2_2VM

mFCBGA479
27.4_0402_1%

U9C

+CPU_CORE

U9B
R290
1
1
R288

T26
U2
U6
U22
U24
V1
V4
V5
V21
V25
W3
W6
W22
W23
W26
Y2
Y5
Y21
Y24
AA1
AA4
AA6
AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22
AA25
AB3
AB5
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB26
AC2
AC5
AC8
AC10
AC12
AC14
AC16
AC18
AC21
AC24
AD1
AD4
AD7
AD9
AD11
AD13
AD15
AD17
AD19
AD22
AD25
AE3
AE6
AE8
AE10
AE12
AE14
AE16
AE18
AE20
AE23
AE26
AF2
AF5
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF24

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

mFCBGA479
C92
10U_1206_6.3V7K

0.01U_0402_16V7K

+VCCP
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

1
C564

1
C348

100U_6.3V_M

Resistor placed within


0.5" of CPU pin.Trace
should be at least 25
miles away from any
other toggling signal.

1
C359

1
C363

1
C431

1
C430

1
C429

1
C428

1
C372

1
C346

C341
0.1U_0402_16V7K
4

2
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

Compal Electronics, Inc.


Title

INTEL CPU BANIAS (2 of 2)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003

Rev
1.0

LA-1701

Sheet
E

of

49

H_D#[0..63]

H_A#[3..31]

HUB_PD[0..10]

HUB_PD[0:10]

U12B

<4> H_DSTBN#0
<4> H_DSTBN#1
<4> H_DSTBN#2
<4> H_DSTBN#3
<4> H_DSTBP#0
<4> H_DSTBP#1
<4> H_DSTBP#2
<4> H_DSTBP#3
<4> H_DINV#0
<4> H_DINV#1
<4> H_DINV#2
<4> H_DINV#3

U7
V4
W2
Y4
Y3
Y5
W3
V7
V3
Y7
V5
W7
W5
W6

AE17

AD4
AF6
AD11
AC15
AD3
AG6
AE11
AC16
AD5
AG5
AH9
AD15

ADS#
HTRDY#
DRDY#
DEFER#
HITM#
HIT#
HLOCK#
BR0#
BNR#
BPRI#
DBSY#
RS#0
RS#1
RS#2

HDSTBN#0
HDSTBN#1
HDSTBN#2
HDSTBN#3
HDSTBP#0
HDSTBP#1
HDSTBP#2
HDSTBP#3
DBI#0
DBI#1
DBI#2
DBI#3

H_SWNG0

R306
150_0402_1%

HLRCOMP
HI_REF

GFRAME#
GDEVSEL#
GIRDY#
GTRDY#
GSTOP#
GPAR
GREQ#
GGNT#

AGP_ADSTB0
AGP_ADSTB0#
AGP_ADSTB1
AGP_ADSTB1#

R24
R23
AC27
AC28

AD_STB0
AD_STB#0
AD_STB1
AD_STB#1

AH28
AH27
AG28
AG27
AE28
AE27
AE24
AE25

SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7

<13> AGP_SBSTB
<13> AGP_SBSTB#

AF27
AF26

SB_STB
SB_STB#

<13> AGP_RBF#
<13> AGP_WBF#

AE22
AE23
AF22

RBF#
WBF#
PIPE#

AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7

+VCCP

R66
49.9_0402_1%

MGH_GTLREF
1
1

C333

C335

R77
C392
100_0402_1%
1U_0603_10V6K

AGP_ST0 AG25
AGP_ST1 AF24
AGP_ST2 AG26

<13> AGP_ST0
<13> AGP_ST1
<13> AGP_ST2
<12> CLK_MCH_66M

CLK_MCH_66M

P22

AGP

GND

ST0
ST1
ST2

AB9
AD10
AF9
AJ9
A7
F8
J7
L8
N8
R8
U8
W8
AA8
AD8
AF7
AJ7
D5
F6
H6
K6
M6
P6
T6
V6
Y6
AB6
AD6
AF5
AJ5
A3
J4
L4
N4
R4
U4
W4
AA4
AC4
AE4
AJ3
E1
J1
L1
N1
R1
U1
W1
AA1
AC1
AE1
AG1

GRCOMP
AGPREF

AD25
AA21

R287
@1K_0402_5%
AGP_ST2

+1.5VS

R291
@1K_0402_5%
AGP_ST1

R292
@1K_0402_5%

MCH STRAP

ST1

ST2

DDR

TEST MODE

400 Mhz PSB

AGP_RCOMP 1
+AGPREF

R300
36.5_0603_1%
2

+1.5VS

+AGPREF

C340
0.1U_0402_16V4Z

R308
1K_0402_1%
+AGPREF

R305
1K_0402_1%

Note:
Placement R308,R305
close to MCH

C379
0.01U_0402_16V7K

RG82P4300M_FCBGA593
R314
@22_0402_5%

+1.8VS

+1.5VS

2
R302
27.4_0402_1%

2
36.5_0402_1%
HUB_VREF

H_RCOMP1
H_RCOMP0
R55
27.4_0402_1%

1
R315

P26

VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141

66IN

RG82P4300M_FCBGA593
A

HUB_PSTRB <15>
HUB_PSTRB# <15>

P27 HUB_RCOMP

GCBE#0
GCBE#1
GCBE#2
GCBE#3

Y24
W28
W27
W24
W23
W25
AG24
AH25

<13>
<13>
<13>
<13>

AD13 H_SWNG1
AA7 H_SWNG0
AC13
AC2

AGP_C/BE#0
V25
AGP_C/BE#1
V23
AGP_C/BE#2
Y25
AGP_C/BE#3 AA23

AGP_FRAME#
AGP_DEVSEL#
AGP_IRDY#
AGP_TRDY#
AGP_STOP#
AGP_PAR
<13> AGP_REQ#
<13> AGP_GNT#

<13>
<13>
<13>
<13>
<13>
<13>

220P_0402_50V7K

HRCOMP1
HRCOMP0

R304
301_0402_1%

N25
N24

HI_STB
HI_STB#

1
1

C330
0.1U_0402_10V6K

220P_0402_50V7K

HSWNG1
HSWNG0

2
1
2
1

+VCCP

M7
P8
AA9
AB12
AB16

R299
150_0402_1%

HVREF0
HVREF1
HVREF2
HVREF3
HVREF4

CPURST#

H_SWNG1

HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9
HUB_PD10

BCLK#
BCLK

R303
301_0402_1%

P25
P24
N27
P23
M26
M25
L28
L27
M27
N28
M24

<4> H_CPURST#

H_RS#0
H_RS#1
H_RS#2

K8
J8

C334
0.1U_0402_10V6K

HUB

HI_0
HI_1
HI_2
HI_3
HI_4
HI_5
HI_6
HI_7
HI_8
HI_9
HI_10

<4> H_ADS#
<4> H_TRDY#
<4> H_DRDY#
<4> H_DEFER#
<4> H_HITM#
<4> H_HIT#
<4> H_LOCK#
<4> H_BR0#
<4> H_BNR#
<4> H_BPRI#
<4> H_DBSY#

HADSTB#0
HADSTB#1

Odem
GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31

<12> CLK_MCH_BCLK#
<12> CLK_MCH_BCLK

R5
N7

+VCCP

<4> H_ADSTB#0
<4> H_ADSTB#1

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

H_REQ#0 U2
H_REQ#1 T7
H_REQ#2 R7
H_REQ#3 U5
H_REQ#4 T4

AA2
AB5
AA5
AB3
AB4
AC5
AA3
AA6
AE3
AB7
AE5
AF3
AC6
AC3
AF4
AE2
AG4
AG2
AE7
AE8
AH2
AC7
AG3
AD7
AH7
AE6
AC8
AG8
AG7
AH3
AF8
AH5
AC11
AC12
AE9
AC10
AE10
AD9
AG9
AC9
AE12
AF10
AG11
AG10
AH11
AG12
AE13
AF12
AG13
AH13
AC14
AF14
AG14
AE14
AG15
AG16
AG17
AH15
AC17
AF16
AE15
AH17
AD17
AE16

R27
R28
T25
R25
T26
T27
U27
U28
V26
V27
T23
U23
T24
U24
U25
V24
Y27
Y26
AA28
AB25
AB27
AA27
AB26
Y23
AB23
AA24
AA25
AB24
AC25
AC24
AC22
AD24

HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63

12

HOST

<13> AGP_SBA[0..7]

AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31

<15>

Odem
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

AGP_SBA[0..7]

U6
T5
R2
U3
R3
P7
T3
P4
P3
P5
R6
N2
N5
N3
J3
M3
M4
M5
L5
K3
J2
N6
L6
L2
K5
L3
L7
K4
J5

AGP_C/BE#[0..3]

<13> AGP_CBE#[0..3]

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

AGP_AD[0..31]

<13> AGP_AD[0..31]

H_REQ#[0..4]
U12A

H_D#[0..63] <4>

<4> H_A#[3..31]
<4> H_REQ#[0..4]

H_RS#[0..2]

<4> H_RS#[0..2]

C381
@10P_0402_50V8K

Compal Electronics, Inc.


Title

ODEM(1/3)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

LA-1701

Date:

Monday, May 12, 2003

Sheet
1

of

49

<9,10> DDR_MMA[0..12]
<9> DDR_SDQ[0..63]
<9> DDR_SDQS[0..8]

DDR_MMA[0..12]
DDR_SDQ[0..63]
DDR_SDQS[0..8]
U12C
DDR_CB[0..7]

<9> DDR_CB[0..7]

E12
F17
E16
G17
G18
E18
F19
G20
G19
F21
F13
E20
G21
G22

SMA0
SMA1
SMA2
SMA3
SMA4
SMA5
SMA6
SMA7
SMA8
SMA9
SMA10
SMA11
SMA12
RSVD2

DDR_SDQS0
DDR_SDQS1
DDR_SDQS2
DDR_SDQS3
DDR_SDQS4
DDR_SDQS5
DDR_SDQS6
DDR_SDQS7
DDR_SDQS8

F26
C26
C23
B19
D12
C8
C5
E3
E15

SDQS0
SDQS1
SDQS2
SDQS3
SDQS4
SDQS5
SDQS6
SDQS7
SDQS8

G11
F11
G8

SWE#
SRAS#
SCAS#

DDR_CLK0
DDR_CLK0#
DDR_CLK1
DDR_CLK1#
DDR_CLK2
DDR_CLK2#
DDR_CLK3
DDR_CLK3#
DDR_CLK4
DDR_CLK4#
DDR_CLK5
DDR_CLK5#

J25
K25
G5
F5
G24
E24
G25
J24
G6
G7
K23
J23

SCK0
SCK#0
SCK1
SCK#1
SCK2
SCK#2
SCK3
SCK#3
SCK4
SCK#4
SCK5
SCK#5

<9,10>
<9,10>
<10>
<10>

DDR_CKE0
DDR_CKE1
DDR_CKE2
DDR_CKE3

G23
E22
H23
F23

SCKE0
SCKE1
SCKE2
SCKE3

<9,10>
<9,10>
<10>
<10>

DDR_SCS#0
DDR_SCS#1
DDR_SCS#2
DDR_SCS#3

E9
F7
F9
E7

SCS#0
SCS#1
SCS#2
SCS#3

<9,10> DDR_SWE#
<9,10> DDR_SRAS#
<9,10> DDR_SCAS#

<9>
<9>
<9>
<9>
<9>
<9>
<10>
<10>
<10>
<10>
<10>
<10>

+1.25VS_SMVREF

<9,10> DDR_SBS0
<9,10> DDR_SBS1

R328

+SDREF

Odem

DDR_MMA0
DDR_MMA1
DDR_MMA2
DDR_MMA3
DDR_MMA4
DDR_MMA5
DDR_MMA6
DDR_MMA7
DDR_MMA8
DDR_MMA9
DDR_MMA10
DDR_MMA11
DDR_MMA12

MEMORY

G12
G13

SBS0
SBS1

J9
J21

SMVREF0
SMVREF1

J28

SMRCOMP

G15

RCVENIN#

G14

RCVENOUT#

0_0805_5%

1
C405
0.1U_0402_16V4Z

+1.25VS
C404
0.1U_0402_16V4Z

R326

1
2
30.1_0603_1%

DDR_RCOMP

C403
0.1U_0402_16V4Z

M_RCV#

2
<4,15> H_DPSLP#
<4> H_DPWR#

NOTE:1.M_RCV#
2.G15 to
3.G14 to
4.Via to

max 2Via
Via max=40mils
Via max=40mils
Via must = 100mils +-5mils

V8
Y8
AD26
AD27

DPSLP#
DPWR#
NC0
NC1

SDQ0
SDQ1
SDQ2
SDQ3
SDQ4
SDQ5
SDQ6
SDQ7
SDQ8
SDQ9
SDQ10
SDQ11
SDQ12
SDQ13
SDQ14
SDQ15
SDQ16
SDQ17
SDQ18
SDQ19
SDQ20
SDQ21
SDQ22
SDQ23
SDQ24
SDQ25
SDQ26
SDQ27
SDQ28
SDQ29
SDQ30
SDQ31
SDQ32
SDQ33
SDQ34
SDQ35
SDQ36
SDQ37
SDQ38
SDQ39
SDQ40
SDQ41
SDQ42
SDQ43
SDQ44
SDQ45
SDQ46
SDQ47
SDQ48
SDQ49
SDQ50
SDQ51
SDQ52
SDQ53
SDQ54
SDQ55
SDQ56
SDQ57
SDQ58
SDQ59
SDQ60
SDQ61
SDQ62
SDQ63
SDQ64
SDQ65
SDQ66
SDQ67
SDQ68
SDQ69
SDQ70
SDQ71

G28
F27
C28
E28
H25
G27
F25
B28
E27
C27
B25
C25
B27
D27
D26
E25
D24
E23
C22
E21
C24
B23
D22
B21
C21
D20
C19
D18
C20
E19
C18
E17
E13
C12
B11
C10
B13
C13
C11
D10
E10
C9
D8
E8
E11
B9
B7
C7
C6
D6
D4
B3
E6
B5
C4
E4
C3
D3
F4
F3
B2
C2
E2
G4
C16
D16
B15
C14
B17
C17
C15
D14

DDR_SDQ0
DDR_SDQ1
DDR_SDQ2
DDR_SDQ3
DDR_SDQ4
DDR_SDQ5
DDR_SDQ6
DDR_SDQ7
DDR_SDQ8
DDR_SDQ9
DDR_SDQ10
DDR_SDQ11
DDR_SDQ12
DDR_SDQ13
DDR_SDQ14
DDR_SDQ15
DDR_SDQ16
DDR_SDQ17
DDR_SDQ18
DDR_SDQ19
DDR_SDQ20
DDR_SDQ21
DDR_SDQ22
DDR_SDQ23
DDR_SDQ24
DDR_SDQ25
DDR_SDQ26
DDR_SDQ27
DDR_SDQ28
DDR_SDQ29
DDR_SDQ30
DDR_SDQ31
DDR_SDQ32
DDR_SDQ33
DDR_SDQ34
DDR_SDQ35
DDR_SDQ36
DDR_SDQ37
DDR_SDQ38
DDR_SDQ39
DDR_SDQ40
DDR_SDQ41
DDR_SDQ42
DDR_SDQ43
DDR_SDQ44
DDR_SDQ45
DDR_SDQ46
DDR_SDQ47
DDR_SDQ48
DDR_SDQ49
DDR_SDQ50
DDR_SDQ51
DDR_SDQ52
DDR_SDQ53
DDR_SDQ54
DDR_SDQ55
DDR_SDQ56
DDR_SDQ57
DDR_SDQ58
DDR_SDQ59
DDR_SDQ60
DDR_SDQ61
DDR_SDQ62
DDR_SDQ63
DDR_CB0
DDR_CB1
DDR_CB2
DDR_CB3
DDR_CB4
DDR_CB5
DDR_CB6
DDR_CB7

RSTIN#
RSVD1
TESTIN#

J27
H27
H26

MCH_TEST#

PCIRST# <13,15,19,20,21,22,25,31>

1
R91

2
+1.5VS
@4.7K_0402_5%

RG82P4300M_FCBGA593

Title

Compal Electronics, Inc.


ICH4-M(2/3)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003

Rev
1.0

LA-1701

Sheet
1

of

49

U12D

+1.5VS

R29
W29
AC29
AG29
U26
AA26
AE26
AJ25
AD23
AF23
R22
U22
W22
AA22
AB21
AD21

P17
N16
P15
R16
T15
U16
N14
P13
R14
U14

+1.2VS

L29
L25
N26
N23
M22

+1.8VS

+VCCP

+2.5V

+1.8VS

AG23
AJ23
AE21
AG21
AJ21
AB20
AC19
AD20
AE19
AF20
AG19
AJ19
AB18
AD18
AF18
AB14
AB10
M8
T8
AB8
C29
G29
A25
D25
K26
D23
H24
K24
L23
A21
F22
H22
K22
D19
H20
A17
F18
H18
D15
F16
H16
A13
F14
H14
D11
H12
A9
F10
H10
D7
H8
K7
A5
E5
H5
J6
C1
G1
T17
T13

C368
0.1U_0402_16V4Z

+2.5V

Odem
VCCAGP0
VCCAGP1
VCCAGP2
VCCAGP3
VCCAGP4
VCCAGP5
VCCAGP6
VCCAGP7
VCCAGP8
VCCAGP9
VCCAGP10
VCCAGP11
VCCAGP12
VCCAGP13
VCCAGP14
VCCAGP15

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCCHL0
VCCHL1
VCCHL2
VCCHL3
VCCHL4

POWER
VCCP0
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
VCCSM37

GND

VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9

VCCGA

ETS#

E29
J29
N29
U29
AA29
AE29
A27
K27
AJ27
E26
G26
J26
L26
R26
W26
AC26
AF25
A23
F24
L24
M23
AC23
AH23
D21
H21
J22
L22
N22
T22
V22
Y22
AB22
AC21
AD22
AF21
AG22
AH21
A19
F20
H19
AB19
AC20
AD19
AE20
AF19
AG20
AH19
D17
H17
N17
R17
U17
AB17
AC18
AE18
AF17
AG18
AJ17
A15
F15
H15
N15
P16
R15
T16
U15
AB15
AD16
AF15
AJ15
D13
E14
H13
N13
P14
R13
T14
U13
AB13
AD14
AF13
AJ13
A11
F12
H11
AB11
AD12
AF11
AJ11
D9
H9

C563
100U_6.3V_M

C401
150U_D2_6.3VM

22U_1206_10V4Z

0.1U_0402_16V4Z

C138

1
C400

C398

1
C399

1
C408

C434
0.1U_0402_16V4Z

2
22U_1206_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

+2.5V
0.1U_0402_16V4Z
1
1

1
C411

C433

2
2
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1
1

C417

C410

2
2
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1
1

C409

C416

0.1U_0402_16V4Z
1
1

C413

2
2
0.1U_0402_16V4Z

C419

2
2
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1
1

C406

C402

2
2
0.1U_0402_16V4Z

C432
C418
0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z

+1.8VS
0.1U_0402_16V4Z
1
1

1
C395
10U_1206_10V4Z

C383

C396

C384
0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z

+1.5VS

10U_1206_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1
C344
150U_D2_6.3VM

C361

1
C373

1
C371

2
10U_1206_10V4Z

C345

1
C336

2
2
0.1U_0402_16V4Z

C321

1
C316

2
2
0.1U_0402_16V4Z

C306
0.1U_0402_16V4Z

+1.2VS

1
C301
150U_D2_6.3VM

150U_D2_6.3VM
1
1
C366

0.22U_0603_10V7K

0.01U_0402_16V7K

C347

1
1
1
C394
C380
C374
C393
0.047U_0603_16V7K
2
2
2
2
0.015U_0402_16V7K 0.022U_0603_16V7K

C353

2
2
2.2U_0805_10V6K

+VCCP
0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1
C357
150U_D2_6.3VM

1
C305

C311

1
C315

C338

2
2
0.1U_0402_16V4Z

1
C320

2
2
0.1U_0402_16V4Z

C310

1
C337

2
2
0.1U_0402_16V4Z

C367
0.1U_0402_16V4Z

G16
G10
G9
H7
G2
G3
H3
H4

R327
1
2
10K_0603_0.5%

+2.5V

VCCHA

C382
10U_1206_10V4Z RG82P4300M_FCBGA593

Title

Compal Electronics, Inc.


ODEM(3/3)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date:
Monday, May 12, 2003

Rev
1.0

LA-1701

Sheet
1

of

49

RP18

RP45

DDR_SDQ5
DDR_SDQ4

1
2

DDR_DQ5
DDR_DQ4

DDR_SDQ3
DDR_SDQ1

10_4P2R_0404_5%
RP38
DDR_DQ3
1
4
DDR_DQ1
2
3

DDR_SDQS0
DDR_SDQ6

10_4P2R_0404_5%
RP37
DDR_DQS0
1
4
DDR_DQ6
2
3

DDR_SDQ13
DDR_SDQ8

1
2

10_4P2R_0404_5%
RP39
DDR_DQ13
4
DDR_DQ8
3

4
3

+2.5V

RP36

DDR_SDQ31
DDR_SDQ30

1
2

DDR_SDQ27
DDR_SDQS3

10_4P2R_0404_5%
RP24
DDR_DQ27
1
4
DDR_DQS3
2
3

DDR_SDQ37
DDR_SDQ32

10_4P2R_0404_5%
RP30
DDR_DQ37
1
4
DDR_DQ32
2
3

DDR_SDQ35
DDR_SDQ39

1
2

10_4P2R_0404_5%
RP31
DDR_DQ35
4
DDR_DQ39
3

4
3

DDR_DQ31
DDR_DQ30

DDR_SDQ56
DDR_SDQ62

1
2

DDR_SDQ58
DDR_SDQ63

10_4P2R_0404_5%
RP59
DDR_DQ58
1
4
DDR_DQ63
2
3

DDR_SDQ60
DDR_SDQ61

10_4P2R_0404_5%
RP60
DDR_DQ60
1
4
DDR_DQ61
2
3

DDR_SDQ59
DDR_SDQ57

1
2

4
3

+2.5V

DDR_DQ56
DDR_DQ62

+1.25VS_SDREF_R
JP30

10_4P2R_0404_5%
RP41
DDR_DQ10
4
DDR_DQ11
3

DDR_SDQ10
DDR_SDQ11

1
2

DDR_SDQ15
DDR_SDQS1

10_4P2R_0404_5%
RP20
DDR_DQ15
1
4
DDR_DQS1
2
3

DDR_SDQ7
DDR_SDQ2

10_4P2R_0404_5%
RP19
DDR_DQ7
1
4
DDR_DQ2
2
3

DDR_SDQ14
DDR_SDQ9

10_4P2R_0404_5%
RP40
DDR_DQ14
1
4
DDR_DQ9
2
3

10_4P2R_0404_5%
RP52
DDR_DQS4
4
DDR_DQ36
3

DDR_SDQS4
DDR_SDQ36

1
2

DDR_SDQ34
DDR_SDQ38

10_4P2R_0404_5%
RP53
DDR_DQ34
1
4
DDR_DQ38
2
3

DDR_SDQ40
DDR_SDQ44

10_4P2R_0404_5%
RP54
DDR_DQ40
1
4
DDR_DQ44
2
3

DDR_SDQ43
DDR_SDQ42

10_4P2R_0404_5%
RP55
DDR_DQ43
1
4
DDR_DQ42
2
3

DDR_SDQS2
DDR_SDQ17

10_4P2R_0404_5%
RP42
DDR_DQS2
1
4
DDR_DQ17
2
3

DDR_SDQ45
DDR_SDQ41

10_4P2R_0404_5%
RP32
DDR_DQ45
1
4
DDR_DQ41
2
3

DDR_SDQ18
DDR_SDQ22

1
2

10_4P2R_0404_5%
RP43
DDR_DQ18
4
DDR_DQ22
3

DDR_SDQ46
DDR_SDQ47

1
2

DDR_SDQ20
DDR_SDQ16

10_4P2R_0404_5%
RP21
DDR_DQ20
1
4
DDR_DQ16
2
3

DDR_SDQ49
DDR_SDQ52

10_4P2R_0404_5%
RP33
DDR_DQ49
1
4
DDR_DQ52
2
3

DDR_SDQ19
DDR_SDQ23

10_4P2R_0404_5%
RP22
DDR_DQ19
1
4
DDR_DQ23
2
3

DDR_SDQ51
DDR_SDQ54

10_4P2R_0404_5%
RP34
DDR_DQ51
1
4
DDR_DQ54
2
3

DDR_SDQ25
DDR_SDQ24

1
2

10_4P2R_0404_5%
RP44
DDR_DQ25
4
DDR_DQ24
3

DDR_SDQS6
DDR_SDQ50

1
2

10_4P2R_0404_5%
RP58
DDR_DQS6
4
DDR_DQ50
3

DDR_SDQ28
DDR_SDQ29

1
2

10_4P2R_0404_5%
RP23
DDR_DQ28
4
DDR_DQ29
3

DDR_SDQ55
DDR_SDQ48

1
2

10_4P2R_0404_5%
RP57
DDR_DQ55
4
DDR_DQ48
3

DDR_CB6
DDR_CB2

10_4P2R_0404_5%
RP46
DDR_F_CB6
1
4
DDR_F_CB2
2
3

DDR_CB5
DDR_CB4

10_4P2R_0404_5%
RP25
DDR_F_CB5
1
4
DDR_F_CB4
2
3

DDR_CB1
DDR_CB3

1
2

10_4P2R_0404_5%
RP47
DDR_F_CB1
4
DDR_F_CB3
3

DDR_SDQS8
DDR_CB7

1
2

10_4P2R_0404_5%
RP26
DDR_DQS8
4
DDR_F_CB7
3

1
2

DDR_MMA1
DDR_MMA2

10_4P2R_0404_5%
RP50
DDR_F_SMA1
1
4
DDR_F_SMA2
2
3

DDR_MMA4
DDR_MMA5

10_4P2R_0404_5%
RP28
DDR_F_SMA4
1
4
DDR_F_SMA5
2
3

DDR_MMA9
DDR_MMA12

10_4P2R_0404_5%
RP48
DDR_F_SMA9
1
4
DDR_F_SMA12
2
3

DDR_MMA7
DDR_MMA11

1
2

DDR_MMA8
DDR_MMA6

10_4P2R_0404_5%
RP49
DDR_F_SMA8
1
4
DDR_F_SMA6
2
3

DDR_DQS0
DDR_DQ3
DDR_DQ7
DDR_DQ13

10_4P2R_0404_5%
RP35
DDR_DQ59
4
DDR_DQ57
3

DDR_DQ9
DDR_DQS1
DDR_DQ15
DDR_DQ10

10_4P2R_0404_5%
<7> DDR_CLK0
<7> DDR_CLK0#

DDR_DQ20
DDR_DQ21
DDR_DQS2
DDR_DQ18
DDR_DQ19
DDR_DQ25
DDR_DQ28
DDR_DQS3
DDR_DQ27
DDR_DQ31
DDR_F_CB0
DDR_F_CB1

10_4P2R_0404_5%
RP56
DDR_DQ46
4
DDR_DQ47
3

DDR_DQS8
DDR_F_CB2
DDR_F_CB3

<7> DDR_CLK2
<7> DDR_CLK2#
DDR_CKE1

<7,10> DDR_CKE1

DDR_F_SMA12
DDR_F_SMA9
DDR_F_SMA7
DDR_F_SMA5
DDR_F_SMA3
DDR_F_SMA1

<7,10> DDR_SCS#0

DDR_F_SMA10
DDR_F_SBS0
DDR_F_SWE#
DDR_SCS#0

10_4P2R_0404_5%

DDR_DQ37
DDR_DQ33

DDR_SDQ21
2
R203
DDR_SDQ0

<7,10> DDR_SBS1
<7,10> DDR_SCAS#

<7,10> DDR_SBS0

DDR_DQ35
DDR_DQ40

DDR_DQ0
1
10_0402_5%

2
R201

DDR_DQ45
DDR_DQS5

DDR_DQ12
1
10_0402_5%

DDR_SDQ26
2
R221

DDR_DQ26
1
10_0402_5%

DDR_SDQ33
2
R206

DDR_DQ33
1
10_0402_5%

DDR_SDQS5 2
R207

DDR_DQS5
1
10_0402_5%

DDR_SDQ53
2
R208

DDR_DQ53
1
10_0402_5%

DDR_SDQS7 2
R224

DDR_DQS7
1
10_0402_5%

DDR_CB0

DDR_DQS4
DDR_DQ34

DDR_DQ21
1
10_0402_5%

DDR_SDQ12
2
R202

10_4P2R_0404_5%
RP29
DDR_F_SMA0
4
DDR_F_SMA10
3

DDR_MMA0
DDR_MMA10

DDR_DQ5
DDR_DQ0

DDR_DQ43
DDR_DQ46

DDR_DQ49
DDR_DQ55
DDR_DQS6
DDR_DQ50
DDR_DQ51
DDR_DQ58
DDR_DQ59
DDR_DQS7

DDR_F_CB0
1
10_0402_5%

2
R200

DDR_SBS1

2
R205

DDR_F_SBS1
1
10_0402_5%

DDR_SCAS#

2
R222

DDR_F_SCAS#
1
10_0402_5%

DDR_SBS0

2
R223

DDR_F_SBS0
1
10_0402_5%

DDR_SRAS#

2
R204

DDR_F_SRAS#
1
10_0402_5%

DDR_DQ56
DDR_DQ60
<10,12,15> SMB_DATA
<10,12,15> SMB_CLK
+3VS

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0#
VSS
DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
CK2#
VDD
CKE1
DU/A13
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE#
S0#
DU
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDD_SPD
VDD_ID

VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/RESET#
VSS
VSS
VDD
VDD
CKE0
DU/BA2
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
RAS#
CAS#
S1#
DU
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

DDR_DQ4
DDR_DQ6

1
C222
0.1U_0402_16V4Z

DDR_SDQ[0..63]

DDR_SDQ[0..63]

DDR_DQ1
DDR_DQ[0..63]
DDR_DQ2
DDR_DQ8
DDR_DQS[0..8]

DDR_DQ12

DDR_SDQS[0..8]
DDR_CB[0..7]

DDR_DQS[0..8]

<10>

DDR_CB[0..7]

DDR_F_CB[0..7]

DDR_DQ16
DDR_DQ17

<10>

DDR_SDQS[0..8]

DDR_DQ14
DDR_DQ11

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

<7>

DDR_DQ[0..63]

DDR_MMA[0..12]

<7>

<7>

DDR_F_CB[0..7]

<10>

DDR_MMA[0..12]

<7,10>

DDR_DQ22
DDR_DQ23
DDR_DQ24
DDR_DQ29
DDR_DQ26
DDR_DQ30
DDR_F_CB4
DDR_F_CB5
DDR_F_CB6
C

DDR_F_CB7

DDR_CKE0

DDR_CKE0 <7,10>

DDR_F_SMA11
DDR_F_SMA8
DDR_F_SMA6
DDR_F_SMA4
DDR_F_SMA2
DDR_F_SMA0
DDR_F_SBS1
DDR_F_SRAS#
DDR_F_SCAS#
DDR_SCS#1

DDR_SCS#1 <7,10>

DDR_DQ32
DDR_DQ36
DDR_DQ38
DDR_DQ39
DDR_DQ44
DDR_DQ41
B

DDR_DQ42
DDR_DQ47
DDR_CLK1# <7>
DDR_CLK1 <7>
DDR_DQ52
DDR_DQ48
DDR_DQ53
DDR_DQ54
DDR_DQ63
DDR_DQ57
DDR_DQ62
DDR_DQ61

AMP1565618_1_REVERSE4.0
A

10_4P2R_0404_5%
RP27
DDR_F_SMA7
4
DDR_F_SMA11
3

<7,10> DDR_SRAS#

DIMM0

10_4P2R_0404_5%

Title

Compal Electronics, Inc.

RP51
<7,10> DDR_SWE#

DDR_SWE#
DDR_MMA3

1
2

4
3

DDR-SODIMM SLOT1

DDR_F_SWE#
DDR_F_SMA3

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003

10_4P2R_0404_5%
5

Rev
1.0

LA-1701

Sheet
1

of

49

+2.5V

+2.5V
+1.25VS_SDREF_R

+1.25VS

JP22

+1.25VS
RP67

RP110
DDR_DQ6
DDR_DQ0

1
2

RP86

4
3

4
3

56_4P2R_0404_5%

DDR_DQ2
DDR_DQ7

1
2

4
3

4
3

4
3

DDR_DQ43
DDR_DQ42

1
2

56 _8P4R_0804_5%
RP94
DDR_MMA7
1
DDR_MMA6
2
DDR_MMA5
3
DDR_MMA4
4

8
7
6
5

56 _8P4R_0804_5%
RP95
DDR_MMA12
1
DDR_MMA11
2
DDR_MMA9
3
DDR_MMA8
4

8
7
6
5

56 _8P4R_0804_5%
RP93
DDR_MMA3
1
DDR_MMA2
2
DDR_MMA1
3
DDR_MMA0
4

DDR_DQ46
DDR_DQ47

56_4P2R_0404_5%

RP104

1
2

DDR_SBS1 <7,9>
DDR_SBS0 <7,9>

DDR_DQS0
DDR_DQ1
DDR_DQ2
DDR_DQ8
DDR_DQ12
DDR_DQS1
DDR_DQ14
DDR_DQ11
<7> DDR_CLK3
<7> DDR_CLK3#

RP81

4
3

4
3

56_4P2R_0404_5%

1
2

DDR_DQ55
DDR_DQ48

DDR_DQ16
DDR_DQ17
DDR_DQS2
DDR_DQ22
DDR_DQ23
DDR_DQ24

56 _8P4R_0804_5%

56_4P2R_0404_5%

DDR_DQ29
DDR_DQS3

RP66
RP105
DDR_DQ15
DDR_DQ14

1
2

RP82

4
3

4
3

1
2

4
3

DDR_DQ49
DDR_DQ52

1
2

DDR_CKE0
DDR_CKE1

DDR_CKE0 <7,9>
DDR_CKE1 <7,9>

DDR_DQ26
DDR_DQ30

56_4P2R_0404_5%
56_4P2R_0404_5%

56_4P2R_0404_5%

DDR_F_CB0
DDR_F_CB1

RP65
RP107
DDR_DQ13
DDR_DQ8
2

1
2

RP80

4
3

4
3

1
2

4
3

DDR_DQ50
DDR_DQ53

1
2

DDR_CKE2
DDR_CKE3

DDR_DQS8
DDR_F_CB2

56_4P2R_0404_5%
56_4P2R_0404_5%

56_4P2R_0404_5%

DDR_F_CB3
RP68

RP106
DDR_DQ9
DDR_DQ12

1
2

RP79

4
3

4
3

1
2

4
3

DDR_DQ51
DDR_DQ54

1
2

DDR_SWE#
DDR_SCAS#

<7> DDR_CLK5
<7> DDR_CLK5#

56_4P2R_0404_5%
56_4P2R_0404_5%

56_4P2R_0404_5%

<7> DDR_CKE3

RP91
RP103
DDR_DQ16
DDR_DQ20

1
2

RP78

4
3

4
3

1
2

4
3

DDR_DQ58
DDR_DQ63

1
2

DDR_SCS#2
DDR_SCS#3

DDR_MMA7
DDR_MMA5
DDR_MMA3
DDR_MMA1

56_4P2R_0404_5%
RP92

RP100

1
2

RP76

4
3

4
3

1
2

4
3

DDR_DQ56
DDR_DQ62

1
2

DDR_SCS#1
DDR_SCS#0

DDR_SCS#1
DDR_SCS#0

<7,9>
<7,9>

56_4P2R_0404_5%
56_4P2R_0404_5%

56_4P2R_0404_5%
RP61

RP102
DDR_DQ17
DDR_DQ21

1
2

RP77

4
3

4
3

56_4P2R_0404_5%

1
2

4
3

DDR_DQ59
DDR_DQ57

1
2

DDR_F_CB0
DDR_F_CB4

<7,9> DDR_SWE#
<7> DDR_SCS#2

56_4P2R_0404_5%

DDR_DQ32
DDR_DQ36

RP63

DDR_DQS4
DDR_DQ38

RP75

4
3

4
3

56_4P2R_0404_5%

1
2

DDR_DQ60
DDR_DQ61

4
3

56_4P2R_0404_5%

1
2

DDR_F_CB2
DDR_F_CB6

DDR_DQ39
DDR_DQ44

56_4P2R_0404_5%

DDR_DQ41
DDR_DQS5

RP98
DDR_DQ28
DDR_DQ29

1
2

DDR_MMA10
DDR_SBS0
DDR_SWE#
DDR_SCS#2

56_4P2R_0404_5%

RP101
DDR_DQ22
DDR_DQ18

1
2

DDR_CKE3
DDR_MMA12
DDR_MMA9

56_4P2R_0404_5%
56_4P2R_0404_5%

DDR_DQ23
DDR_DQ19

4
3

R228 2
R229 2

1 56_0402_5% DDR_DQS0
1 56_0402_5% DDR_DQS1

R230 2
R231 2

1 56_0402_5% DDR_DQS2
1 56_0402_5% DDR_DQS3

RP62

4
3

1
2

DDR_F_CB1
DDR_F_CB5

DDR_DQ42
DDR_DQ47

56_4P2R_0404_5%
56_4P2R_0404_5%
RP99
DDR_DQ25
DDR_DQ24

1
2

4
3

4
3

1
2

DDR_F_CB3
DDR_F_CB7

DDR_DQS6
DDR_DQ53

56_4P2R_0404_5%

RP97

1
2

DDR_DQ52
DDR_DQ48

RP64

56_4P2R_0404_5%

DDR_DQ27
DDR_DQ26

4
3

R232 2
R233 2

1 56_0402_5% DDR_DQS4
1 56_0402_5% DDR_DQS5

DDR_DQ54
DDR_DQ63

56_4P2R_0404_5%
DDR_DQ57
DDR_DQS7

RP96
DDR_DQ30
DDR_DQ31

1
2

4
3

R234 2
R235 2

1 56_0402_5% DDR_DQS6
1 56_0402_5% DDR_DQS7

R236 1

2 56_0402_5% DDR_DQS8

DDR_DQ62
DDR_DQ61

56_4P2R_0404_5%
<9,12,15> SMB_DATA
<9,12,15> SMB_CLK

RP88

VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0#
VSS

VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

1
R343

DDR_DQ5
DDR_DQ0

2
0_0805_5%

DDR_DQ38
DDR_DQ34

1
2

4
3

DDR_DQ35
DDR_DQ39

1
2

56_4P2R_0404_5%
RP87
4
3

DDR_DQ32
DDR_DQ37

56_4P2R_0404_5%
RP90
1
4
2
3

DDR_DQ33
DDR_DQ36

1
2

+3VS

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
CK2#
VDD
CKE1
DU/A13
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE#
S0#
DU
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDD_SPD
VDD_ID

DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/RESET#
VSS
VSS
VDD
VDD
CKE0
DU/BA2
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
RAS#
CAS#
S1#
DU
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

+SDREF

C234
0.1U_0402_16V4Z

2
DDR_DQ3
DDR_DQ7
DDR_DQ13
1

DDR_DQ9
DDR_SDQ[0..63]

DDR_DQ15
DDR_DQ10

DDR_SDQ[0..63]

DDR_DQ[0..63]

DDR_DQS[0..8]

RP83

4
3
56_4P2R_0404_5%

DDR_DQ10
DDR_DQ11

1
2

56_4P2R_0404_5%

RP109

1
2

DDR_DQ45
DDR_DQ41

RP84

4
3
56_4P2R_0404_5%

DDR_DQ1
DDR_DQ3

1
2

56_4P2R_0404_5%

RP111

1
2

8
7
6
5

RP85

4
3
56_4P2R_0404_5%

DDR_DQ4
DDR_DQ5

1
2
3
4

DDR_DQ4
DDR_DQ6

56_4P2R_0404_5%

RP108
1

1
2

8
7
6
5

DDR_DQ40
DDR_DQ44

DDR_MMA10
DDR_SBS1
DDR_SBS0
DDR_SRAS#

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

DDR_SDQS[0..8]

DDR_DQ20
DDR_DQ21

<7,9>

DDR_DQ[0..63]

<9>

DDR_DQS[0..8]

<9>

DDR_SDQS[0..8]

DDR_CB[0..7]

DDR_CB[0..7]

DDR_DQ18
DDR_F_CB[0..7]
DDR_DQ19
DDR_DQ25

<7,9>

<7,9>

DDR_F_CB[0..7]

<9>

DDR_MMA[0..12]

<7,9>

DDR_DQ28
DDR_MMA[0..12]
DDR_DQ27
DDR_DQ31
DDR_F_CB4
DDR_F_CB5
DDR_F_CB6
2

DDR_F_CB7

DDR_CKE2

DDR_CKE2 <7>

DDR_MMA11
DDR_MMA8
DDR_MMA6
DDR_MMA4
DDR_MMA2
DDR_MMA0
DDR_SBS1
DDR_SRAS#
DDR_SCAS#
DDR_SCS#3

DDR_SRAS# <7,9>
DDR_SCAS# <7,9>
DDR_SCS#3 <7>

DDR_DQ37
DDR_DQ33
DDR_DQ34
DDR_DQ35
DDR_DQ40
3

DDR_DQ45

DDR_DQ43
DDR_DQ46
DDR_CLK4# <7>
DDR_CLK4 <7>
DDR_DQ49
DDR_DQ55

DDR_DQ50
DDR_DQ51
DDR_DQ58
DDR_DQ59
DDR_DQ56
DDR_DQ60
+3VS

AMP11376408_STANDARD5.2
4

DIMM1

56_4P2R_0404_5%
RP89
4
3

Title

Compal Electronics, Inc.


DDR-SODIMM SLOT1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003

56_4P2R_0404_5%

Rev
1.0

LA-1701

Sheet
E

10

of

49

Layout note :
Distribute as close as possible
to DDR-SODIMM.

+2.5V

1
C223
0.1U_0402_16V4Z

1
C224
0.1U_0402_16V4Z

1
C225
0.1U_0402_16V4Z

1
C226
0.1U_0402_16V4Z

1
C227
0.1U_0402_16V4Z

1
C229
0.1U_0402_16V4Z

+2.5V

1
C230
0.1U_0402_16V4Z

1
C231
0.1U_0402_16V4Z

1
C502
0.1U_0402_16V4Z

C503
0.1U_0402_16V4Z

+2.5V

1
C504
0.1U_0402_16V4Z

1
C228
0.1U_0402_16V4Z

1
C497
0.1U_0402_16V4Z

1
C498
0.1U_0402_16V4Z

1
C499
0.1U_0402_16V4Z

1
C500
0.1U_0402_16V4Z

1
C501
0.1U_0402_16V4Z

C221
150U_D2_6.3VM

C505
150U_D2_6.3VM

Layout note :
Place one cap close to every 2 pull up resistors termination to
+1.25V
2

+1.25VS

1
C546
0.1U_0402_16V4Z

1
C545
0.1U_0402_16V4Z

1
C544
0.1U_0402_16V4Z

1
C543
0.1U_0402_16V4Z

1
C542
0.1U_0402_16V4Z

1
C541
0.1U_0402_16V4Z

1
C540
0.1U_0402_16V4Z

1
C539
0.1U_0402_16V4Z

1
C538
0.1U_0402_16V4Z

C536
0.1U_0402_16V4Z

+1.25VS

1
C535
0.1U_0402_16V4Z

1
C534
0.1U_0402_16V4Z

1
C533
0.1U_0402_16V4Z

1
C531
0.1U_0402_16V4Z

1
C240
0.1U_0402_16V4Z

1
C530
0.1U_0402_16V4Z

1
C529
0.1U_0402_16V4Z

1
C528
0.1U_0402_16V4Z

1
C527
0.1U_0402_16V4Z

C526
0.1U_0402_16V4Z

+1.25VS

1
3

1
C525
0.1U_0402_16V4Z

1
C524
0.1U_0402_16V4Z

1
C523
0.1U_0402_16V4Z

1
C522
0.1U_0402_16V4Z

1
C521
0.1U_0402_16V4Z

1
C520
0.1U_0402_16V4Z

1
C519
0.1U_0402_16V4Z

1
C518
0.1U_0402_16V4Z

1
C517
0.1U_0402_16V4Z

C515
0.1U_0402_16V4Z

+1.25VS

1
C514
0.1U_0402_16V4Z

1
C241
0.1U_0402_16V4Z

1
C512
0.1U_0402_16V4Z

1
C511
0.1U_0402_16V4Z

1
C510
0.1U_0402_16V4Z

1
C242
0.1U_0402_16V4Z

1
C508
0.1U_0402_16V4Z

1
C507
0.1U_0402_16V4Z

1
C236
0.1U_0402_16V4Z

C237
0.1U_0402_16V4Z

+1.25VS

1
C537
0.1U_0402_16V4Z

1
C238
0.1U_0402_16V4Z

1
C239
0.1U_0402_16V4Z

1
C243
0.1U_0402_16V4Z

1
C244
0.1U_0402_16V4Z

1
C245
0.1U_0402_16V4Z

1
C246
0.1U_0402_16V4Z

1
C247
0.1U_0402_16V4Z

1
C516
0.1U_0402_16V4Z

C513
0.1U_0402_16V4Z

+1.25VS
4

1
C248
0.1U_0402_16V4Z

1
C249
0.1U_0402_16V4Z

1
C509
0.1U_0402_16V4Z

C532
0.1U_0402_16V4Z

Title

Compal Electronics, Inc.


DDR SODIMM Decoupling

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003

Rev
1.0

LA-1701

Sheet
E

11

of

49

Clock Generator
+3VS

+3V_CLK
L13
CHB2012U121_0805
Width=40 mils
1
2

SEL2

SEL1

SEL0

CPUCLKC[0..2]

CPUCLKT[0..2]

166.67

166.67

0
0

0
1

1
0

100.00
200.00

100.00
200.00

133.33

133.33

1
C192
10U_1206_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C186

1
C166

C144

2
2
0.1U_0402_16V4Z

1
C181

2
2
0.1U_0402_16V4Z

C462

1
C471

2
2
0.1U_0402_16V4Z

C465

C464

2
2
0.1U_0402_16V4Z
1

C151
@10P_0402_50V8K
XTALIN
2

XTAL_IN

1
R366

3
54
55
40

2
1K_0402_5%

25
34
53

<16,29> SLP_S1#
<16> STP_PCI#
<16,41> STP_CPU#

XTAL_OUT

VSSA
CPUCLKT2

C191
10U_1206_10V4Z

27
45

0.1U_0402_16V4Z
CLK_BCLK
1

44

CLK_BCLK#

49

CLK_MCH

48

CLK_MCH#

52

CLK_ITP

SEL0
SEL1
SEL2

PWR_DWN#
PCI_STOP#
CPU_STOP#

CPU_CLKC2
CPUCLKT1

<41> CLKEN#

1
R198

28

2
10K_0402_5%
1

+3VS

D
Q29
@2N7002 1N_SOT23

2
G
3

<16,32,41> VGATE

1
R362

+3VS

2
10K_0402_5%

43

MULT0
CPUCLKT0

29
30

33
35

R364 1

2 475_0402_1%

<16> CLK_ICH_48M

R180 1

2 33_0402_5%

CLK_ICH48M

39

<31> CLK_SD_48M

R186 1

2 33_0402_5%

CLK_SD48M

38

R128 1
1
R127 1
R126

2 33_0402_5%
2
2 33_0402_5%
33_0402_5%

CLK_ICH14M

CPUCLKC0
3V66_0
3V66_1/VCH_CLK

3V66_5
3V66_4
3V66_3
3V66_2

IREF

48MHZ_USB

PCICLK_F2
PCICLK_F1
PCICLK_F0

48MHZ_DOT

REF

4
9
15
20
31
36
41
47

56

SDATA
SCLK

GND_REF
GND_PCI_0
GND_PCI_1
GND_3V66_0
GND_3V66_1
GND_48MHZ
GND_IREF
GND_CPU

<16> CLK_ICH_14M
<22> CLK_14M_SIO
<23> CLK_14M_CODEC

42

C142
@10P_0402_50V8K

2
R169
33_0402_5%

CLK_CPU_BCLK <4>
R170
49.9_0402_1%
1
2
1
2
R173 49.9_0402_1%

R172
33_0402_5%
2

CLK_CPU_BCLK#

2
R160
33_0402_5%

CLK_MCH_BCLK
R161
49.9_0402_1%
1
2
1
2
49.9_0402_1%
R167

R166
33_0402_5%
2

PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0

51

CLK_ITP#

<4>
<6>

CLK_MCH_BCLK#

<6>

CLK_CPU_ITP <4>
R151
49.9_0402_1%
1
2
1
2
R156 49.9_0402_1%

R150
33_0402_5%

S
<9,10,15> SMB_DATA
<9,10,15> SMB_CLK

C171
@10P_0402_50V8K

VTT_PWRGD#
CPUCLKC1

+3VS

1
C187

XTALOUT
2
C154
@10P_0402_50V8K

L14
CHB2012U121_0805
1
2

+3V_VDD

26

Y2
14.318MHZ_16PF_DSX840GA
R140
1K_0402_5%

@1K_0402_5%
R139 2
1
1
2
R132
1K_0402_5%

VDDA

R133
@1K_0402_5%

VDD_REF
VDD_PCI_0
VDD_PCI_1
VDD_3V66_0
VDD_3V66_1
VDD_48MHZ
VDD_CPU_0
VDD_CPU_1

+3VS

+3VS

U18

1
8
14
19
32
37
46
50

R155
33_0402_5%
2

CLK_CPU_ITP# <4>

24
23
22
21

AGP_66M
MCH_66M
ICH_66M

1
1
1

2 R191
2 R188
2 R185

33_0402_5%
33_0402_5%
33_0402_5%

7
6
5

PCI_ICH

2 R158

33_0402_5%

18
17
16
13
12
11
10

PCI_1394
PCI_SD
PCI_LAN
PCI_PCM
PCI_MINI
PCI_SIO
PCI_LPC

1
1
1
1
1
1
1

2
2
2
2
2
2
2

R178
R179
R171
R168
R165
R164
R157

33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%

C177
@10P_0402_50V8K

ICS950810CG_TSSOP56

CLK_AGP_66M <13>
CLK_MCH_66M <6>
CLK_ICH_66M <15>

CLK_PCI_ICH

<15>

CLK_PCI_1394
CLK_PCI_SD
CLK_PCI_LAN
CLK_PCI_PCM
CLK_PCI_MINI
CLK_PCI_SIO
CLK_PCI_LPC

<20>
<31>
<19>
<21>
<25>
<22>
<29>
3

C184
@10P_0402_50V8K

C180
@10P_0402_50V8K

Compal Electronics, Inc.

Title

Clock Generator
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003

Rev
1.0

LA-1701

Sheet

12
H

of

49

AGP CONN

<6> AGP_SBA[0..7]
<6> AGP_CBE#[0..3]

AGP_SBA[0..7]

AGP_AD[0..31]

<6> AGP_AD[0..31]

AGP_CBE#[0..3]

AGP_ST[0..2]

<6> AGP_ST[0..2]

JP12
<12> CLK_AGP_66M

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23

AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
AGP_CBE#2
AGP_CBE#3
AGP_ADSTB1
AGP_ADSTB1#

<6> AGP_ADSTB1
<6> AGP_ADSTB1#

AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBSTB
AGP_SBSTB#

<6> AGP_SBSTB
<6> AGP_SBSTB#

AGP_ST0
AGP_ST1
AGP_ST2

JP13

GND
3
5
7
9
11
13
15
17
19
GND
23
25
27
29
31
33
35
37
39
GND
43
45
47
49
51
53
55
57
59
GND
63
65
67
69
71
73
75
77
79
GND
83
85
87
89
91
93
95
97
GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100

GND
4
6
8
10
12
14
16
18
20
GND
24
26
28
30
32
34
36
38
40
GND
44
46
48
50
52
54
56
58
60
GND
64
66
68
70
72
74
76
78
80
GND
84
86
88
90
92
94
96
98
GND

PCIRST# <7,15,19,20,21,22,25,31>

AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7

GREEN

<14,33> GREEN

BLUE

<14,33> BLUE

HSYNC

<14> HSYNC

VSYNC

<14> VSYNC

AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_CBE#0

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

RED

<14,33> RED

LUMA

<14,33> LUMA

CRMA

<14,33> CRMA

COMPS

<14,33> COMPS

ENAVDD
ENABLT#
<16> C3_STAT#

AGP_CBE#1
AGP_ADSTB0
AGP_ADSTB0#

<16> AGP_BUSY#
<22> PID0
<22> PID1
<22> PID2
<22> PID3

AGP_ADSTB0 <6>
AGP_ADSTB0# <6>

AGP_SBA5
AGP_SBA6
AGP_SBA7
AGP_IRDY#

<14> DDCDATA
<14> DDCCLK

AGP_IRDY# <6>

AGP_TRDY#
AGP_STOP#
AGP_PAR
AGP_FRAME#
AGP_DEVSEL#
AGP_RBF#
AGP_WBF#
AGP_REQ#
AGP_GNT#

AGP_TRDY# <6>
AGP_STOP# <6>
AGP_PAR <6>
AGP_FRAME# <6>
AGP_DEVSEL# <6>
AGP_RBF# <6>
AGP_WBF# <6>
AGP_REQ# <6>
AGP_GNT# <6>

<16,30> SUS_STAT#
<14,29,33> MSEN#
+1.5VS
+1.8VS

PCI_PIRQA# <15,20>
+3VS

+2.5VS

<16> VB1

FOXCONN-100P

+2.5VS

+12VALW

R16
100K_0402_5%

L6
1
2
CPUB++
KC FBM-L11-201209-221LMAT_0805

1
C45
68P_0402_50V8J

LCDVDD

DAC_BRIG
DISPOFF#
INVT_PWM

DAC_BRIG <29>
INVT_PWM <29>

+1.5VS

+1.8VS

VB0 <16>
+2.5VS

VB2 <16>

1
C94
0.1U_0402_16V4Z

C89
0.1U_0402_16V4Z

Q8
SI2302DS 1N_SOT23

0.047U_0402_16V4Z

+1.5VS

1
2

1
C111
0.1U_0402_16V4Z

+3VS

LCDVDD

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100

+12VALW

GND
4
6
8
10
12
14
16
18
20
GND
24
26
28
30
32
34
36
38
40
GND
44
46
48
50
52
54
56
58
60
GND
64
66
68
70
72
74
76
78
80
GND
84
86
88
90
92
94
96
98
GND

+1.8VS

1
C302
0.1U_0402_16V4Z

LCDVDD

CPUB++_L

GND
3
5
7
9
11
13
15
17
19
GND
23
25
27
29
31
33
35
37
39
GND
43
45
47
49
51
53
55
57
59
GND
63
65
67
69
71
73
75
77
79
GND
83
85
87
89
91
93
95
97
GND

FOXCONN-100P

+3VS

LCD POWER CIRCUIT

1
R17

D
Q7
2N7002 1N_SOT23

2
G

2
G

150K_0402_5%

1
C25

1
C28

1
C27
4.7U_0805_10V4Z

C24
4.7U_0805_10V4Z

+3VS

0.1U_0402_16V7K

S Q5
2N7002 1N_SOT23

R52
4.7K_0402_5%

1 2

R15
100K_0402_5%

R14
100_0402_5%

D10
<29> BKOFF#

DISPOFF#

Q6

22K

<29> ENABLT#

DTC124EK_SOT23

ENABLT#

RB751V_SOD323

22K

ENAVDD

Q15
2N7002 1N_SOT23

2
G

Title

Compal Electronics, Inc.


AGP & LCD CONN

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003

Rev
1.0

LA-1701

Sheet
1

13

of

49

CRT Connector
D2
DAN217_SOT23

D3
DAN217_SOT23

+5VS

+3VS

+RCRT_VCC

CRTVDD

D16

D1
DAN217_SOT23

F1
POLYSWITCH_1A

W=40mils

RB411D_SOT23

C255
0.1U_0402_16V7K

2
JP1
CRT-15P

C264
C265
@22P_0402_25V8K
2
2
2 @22P_0402_25V8K
@22P_0402_25V8K

75_0402_1%
+5VS

1
C1
18P_0402_50V8J

DDC_MD2

1
C2
18P_0402_50V8J

C4
18P_0402_50V8J

R246
2.2K_0402_5%

1
R265
4.7K_0402_5%

R245
2.2K_0402_5%

R264
4.7K_0402_5%

75_0402_1%

1
L19

2
FBM-L10-160808-300LM-T

D_HSYNC_L

1
L18

2
FBM-L10-160808-300LM-T

D_VSYNC_L

Q1
3
S

C263

BLUE_L

1
R256

CRTVDD

R257

+3VS
CRTVDD

R258
75_0402_1%

<13,33> BLUE

GREEN_L

<13,33> GREEN

2
L22
FCM2012C-800_0805
1
2
L21
FCM2012C-800_0805
1
2
L20
FCM2012C-800_0805

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

<13,29,33> MSEN#

RED_L

<13,33> RED

DDCDATA <13>

C573

C3

SN74AHCT126PWR_TSSOP14

R254
@10K_0402_5%

7
5

10P_0402_50V8K

C5
10P_0402_50V8K

C6
100P_0402_50V8J
C52
68P_0402_50V8K

D_VSYNC <33>
D_HSYNC <33>

CRTVDD

2
G

R269

+3VS

10K_0402_5%

C257
68P_0402_50V8K
D_DDCCLK

U43B

DDCCLK <13>

BSN20_SOT23

<33>

D_DDCDATA

<33>

<13> VSYNC

P
OE

14
4

+5VS

3
R255
@10K_0402_5%

Q2
3

U43A

2
G

<13> HSYNC

0.1U_0402_16V4Z

P
OE

14
1

BSN20_SOT23

SN74AHCT126PWR_TSSOP14

Unused GATE

1
C15

C256
270P_0402_50V7K

COMPS_CL

P
OE

CF12

1
CF1

CF16

CF14

CF5

CF6

H17
HOLEA

H14
HOLEA

H19
HOLEA

H21
HOLEA

CF4

H1
HOLEA

H2
HOLEA

H18
HOLEA

H16
HOLEA

H3
HOLEA

H22
HOLEA

H11
HOLEA

H9
HOLEA

H13
HOLEA

H12
HOLEA

H7
HOLEA

H10
HOLEA

H4
HOLEA

1
H8
HOLEA

H5
HOLEA

H15
HOLEA

C7
270P_0402_50V7K

H23
HOLEA

H6
HOLEA

H20
HOLEA

H24
HOLEA

H25
HOLEA

S CONN._SUYIN

C8

CF8

1
CF13

1
2
3
4
5
6
7

CRMA_CL

1
C13
150P_0402_50V8J

FM6

JP3

1
C14
150P_0402_50V8J

R6

R8

R7
75_0402_1%

7
2
FCM1608C-121T_0603

11

SN74AHCT126PWR_TSSOP14

CF10

1
CF15

1
L2

FM4

CF3

1
CF11

<13,33> COMPS

U43D

S-Video
LUMA_CL

2
FCM1608C-121T_0603
2 C11
47P_0402_50V8J

1
L3
1

<13,33> CRMA

FM5

CF9

1
CF7

FM3

CF2

1
1

SN74AHCT126PWR_TSSOP14

FM1

C10
47P_0402_50V8J
1
2
L1
FCM1608C-121T_0603
1
2 C12
47P_0402_50V8J

12

FM2

<13,33> LUMA

14
10
A

U43C

P
OE

+3VS

D15
DAN217_SOT23

D13
DAN217_SOT23

D14
DAN217_SOT23

+5VS

14
13

+5VS

TV-Out Connector

H26
HOLEA

270P_0402_50V7K

150P_0402_50V8J

75_0402_1% 75_0402_1%

Compal Electronics, Inc.


Title

CRT & TVout Connector


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003

Rev
1.0

LA-1701

Sheet
E

14

of

49

U8A

10_0402_5%

C447
15P_0402_50V8J

CLK_ICH_66M

R346
@22_0402_5%

C460
@10P_0402_50V8K

<19,20,21,25>
<19,20,21,25>
<19,20,21,25>
<19,20,21,25>

PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

<20>
<19>
<21>
<25>
<25>

PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4

<20>
<19>
<21>
<25>
<25>

PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3
PCI_GNT#4

1
2
3
4
5

+3VS

10
9
8
7
6

PCI_PIRQA#
PCI_PIRQB#
PCI_REQ#4
PCI_REQB#

+3VS

C1
E6
A7
B7
D6

PCIRST#
PCI_SERR#
PCI_STOP#
PCI_TRDY#

<18> PIDERST#
<18> SIDERST#

8.2K_10P8R_1206_5%

PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3
PCI_GNT#4

PCI_PERR#
PCI_LOCK#

<7,13,19,20,21,22,25,31> PCIRST#
<19,21,25> PCI_SERR#
<19,20,21,25> PCI_STOP#
<19,20,21,25> PCI_TRDY#

RP9
PCI_PERR#
PCI_REQA#
PCI_STOP#
PCI_SERR#

B1
A2
B3
C7
B6

PCI_FRAME#
PCI_DEVSEL#
PCI_IRDY#

<19,20,21,25> PCI_FRAME#
<19,20,21,25> PCI_DEVSEL#
<19,20,21,25> PCI_IRDY#
<19,20,21,25> PCI_PAR
<19,20,21,25> PCI_PERR#

PCI Pullups

PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4

CLK_PCI_ICH

<12> CLK_PCI_ICH

J2
K4
M4
N4

PCI_REQA#
PCI_REQB#
PIDERST#
SIDERST#

P5
F1
M3
L5
G1
L4
M2
W2
U5
K5
F3
F2
B5
A6
E8
C5

C/BE#0
C/BE#1
C/BE#2
C/BE#3

A20GATE
A20M#
DPSLP#
FERR#
IGNNE#
INIT#
INTR
NMI
CPU_PWRGOOD
RCIN#
SLP#
SMI#
STPCLK#

CPU I/F

1
2
3
4
5

+3VS

10
9
8
7
6

HI0
HI1
HI2
HI3
HI4
HI5
HI6
HI7
HI8
HI9
HI10
HI11

HUB I/F

CLK66
REQ#0
REQ#1
REQ#2
REQ#3
REQ#4

HI_STB
HI_STB#
HICOMP
HUB_VREF
HUB_VSWING

GNT#0
GNT#1
GNT#2
GNT#3
GNT#4
PCICLK
FRAME#
DEVSEL#
IRDY#
PAR
PERR#
LOCK#
PME#
PCIRST#
SERR#
STOP#
TRDY#
REQA#/GPI0
REQB#/GPI1/REQ5#
GNTA#/GPO16
GNTB#/GPO17/GNT5#

EE_CS
EE_IN
EE_OUT
EE_SHCLK

+3VS
PCI_PIRQC#
PCI_PIRQD#
SIRQ
PCI_LOCK#

LAN

8.2K_10P8R_1206_5%

APICCLK
APICD0
APICD1
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#/GPI2
PIRQF#/GPI3
PIRQG#/GPI4
PIRQH#/GPI5
IRQ14
IRQ15
SERIRQ

EEPROM I/F

RP11
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_FRAME#

INTRUDER#
SMLINK0
SMLINK1
SMB_CLK
SMB_DATA
GPI11

SMB_CLK <9,10,12>
SMB_DATA <9,10,12>

+1.8VS

SM I/F

W6
AC3
AB1
AC4
AB4
AA5

LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
I/F LAN_TXD1
LAN_TXD2
LAN_CLK
LAN_RSTSYNC
LAN_RST#

Y22
AB23
U23
AA21
W21
V22
AB22
V21
Y23
U22
U21
W23
V23

L19
L20
M19
M21
P19
R19
T20
R20
P23
L22
N22
K21
T21

1 R359
2
56_0402_5%

HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9
HUB_PD10
1

HUB_PD[0..10]

J19
H19
K20
D5
C2
B4
A3
C8
D7
C3
C4
AC13
AA19
J22
D10
D11
A8
C12

C141
0.1U_0402_16V4Z

HUB_PD[0..10]

<6>

Note:
R122,R123 placement
center of MCH and
ICH4M

R339
2 @56_0402_5%

CLK_ICH_66M

CLK_ICH_66M <12>

P21
N20
R23
M23
R22

HUB_VREF
GATEA20 <29>
H_A20M# <4>
R122
H_DPSLP# <4,7>
H_FERR#
150_0402_1%
H_FERR# <4>
HUB_VREF
H_IGNNE# <4>
H_INIT# <4>
1
1
H_INTR <4>
H_NMI <4>
C444
R123
C453
H_CPUPWRGD <4>
150_0402_1%
0.01U_0402_16V7K
RC# <29>
2
2
H_CPUSLP# <4>
H_SMI# <4>
0.01U_0402_16V7K
H_STPCLK# <4>

R344

INTRUDER#
SMLINK0
SMLINK1
SMB_CLK
SMB_DATA
SMB_ALERT#/GPI11

CLK_PCI_ICH

ICH4
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

H5
J3
H3
K1
G5
J4
H4
J5
K2
G2
L1
G4
L2
H2
L3
F5
F4
N1
E5
N2
E3
N3
E4
M5
E2
P1
E1
P2
D3
R1
D2
P4

Interrupt I/F

PCI_AD[0..31]

<19,20,21,25> PCI_AD[0..31]

PCI I/F

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

+3VS
2

HUB_PSTRB <6>
HUB_PSTRB# <6>

SMB_CLK

SMB_DATA

R373
10K_0402_5%
1
2
R372
10K_0402_5%

HUB_RCOMP_ICH
HUB_VREF

APICCLK
APICD0
APICD1
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
PD_IRQ14
SD_IRQ15
SIRQ

+3VS
PCI_PIRQA# <13,20>
PCI_PIRQB# <19>
PCI_PIRQC# <21,25>
PCI_PIRQD# <25>

PD_IRQ14 <18>
SD_IRQ15 <18>
SIRQ <21,22,29,31>

PD_IRQ14

SD_IRQ15

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

1
2
3
4

2
R370
8.2K_0402_5%
2
R369
8.2K_0402_5%
RP74

8
7
6
5
8.2K _8P4R_0804_5%

R85
@1K_0402_5%

A10
A9
A11
B10
C10
A12
C11
B11
Y5

+RTCVCC

INTRUDER# 1

2
R354
330K_0402_5%

H_FERR#

R356
10K_0402_5%
FW82801DBM_BGA421
+VCCP
+3VS
+3VS

5
P
2

U37

B_PCIRST# <18,29>

@74LVC1G125GW_SOT3535

APICCLK
APICD0
APICD1

1
R322

PIDERST#
2
@1K_0402_5%

R333

R332
0_0402_5%

R338
10K_0402_5%

2
0_0402_5%

1
R347

+3VALW

8.2K _8P4R_0804_5%

PCIRST#

PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3

OE#

8
7
6
5

R358
56_0402_5%
1
2
R131
36.5_0402_1%

1
2
3
4

HUB_RCOMP_ICH
RP72

SMLINK0

R374
1
2
4.7K_0402_5%

SMLINK1

R376
1
2
4.7K_0402_5%

GPI11

10K_0402_5%

Title

R371 2
1
10K_0402_5%

Compal Electronics, Inc.


ICH4-M(1/3)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003

Rev
1.0

LA-1701

Sheet
D

15

of

49

+3VS
D12

+3VS
R345

ATF_INT#

2
R141
10K_0402_5%

EC_THRM# <29>

RB751V_SOD323

100K_0402_5%
U8B

PM

SSMUXSEL
CPUPERF#
VGATE/VRMPWRGD

IST

GPI7
GPI8
GPI12
GPI13
GPIO25
GPIO27
GPIO28

GPIO

PM_CLKRUN#

1
R375
10K_0402_5%

AC97_BITCLK
AC97_SDIN0
AC97_SDIN1
AC97_SDIN2
ICH_AC_SDOUT
ICH_AC_SYNC

B8
C13
D13
A13
B13
D9
C9

PDA0
PDA1
PDA2
PDCS1#
PDCS3#
PDDREQ
PDDACK#
PDIOR#
PDIOW#
PIORDY
PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

AC97 I/F
AC_BITCLK
AC_RST#
AC_SDATAIN0
AC_SDATAIN1
AC_SDATAIN2
AC_SDATAOUT
AC_SYNC

IDE I/F

+3VS
<22,29,31> LPC_AD0
<22,29,31> LPC_AD1
<22,29,31> LPC_AD2
<22,29,31> LPC_AD3
<29,31> LPC_DRQ#0
<22> LPC_DRQ#1
<22,29,31> LPC_FRAME#

SB_SPKR
2
R117
@1K_0402_5%

+3VS

ICH_AC_SDOUT
1
R325
@10K_0402_5%

<27>
<27>
<27>
<27>
<33>
<33>
<33>
<33>
<27>
<27>
<28,31>
<28,31>

+3VS

AGP_BUSY#

1
R130
10K_0402_5%

+3VALW
RP73

1
2
3
4

8
7
6
5

OVCUR#1
OVCUR#2
OVCUR#3
OVCUR#5

10K_8P4R_0804_5%

<27> OVCUR#4

PM_RSMRST#
1
10K_0402_5%

2
R368

2 R95
1
22.6_0402_1%

PM_DPRSLPVR
1
@10K_0402_5%

2
R446

<13> VB0
<13> VB1
<13> VB2

@0_0402_5%
BID0
BID1
BID2

LPC I/F

SDDREQ
SDDACK#
SDIOR#
SDIOW#
SIORDY

B15
C14
A15
B14
A14
D14

OC#0
OC#1
OC#2
OC#3
OC#4
OC#5

USB_RBIAS

A23
B23

USB_RBIAS
USB_RBIAS#

VB0
VB1
VB2
BID0
BID1
BID2

SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

USB I/F

OVCUR#0
OVCUR#1
OVCUR#2
OVCUR#3
OVCUR#4
OVCUR#5

J20
G22
F20
G20
F21
H20
F23
H22
G23
H21
F22
E23

SDA0
SDA1
SDA2
SDCS1#
SDCS3#

GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO39
GPIO40
GPIO41
GPIO42
GPIO43

CLOCK
GPIO

PD_DREQ
PD_DACK#
PD_IOR#
PD_IOW#
PD_PIORDY

AB11
AC11
Y10
AA10
AA7
AB8
Y8
AA8
AB9
Y9
AC9
W9
AB10
W10
W11
Y11

PD_D0
PD_D1
PD_D2
PD_D3
PD_D4
PD_D5
PD_D6
PD_D7
PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15

AA20
AC20
AC21
AB21
AC22

SD_A0
SD_A1
SD_A2
SD_CS#1
SD_CS#3

AB18
AB19
Y18
AA18
AC19

SD_DREQ
SD_DACK#
SD_IOR#
SD_IOW#
SD_SIORDY

W17
AB17
W16
AC16
W15
AB15
W14
AA14
Y14
AC15
AA15
Y15
AB16
Y16
AA17
Y17

SD_D0
SD_D1
SD_D2
SD_D3
SD_D4
SD_D5
SD_D6
SD_D7
SD_D8
SD_D9
SD_D10
SD_D11
SD_D12
SD_D13
SD_D14
SD_D15

CLK_ICH_14M
CLK_ICH_48M

J23
F19

RTCRST#

W7

RTC_RST#

Y6

VBIAS

RTCX1

AC7

RTCX1

RTCX2

AC6

RTCX2

VBIAS

SPKR

MISC

AA11
Y12
AC12
W12
AB12

CLK14
CLK48

THRMTRIP#

2
1
@10K_0402_5%
2

PD_A0 <18>
PD_A1 <18>
PD_A2 <18>
PD_CS#1 <18>
PD_CS#3 <18>

PD_D[0..15]
SD_D[0..15]

PD_D[0..15]

<18>

SD_D[0..15]

<18>

SYSRST#

4
U38
@74AHC1G08

2
R385

PD_DREQ <18>
PD_DACK# <18>
PD_IOR# <18>
PD_IOW# <18>
PD_PIORDY <18>

1
0_0402_5%

CLK_ICH_14M

R336
@22_0402_5%

SD_A0 <18>
SD_A1 <18>
SD_A2 <18>
SD_CS#1 <18>
SD_CS#3 <18>

C438
@10P_0402_50V8K

CLK_ICH_48M

SD_DREQ <18>
SD_DACK# <18>
SD_IOR# <18>
SD_IOW# <18>
SD_SIORDY <18>

R331
@22_0402_5%

1
C420
@10P_0402_50V8K

+RTCVCC
3

1
2
R353
180K_0402_5%

1
CLK_ICH_14M <12>
CLK_ICH_48M <12>

1
2

J2
JOPEN

C461
0.1U_0402_16V4Z

2R_VBIAS 1
2
R389
C481
1K_0402_5%
0.047U_0603_16V7K

1
2
R196
10M_0603_5%

H23 SB_SPKR

SB_SPKR <23>

W20 THRMTRIP#

THRMTRIP# <4>

FW82801DBM_BGA421

R98

R115

0_0402_5%

0_0402_5%

0_0402_5%

<23,25,28> AC97_SYNC

R321
33_0402_5%
2

R335

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_DRQ#0
LPC_DRQ#1
LPC_FRAME#

USBP0+
USBP0USBP1+
USBP1USBP2+
USBP2USBP3+
USBP3USBP4+
USBP4USBP5+
USBP5-

1
R390

<4> ITP_DBRESET#

2
1
1
2
R384
10M_0603_5%
X2
1
1
32.768KHz_12.5P_CM155
C203
C190
15P_0402_50V8J
15P_0402_50V8J
2
2

1
R383
@22M_0603_5%

R197
@2.4M_0603_1%

R106

@0_0402_5%

R100

@0_0402_5%

R337

1
2

+3VS

C20
D20
A21
B21
C18
D18
A19
B19
C16
D16
A17
B17

USB20P0+
USB20P0USB20P1+
USB20P1USB20P2+
USB20P2USB20P3+
USB20P3USB20P4+
USB20P4USB20P5+
USB20P5-

<27> OVCUR#0

T2
R4
T4
U2
U3
U4
T5

AA13
AB13
W13
Y13
AB14

PD_A0
PD_A1
PD_A2
PD_CS#1
PD_CS#3

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_DRQ#0
LPC_DRQ#1
LPC_FRAME#

C486
+3VALW
@1U_0805_25V4Z
1
2

<23,25,28> AC97_BITCLK
<23,25,28> AC97_RST#
<23> AC97_SDIN0
<28> AC97_SDIN1
<25> AC97_SDIN2

+3VS

EC_SMI# <29>
SCI# <29>
EC_LID_OUT# <29>
EC_FLASH# <30>

<12,32,41> VGATE

R355
8.2K_0402_5%

J21
Y20
V19

ACIN <29,33,35,37>

RB751V_SOD323
EC_SMI#
SCI#
EC_LID_OUT#

CPUPERF#
CPUPERF#

D27
1

+3VS

+VCCP

R3
V4
V5
W3
V2
W1
W4

<13,30> SUS_STAT#

ICH4
AGPBUSY#
SYSRST#
BATLOW#
C3_STAT#
CLKRUN#
DPRSLPVR
PWRBTN#
PWROK
RI#
RSMRST#
SLP_S1#
SLP_S3#
SLP_S4#
SLP_S5#
STP_CPU#
STP_PCI#
SUS_CLK
SUS_STAT#/LPCPD#
THRM#

<29> PM_BATLOW#
<13> C3_STAT#
<19,21,22,25,29> PM_CLKRUN#
<41> PM_DPRSLPVR
<29> PWRBTN_OUT#
<32> PM_POK
<29> EC_RIOUT#
<21,29> PM_RSMRST#
<12,29> SLP_S1#
<29,33> SLP_S3#
<29> SLP_S4#
<29> SLP_S5#
<12,41> STP_CPU#
<12> STP_PCI#

R2
Y3
AB2
T3
AC2
PM_DPRSLPVR V20
AA1
AB6
EC_RIOUT#
Y1
PM_RSMRST#
AA6
W18
Y4
Y2
SLP_S5#
AA2
W19
Y21
AA4
SUS_STAT#
AB3
ATF_INT#
V1

AGP_BUSY#
SYSRST#
PM_BATLOW#
C3_STAT#

<13> AGP_BUSY#

<23,25,28> AC97_SDOUT

C391
@22P_0402_50V8J

2
R320
33_0402_5%

ICH_AC_SYNC
4

ICH_AC_SDOUT

C390
@22P_0402_50V8J

Title

Compal Electronics, Inc.


ICH4-M(2/3)

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Monday, May 12, 2003
Date:

Rev
1.0

LA-1701

Sheet
D

16

of

49

U8C

C435

C456

C446

2
2
0.1U_0402_16V7K

VCC5REF1
VCC5REF2
VCC5REFSUS1

VCC_CPU_IO_0
VCC_CPU_IO_1
VCC_CPU_IO_2
VCCPLL
VCCRTC

C451
0.1U_0402_16V7K

+1.5VS
+1.5VS
C442
0.1U_0402_16V7K
+3VALW

C441
0.1U_0402_16V7K

1
C423
0.1U_0402_16V7K

C459

C425
0.1U_0402_16V7K

C443
0.01U_0402_16V7K

+VCCP

1
C449
0.1U_0402_16V7K

C445
0.1U_0402_16V7K

C452
0.1U_0402_16V7K

K10
K12
K18
K22
P10
T18
U19
V14

VCCPLL power place

+1.8VS

0.1U_0402_16V7K
1
1

VCCLAN1.5 power place

+3VALW

1
C454
0.1U_0402_16V7K

C457
0.1U_0402_16V7K

VCC1.5 power place

E11
F10
F15
F16
F17
F18
K14
V7
V8
V9

C450
0.1U_0402_16V7K

VCCHI power place

+1.5VALW
2

E12
E13
E20
F14
G18
R6
T6
U6

+3VALW +5VALW

E15

D19
1SS355_SOD323

VCC5REF

E7
V6

VCC5REFSUS
+1.8VS

VCC5REFSUS

+3VS

R319
1K_0402_5%

L23
M14
P18
T22

+5VS

D20
1SS355_SOD323
VCC5REF

1
VCCHI_0
VCCHI_1
VCCHI_2
VCCHI_3

C455
0.1U_0402_16V7K

VCCSUS1.5_0
VCCSUS1.5_1
VCCSUS1.5_2
VCCSUS1.5_3
VCCSUS1.5_4
VCCSUS1.5_5
VCCSUS1.5_6
VCCSUS1.5_7

C426
0.1U_0402_16V7K

R323
1K_0402_5%

VCC1.5_0
VCC1.5_1
VCC1.5_2
VCC1.5_3
VCC1.5_4
VCC1.5_5
VCC1.5_6
VCC1.5_7

POWER

+1.5VS

+1.5VS

GND

1
C424
C436
0.1U_0402_16V7K

C437

2
2
0.1U_0402_16V7K

+3VS

0.1U_0402_16V7K

VCCSUS3.3_0
VCCSUS3.3_1
VCCSUS3.3_2
VCCSUS3.3_3
VCCSUS3.3_4
VCCSUS3.3_5
VCCSUS3.3_6
VCCSUS3.3_7
VCCSUS3.3_8
VCCSUS3.3_9

1
C458
0.1U_0402_16V7K

+1.5VALW
0.1U_0402_16V7K
0.1U_0402_16V7K
1
1
1
1

+3VS

VCC3.3_0
VCC3.3_1
VCC3.3_2
VCC3.3_3
VCC3.3_4
VCC3.3_5
VCC3.3_6
VCC3.3_7
VCC3.3_8
VCC3.3_9
VCC3.3_10
VCC3.3_11
VCC3.3_12
VCC3.3_13
VCC3.3_14
VCC3.3_15

A5
AC17
AC8
B2
H18
H6
J1
J18
K6
M10
P12
P6
U1
V10
V16
V18

+3VS

ICH4
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101

D22
E10
E14
E16
E17
E18
E19
E21
E22
F8
G19
G21
G3
G6
H1
J6
K11
K13
K19
K23
K3
L10
L11
L12
L13
L14
L21
M1
M11
M12
M13
M20
M22
N10
N11
N12
N13
N14
N19
N21
N23
N5
P11
P13
P20
P22
P3
R18
R21
R5
T1
T19
T23
U20
V15
V17
V3
W22
W5
W8
Y19
Y7
A16
A18
A20
A22
A4
AA12
AA16
AA22
AA3
AA9
AB20
AB7
AC1
AC10
AC14
AC18
AC23
AC5
B12
B16
B18
B20
B22
B9
C15
C17
C19
C21
C23
C6
D1
D12
D15
D17
D19
D21
D23
D4
D8
A1

1
C414
0.1U_0402_16V7K

C415
0.1U_0402_16V7K

+VCCP

AA23
P14
U18
C22
AB5

+1.5VS
+RTCVCC
3

VCCLAN3.3_0
VCCLAN3.3_1

E9
F9

+3VALW

VCCLAN1.5_0
VCCLAN1.5_1

F6
F7

+1.5VALW

RTCVREF

+RTCVCC
D25
R310

R445

1
2

BATT1.1

100_0603_1%
DAN202U_SC70

BATT1.2

W=20mils
511_0603_1%

C467
0.1U_0402_16V7K

JP27

ML1220

FW82801DBM_BGA421

Compal Electronics, Inc.

Title

ICH4-M(3/3)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Monday, May 12, 2003
Date:

Rev
1.0

LA-1701

Sheet

17
H

of

49

+5VS

C551
1000P_0402_50V7K

B_PCIRST#

<15,29> B_PCIRST#

1
2

1
C552
0.1U_0402_16V7K

C549
1U_0603_10V6K

C550
10U_1206_16V4Z

Place component's closely IDE CONN.


U40A
D

O
I1

<15> PIDERST#

I0

HD_RST#

74HCT08PW_TSSOP14

R397
1
2
@10K_0402_5%
HD_RST#
PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0

U40B

<15> SIDERST#

B_PCIRST# 5

I0
O

CD_RST#

I1
74HCT08PW_TSSOP14

PD_DREQ
PD_IOW#
PD_IOR#
PD_PIORDY
PD_DACK#
PD_IRQ14
PD_A1
PD_A0
PD_CS#1
HDD_LED#

<16> PD_DREQ
<16> PD_IOW#
<16> PD_IOR#
<16> PD_PIORDY
U40C
HDD_LED#

ODD_LED# 10

PD_D[0..15]

<16> PD_D[0..15]

14

+5VS

I0
O

<16> PD_DACK#
<15> PD_IRQ14
<16> PD_A1
<16> PD_A0
<16> PD_CS#1

2
R399
4.7K_0402_5%

+3VS
DEV_LED# <28>

I1
74HCT08PW_TSSOP14

+5VS

1
R398

+5VS

2
100K_0402_5%

JP25

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44

PD_D8
PD_D9
PD_D10
PD_D11
PD_D12
PD_D13
PD_D14
PD_D15

PD_CSEL 1
R400

2
470_0402_5%

PD_A2
PD_CS#3

PD_A2 <16>
PD_CS#3 <16>
+5VS

HDD CONN
C

+5VS

1
1
C553
10U_1206_16V4Z

1
C554
1000P_0402_50V7K

C555
0.1U_0402_16V7K

2
2
Place component's closely IDE CONN.

<16> SD_D[0..15]

SD_D[0..15]

C235

10U_1206_6.3V6M
2
1
R237 @10K_0402_5%

CDROM_L

<23> CDROM_L

CD_RST#
SD_D7
SD_D6
SD_D5
SD_D4
SD_D3
SD_D2
SD_D1
SD_D0

Unused GATE
U40D

12
13

I0
O

<16> SD_SIORDY

11

I1
+3VS

74HCT08PW_TSSOP14

SD_IOW#

<16> SD_IOW#

2
R239
4.7K_0402_5%

+5VS

SD_IRQ15

<15> SD_IRQ15
<16> SD_A1
<16> SD_A0
<16> SD_CS#1

1
R396

SD_CS#1
ODD_LED#

2
100K_0402_5%

+5VS
+5VS

SD_CSEL
R242
470_0402_5%

CD_AGND <23>

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

CDROM_R

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

CDROM_R <23>

SD_D8
SD_D9
SD_D10
SD_D11
SD_D12
SD_D13
SD_D14
SD_D15
SD_DREQ
SD_IOR#

SD_DREQ <16>
SD_IOR# <16>

SD_DACK#
PDIAG#

SD_CS#3
W=80mils

2
C250
1
R241

R240

SD_DACK# <16>
100K_0402_5%
2
+5VS
SD_A2 <16>
SD_CS#3 <16>
+5VS
+5VS
+5VS

0.1U_0402_16V7K
2
+5VS
100K_0402_5%

CD-ROM CONN.
A

CD_AGND
JP23

Compal Electronics, Inc.


Title

HDD & CDROM Connector


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003

Rev
1.0

LA-1701

Sheet
1

18

of

49

JP4
Q32
SI2301DS_SOT23
+3VALW

TX+

RJ45_TXX-

TX-

<33> RJ45_RXX+

LANGND

1
75_0402_1%

2
R248

RJ45_RXX+

LANGND_1

<33> RJ45_RXXLANGND

1
75_0402_1%

2
R249

RJ45_RXX-

LANGND_2

IDSEL

21
22

PERR#
SERR#

<15> PCI_REQ#1
<15> PCI_GNT#1

118
117

REQ#
GNT#

<15> PCI_PIRQB#

114

INTA#

<21,25,29> ONBD_LAN_PME#

76

PCIRST#

115

<12> CLK_PCI_LAN
<16,21,22,25,29> PM_CLKRUN#

116
75

TXD+
TXDRXIN+
RXIN-

PAR
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#

WE#
OE#

1
R294

2
5.6K_0402_5%

83

RTT2
RTT3

82
81

X1
X2

79
78

RTSET

84

ANODE2

N/C6

NC

CLK
CLKRUN#

ROMCS#

LANVDD

LAN_LED0#

18

14

C267
1000P_0402_50V7K

C259
RJ-45 & RJ-11
220P_1808_3KV8K

C268
1000P_0402_50V7K

LANVDD
JP9

1
2
MODEM CONN.
C

LANVDD

ISOB

R39 2

R276
0_0402_5%
LAN_LED0# <33>
LAN_LED1# <33>

1 1K_0402_5%

R40
49.9_0402_1%

R41
49.9_0402_1%

+3VS

LAN_TX+
LAN_TXLAN_RX+
LAN_RX-

2 15K_0402_5%

C285
0.1U_0402_10V6K

1
1

LAN_LED0#
LAN_LED1#
R44 1

U1
LAN_TXLAN_TX+

8
7
6
C40
0.1U_0402_10V6K
1
2

3
2
1

LAN_RXLAN_RX+

1:1

TDTD+
CT

TXTX+
CT

CT
RDRD+

CT
RXRX+

9
10
11
14
15
16

Y1

RST#

R262
1
330_0402_5%

TIP

12
1

C260
220P_1808_3KV8K

CLKOUT

PME#

RING

11

MOD_TIP

LANVDD

89
88

LWAKE

ACT_CR

YELLOW-ACT

MOD_TIP
MOD_RING

99
98
97

92
91
87
86

CATHODE2

N/C5

VH1
DSSA-P3100SB

C331
0.1U_0402_10V6K

108
107
105
104
103
102
101
100

95

17

LANVDD

CLKOUT
XTALFB

2
R43

1
1.69K_0603_1%

XTALFB

25MHz_25ppm
CRYSTAL
C47
27P_0402_50V8J

R13
75_0402_1%
LANGND

C57
27P_0402_50V8J

110

RJ45_RXXRJ45_RXX+
R12
75_0402_1%

NS0013_16P
R33
49.9_0402_1%

R34
49.9_0402_1%

RJ45_TXXRJ45_TXX+

ISOLATE#

<15,20,21,25> PCI_PERR#
<15,21,25> PCI_SERR#

<7,13,15,20,21,22,25,31>

LED0
LED1
LED2

N/C4

23
15
16
17
19
20

<15,20,21,25> PCI_PAR
<15,20,21,25> PCI_FRAME#
<15,20,21,25> PCI_IRDY#
<15,20,21,25> PCI_TRDY#
<15,20,21,25> PCI_DEVSEL#
<15,20,21,25> PCI_STOP#

C/BE#0
C/BE#1
C/BE#2
C/BE#3

MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7

EECS

2 R261 1
330_0402_5%

N/C3

10
5
DO
GND
6
DI
NC
7
SK
NC
8
CS
VCC
AT93C46-10SI-2.7_SO8

LINK_CR

2
U34

4
3
2
1

15

R83

2
100_0402_5%

EECS
EEDO
EEDI
EESK

50
47
48
49
51
52
53
57
60
61
63
64
65
66
67
68
69
70

PCI_AD17

36
24
14
2

EECS
MA0/EEDO
MA1/EEDI
MA2/EESK
MA3
MA4
MA5
MA6/9356SEL
MA7
MA8/Aux. PWR
MA9
MA10
MA11
MA12
MA13
MA14
MA15
MA16

ANODE1

RX-

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

GREEN-LINK

N/C2

PCI_CBE#[0..3]

<15,20,21,25> PCI_CBE#[0..3]

45
44
43
42
41
39
38
37
34
33
32
31
29
28
27
26
13
11
10
9
8
6
5
4
128
127
126
125
123
122
121
120

MOD_RING

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

U5

PCI I/F
LAN I/F

<15,20,21,25> PCI_AD[0..31]

LAN_LED1#

N/C1

1
PCI_AD[0..31]

13
16

RX+

EN_WOL# <29>

NC
CATHODE1

RJ45_TXX+

<33> RJ45_TXX-

LANVDD

<33> RJ45_TXX+

C16
1000P_1206_2KV7K
CHASSIS GND

C48
0.1U_0402_10V6K

R58

10_0402_5%
C73
10P_0402_50V8K

7
18
30
40
55
56
62
74
80
85
93
111
112
113
124

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

Power

NC
NC
NC
NC
NC

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

54
71
72
73
94
1
12
25
35
46
58
59
77
90
96
106
109
119

LANVDD

1
C317
10U_0805_10V4Z

C318
0.1U_0402_10V6K

C80
0.1U_0402_10V6K

C329
0.1U_0402_10V6K

C375
0.1U_0402_10V6K

C63
0.1U_0402_10V6K

C354
0.1U_0402_10V6K

C314
0.1U_0402_10V6K

C376
0.1U_0402_10V6K

C313
0.1U_0402_10V6K

C377
0.1U_0402_10V6K

C312
0.1U_0402_10V6K

C66
0.1U_0402_10V6K

C378
0.1U_0402_10V6K

RTL8139CL_LQFP128
A

Compal Electronics, Inc.


Title

LAN RealTech8139CL+
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003

Rev
1.0

LA-1701

Sheet
1

19

of

49

+3VS

+3VS

66

1394@0.1U_0402_10V6K

XTPB1M
XTPB1P
XTPA1M
XTPA1P
XTPBIAS1

67
68
69
70
71

XTPB0XTPB0+
XTPA0XTPA0+
XTPBIAS0

74
75
76
77
78

XTPB1XTPB1+
XTPA1XTPA1+
XTPBIAS1

XTPBIAS0
XTPA0+
XTPA0XTPB0+
XTPB0-

1394@1394_FOX

R251
R274

R250

1394@54.9_0402_1%

C283

1394@54.9_0402_1%

1 1394@47P_0402_50V8J

1394@6.34K_0603_1%

1
C262

81
82
83
84
85
55

R260

1394@270P_0402_25V8K 2

1394@5.1K_0603_1%

C17
1394@0.1U_0402_10V6K
2
1

X3

VT6307S-CD_LQFP128
XI 2

XO

R26
1394@54.9_0402_1%

R273
1394@4.7K_0402_5%

22P_0402_50V8J

1394@10P_0402_50V8K

XTPBIAS1
XTPA1+
XTPA1XTPB1+
XTPB1-

C277
1394@10P_0402_50V8K

2
1394@54.9_0402_1%

XO

XI

C276

2
R275
2
1394@1M_0402_1%

C29
1394@0.33U_0805_16V7K

XTPA1+ <33>
XTPA1- <33>
XTPB1+ <33>
XTPB1- <33>

Place close to 1394 CONN.


XTPA0+
XTPA0XTPB0+
XTPB0-

R20

R21

1394@54.9_0402_1%

1394@54.9_0402_1%

1
TVS7

@SF10402ML080C

1
TVS8

TVS9

@SF10402ML080C

2
2
@SF10402ML080C

TVS6

2
1

C23
1394@270P_0402_50V7K
2

2
2
@SF10402ML080C

R19
1394@5.1K_0603_1%

+3VS

1
R25

1394@24.576MHz_16P_3XG-24576-43E1

C42

JP5

4
3
2
1

R270
1394@1K_0402_5%

C258
1394@0.33U_0805_16V7K

1394_XREXT

10_0402_5%

1
2

60
63

R253
R252
1394@54.9_0402_1%
1394@54.9_0402_1% 2

58

57

64
54
53
52
51
50
49
48
45
44
43
42
41
37
35

NC3
NC4
NC5
NC6
NC7
PHYRESET

R272
1394@1K_0402_5%

34
39
40

XTPB0M
XTPB0P
XTPA0M
XTPA0P
XTPBIAS0

Place close to 1394 chip

XREXT

+3VS
EEDI_1394
EECK_1394

XCPS

26
27
28
29

1394@0.1U_0402_10V6K

PME#
NC1
NC2

79

EECS
EEDO
SDA/EEDI
SCL/EECK

R247
1394@510_0402_5%

1394@0.1U_0402_10V6K

GNDATX1
GNDARX2

2
1
C287

IEEE 1394
VT6307S

22
112
33
23
13
6
126
118
108
100
91
31

R35

65
86

8
A0
VCC
7
A1
WC
EECK_1394
6
A2
SCL
EEDI_1394
5
GND
SDA
1394@AT24C02N-10SC-2.7_SO8

2
1
C284

GNDARX1
VDDARX2

CBE0#
CBE1#
CBE2#
CBE3#
IDSEL
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
PAR
REQ#
GNT#
INTA#
PCIRST#
PCICLK

61
72

+3VS

1
2
3
4

80
62

U28
1394@0.1U_0402_10V6K

73

GNDATX0

VDDATX1

56

59
VDDATX0

47
38
PGND2
PGND1

36
46

99
110
122
5
17
32
21
111
30

GNDARX0
VDDARX1

C19

GNDATX2
VDDARX0

CLK_PCI_1394

105
120
121
123
124
125
127
128
93
92
88
89
90

87
C295

XO

1 R49
2
1394@100_0402_5%

PVDD1
PVDD2

12
1
119
104

+3VS

VDDATX2

XI

PCI_AD16
<15,19,21,25> PCI_FRAME#
<15,19,21,25> PCI_IRDY#
<15,19,21,25> PCI_TRDY#
<15,19,21,25> PCI_DEVSEL#
<15,19,21,25> PCI_STOP#
<15,19,21,25> PCI_PERR#
<15,19,21,25> PCI_PAR
<15> PCI_REQ#0
<15> PCI_GNT#0
<13,15> PCI_PIRQA#
<7,13,15,19,21,22,25,31> PCIRST#
<12> CLK_PCI_1394

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_CBE#[0..3]

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

NC21
NC20
NC19
NC18
NC17
NC16
NC15
NC14
NC13
NC12
I2CEEENA
NC11
NC10
NC9
NC8

<15,19,21,25> PCI_CBE#[0..3]

25
24
20
19
18
16
15
14
11
10
9
8
7
4
3
2
117
116
115
114
113
109
107
106
103
102
101
98
97
96
95
94

VSSC2
VSSC1
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
RAMVSS

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDDC2
VDDC1
RAMVDD

U2
PCI_AD[0..31]

C55
C53
C54
C282
C288
C43
C293
C21
C18
1394@0.1U_0402_10V6K
1394@0.1U_0402_10V6K
1394@0.1U_0402_10V6K
1394@0.1U_0402_10V6K
1394@0.1U_0402_10V6K
2
2
2
2
2
2
2
2
2
1394@0.1U_0402_10V6K
1394@0.1U_0402_10V6K
1394@0.1U_0402_10V6K
1394@0.1U_0402_10V6K

C31

<15,19,21,25> PCI_AD[0..31]

+3VS

C20 1394@0.1U_0402_10V6K
C56 1394@0.1U_0402_10V6K C26
2
1
2
1
2
1
1394@0.1U_0402_10V6K
1394@0.1U_0402_10V6K
2
1

+3VS

+3VS

Compal Electronics, Inc.


Title

IEEE1394 Controller & PHY


Size

Document Number

Rev
1.0

LA-1701
Date:
A

Monday, May 12, 2003

Sheet
E

20

of

49

+12VALW

VCC
VCC
VCC

12V

13
12
11

C44
4.7U_0805_10V4Z
S1_VPP

S1_VCC

+5VALW

VPP

1
5
6

2
VCCD0
VCCD1
VPPD0
VPPD1

+3VALW

C296

2
1
C36
4.7U_0805_10V4Z

C60
0.1U_0402_16V7K

1
C304

S1_VPP

1 R23
2
+3VS
@0_1206_5%
1
2
+3VALW
R30
0_1206_5%

2
0.1U_0402_16V7K

8
VPPD0
VPPD1
VCCD0#
VCCD1#

1
C274

S1_VCC
J11

+3VALW

CP-2211_SSOP16

16

OC

SHDN

3.3V
3.3V

GND

3
4

C35
0.1U_0402_16V7K

VCCD0#
VCCD1#
VPPD0
VPPD1

1
2
15
14

0.1U_0402_16V7K
1

+3V_CB

10

5V
5V

C46
0.1U_0402_16V7K

U3

C39
0.1U_0402_16V7K

S1_VCC

1
C33
0.1U_0402_16V7K

2
0.1U_0402_16V7K

1
C358
4.7U_1206_25VFZ

1
C355
10U_1206_16V4Z
0.1U_0402_16V4Z

1
C343

C339
0.1U_0402_16V7K

CARDBUS HOUSING

1
C299

1
C297

1
C289

1
C275

1
C22

+12VS

Q36

CB_REQ#

<15> PCI_REQ#2

<7,13,15,19,20,22,25,31> PCIRST#
<15,19,20,25> PCI_FRAME#
<15,19,20,25> PCI_IRDY#
<15,19,20,25> PCI_TRDY#
<15,19,20,25> PCI_DEVSEL#
<15,19,20,25> PCI_STOP#
<15,19,20,25> PCI_PERR#
<15,19,25> PCI_SERR#
<15,19,20,25> PCI_PAR

2N7002 1N_SOT23

PCI_CBE#3
PCI_CBE#2
PCI_CBE#1
PCI_CBE#0

12
27
37
48

C/BE3#
C/BE2#
C/BE1#
C/BE0#

20
28
29
31
32
33
34
35
36
1
2
21
59
70

CB_REQ#

<15> PCI_GNT#2
<12> CLK_PCI_PCM

CLK_PCI_PCM

<19,25,29> PCM_PME#
<29> PCM_SUSP#
PCI_AD20

1
R285

<15,25> PCI_PIRQC#

1
R271

+3VALW

PCM_RI#
2
22K_0402_5%

<15,22,29,31> SIRQ
<30> PCM_RI#
<16,19,22,25,29> PM_CLKRUN#
<16,29> PM_RSMRST#

1
R281
4

PM_RSMRST#

66

63

125
112
99
88

S1_REG#
S1_A12
S1_A8
S1_CE1#

RST#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
PAR
REQ#
GNT#
PCLK

CRST#/RESET
CFRAME#/A23
CIRDY#/A15
CTRDY#/A22
CDEVSEL#/A21
CSTOP#/A20
CPERR#/A14
CSERR#/WAIT#
CPAR/A13
CREQ#/INPACK#
CGNT#/WE#
CCLK/A16

119
111
110
109
107
105
104
133
101
123
106
108

RI_OUT#/PME#
SUSPEND#

CSTSCHG/BVD1
CCLKRUN#/WP

135
136

S1_RST
S1_A23
S1_A15
S1_A22
S1_A21
S1_A20
S1_A14
S1_WAIT#
S1_A13
S1_INPACK#
S1_WE#
1
2
R289
33_0402_5%
S1_BVD1
S1_WP

IDSEL

CBLOCK#/A19

MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6

CINT#/READY

VCC/GRST#

SPKOUT
CAUDIO/BVD2
CCD2#/CD2#
CCD1#/CD1#
CVS2/VS2#
CVS1/VS1#

103

S1_A19

132

S1_RDY#

62
134

S1_BVD2

137
75
117
131

S1_CD2#
S1_CD1#
S1_VS2
S1_VS1

S1_VCC

R282
47K_0402_5%

S1_VPP
S1_VCC
S1_VCC

S1_A21
S1_RDY#
S1_A20
S1_WE#
S1_A19
S1_A14
S1_A18
S1_A13
S1_A17
S1_A8
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_VS1
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_CE1#
S1_D14
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_CD1#
S1_D3

S1_A23
2
@22K_0402
S1_WP
2
@22K_0402
S1_RST
2
@47K_0402_5%
S1_CE1#
2
@47K_0402_5%
S1_CE2#
2
@47K_0402_5%

1
R51
1
R50
1
R447
1
R448
1
R449

S1_A16

PCM_SPK# <23>

2
S1_D2
S1_A18
S1_D14

2
C286

a68
a34
a67
a33
a66
a32
a65
a31
a64
a30
a63
a29
a62
a28
a61
a27
a60
a26
a59
a25
a58
a24
a57
a23
a56
a22
a55
a21
a54
a20
a53
a19
a52
a18
a51
a17
a50
a16
a49
a15
a48
a14
a47
a13
a46
a12
a45
a11
a44
a10
a43
a9
a42
a8
a41
a7
a40
a6
a39
a5
a38
a4
a37
a3
a36
a2
a35
a1

a68
a34
a67
a33
a66
a32
a65
a31
a64
a30
a63
a29
a62
a28
a61
a27
a60
a26
a59
a25
a58
a24
a57
a23
a56
a22
a55
a21
a54
a20
a53
a19
a52
a18
a51
a17
a50
a16
a49
a15
a48
a14
a47
a13
a46
a12
a45
a11
a44
a10
a43
a9
a42
a8
a41
a7
a40
a6
a39
a5
a38
a4
a37
a3
a36
a2
a35
a1

83
82
81
80
76
75
74
73

CB1410_LQFP144

@10_0402_5%

VCCI

138
122
102
86
50
30
14
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7

126
90

44
18

72
71

CC/BE3#/REG#
CC/BE2#/A12
CC/BE1#/A8
CC/BE0#/CE1#

PQFP 144
22.2 X 22.2 X 1.60

6
22
42
58
78
94
114
130

CLK_PCI_PCM

2
13
100_0402_5%
60
61
64
65
PCM_RI#
67
68
69

S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3

CAD31/D10
CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0
CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6
CAD19/A25
CAD18/A7
CAD17/A24
CAD16/A17
CAD15/IOWR#
CAD14/A9
CAD13/IORD#
CAD12/A11
CAD11/OE#
CAD10/CE2#
CAD9/A10
CAD8/D15
CAD7/D7
CAD6/D13
CAD5/D6
CAD4/D12
CAD3/D5
CAD2/D11
CAD1/D4
CAD0/D3

1
C59

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
2
2 0.1U_0402_16V7K
2
2 0.1U_0402_16V7K
2
2 0.1U_0402_16V7K
2

S1_CD2#
S1_WP
S1_D10
S1_D2
S1_D9
S1_D1
S1_D8
S1_D0
S1_BVD1
S1_A0
S1_BVD2
S1_A1
S1_REG#
S1_A2
S1_INPACK#
S1_A3
S1_WAIT#
S1_A4
S1_RST
S1_A5
S1_VS2
S1_A6
S1_A25
S1_A7
S1_A24
S1_A12
S1_A23
S1_A15
S1_A22
S1_A16

1
C61

144
142
141
140
139
129
128
127
124
121
120
118
116
115
113
98
96
97
93
95
92
91
89
87
85
82
83
80
81
77
79
76

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

RSVD/D14
RSVD/A18
RSVD/D2

3
4
5
7
8
9
10
11
15
16
17
19
23
24
25
26
38
39
40
41
43
45
46
47
49
51
52
53
54
55
56
57

84
100
143

+3V_CB

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

VCCSK0
VCCSK1

<15,19,20,25> PCI_CBE#[0..3]

VPPD1
VPPD0

PCI_CBE#[0..3]

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

<15,19,20,25> PCI_AD[0..31]

VCCD1#
VCCD0#

PCI_AD[0..31]

VCCP0
VCCP1

U31

74
73

JP11
PM_RSMRST#

83
82
81
80
76
75
74
73

C58
1000P_0402_50V7K

PCMC68PIN

C294
1000P_0402_50V7K

@15P_0402_50V8J

Compal Electronics, Inc.


Title

CardBus Controller CB1410 & Socket


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003

Rev
1.0

LA-1701

Sheet
E

21

of

49

10

+3VS
LPD[0..7]

U33

<16,29,31> LPC_FRAME#
<16> LPC_DRQ#1
<7,13,15,19,20,21,25,31>

PCIRST#
+3VS

+3VS
<15,21,29,31> SIRQ
<16,19,21,25,29> PM_CLKRUN#
<12> CLK_PCI_SIO

1
R78
1
R63

2
10K_0402_5%
2
10K_0402_5%

LPC_SMI#

<13>
<13>
<13>
<13>

LPC_PME#

LPC_FRAME#

24
25

CLK_PCI_SIO
CLK_14M_SIO

19

PID0
PID1
PID2
PID3

1
2
3
4

2
2 1

2 1

R324
@33_0402

C397
@22PF_0402

8
7
6
5

PID0
PID1
PID2
PID3

C369
@15PF_0402

RP71

48
54
55
56
57
58
59
6
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47

CLK_PCI_SIO

R309
@10_0402
+3VS

100K_8P4R_0804_5%

1
R312
1
R307

26
27
50
17
30
28
29

PID0
PID1
PID2
PID3

CLK_14M_SIO

20
21
22
23

1
2
R401
10K_0402_5%
LPC_SMI#
LPC_PME#
SIRQ

<12> CLK_14M_SIO

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

2
10K_0402_5%
2
10K_0402_5%

51
52
64
18

+3VS

53
65
93

PD0/INDEX#
PD1/TRK0
PD2/WRTPRT#
PD3/RDATA#
PD4/DSKCHG#
PD5
PD6/MTR0#
PD7

LFRAME#
LDRQ#
PCIRST#
LPCPD#
GPIO12/IO_SMI#
IO_PME#
SIRQ
CLKRUN#
PCICLK
CLK14
GPIO10
GPIO15
GPIO16
GPIO17
GPIO20
GPIO21
GPIO22
GPIO24
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47

BUSY/MTR1#
PE/WDATA#
SLCT/WGATE#
ERROR#/HDSEL#
ACK#/DS1#
INIT#/DIR#
AUTOFD#/DRVDEN0#
STROBE#/DS0#
SLCTIN#/STEP#
DTR2#
CTS2#
RTS2#
DSR2#
TXD2
RXD2
DCD2#
RI2#
DTR1#
CTS1#
RTS1#
DSR1#
TXD1
RXD1
DCD1#
RI1#
IRMODE/IRRX3
IRRX2
IRTX2

GPIO13/IRQIN1
GPIO14/IRQIN2
GPIO23/FDC_PP
VTR
VCC
VCC
VCC
VSS
VSS
VSS
VSS

RDATA#
WDATA#
WGATE#
HDSEL#
DIR#
STEP#
DS0#
INDEX#
DSKCHG#
WRTPRT#
TRK0#
MTR0#
DRVDEN0
DRVDEN1
GPIO11/SYSOPT

68
69
70
71
72
73
74
75

LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7

79
78
77
81
80
66
82
83
67

LPTBUSY
LPTPE
LPTSLCT
LPTERR#
LPTACK#
LPTINIT#
LPTAFD#
LPTSTB#
LPTSLCTIN#

100
99
98
97
96
95
94
92

RP4

LPD[0..7] <26,33>

CTS2#
DSR2#
DCD2#
RI2#

1
2
3
4

8
7
6
5

4.7K_8P4R_0804_5%
RP3
DCD#1
DSR1#
CTS1#
RI1#

LPTBUSY <26,33>
LPTPE <26,33>
LPTSLCT <26,33>
LPTERR# <26,33>
LPTACK# <26,33>
LPTINIT# <26,33>
LPTAFD# <26,33>
LPTSTB# <26,33>
LPTSLCTIN# <26,33>

+5VS

4
3
2
1

5
6
7
8
4.7K_8P4R_0804_5%

RXD1

2
R53

RXD2

1
2
R54 1K_0402_5%

1
1K_0402_5%

CTS2#
DSR2#
RXD2
DCD2#
RI2#

89
88
87
86
85
84
91
90

DTR1#
CTS1#
RTS1#
DSR1#
TXD1
RXD1
DCD#1
RI1#

63
61
62

IRMODE
IRRX
IRTXOUT

16
10
11
12
8
9
5
13
4
15
14
3
1

RDATA#
WDATA#
WGATE#
HDSEL#
FDDIR#
STEP#
DRV0#
INDEX#
DSKCHG#
WP#
TRACK0#
MTR0#
3MODE#

+3VS
DTR#1 <33>
CTS#1 <33>
RTS#1 <33>
DSR#1 <33>
TXD1 <33>
RXD1 <33>
DCD#1 <33>
RI#1 <30,33>

+5VS
R225
JP10
@1K_0402_5%

1
2
3
4
5
6
7
8
9
10

1
2
3
4
5
6
7
8
9
10
@96212-1011S

RXD1
TXD1
DSR1#
RTS1#
CTS1#
DTR1#
RI1#
DCD#1

IRMODE <26>
IRRX <26>
IRTXOUT <26>

For SW debug use when no seial port


D

+5VS

+3VS

RP70
WP#
TRACK0#
INDEX#
DSKCHG#

49
2

7
31
60
76

LAD0
LAD1
LAD2
LAD3

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

<16,29,31>
<16,29,31>
<16,29,31>
<16,29,31>

SMsC LPC47N227

1
2
3
4

R80
@1K_0402_5%

8
7
6
5
1K_8P4R_0804_5%

+3VS

RP5
WDATA#
WGATE#
HDSEL#
FDDIR#

C
1

C85
4.7U_0805_10V4Z

1
C370

1
C360

C65

R81
1K_0402_5%

Base I/O Address

1
C342
0.1U_0402_10V6K

* 0 = 02Eh
1 = 04Eh

+5VS

6
7
8
9
10

5
4
3
2
1

STEP#
MTR0#
RDATA#
DRV0#

+5VS

1K_10P8R_1206_5%

0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K


+5VS

2
R297

3MODE#
1
10K_0402_5%

Title

Compal Electronics, Inc.

LA-XXXX
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003

Rev
1.0

LA-1701

10

Sheet

22

of

49

U23
@0.1U_0402_16V4Z2

+5VS
C198

GND

VOUT

R181
10K_0402_1%

1U_0603_10V6K
SN74LVC14APWLE_TSSOP14

VDDA_CODEC
W=40Mil

+5VS

R427

1U_0603_10V6K
SN74LVC14APWLE_TSSOP14

R89
1
2
560_0402_5%

MONO_INR

VIN

VOUT

DELAY

C150
7
0.1U_0402_10V6K
8

SENSE or ADJ

ERROR
SD

2
R411

+5VS

R176
1
2
28.7K_0603_1%

C168

CNOISE

1
C156

1
10K_0402_5%

R177
10K_0603_1%

GND

SI9182DH-AD_MSOP8

R174
2.4K_0402_5%

Q24
2SC2411K_SOT23

2
B

C149
4.7U_0805_6.3V6K

1U_0603_10V6K
1
2

C114
2
1

10

C167
1
2

4.7U_0805_6.3V6K

C165
0.1U_0402_10V6K

0.01U_0402_25V7Z

O
7

MONO_INC

39.2K_0402_1%

14

MONO_IN 1

U4E

@0.1U_0402_16V4Z

U19

+3VALW

C170
1U_0603_10V6K
1

11

+5VAMP

C179

2
+5VAMP
0_1206_5%

1
R192

+5VS

R182
10K_0402_1%

<21> PCM_SPK#

R193
@10K_0402_1%

R88
1
2
560_0402_5%

@100P_0402_50V8K

C113
1

SUSP# <29,34,38>

2 @30K_0603_1%

C183 2

@LP3965-ADJ

U4D

R1901

14

SN74AHCT1G125GW_SOT353-5
C99
0.22U_0603_10V7K

R84
1
2
10K_0402_1%

@1U_0603_10V6K

SUSP#

1
4

1
U7

+5VAMP

5
1
A

P
OE#

SD
ADJ

+3VALW
R82
100K_0402_1%

VIN

C205

5
@10U_1206_6.3V6M~D

C108
0.1U_0402_16V4Z

C207

+3VALW
+3VALW

<29> BEEP#

+5VAMP_CODEC

1
L34

2
0_0805_5%

1
L35

2
+5VAMP
@0_0805_5%

VDDA_CODEC

+3VALW
U4F

12

1U_0603_10V6K
SN74LVC14APWLE_TSSOP14

C161
0.1U_0402_16V4Z
2

D11
RB751V_SOD323

R92
@10K_0402_5%

C472
0.1U_0402_16V4Z

MONO_INR

<33> DLINE_IN_R

R212 2
R219 1

1 4.7K_0402_5%
2 4.7K_0402_5%

DLINE_IN_R_L

R213 2
R220 1

1 4.7K_0402_5%
2 4.7K_0402_5%

DLINE_IN_R_R

15
2 R199
C213
1

<18> CDROM_L
3

<18> CDROM_R

<18> CD_AGND

R209 2
R214 1
R211 2
R216 1

1 4.7K_0402_5%
2 1.3K_0402_5%

R215 1

R210 2

1 1.1K_0402_5%

R218
R217

<25> MDC_AUDIO_MON

1 4.7K_0402_5%
2 1.3K_0402_5%

1
1

2.7K_0402_5%

2
2

1
R444
2 1U_0603_10V6K

2
17
4.7K_0402_5%
DLINE_IN_RC_L
23

2 1U_0603_10V6K

DLINE_IN_RC_R

<24> HPS

C214 1
CDROM_R_R

R388
R387

2
1

1
2

2 1U_0603_10V6K

CDROM_RC_L

18

C210 1

2 1U_0603_10V6K

CDROM_RC_R

20

C209 1

2 1U_0603_10V6K

CDGNDA

19

1
C211
1
C212
1
C487
1
C483

<28> MIC1

0_0402_5%
10K_0402_5%

MDC_AUDIO_MONR

MD_SPKR

2
1U_0603_10V6K
2 MDC_AUDIO_MONRC
@1U_0603_10V6K
2
1U_0603_10V6K
2 MD_SPKRC
0.1U_0402_16V4Z

<16,25,28> AC97_RST#

2
0_1206_5%

1
L10

2
0_1206_5%

C482
0.1U_0603_16V7K

2
C493

<24> EAPD
<33> SPDIFO

C155
@0.1U_0402_16V4Z

@0.1U_0402_16V4Z
C204
2
1

R357

R360

41

LINE_OUTL <24>
LINE_OUTR <24>
MDMIC C159 1

2 1U_0603_10V6K

R377 2

1 33_0402_5%

AC97_BITCLK <16,25,28>

R378 2

1 33_0402_5%

AC97_SDIN0 <16>

XTL_IN

XTL_OUT

28

0.1U_0402_16V4Z
C477
2
1

4.7K_0402_5%

CLK_14M_CODEC

CODEC_REF

@24.576MHz

<12>

R175
@10_0402_5%
1

C162
@22P_0402_50V8J

C164
@15P_0402_50V8J

AUD_REF

AFILT1
AFILT2
AFILT3
AFILT4

SDATA_OUT

SPDIFO
DVSS1
DVSS2

29
30
31
32

NC
NC

12
42

AVSS1
AVSS2
AVSS3
AVSS4

26
40
44
33

AFILT1
AFILT2
AFILT3
AFILT4

1
C189 1

2 270P_0402_50V7K

C185 1

2 270P_0402_50V7K

C182 1

2 270P_0402_50V7K

C178 1

2 270P_0402_50V7K

1
C202
1U_0603_10V6K

C197
0.1U_0402_16V4Z

R365

R363

FREQ. SEL

24.576MHZ

Crystal

Stuff

Stuff

14.318MHZ

External

AD1981B_LQFP48

Compal Electronics, Inc.


Title

AC97 CODEC

@0.1U_0402_16V4Z

1 CLK_14M_CODEC
0_0402_5%

27

@0.1U_0402_16V4Z
C474
2
1 GNDA

GND

Y3

3
C188
@22P_0402_50V8J

VREF

EAPD

2
R184

R189
2
1
@1M_0402_5%

CD_GND

47

MD_MIC <25,28>

SDATA_IN
CD_R

ID0
ID1

C163
10U_0805_10V4Z

BIT_CLK
CD_L

45
46

HP_LOUT_R

LINE_IN_R

SYNC

4
7

0.1U_0402_16V4Z

DVDD2

DVDD1

34

38

43
AVDD3

AVDD4

25

LINE_IN_L

RESET#

48

@4.7K_0402_5%

L36
1
2
FBM-L10-160808-301-T_0603
2
1
R361
0_0402_5%

39

11

<16,25,28> AC97_SDOUT

1K_0402_5%
1K_0402_5%

HP_LOUT_L

VREFOUT

37

JS0

PHONE

10

C468
0.1U_0402_16V4Z

+3VS

C478

36

MONO_OUT

MIC2

2 33_0402_5%

35

JS1

13

2 33_0402_5%

2
2

LINE_OUT_R

22

1 R367
1
1

LINE_OUT_L

AUX_R

MIC1

1 R381

R365
R363

AUX_L

21

<16,25,28> AC97_SYNC

C494
@0.1U_0402_16V4Z

1
L9

24

C208 1

<28> MIC2
<25,28> MD_SPK

1 0_0402_5%16

CDROM_R_L

CD_GNA

@10K_0402_5%
@1K_0402_5%

14

AVDD2

AVDD1

U22

L37
1
2
FBM-L10-160808-301-T_0603

+3VS_CODEC

<33> DLINE_IN_L

1
1
C160
C172
C473
0.1U_0402_16V4Z 0.1U_0402_16V4Z
10U_1206_6.3V6M
2
2

O
G

13

<16> SB_SPKR

C115
R90
2
1 1
2
560_0402_5%

14

+5VAMP_CODEC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003

Rev
1.0

LA-1701

GNDA
B

Sheet

23
H

of

49

+5VAMPP

+5VAMP
40mils

1
L15

1
+

10U_1206_6.3V7K

C488
0.1U_0603_25V7M

2 0_0402_5%
2 @0_0402_5%

+5VAMP

SE/BTL#

LHPIN
LLINEIN

14

PC-BEEP

HP/LINE#

15

1
1 L17
1 L16
1 L12
L11

GAIN1
GAIN0
SHUTDOWN#

3
2

100K_0402_5% @100K_0402_5%

Gain Settings
C217
0.47U_0603_10V7K

R391
@100K_0402_5%

1
12
13
24

R392
100K_0402_5%

2
1

GAIN0

GAIN1

SE/BTL#

Av(inv)

6 dB

10 dB

EAPD# <28>

15.6 dB

21.6 dB

4.1 dB

D
Q51
2N7002 1N_SOT23

2
G
3

SPKR+ <28>

R394

100K_0402_5%

<23> EAPD

SPKL+ <28>

SPKR+

11

R432

EAPD#

SPKL+

2
100U_6.3V_M
2
100U_6.3V_M

+5VAMP

17
R393

BYPASS

1
C565
1
C566

HPS

TPA0312PWP_TSSOP24~D

SPKLSPKL+_C
SPKRSPKR+_C

2
0_1206_5%
2
0_1206_5%
2
0_1206_5%
2
0_1206_5%

SPK_LSPK_L+
SPK_RSPK_R+

LIN

9
4
16
21

18
7

19

RIN

22

LOUTLOUT+
ROUTROUT+

RHPIN

R162 1
R163 1

PVDD2
PVDD1

0.47U_0603_10V7K
2

10

VDD

C176
1

RLINEIN

<28,29> EC_MUTE#

0.47U_0603_10V7K
2
0.47U_0603_10V7K
L_HP_C
2
0.022U_0603_25V7K
LINE_C_OUTL
2

20

EAPD#

C216
1
C489
1
C201
1

23

R429
0_0402_5%
0_0402_5%
2

0.022U_0603_25V7K
LINE_C_OUTR
2
0.47U_0603_10V7K
R_HP_C
2
0.47U_0603_10V7K
2

<23> LINE_OUTL

R419
1

@0_0402_5%
LINE_R_OUTL
2

R416
1

1
C175
0.1U_0603_25V7M

C174
1
C490
1
C215
1

GND1
GND2
GND3
GND4

@0_0402_5%
2

U24

R428
0_0402_5%
R413
1

@150U_D2_6.3VM

C492

0_0402_5%
LINE_R_OUTR
2

<23> LINE_OUTR

R414
1

C206

2
0_1206_5%

JP19

S
SPKL+_C
SPKL-

+5VAMP

1
2

1
2
L-SPK CONN
JP18
1 1
2 2

R420
1
2
100K_0402_5%

HP_PLUG

<28> HP_PLUG

R159
100K_0402_5%

C562

I1

I0

SPKR+_C
SPKRHPS
O 4
U21
TC7SH32FU_SSOP5

HPS <23>

C193

C194

C195

C196

R-SPK CONN.

47P_0402_50V8J
2
2
2
47P_0402_50V8J
47P_0402_50V8J
47P_0402_50V8J

0.1U_0603_16V7K

<33> DOCK_HPS

+5VAMP

Compal Electronics, Inc.


Title

AMP & Audio Jack


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003

Rev
1.0

LA-1701

Sheet
E

24

of

49

+3VS

+5VS

+5VS

+3VALW

1
C77
0.01U_0402_16V7K

1
C74
10U_1206_6.3V6M

1
C75
0.01U_0402_16V7K

1
C95
0.1U_0402_16V7K

1
C97
4.7U_0805_6.3V6K

1
C323
0.01U_0402_16V7K

1
C90
0.1U_0402_16V7K

1
C322
4.7U_0805_6.3V6K

1
C96
0.01U_0402_16V7K

+3VAUX
Q16
1SI2301DS_SOT23

C84
1U_0603_10V6K

1
C100
C107
4.7U_0805_6.3V6K
0.1U_0402_16V7K
2
2
1

C106

0.01U_0402_16V7K
<31> Wireless_OFF

PCI_AD[0..31]

PCI_AD[0..31]

<15,19,20,21>

JP28
TIP

R65
<15,21> PCI_PIRQC#

@0_0402_5%
2

0_0402_5%
2

R64
<15> PCI_PIRQD#

D17

1
RB751V_SOD323

<28,29,31> Wireless_OFF#
+3VS
<15> PCI_REQ#4

W=40mils

CLK_PCI_MINI

<12> CLK_PCI_MINI
<15> PCI_REQ#3

PCI_REQ#3
PCI_AD31
PCI_AD29

R298
@1K_0402_5%
1
2

<31> CH_DATA
<15,19,20,21> PCI_CBE#3

CLK_PCI_MINI

PCI_AD27
PCI_AD25
PCI_AD23

PCI_AD21
PCI_AD19
R301
10_0402_5%

<15,19,20,21> PCI_CBE#2
<15,19,20,21> PCI_IRDY#

C319
10P_0402_50V8K

PCI_AD17
PCI_CBE#2
PCI_IRDY#

<16,19,21,22,29> PM_CLKRUN#
<15,19,21> PCI_SERR#

PCI_SERR#

<15,19,20,21> PCI_PERR#
<15,19,20,21> PCI_CBE#1

PCI_PERR#
PCI_CBE#1
PCI_AD14
PCI_AD12
PCI_AD10

PCI_AD8
PCI_AD7
PCI_AD5

+5VS
<16,23,28> AC97_SYNC
<16> AC97_SDIN2
<16,23,28> AC97_BITCLK

<23> MDC_AUDIO_MON
<23,28> MD_MIC
<30> MODEM_RI#
+5VS

PCI_AD3
W=30mils
PCI_AD1

AC97_SYNC
AC97_SDIN2
AC97_BITCLK
C76
2
1
+3VALW
@15P_0402_50V8J
MDC_AUDIO_MON
MD_MIC

MODEM_RI#
W=30mils

3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
127

1
KEY
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123

2
KEY
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

127

128

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

RING

W=40mils

+5VS

PCI_GNT#4
W=40mils

1 R72
2
PCI_AD30 @1K_0402_5%

@0_0402_5%
2 PCI_PIRQC#

R69
1

0_0402_5%
2 PCI_PIRQD#

PCI_GNT#4 <15>
+3VALW
PCIRST# <7,13,15,19,20,21,22,31>
+3VS
PCI_GNT#3 <15>

W=40mils
PCI_GNT#3

PCI_AD28
PCI_AD26
PCI_AD24
MINI_IDSEL

R70
1

MINI_PME# <19,21,29>
CH_CLK <31>

PCI_AD18
2 R76
100_0402_5%

PCI_AD22
PCI_AD20
PCI_AD18
PCI_AD16
PCI_FRAME#
PCI_TRDY#
PCI_STOP#
PCI_DEVSEL#

PCI_PAR <15,19,20,21>

PCI_FRAME# <15,19,20,21>
PCI_TRDY# <15,19,20,21>
PCI_STOP# <15,19,20,21>
PCI_DEVSEL# <15,19,20,21>

PCI_AD15
PCI_AD13
PCI_AD11
PCI_AD9
PCI_CBE#0

PCI_CBE#0 <15,19,20,21>

PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0

AC97_SDOUT
AC97_RST#
MD_SPK

W=40mils

AC97_SDOUT <16,23,28>
AC97_RST# <16,23,28>
MD_SPK <23,28>

+3VAUX

128

Mini-PCI SLOT

Compal Electronics, Inc.


Title

Mini PCI Slot


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003

Rev
1.0

LA-1701

Sheet
E

25

of

49

Parallel Port

LPD[0..7]

<22,33> LPD[0..7]
+5V_PRN
D4

RB420D_SOT23

CP4

w=20mils

LPD3
LPD2
LPD1
LPD0
LPD7
LPD6
LPD5
LPD4

+5VS

R5
1K_0402_5%

C9
0.1U_0402_16V7K

9
10
11
12
13
14
15
16

W=20mils
LPTSTB# 1

<22,33> LPTSTB#

R4

2
33_0402_5%

LPTAFD# 1
R1

2
33_0402_5%

<22,33> LPTERR#

FD6
FD7
LPTACK#
LPTBUSY
LPTPE

<22,33> LPTPE

LPTSLCT

<22,33> LPTSLCT

LPTINIT#

<22,33> LPTINIT#

1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13

AFD/3M#
FD0
LPTERR#
FD1
LPT_INIT#
FD2
SLCTIN#
FD3

FD5

<22,33> LPTBUSY

AFD/3M#
LPTERR#
LPT_INIT#
SLCTIN#

FD3
FD2
FD1
FD0
FD7
FD6
FD5
FD4

LPTSLCTIN#

<22,33> LPTSLCTIN#

LPTACK#
LPTBUSY
LPTPE
LPTSLCT

LPT_INIT#
2
33_0402_5%

R3

SLCTIN#
2
33_0402_5%

+5V_PRN
RP2
FD0
FD1
FD2
FD3

1
2
3
4
5

+5V_PRN

10
9
8
7
6

8
7
6
5

FD0

TVS22 1

2 @SF10402ML080C

FD1

TVS20 1

2 @SF10402ML080C

FD2

TVS19 1

2 @SF10402ML080C

FD3

TVS2 1

2 @SF10402ML080C

FD4

TVS17 1

2 @SF10402ML080C

FD5

TVS16 1

2 @SF10402ML080C

FD6

TVS15 1

2 @SF10402ML080C

FD7

TVS14 1

2 @SF10402ML080C

+5V_PRN_R TVS24 1

2 @SF10402ML080C

AFD/3M#

TVS23 1

2 @SF10402ML080C

LPTERR#

TVS21 1

2 @SF10402ML080C

LPT_INIT#

TVS1 1

2 @SF10402ML080C

SLCTIN#

TVS18 1

2 @SF10402ML080C

LPTACK#

TVS13 1

2 @SF10402ML080C

LPTBUSY

TVS12 1

2 @SF10402ML080C

LPTPE

TVS11 1

2 @SF10402ML080C

LPTSLCT

TVS10 1

2 @SF10402ML080C

CP1

R2

1
2
3
4

220P_1206_8P4C_50V8K

33_16P8R_1206_5%

FD4

<22,33> LPTACK#

8
7
6
5
4
3
2
1

+5V_PRN_R
JP2

<22,33> LPTAFD#

RP69

FD7
FD6
FD5
FD4

4.7K_10P8R_1206_5%
+5V_PRN

1
2
3
4

8
7
6
5

220P_1206_8P4C_50V8K
CP3
FD0
FD1
FD2
FD3

1
2
3
4

8
7
6
5

220P_1206_8P4C_50V8K
CP2
FD4
FD5
FD6
FD7

1
2
3
4

8
7
6
5

220P_1206_8P4C_50V8K

RP1
SLCTIN#
LPT_INIT#
LPTERR#
AFD/3M#

1
2
3
4
5

+5V_PRN

10
9
8
7
6

LPTACK#
LPTBUSY
LPTPE
LPTSLCT

4.7K_10P8R_1206_5%

LPTCN-25-SUYIN

FIR Module
+5VS

R227

FIR@10_1206

FIR@10_1206

C220

FIR@22UF_10V_1206

+5VS_FIR

C218

FIR@0.1U_0402_10V6K
2

R226

+3VS

U25

T = 20mil
C219
FIR@0.1U_0402_10V6K

2
4
6
8

IRED_C
RXD
VCC
GND

IRED_A
TXD
SD/MODE
MODE

1
3
5
7

+ C233
FIR@10U_TE-01_6.3VM

T = 40mil

T = 12mil
T = 12mil

IRTXOUT
IRMODE

T = 12mil

IRRX

C232
FIR@0.1U_0402_10V6K

IRTXOUT <22>
IRMODE <22>
IRRX <22>

FIR@IR_VISHAY_TFDU6101E-TR4_8P

Title

Compal Electronics, Inc.


LPT Port & FIR

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
LA-1701
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003
5

Rev
1.0
Sheet
1

26

of

49

USB CONNECTOR 1
D

USB CONNECTOR 2
D

+5V

USB_VCCA

U27

USB_VCCA

W=40mils
VIN
VOUT
VIN/CE VOUT

1
5

R243
470K_0402_5%

2
2

C251
150U_D2_6.3VM

1
1

+
C261
0.1U_0402_10V6K

OVCUR#0

+
C266
1000P_0402_50V7K

C252
150U_D2_6.3VM

C272
0.1U_0402_10V6K

R244

2
C254
1000P_0402_50V7K

560K_0402_5%

C271
1000P_0402_50V7K

OVCUR#0 <16>

4.7U_0805_10V4Z

GND
RT9701-CBL_SOT23_5

W=40mils

1
1

3
4

C278

<16> USB20P1-

<16> USB20P1+

2
<16> USB20P0-

<16> USB20P0+

L28
0_0603_5%
1
L24

L25

4 @DLW21SN900SQ2

VCC
DD+
GND
USB_CONN1

JP7

1
2
3
4

USB1DUSB1D+

1
4 @DLW21SN900SQ2

JP8

1
2
3
4

USB0DUSB0D+

L30
0_0603_5%
1

1
L31
0_0603_5%
USB_VCCA
USB1DUSB1D+

TVS30

L29
0_0603_5%

VCC
DD+
GND
USB_CONN1

1
TVS29

TVS28

@SF10402ML080C
USB_VCCA
USB0DUSB0D+

TVS27

TVS26

@SF10402ML080C

2
2
@SF10402ML080C

TVS25

@SF10402ML080C

@SF10402ML080C

2
2
@SF10402ML080C

USB CONNECTOR 3
+5V

USB_VCCC

U26

VIN
VOUT
VIN/CE VOUT

W=40mils

1
5

1
1

3
4
2

OVCUR#2

C270
0.1U_0402_10V6K

C269
1000P_0402_50V7K

OVCUR#4 <16>

4.7U_0805_10V4Z

R259
470K_0402_5%

C279

GND
RT9701-CBL_SOT23_5

C253
150U_D2_6.3VM

1
C273
1000P_0402_50V7K

R266
560K_0402_5%

2
<16> USB20P4-

<16> USB20P4+

L26
0_0603_5%
1
L23

JP6

1
2
3
4

USB4DUSB4D+

1
4 @DLW21SN900SQ2

1
L27
0_0603_5%
USB_VCCC
USB4DUSB4D+

VCC
DD+
GND
USB_CONN1

TVS33

1
TVS32

TVS31

@SF10402ML080C

@SF10402ML080C

2
2
@SF10402ML080C

Title

Compal Electronics, Inc.


USB Connector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003

Rev
1.0

LA-1701

Sheet
1

27

of

49

INT_KBD CONN.

MDC Conn.
JP16

+3VMDC

1
R349
1
R348

+3V

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

<23,25> MD_MIC

+3VALW

2
MDC@0_0805
2
@0_0805

C466
MDC@0.1U_0402_10V6K

C463
MDC@4.7UF_10V_0805

+3VMDC
+3VS
<16,23,25> AC97_SDOUT
<16,23,25> AC97_RST#
+3VS

MONO_OUT/PC_BEEP
AUDIO_PWRDN/DETECH
GND
MONO_PHONE
AUXA_RIGHT
RESERVED/BT_ON#
AUXA_LEFT
GND
CD_GND
+5Vmain
CD_RIGHT
RESERVED/USB+
CD_LEFT
RESERVED/USBGND
RESERVED/PRIMARY_DN
+3.3Vaux/BT_VCC
RESERVED/+5VD/WAKEUP
GND
RESERVED/GND
+3.3Vmain
AC97_SYNC
AC97_SDATA_OUT
AC97_SDATA_IN1
AC97_RESET#
AC97_SDATA_IN0
GND
GND
AC97_MSTRCLK
AC97_BITCLK

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

L33
L32

BT_DETACH <30>
MD_SPK <23,25>
BT_ON# <30>
BT_PRES# <30>
+5VS
USB20P5+ <16,31>
USB20P5- <16,31>

1 @0_0603
1 @0_0603

2
2

AC97_SYNC <16,23,25>
AC97_SDIN1 <16>

1 R352
MDC@22_0402
1 R350
MDC@22_0402

JP21
KSO0
KSO2
KSO5
KSIN14
KSIN8
KSIN12
KSIN10
KSI0
KSI4
KSI2
KSI1
KSI3
KSO3
KSO8
KSO4
KSO7
KSO6
KSO10
KSO1
KSI5
KSI6
KSI7
KSIN13
KSIN11
KSIN9
KSO9

<30> KSIN14
<30> KSIN8
<30> KSIN12
<30> KSIN10

AC97_BITCLK <16,23,25>

+5VS

C173
MDC@0.1U_0402_10V6K

MDC@1000PF_0402

C158
MDC@1000PF_0402

MDC@AMP 3-1473290-0

C169

C157
MDC@0.1U_0402_10V6K

JP20

<24> SPKR+
<24> SPKL+

SPKR+
SPKL+

60
58
56
54
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

JP24

1
1
2
2
3
3
4
4
5
5
6 6
FUN. BUTTON CONN.

R430
1
R431
1

EC_MUTE_IN# <30>
VOL_UP# <30>
VOL_DW# <30>

@0_0402_5%
2 EC_MUTE#
0_0402_5%
2 EAPD#

EC_MUTE# <24,29>
EAPD# <24>

<23> MIC1
<23> MIC2
CODEC_REF
+5VAMP_CODEC
<24> HP_PLUG
+5V
+5VS
+5VALW
<18> DEV_LED#
<30> BT/WL_ON/OFF#
<25,29,31> Wireless_OFF#
<30> TP_ON/OFF#
<30> TPAD_LED#
<30,33> POWER1_LED#
<30> FULL_LED#
<30> CHARGING_LED#
<29> TP_CLK
<29> TP_DATA

Power button
3

MIC2
HP_PLUG

DEV_LED#
BT/WL_ON/OFF#
Wireless_OFF#
TP_ON/OFF#
TPAD_LED#
POWER1_LED#
FULL_LED#
CHARGING_LED#
TP_CLK
TP_DATA

+5VALW

1
DLINE_OUT_R
DLINE_OUT_L

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

CP7
+5VAMP_CODEC

CODEC_REF
+5VAMP_CODEC

+5V
+5VS
+5VALW

KSO0
KSO2
KSO5
KSIN14
KSIN8
KSIN12
KSIN10
KSI0
KSI4
KSI2
KSI1
KSI3
KSO3
KSO8
KSO4
KSO7
KSO6
KSO10
KSO1
KSI5
KSI6
KSI7
KSIN13
KSIN11
KSIN9
KSO9

C200
0.1U_0402_10V6K

MIC2

DEV_LED#
BT/WL_ON/OFF#
Wireless_OFF#
TP_ON/OFF#
TPAD_LED#
POWER1_LED#

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

K/B CONN.

1
C199
0.1U_0402_10V6K

MIC1

HP_PLUG

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

KSO8
KSO3
KSI3
KSI1

1
2
3
4

CP9
KSO5
KSO2
KSO0

8
7
6
5

100P_1206_8P4C_50V8
C495
0.1U_0402_10V6K

1
2
3
4

8
7
6
5

100P_1206_8P4C_50V8

CP6
KSO10
KSO6
KSO7
KSO4

1
2
3
4

8
7
6
5

100P_1206_8P4C_50V8

FULL_LED#
CHARGING_LED#
TP_CLK
TP_DATA

CP5
KSO9
KSI7
KSI5
KSO1

1
2
3
4

CP8
KSI2
KSI4
KSI0
KSI6

8
7
6
5

100P_1206_8P4C_50V8

1
2
3
4

8
7
6
5

100P_1206_8P4C_50V8

LID SW

+3VALW

2
5

MIC1

4
2

DLINE_OUT_R
DLINE_OUT_L

+5VS

SPKR+
SPKL+

59
60
59
57
58
57
55
56
55
53
54
53
51
52
51
49
50
49
47
48
47
45
46
45
43
44
43
42
41 41
40
39 39
38
37 37
36
35 35
34
33 33
32
31 31
30
29 29
28
27 27
26
25 25
24
23 23
22
21 21
20
19 19
18
17 17
16
15 15
14
13 13
12
11 11
10
9 9
8
7 7
6
5 5
4
3 3
2
1 1
SW BD CONN

ON/OFF BUTTON

SW1
ON/OFF

STS-KB5_5P

R329
100K_0402_5%

D28

D21

3
@SM05_SOT23

<33> ON/OFF

ON/OFF

ON/OFFBTN#

ON/OFFBTN# <29>

1
2

+3VALW

51_ON# <35>

DAN202U_SC70

<29> LID_SW#

LID_SW#

SW2

<29> EC_ON

22K
1 R334
2 2
0_0402_5% 22K

D22
RLZ20A_LL34
C421
2 0.01U_0402_16V7K

1
3
TVS3
HORNG CHIH
@SF10402ML080C

2
DTC124EK_SOT23

D26
17-21/GVC-AMPB/3T_GRN

Q44

4.7K_0402

2 2

150_0402_5%

R330
R421

GREEN

+5VS

MUTE#

<33> DLINE_OUT_R
<33> DLINE_OUT_L

+5VS

MUTE#
EC_MUTE_IN#
VOL_UP#
VOL_DW#

<30> KSIN13
<30> KSIN11
<30> KSIN9

TP & LED BD.

FUN. BUTTON BD.

KSI[0..7]

<29> KSI[0..7]

BT_WAKE_UP <29>

KSO[0..10]

<29> KSO[0..10]

2
G
@2N7002
Q43

WHEN R=0,Vbe=1.35V
WHEN R=33K,Vbe=0.8V

Title

Compal Electronics, Inc.


MDC/BT/KBD/ON_OFF/LID

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003

Rev
1.0

LA-1701

Sheet

28

of

49

R148

+3VALW

<15,21,22,31> SIRQ
<16,31> LPC_DRQ#0
<16,22,31> LPC_FRAME#
<16,22,31> LPC_AD0
<16,22,31> LPC_AD1
<16,22,31> LPC_AD2
<16,22,31> LPC_AD3
EC_RST# <12> CLK_PCI_LPC

1 R443
2
@0_0402_5%

CLK_PCI_LPC

7
8
9
15
14
13
10
18
19
22
23

SCI#

31

GATEA20
RC#
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

CLK_PCI_LPC

71
72
73
74
77
78
79
80

R142
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10

10_0402_5%

KBA[0..19]

C153
10P_0402_50V8K

KBA[0..19] <30>

EC_TINIT#
EC_TCK
EC_TDO
EC_TDI
EC_TMS

RP6

10
9
8
7
6

KBD_DATA
KBD_CLK
TP_DATA
TP_CLK

1
2
3
4
5

+5V

<33> KBD_CLK
<33> KBD_DATA
<33> PS2_CLK
<33> PS2_DATA
<28> TP_CLK
<28> TP_DATA
<28> LID_SW#
<28> BT_WAKE_UP

10K_10P8R_1206_5%
SD307100207
+3VALW

RP10

8
7
6
5
10K_8P4R_0804_5%
SD309100200

2 R94
20M_0603_5%
2
1
2
1 R93
120K_0402_5%
1
1
32.768KHz_12.5P_CM155
C119
10P_0402_50V8K
2
2
1

KBD_CLK
KBD_DATA
PS2_CLK
PS2_DATA
TP_CLK
TP_DATA
LID_SW#
BT_WAKE_UP

105
106
107
108
109
110
111
114
115
116
117
118
119

CRY1

158

CRY2

160

X1

C118
10P_0402_50V8K
+5VALW
RP15
EC_SMD_2
EC_SMC_2
EC_SMD_1
EC_SMC_1

1
2
3
4

8
7
6
5
10K_8P4R_0804_5%

+3VALW

1
R67

EC_SMI#
MSEN#
CONA

FSEL#

R96
4

62
63
69
70
75
76
148
149
155
156
3
4
27
28

<34,38> SYSON
<23,34,38> SUSP#
<34,39,41> VR_ON
<25,28,31> Wireless_OFF#
<16,21> PM_RSMRST#
<13> ENABLT#
<4> PROCHOT#
<13> BKOFF#
<30> FSEL#

KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7

161

95

IOPB0/URXD
IOPB1/UTXD
IOPB2/USCLK
IOPB3/SCL1
IOPB4/SDA1
IOPB7/RING/PFAIL/RESET2

Key matrix scan


PORTB

KBSOUT0
KBSOUT1
KBSOUT2
KBSOUT3
KBSOUT4
KBSOUT5
KBSOUT6
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12
KBSOUT13
KBSOUT14
KBSOUT15

IOPC0
IOPC1/SCL2
IOPC2/SDA2
IOPC3/TA1
IOPC4/TB1/EXWINT22
IOPC5/TA2
IOPC6/TB2/EXWINT23
IOPC7/CLKOUT

PORTC

TINT#
TCK
TDO
TDI
TMS

PORTD-1

IOPD0/RI1/EXWINT20
IOPD1/RI2/EXWINT21
IOPD2/EXWINT24/RESET2

PORTE

IOPE4/SWIN
IOPE5/EXWINT40
IOPE6/LPCPD/EXWIN45
IOPE7/CLKRUN/EXWINT46

JTAG debug port

PSCLK1/IOPF0
PSDAT1/IOPF1
PSCLK2/IOPF2
PSDAT2/IOPF3
PSCLK3/IOPF4
PSDAT3/IOPF5
PSCLK4/IOPF6
PSDAT4/IOPF7

PORTH
PS2 interface

10K_0402_5%

173
174
47

IOPM0/D8
IOPM1/D9
IOPM2/D10
IOPM3/D11
IOPM4/D12
IOPM5/D13
IOPM6/D14
IOPM7/D15

PORTK
PORTM

32
33
36
37
38
39
40
43

INVT_PWM <13>
BEEP# <23>
EN_WOL# <19>
ACOFF <36>
PM_BATLOW# <16>
EC_ON <28>
EC_LID_OUT# <16>
EC_THRM# <16>

168
169
170
171
172
175
176
1

DEV_ID0
DEV_ID1
DEV_ID2
EC_SMC_1
EC_SMD_1

EC_SMC_2
EC_SMD_2

PCI_PME#

ADP_I <36>

ENV1

TRIS

OBD

DEV

PROG

EC_SMC_1 <30,33,42>
EC_SMD_1 <30,33,42>
B_PCIRST# <15,18>

ON/OFFBTN# <28>
SLP_S5# <16>
RING# <30>
PM_CLKRUN# <16,19,21,22,25>

SELIO#

152

SELIO#

IOPD4
IOPD5
IOPD6
IOPD7

41
42
54
55
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15

113
112
104
103
48

KBA16
KBA17
KBA18
KBA19

(ENV1)

KBA2

(BADDR0)

KBA3

(BADDR1)

R74
1
2
@10K_0402_5%
R73
1
2
10K_0402_5%

KBA5

(SHBM)

CONA

1
R71
1
R97

2
10K_0402_5%

2
20K_0402_5%
2

+3VALW

R62
100K_0402_5%

<19,21,25> PCM_PME#
<19,21,25> MINI_PME#
<19,21,25> ONBD_LAN_PME#
<19,21,25> USB20_PME#
PCI_PME#

+3VALW

RP12
DEV_ID2
DEV_ID1
DEV_ID0

1
2
3
4

8
7
6
5

10K_8P4R_0804_5%
FREAD# <30>
FWR# <30>

EC DEBUG port

SELIO# <30>

JP14

NUMLED# <30>
CAPSLED# <30>

143
142
135
134
130
129
121
120

R75
2
10K_0402_5%

KBA1

PWRBTN_OUT# <16>
EC_SMC_2 <4>
EC_SMD_2 <4>
FANSPEED1 <4>
AIR_ACIN <36>
EC_MUTE# <24,28>

2
44
24
25

IOPJ0/RD
IOPJ1/WR0

SHBM=1: Enable shared memory with host BIOS


TRIS=1: While in IRE and OBD, float all the
signals for clip-on ISE use
+3VALW

ACIN <16,33,35,37>
SLP_S4# <16>
SLP_S3# <16,33>

FREAD#
FWR#

IOPL0/A16
IOPL1/A17
IOPL2/A18
IOPL3/A19
IOPL4/WR1#

R86
2
10K_0402_5%

26
29
30

150
151

PORTL

SEL0#
SEL1#
CLK

DAC_BRIG <13>
EN_FAN1 <4>
IREF <36>

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

IOPK0/A8
IOPK1/A9
IOPK2/A10
IOPK3/A11
IOPK4/A12
IOPK5/A13_BE0
IOPK6/A14_BE1
IOPK7/A15_CBRD

1
1

99
100
101
102

153
154
162
163
164
165

BATT_OVP <36>

ENV0
IRE

C112
0.22U_0603_10V7K

138
139
140
141
144
145
146
147

PORTJ-2

ECAGND
0.01U_0402_16V7K

IOPI0/D0
IOPI1/D1
IOPI2/D2
IOPI3/D3
IOPI4/D4
IOPI5/D5
IOPI6/D6
IOPI7/D7

PORTD-2

LI/NIMH# <42>

IOPH0/A0/ENV0
IOPH1/A1/ENV1
IOPH2/A2/BADDR0
IOPH3/A3/BADDR1
IOPH4/A4/TRIS
IOPH5/A5/SHBM
IOPH6/A6
IOPH7/A7

32KX2

IOPJ2/BST0
IOPJ3/BST1
IOPJ4/BST2
IOPJ5/PFS
IOPJ6/PLI
IOPJ7/BRKL_RSTO

ADP_IR

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7

PORTI

32KX1/32KCLKIN

1
C116

124
125
126
127
128
131
132
133

PORTJ-1

R99

LID_SW#
2
20K_0402_5%
MSEN#
2
20K_0402_5%

<16> EC_SMI#
<13,14,33> MSEN#
<33> CONA
<16> EC_RIOUT#
<21> PCM_SUSP#
<12,16> SLP_S1#

IOPA0/PWM0
IOPA1/PWM1
IOPA2/PWM2
IOPA3/PWM3
IOPA4/PWM4
IOPA5/PWM5
IOPA6/PWM6
IOPA7/PWM7

PWM
or PORTA

81
82
83
84
87
88
89
90
93
94

1
2
3
4
5
6
7
8
9
10

1
2
3
4
5
6
7
8
9
10

+5VALW

EC_TINIT#
EC_TCK
EC_TDO
EC_TDI
EC_TMS
DEV_ID0
DEV_ID1
DEV_ID2

@96212-1011S

FSTCHG <36>

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10

ADB[0..7] <30>

49
50
51
52
53
56
57
58
59
60
61
64
65
66
67
68

GA20/IOPB5
KBRST/IOPB6

AGND

ADB[0..7]

1
2
3
4

DA0
DA1
DA2
DA3

DA output

IOPD3/ECSCI#

11
12
20
21
85
86
91
92
97
98

FSEL#
SELIO#
FREAD#
EC_SMI#

AD Input

96

<15> RC#

5
6

KSI[0..7]
KSO[0..10]

<28> KSI[0..7]
<28> KSO[0..10]

PS2_DATA
PS2_CLK

Host interface

<16> SCI#

C128
1U_0603_10V6K

I/O Address
BADDR1-0
Index
Data
2E
2F
0 0
0 1
4E
4F
1 0
(HCFGBAH, HCFGBAL) (HCFGBAH, HCFGBAL)+1
1 1
Reserved

BATT_TEMP <42>

AD0
AD1
AD2
AD3
IOPE0AD4
IOPE1/AD5
IOPE2/AD6
IOPE3/AD7
DP/AD8
DN/AD9

JOPEN

<15> GATEA20

+5V

SERIRQ
LDRQ#
LFRAME#
LAD0
LAD1
LAD2
LAD3
LCLK
RESET1#
SMI#
PWUREQ#

RTCVREF

VBAT

J1
10K_0402_5%

R146
10K_0402_5%

R145
10K_0402_5%

C146
U15
0.1U_0402_16V7K

+3VS

AVCC

L8
1
2
+3VALW
EC_AVCC
1
MURATA BLM11A20PT_0603 2
C86
C91
0.1U_0402_16V7K
1000P_0402_50V7K
L7
1
2 1 ECAGND 2
MURATA BLM11A20PT_0603

1
C148
4.7U_0805_6.3V6K

34
45
123
136
157
166

C109
0.01U_0402_16V7K

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6

C132

2
2
2
0.1U_0402_16V7K

2
16

C137

EC_AVCC

+3VALW
+3VS

VDD

C147
4.7U_0805_6.3V6K

0.1U_0402_16V7K
1
1

GND1
GND2
GND3
GND4
GND5
GND6
GND7

17
35
46
122
159
167
137

+3VALW

ECAGND

PC87591L-VPCN01 A2_LQFP176

C572
@1U_0603_10V6K
Title

Compal Electronics, Inc.


EC PC87591L

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
LA-1701
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003
A

Rev
1.0
Sheet
E

29

of

49

INPUT

KBA[0..19]
ADB[0..7]

<29> KBA[0..19]
<29> ADB[0..7]

OUTPUT

+3VALW

8
7
6
5

C120
1
2

RP14
100K_8P4R_0804_5%
SD309100300

SELIO#

20
1
2

11
1

O
B

SN74LVC32APWLE_TSSOP14

LARST#

KBA2
SELIO#

U16A

3
4
7
8
13
14
17
18

D0
D1
D2
D3
D4
D5
D6
D7

VCC

SN74LVC244APWLE_TSSOP20

14

0.1U_0402_16V7K

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

CP
MR

GND

+3VALW
C133
2
1

20
10

U17

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

2
5
6
9
12
15
16
19

FULL_LED# <28>
POWER1_LED# <28,33>
CHARGING_LED# <28>
BT_ON# <28>
BT_DETACH <28>
TPAD_LED# <28>

SN74HCT273PW_TSSOP20

C143

SN74LVC32APWLE_TSSOP14

<29> SELIO#

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

KBA1

1G
2G

U16B

C135
2
0.1U_0402_16V7K

18
16
14
12
9
7
5
3

10

14

1
19

1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4

<28> TP_ON/OFF#
<28> EC_MUTE_IN#
<28> BT/WL_ON/OFF#
<28> VOL_UP#
<28> VOL_DW#
<28> BT_PRES#

1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4

U11

VCC

2
4
6
8
11
13
15
17

+5VALW

0.1U_0402_16V7K

GND

1
2
3
4

1
2
3
4

RP13
100K_8P4R_0804_5%
SD309100300

8
7
6
5

+3VALW

+5VALW

2
R125
20K_0402_5%

2
1U_0603_10V6K

+3VALW

8
7
6
5

C93
RP7

100K_8P4R_0804_5%
SD309100300

+3VALW

20

18
16
14
12
9
7
5
3

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

+3VALW

1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4

+3VALW

2 C152
0.1U_0402_16V7K

R37
10K_0402_5%
R152
10K_0402_5%

D8

1
2
3
4

D9

1
AT24C16N10SI-2.7_SO8

<25> MODEM_RI#

RB751V_SOD323

R144
1K_0402_5%

R143
1K_0402_5%

<29> RING#

SN74LVC32APWLE_TSSOP14

A0
A1
A2
GND

<29,33,42> EC_SMC_1
<29,33,42> EC_SMD_1

SN74LVC244APWLE_TSSOP20

VCC
WP
SCL
SDA

1
O

10

10

U16C

SELIO#

8
7
6
5

RB751V_SOD323

KBA3

1G
2G

GND

14

1
19

<21> PCM_RI#

U20

1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4

U6

2
4
6
8
11
13
15
17

<28> KSIN8
<28> KSIN9
<28> KSIN10
<28> KSIN11
<28> KSIN12
<28> KSIN13
<28> KSIN14

0.1U_0402_16V7K

VCC

1
2
3
4

100K_8P4R_0804_5%
SD309100300

1
2
3
4

RP8

8
7
6
5

+3VALW

+3VALW

U29

SUS_STAT# <13,16>

2
G

+5VS

13

3
S

1
D

1
2
R422
@100K_0402_5%

+3VALW

EC_FLASH# <16>

Q19
2N7002 1N_SOT23

U16D
SN74LVC32APWLE_TSSOP14

FWR# <29>
GREEN

R11

330_0402_5%

330_0402_5%

GREEN

D6

Q31

B
<29> CAPSLED#

A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS

VCC
WE*
A17
A14
A13
A8
A9
A11
OE*
A10
CE*
DQ7
DQ6
DQ5
DQ4
DQ3

8
7
6
5
4
3
2
1
32
31
30
29
28
27
26
25

FWE#
KBA17
KBA14
KBA13
KBA8
KBA9
KBA11
FREAD#
KBA10
FSEL#
ADB7
ADB6
ADB5
ADB4
ADB3

KBA16
KBA15
KBA14
KBA13
KBA12
KBA11
KBA9
KBA8
FWE#
RESET#
KBA18
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

@SUYIN-80065A-040G2T
39F040_TSOP

1
Q33
E

PDTA114EK_SOT23
B

10K

<29> NUMLED#
10K

JP31
+3VALW
U35

10K

23
39

10K

KBA17
KBA19
KBA10
ADB7
ADB6
ADB5
ADB4

GND0
GND1

D7
17-21/GVC-AMPB/3T_GRN

CE#
OE#
WE#

PDTA114EK_SOT23

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

R10

17-21/GVC-AMPB/3T_GRN

@SST39VF080-70_TSOP40

KBA18
KBA16
KBA15
KBA12
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1
KBA0
ADB0
ADB1
ADB2

+5VS

2
FWE# 11

12

R116
20K_0402_5%

2 2

RESET#

2 2

10
11
12
29
38

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

C124
0.1U_0402_16V4Z

RP#
NC
READY/BUSY#
NC0
NC1

25
26
27
28
32
33
34
35

+3VALW

14

D0
D1
D2
D3
D4
D5
D6
D7

31
30

22
24
9

VCC0
VCC1

FSEL#
FREAD#
FWE#

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19

21
20
19
18
17
16
15
14
8
7
36
6
5
4
3
2
1
40
13
37

<29> FSEL#
<29> FREAD#

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

RI#1
2
RI#1 <22,33>
G
Q11
@2N7002 1N_SOT23

TVS5
@SF10402ML080C_0402

TVS4
@SF10402ML080C_0402

+3VALW
ADB3
ADB2
ADB1
ADB0
FREAD#
FSEL#
KBA0

Compal Electronics, Inc.


Title

BIOS & EC I/O Port


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003

Rev
1.0

LA-1701

Sheet

30

of

49

+3VS
D

R405
WR_PT
1
SDPWCTL#

C557

36
35
34
33
32
31
30
29
28
27
26
25

C556

U42
SD@10U_1206_6.3V6M

SDPWCTL#
SDLED
SCC4
SCC8
MSLED
MSPWCTL#
VSS
MSCLK
MS1
MS2
MS3
MS4

SD@0.1U_0402_10V6K

SD@1K_0402_5%
SDLED
2

JP17
R406
SD_CLK
1
2
SD@FBM-11-100505-600T_0402
+3VS

<16,22,29> LPC_AD[0..3]

LPC_AD[0..3]

SD1
SD2
SD3
SD4
SD5
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

<15,21,22,29> SIRQ

37
38
39
40
41
42
43
44
45
46
47
48

SDCLK
SD1
SD2
VDD3V
SD3
SD4
SD5
LAD3
LAD2
LAD1
LAD0
SERIRQ

W83L518D (LPC)

MS5
XIN
XOUT
SCRST#
SCIO
SCCLK
SCPSNT
SCPWCTL#
SCLED
VDD
SCBLED
SCBPWCTL#

24
23
22
21
20
19
18
17
16
15
14
13

CLK_SD_48M

CLK_SD_48M <12>

SDLED
R407
1
2
SD@8.2K_0402_5%

+5VS
C298
+5VS

MMC_DET#
C558
SD@0.1U_0402_10V6K

SD@0.1U_0402_10V6K

1
3
5
7
9
11
13
15

MMC_DET#
SD2
SD4
SD_CLK

2
4
6
8
10
12
14
16

+3VS

SD@SD_16PIN

C300
SD@0.1U_0402_10V6K

C559
SD@10U_1206_6.3V6M
C

SD@W83L518D (LPC)

R408

CLK_PCI_SD
R147 2
1
0_0402_5%

<12> CLK_PCI_SD
<16,29> LPC_DRQ#0
<16,22,29> LPC_FRAME#
<7,13,15,19,20,21,22,25> PCIRST#

CLK_SD_48M

CLK_PCI_SD

1
2
3
4
5
6
7
8
9
10
11
12

PCICLK
LPC_DRQ#
LFRAME#
lESET#
PME#
VSS
SCBC4
SCBC8
SCBRST#
SCBIO
SCBCLK
SCBPSNT

WR_PT
SD1
SD3
SD5
SDPWCTL#

R409

@10_0402

10_0402_5%

1
1

C561

C560

10P_0402_50V8K

@10PF_0402

R424

1
+3VALW

+3VAUX_BT

2 0_0603_5%
2 0_0603_5%

C568

1
C569
4.7U_0805_6.3V6K
0.1U_0402_16V7K
2
2
1

C570

1U_0603_10V6K

USB20P5+ <16,28>
USB20P5- <16,28>

C571

0.01U_0402_16V7K
R442

CH_DATA <25>
CH_CLK <25>

<25> Wireless_OFF

BT_CONN
<25,28,29> Wireless_OFF#

R425 1
R426 1

1
2
3
4
5
6
7
8

1
2
3
4
5
6
7
8

+3VAUX_BT

1
JP32

@0_0805_5%
Q53
SI2301DS_SOT23

+5VALW

100K_0402_5%
Q54
2N7002 1N_SOT23

2
G

Compal Electronics, Inc.


Title

SD CARD/BT Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003

Rev
1.0

LA-1701

Sheet
1

31

of

49

+5VS
+3VALW

+3VALW

R59

14

U4A

100K_0402_5%
SN74LVC14APWLE_TSSOP14

U4B

O
G

O
G

D18

RB751V_SOD323
SN74LVC14APWLE_TSSOP14

C79
1U_0603_10V6K

+3VS

<12,16,41> VGATE

R61

14

@10K_0402_5%

+3VALW

R317
10K_0402_5%

+3VS

PM_POK <16>

U4C

14

R68
47K_0402_5%

R60
330K_0402_5%

O
G

1
C78
0.47U_0603_10V7K

Q39
2N7002 1N_SOT23

2
G

SN74LVC14APWLE_TSSOP14

Title

Compal Electronics, Inc.


RESET CKT

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003

Rev
1.0

LA-1701

Sheet

32

of

49

SPR CONN. 154PIN


JP26
1

<22,26> LPTSLCTIN#
<22,26> LPTINIT#
<22,26> LPTERR#
<22,26> LPTAFD#
<22,26> LPTSLCT
<22,26> LPTPE
<22,26> LPTBUSY
<22,26> LPTACK#
<22,26> LPTSTB#
<22,26> LPD7
<22,26> LPD6
<22,26> LPD5
<22,26> LPD4
<22,26> LPD3
<22,26> LPD2
<22,26> LPD1
<22,26> LPD0

USB20P2R437
USB20P2+
R438
USB20P3R439
USB20P3+
R440

<16> USB20P2<16> USB20P2+


<16> USB20P3<16> USB20P3+

<23> SPDIFO

<23> DLINE_IN_L
<23> DLINE_IN_R
<28> DLINE_OUT_L
<28> DLINE_OUT_R

<20> XTPB1-

R277 1

<20> XTPB1+

R278 1

<20> XTPA1-

R279 1

<20> XTPA1+

R280 1
<19> LAN_LED0#
<29> CONA

+5VS

R22
100K_0402_5%

SPR@2200P_0402_25V7K
<19> RJ45_RXX+
<19> RJ45_RXX-

R18
100K_0402_5%

+12V

P2

G2

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77

G2
R441

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77

ON/OFF
SLP_S3#
POWER1_LED
KBD_DATA
KBD_CLK
PS2_DATA
PS2_CLK
EC_SMD_1
EC_SMC_1
COMPS
CRMA
LUMA

ON/OFF <28>
SLP_S3# <16,29>
+3V

SPR@1K_0402_5%

KBD_DATA <29>
KBD_CLK <29>
PS2_DATA <29>
PS2_CLK <29>
EC_SMD_1 <29,30,42>
EC_SMC_1 <29,30,42>

POWER1_LED

Q52
2
POWER1_LED# <28,30>
G
SPR@2N7002 1N_SOT23

COMPS <13,14>
CRMA <13,14>
LUMA <13,14>

D_VSYNC_R
1
D_HSYNC_R R435 1
D_DDCCLK R436
D_DDCDATA
MSEN
BLUE_S 1
GREEN_S 1 R48
RED_S
1 R47
R46

D_VSYNC
2
2 SPR@0_0402_5% D_HSYNC
SPR@0_0402_5%

D_VSYNC <14>
D_HSYNC <14>
D_DDCCLK <14>
D_DDCDATA <14>
MSEN# <13,14,29>

2
2 SPR@0_0402_5%
2 SPR@0_0402_5%
SPR@0_0402_5%

BLUE <13,14>
GREEN <13,14>
RED <13,14>

Q14
SPR@2N7002 1N_SOT23

2
G

ON/OFF

<16,29,35,37> ACIN

SPR@1000P_0402_50V7K

<22> CTS#1
<22> RTS#1
<22> DSR#1
<22,30> RI#1
<22> DCD#1
<22> RXD1
<22> TXD1
<22> DTR#1

+5VS

A1
1SPR@1K_0402_5% A2
+5V
A3
+3V
R27 2
SPR@0_0402_5%
A4
1
ACIN
A5
A6
CTS#1
A7
RTS#1
A8
DSR#1
A9
RI#1
A10
DCD#1
A11
RXD1
A12
TXD1
A13
DTR#1
A14
A15
LPTSLCTIN#
A16
LPTINIT#
A17
LPTERR#
A18
LPTAFD#
A19
LPTSLCT
A20
LPTPE
A21
LPTBUSY
A22
LPTACK#
A23
LPTSTB#
A24
LPD7
A25
LPD6
A26
LPD5
A27
LPD4
A28
LPD3
A29
LPD2
A30
LPD1
A31
LPD0
A32
A33
A34
A35
A36
USB20P2-_R
1
2
A37
SPR@0_0402_5%
A38
USB20P2+_R
1
2
A39
SPR@0_0402_5%
A40
USB20P3-_R
A41
1
2
SPR@0_0402_5%
A42
USB20P3+_R
1
2
A43
SPR@0_0402_5%
A44
A45
A46
A47
DOCK_HPS#
A48
A49
SPDIFO
A50
A51
A52
A53
DLINE_IN_L
A54
DLINE_IN_R
A55
A56
DLINE_OUT_L
A57
DLINE_OUT_R
A58
A59
A60
XTPB1-_R
2 SPR@0_0402_5%
A61
A62
XTPB1+_R
2 SPR@0_0402_5%
A63
A64
XTPA1-_R
2 SPR@0_0402_5%
A65
A66
XTPA1+_R
SPR@0_0402_5%
2
A67
A68
LAN_LED0#
A69
CONA
A70
A71
2
1
2
A72
A73
R29 SPR@75_0402_1%
C30
A74
RJ45_RXX+
A75
RJ45_RXXA76
A77
R28

D29
SM05_SOT23

C38

P2

+5VALW

G1

SPR@1000P_0402_50V7K

DOCKVIN

G1

P1

P1

C41

+5V

L5
SPR@KC FBM-L18-453215-900LMA90T_1812
2
1
VIN
DOCKVIN

R45
1

L4
1
2
SPR@0_0603_5%

SPR@1K_0402_5%
2
+5V

C32

LAN_LED1# <19>

2
R42

1
2
1
SPR@75_0402_1%
C51 SPR@2200P_0402_25V7K
RJ45_TXX+
RJ45_TXX+ <19>
RJ45_TXXRJ45_TXX- <19>

SPR@0.1U_0402_16V4Z

GND

GNDA

GND
GND
GND
GND
GND
GND

Q10
2N7002 1N_SOT23

2
G

1
2
3
4
5
6

DOCK_HPS#

DOCK_HPS <24>

SPR@SPR-154PIN

Compal Electronics, Inc.


Title

SPR Connector
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003

Rev
1.0

LA-1701

Sheet
E

33

of

49

+12VALW TO +12V Transfer

+3VALW to +3VS Transfer

+12VALW
+3V

+3VALW

C130

0.1U_0402_10V6K
2
10U_1206_6.3V6M

5VON

D
S 1
D
S 2
3
D
S
4
D
G
C440
SI4800DY_SO8
2 10U_1206_6.3V6M

R395
100K_0402_5%

C125

100K_0402_5%

1
1
C407

R382
100K_0402_5%

C480
0.1U_0402_16V7K

1
2

C412
10U_1206_6.3V6M

C476
1U_0805_16V7K

2
3

1
R24
1

8
7
6
5

D
S 1
D
S 2
3
D
S
C134
4
D
G
SI4800DY_SO8
2 10U_1206_6.3V6M

RUNON

Q47
NDS352P 1P_SOT23

R380
51K_0402_5%

+12VALW

8
7
6
5

+12VALW

+12VALW

+3VS
U36

1 2

U10

+3VALW

+3VALW to +3V Transfer

+12V

C506
0.01U_0402_16V7K

5VON

Q49
2N7002 1N_SOT23

+5VALW

+5VALW

1
2
3
4

SI4800DY_SO8

2
2

10U_1206_6.3V6M

8
7
6
5

1
1
C307
10U_1206_6.3V6M
C303
0.1U_0402_16V7K
2

D
D
D
D

+12VALW

1
2
3
4

S
S
S
G

C496
SI4800DY_SO8
2 10U_1206_6.3V6M

5VON

1
C547
10U_1206_6.3V6M
C548
0.1U_0402_16V7K
2

R379
100K_0402_5%

1
C491

2
10U_1206_6.3V6M

C292
C485
10U_1206_6.3V6M

1
C308

R284
@475_0402_1%

C309

D
Q48
2N7002 1N_SOT23

2
G
3

1
C469
1U_0805_16V7K

C291
10U_1206_10V4Z

RUNON

D
S 1
D
S 2
D
S 3
D
G 4
SI4800DY_SO8
1
C290

+12VS

0.1U_0402_16V4Z

U30

8
7
6
5

10U_1206_10V4Z

C484

D
S 1
D
S 2
D
S 3
D
G 4
SI4800DY_SO8

R386
51K_0402_5%

+1.5VS

Q46
NDS352P 1P_SOT23

+1.5VALW

+2.5VS

8
7
6
5

+1.5VALW to +1.5VS Transfer

U39

C475
1U_0805_16V7K

2
0.1U_0402_16V7K

+2.5V

1
C479

RUNON

+2.5V to +2.5VS Transfer

+12VALW

S
S
S
G

D
D
D
D

C332

+12VALW TO +12VS Transfer

+5VS
U41

1 2

8
7
6
5

C470
1U_0805_16V7K

+5VALW to +5VS Transfer

+5V
U32

+5VALW to +5V Transfer

2
G
3

1
2
G

1
Q50
2N7002 1N_SOT23

SUSP

2
G

C123
0.01U_0402_16V7K

Q9
2N7002 1N_SOT23

0.1U_0402_16V7K

SYSON#

22U_1206_10V4Z

RUNON
10U_1206_10V4Z

SUSP
2
G
Q35
@2N7002_SOT23

RUNON

0.1U_0402_16V7K

+5VALW

R87
100K_0402_5%

Discharge circuit
+CPU_CORE

+5VALW

1
D

SYSON

<29,38> SYSON

Q17
2N7002 1N_SOT23

2
G

Q40
2N7002 1N_SOT23

2
G
Q18
2N7002 1N_SOT23

2
G

<29,39,41> VR_ON

2N7002 1N_SOT23

SYSON#

+5VALW

1 2

1
1

Q25

2
G

VR_ON#

<39> VR_ON#
D

Q38
SYSON#
2N7002 1N_SOT23

2
G

1 2

R313
470_0402_5%

1
1 2
Q42
SYSON#
2N7002 1N_SOT23

2
G
3

R187
470_0805_5%

Q45
SYSON#
2N7002 1N_SOT23
S

R113
100K_0402_5%

R295
470_0402_5%

2
G

R318
470_0402_5%

1 2

1 2
Q41
SYSON#
2N7002 1N_SOT23

2
G
3

R351
470_0402_5%

+12V

+5V

1
1 2

R311
470_0402_5%

VR_ON#

+3V

+2.5V

<40> SYSON#
+VCCP

R183
100K_0402_5%
+1.2VS

+12VS

R194
470_0402_5%

SUSP

<40> SUSP

R286
470_0805_5%

R283
470_0402_5%

Q27
SUSP 2
2N7002 1N_SOT23
G

1 2

Q12
SUSP 2
2N7002 1N_SOT23
G

1 2

Q28
SUSP 2
2N7002 1N_SOT23
G

SUSP 2
G

1 2

1 2

2N7002 1N_SOT23

1 2

Q13

R31
470_0402_5%

Q37
SUSP 2
2N7002 1N_SOT23
G

+5VS

Q26
2N7002 1N_SOT23

2
G

<23,29,38> SUSP#
D

Q30
SUSP 2
2N7002 1N_SOT23
G

+3VS

R195
470_0402_5%

SUSP 2
G

R38
470_0402_5%

1 2

1 2

R238
470_0402_5%

+2.5VS

+1.8VS

+1.25VS

Q34
2N7002 1N_SOT23

Compal Electronics, Inc.


Title

DC/DC Circuits
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003

Rev
1.0

LA-1701

Sheet
E

34

of

49

Detector

VIN
PL15
FBM-L18-453215-900LMA90T_1812

PR166
1M_0603_1%
1
2

LM393M_SO8

1
PR175
10K_0603_5%

PACIN

PACIN <36>

1
O
PU13A

PR168
8.2K_0805_5%

1
2
8

3.2V

ACIN <16,29,33,37>

PZD2
RLZ4.3B

PR173
10K_0603_5%

PR169
10K_0603_5%
1
2

VIN

PR170
22K_0603_1%
1
2

PR172
365K_0603_1%
2
1

RLS4148

PR174
200_1206_5%
1
2

PC140
68P_0603_50V8J

VS

PD23

VIN
PC139
0.01U_0603_50V7K

VIN
PR167
453K_0603_1%
2
1

PR171
200_1206_5%
1
2

VS

PZD1
@RLZ24B

ADPGND

PC136
1000P_0603_50V7K

13.217
11.566

PC141
0.1U_0603_16V7K

4 2
SINGATRON_2DC_S736I201

VIN detector
14.229 13.717
12.520 12.110

PR165
@10_1206_5%

PC137
100P_0603_50V8J
2
1

1
4

ADPIN

3 1

PC138
1000P_0603_50V7K
2
1

PD22
EC10QS04
PC135
100P_0603_50V8J

PCN2

VL

5V

PD34
RLS4148

VMB

PR223
2
1.5K_1206_5%

PR176
2
1.5K_1206_5%

PR178
2
1.5K_1206_5%

PR181
2
1.5K_1206_5%

+5VP

VIN

B+

PZD4
RLZ5.1B

PC143
0.1U_0805_25V7K

VS1

PD26
RLS4148

PR183
10K_0603_5%
1
2

PR185
806K_0603_1%

PR184
2M_0603_5%
2
1

VL

ACIN
PC148
1U_0805_25V4Z

Precharge detector
12.432 11.717 11.061
10.188
9.702
9.051

VL

5V

PC145
1000P_0603_50V7K

PR189
1.5M_0603_1%

PR188
10K_0603_5%

PR187
2M_0603_5%

PC149
4.7U_1206_25VFZ

PZD5
RLZ16B

PQ37
2N7002_SOT23

PR192
47K_0603_5%

2
G

1000P_0603_50V7K
2
1

2
3

511_0603_1%

P
1

<36> ACON

RB715F_SOT323

PR290
RTCVREF 1

<4,37,42> MAINPWON

PR186
200_0805_5%

PU14
S-81233SGUP

RTCVREF

PU13B
LM393M_SO8

PC146

3.3V
3

PC147
0.1U_0603_16V7K
2
1

PD27
CHGRTCP

5V

PR182
22K_0603_5%

PC144
0.1U_0603_16V7K

<28> 51_ON#

RLZ4.3B

PC142
0.22U_1206_25V7K

PR179
100K_0603_5%
2
1

1
2
PR180
150K_0603_5%

PZD3
CHGRTCP 2

PR177
10K_0603_5%

PQ36
TP0610T_SOT23
3
1

PACIN

+3VALW

+1.2VSP

PJP5
3MM
4

+5VALWP

Precharge detector
9.507 9.030 8.589
7.263 7.015 6.579

+1.2VS

100K

+5VALW

+1.5VALWP

+5VALWP

100K

PJP6
3MM

PQ38
DTC115EUA

+3VALWP

PJP4
3MM

PR259
@66.5K_0603_1%

BAT ONLY
PJP3
3MM

+1.5VALW

+1.25VS

PJP7
PJP8
3MM

2MM
+12VALWP

2
+12VALW

+1.25VSP

PJP9
3MM

1
+2.5VP

PJP15
2MM
+1.8VSP

+1.8VS

Compal Electronics, Inc.


Title

PJP14

+2.5V

Detector

2MM
+1.05VSP

+VCCP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS
CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003

Rev

1.0

LA-1701

Sheet
E

35

of

49

Charger

PD39

Iadp=0~3.0A
B++
P3

2
3
2
1

8
7
6
5

2
PR77
47K_0603_5%

PQ19
SI4835DY_SO8
PR79
0_0603_5%

1
2
3

PC222
0.01U_0603_50V7K
1
2

PQ18
SI4835DY_SO8

PC65
2200P_0603_50V7K

PC64
0.1U_0805_25V7K
2
1

PC63
4.7U_1210_25V6K
2
1

PR76
200K_0402_5%

8
7
6
5

1
2
3

PR75
0.02_2512_1%
2
1
PC225
47U_25V_M

PQ17
SI4835DY_SO8

PL7
FBM-L18-453215-900LMA90T_1812

PC224
47U_25V_M

PD40
B540C
VIN

B540C

B+

PC62
4.7U_1210_25V6K
2
1

P2

VIN

PR80
10K_0603_5%

+INC2

24

-INC2

PU5

ACOFF#

<29> ADP_I

VREF

VH

FB1

VCC

PC78
0.01U_0402_16V7K

17

+INE1

-INE3

16

15

OUTD

CTL

-INC1

+INC1

CC=0(0.5A) ~ 2.7A
CV=16.8V (8 CELLS)

PC73
2 0.1U_0805_25V7K
PL8
15U_SPC-1204P-150_4A_20%
1
2

1
2
PR87
66.5K_0603_1%
PC75
1
2

47K_0603_5%

11

PQ20
DTC115EUA

LXCHRG

18

RT

FB3

5
6
7
8

PC70
0.1U_0603_16V7K
1
2

19

-INE1

OUTC1

2
ACOFF <29>

100K

20

PR91

10

100K

2
PC67
0.1U_0805_25V7K

PD14
EC31QS04

1500P_0603_50V7K
ACON

14

PR88
0.02_2512_1%
1
2

BATT+
BATT+

PD38
@EC31QS04

PR90
2
1
10K_0603_5%

OUT

21

PC66
2200P_0603_50V7K
2

PC77
4.7U_1210_25V6K
2
1

2
7
PR86
1K_0603_5%
8
9

PR92
66.5K_0603_1%
2
1

IREF=1.164*Icharge
IREF=0.580~3.132V

PC72
2200P_0603_50V7K

1
2
PR89
127K_0603_1%

<29> IREF

FB2

PC76
4.7U_1210_25V6K
2
1

-INE2 VCC(o)

CS

22

PC74
4.7U_1210_25V6K
2
1

5.0V

CS

PR85
2
1
2
10K_0603_5%
PC69
4700P_0603_50V7K

+INE2

23

GND

PR83
31.6K_0603_1%
2
1

ACON

<35> ACON

OUTC2

1
12

2
PR93
@10K_0603_5%

13
PC79

MB3887_SSOP24

@10P_0603_50V8F

PQ21
2N7002_SOT23

PC71
0.1U_0603_16V7K

2
G
3

<35> PACIN

PR82
3K_0402_5%
1
2

PR84
10K_0603_1%
2
1

PC68
0.01U_0402_16V7K
2
1

1.202V

PR78
150K_0402_5%

ACOFF#

PR81
100K_0603_5%

PD13
1SS355_SOD323
2

2
BATT+

4.2V

PR94
47.5K_0603_0.1%

PR95
143K_0603_0.1%

<29> AIR_ACIN

PC80
@22P_0603_50V8J

+3VALWP

2
2

PQ23
DTC115EUA

VIN

100K
<29> FSTCHG

100K

PR278
(17V+-5%)
57.6K_0603_1%

PQ24
DTC115EUA
100K

PR286
10K_0603_5%

2.5VREF

100K

100K

PQ50
DTC115EKA_SOT23

100K

2
PR277
10K_0603_5%
2
1

PR279
10K_0603_0.1%

2
2

PR217
200K_0603_0.5%

PU16B
LM358A_SO8
PR285
10K_0603_5%
2
1

PZD6
RLZ4.3B
2

1
PU16A
LM358A_SO8

PC162
0.01U_0603_50V7K

1
PR213
1M_0603_0.5%

1
2
P
G

PC161
@0.1U_0603_16V7K
2
1

PR216
2.2K_0603_5%
2
1

<29> BATT_OVP

0
4

PR96
47K_0603_5%

CS

PC158
0.1U_0603_50V4Z

VS

CS

PR209
604K_0603_1%

OVP voltage : LI-MH 8 CELL(4S2P)


BATT+ : 18.0V--> BATT_OVP : 2.0V
(BATT_OVP voltage = 0.1109*BATT+)

Compal Electronics, Inc.


Title

Charger
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003

Rev

LA-1701

0.1
Sheet
E

36

of

49

+3.3V/+5V/+12V
B++

PR54
@10K_1206_5%
2
1

PL5

FBM-L18-453215-900LMA90T_1812
PC33
4.7U_1210_25V6K
2

D1
G1
D1 S1/D2
G2 S1/D2
S2 S1/D2

PR60
2
0_0603_5%

1
2

1
PR64
0.012_2512_1%

PR63
2M_0402_5%

2.5VREF

1
1

1
+

PC58
100P_0402_50V8K

PD12
EC31QS04

PR71
47K_0402_1%

PC57
150U_D2_6.3VM

PR69
0_0402_5%

PC59
150U_D2_6.3VM

+5VALWP

PC55
4.7U_1206_10V7K

DL5

PR70
10.2K_0402_1%
2
1

VL

PC51
47P_0402_50V8J
CSH5

LX5

PR68
@0_0402_5%

1
PR72
10K_0402_1%
1
2

DH51

DH5

PC56
680P_0402_50V7K

+5VP

BST5

RUN/ON3

8
7
6
5

SI4814DY_SO8

21

4
5
18
16
17
19
20
14
13
12
15
9
6
11

GND

28

VL

22
7

12OUT
VDD
BST5
DH5
PU4
LX3
MAX1632_SSOP28 LX5
DL3
DL5
PGND
CSH5
CSH3
CSL5
CSL3
FB5
FB3
SEQ
SKIP#
REF
SHDN#
SYNC
RST#
TIME/ON5

PR67
@300K_0402_5%

1
2
3
10
23

PR65
10K_0402_5%

PC54
100P_0402_50V8K

PD11
EP10QY03

1
2

PR73
10K_0402_1%

MAINPWON <4,35,42>
PC60
@0.047U_0603_16V4Z
PR74
47K_0603_5%
2

+5V Ipeak = 6.66A ~ 10A


VL

DH3

<16,29,33,35> ACIN

CSH3
PR66
3.57K_0603_1%
1
2

BST3

27

V+

PR61
1M_0402_1%
1
2

1
2

PC53
150U_D2_6.3VM

PC52
150U_D2_6.3VM

25

26
24

PR62
0.012_2512_1%

1
1
2

PC46
4.7U_1210_25V6K

1
2

PC45
4.7U_1210_25V6K

1
2

PC44
0.1U_0805_25V7K

1
2

PQ15

1
2
3
4

PC43
2200P_0603_50V7K

2
2

PC48
4.7U_1210_25V6K

PR287
2.7K_1206_5%

PR59
0_0603_5%

PT1
9U_SDT-1204P-9R0-120_4.5A_20%

DH3

PC50
47P_0402_50V8J

PQ51
2N7002_SOT23
ACIN
2
G

PC40
0.1U_0805_25V7K
1
2
B+++

PC47
0.1U_0805_25V7K
2
1

+3.3V Ipeak = 6.66A ~ 10A

+3VALWP

FLYBACK

PC42
0.1U_0603_16V7K

2
1

PC41
4.7U_1206_10V7K

+12VALWP

DL3

PL6
10U_SPC-1204P-100_4.5A_20%

2
2

LX3

PR57
0_0603_5%

PD9
EC11FS2_SOD106

PC34
470P_0805_100V7K
SNB 2

VL
VS

DH31

8
D1
G1
7
D1 S1/D2
6
G2 S1/D2
5
S2 S1/D2
SI4814DY_SO8

PR58
10_1206_5%
1

PQ14

1
2
3
4

BST51

PR55
22_1206_5%

PR56
0_0603_5%
1
2

1
2

PC39
4.7U_1210_25V6K

1
2

PC38
4.7U_1210_25V6K

1
2

PC37
2200P_0603_50V7K

1
2

PC36
0.1U_0805_25V7K

PD10
DAP202U_SOT323

PC35
0.1U_0805_25V7K
BST31
1
2

B+++

PC61
1U_0805_25V4Z

Title

3.3V / 5V / 12V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINSSize
CONFIDENTIAL
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Monday, May 12, 2003

Rev

LA-1701

0.1
Sheet
E

37

of

49

+2.5VP/+1.8VSP
D

PC173
4.7U_1210_25V6K
2
1

B++

PR230
51_1206_5%

+5VALWP

VCC

PR235
1.74K_0603_1%
7
1
2

UGATE1

UGATE2

PU18

PHASE1

PHASE2

ISL6225
ISEN1

ISEN2

1 PR234 2
0_0603_5%

24

8
7
6
5

25
PR236
1.5K_0603_1%
22 1
2

G1
D1
S1/D2 D1
S1/D2 G2
S1/D2 S2

1
2
3
4

LGATE2

1
2

PC179
4.7U_1210_25V6K

1
2

PC178
4.7U_1210_25V6K

PR237
0_0603_5%

PGND1

PGND2

26

9
10
8
15

VOUT1
VSEN1
EN1
PG1

VOUT2
VSEN2
EN2
PG2/REF

20
19
21
16

OCSET2

18

2
2

1
+

1
+

PR238
10.5K_0603_1%

EN1

1
2

PC192
@1000P_0603_50V7K

PR242
10K_0603_1%

PR241
@0_0603_5%

2
1SUSP#
PR288
@0_0603_5%

1
PR248
0_0603_5%

PR246
147K_0603_0.1%

2
<29,34> SYSON

DDR
13

IS6225
PR245
84.5K_0603_1%

PC193
@1000P_0603_50V7K

OCSET1

PR244
@0_0603_5%

PR243
10K_0603_1%

11

GND

2
2

SI4814DY_SO8

27

LGATE1

PR240
0_0603_5%

PC190
0.01U_0603_50V7K

PC189
@150U_D2_6.3VM

EN1

PC227
100U_6.3V

PC177
0.1U_0805_25V7K

1
2

PR232
0_0603_5%
PQ43

PC176
2200P_0603_50V7K

28

23

+1.8VSP

PL19
5UH_SPC_06704-5R0A

PC183
0.1U_0805_25V7K
2
1

PC187
4.7U_0805_6.3V6K
2
1

1 PR233 2
0_0603_5%

8
7
6
5

SI4814DY_SO8

PR239
18.2K_0603_1%

BOOT2

D1
G1
D1 S1/D2
G2 S1/D2
S2 S1/D2

BOOT1

1
2
3
4

17

PC191
0.01U_0603_50V7K

SOFT2

PR231
0_0603_5%

PQ42

PC181
4.7U_0805_6.3V6K

SOFT1

SUSP# <23,29,34>

1
2

PC226
100U_6.3V

PC182
0.1U_0805_25V7K
2
1

PR162
1K_0603_5%
2
1

PL18
4.7U_SPC-1204P4R7_5.7A_20%
2
1
PC186
4.7U_0805_6.3V6K

PC184
150U_D2_6.3VM

+2.5VP

14

PC180
0.01U_0603_50V7K
2
1 12

VIN

PC174
2.2U_0805_10V6K

PR255
2.2_0603_5%

PC175
0.1U_0805_25V7K

PD37
DAP202U_SOT323

PC172
4.7U_1210_25V6K
2
1

PC171
0.1U_0805_25V7K
1
2

PC170
2200P_0603_50V7K
2
1

PL17
HCB4532K-800T90_1812

1
PR247
0_0603_5%

+3VALWP

PR249
@10K_0603_5%

Compal Electronics, Inc.


Title

DDR POWER 2.5V / 1.8V


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS
CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 12, 2003

Rev

1.0

LA-1701

Sheet
1

38

of

49

+1.2VSP/+1.5VALWP/1.05VSP
PL1
HCB4532K-800T90_1812
1
2

CPUB+

PC4
4.7U_1210_25V6K
2
1

PR1
51_1206_5%

+5VALWP
D

28

14

UGATE1

UGATE2

PU1

PHASE1

PHASE2

24

PR6 2
0_0603_5%

8
7
6
5

25

ISL6225

G1
D1
S1/D2 D1
S1/D2 G2
S1/D2 S2

1
2
3
4

1 PR8
2
1.5K_0603_1%

PR9
0_0603_5%

PR10
3.48K_0603_1%

1 EN2
PR20
0_0402_5%

PR14
10K_0603_1%

18
1VR_ON

PC23
@1000P_0603_50V7K

PR13
@0_0603_5%

PR289
@0_0402_5%

PR18
147K_0603_0.1%

PR17
84.5K_0603_1%

+3VALWP

OCSET2

IS6225

OCSET1

20
19
21
16

VOUT2
VSEN2
EN2
PG2/REF

VOUT1
VSEN1
EN1
PG1

26

11

PGND2

DDR

9
10
8
15

PGND1

LGATE2

22
27

13

EN2

PC24
@1000P_0603_50V7K

SI4814DY_SO8

ISEN2

2
2

PR16
@0_0603_5%

PC10
4.7U_1210_25V6K

1
2

PC21
0.01U_0603_50V7K

PR7
2
7
ISEN1
1.74K_0603_1%
2
LGATE1

PR12
0_0603_5%

PR15
10K_0603_1%

PC9
4.7U_1210_25V6K

PR11
6.81K_0603_1%

8
7
6
5

SI4814DY_SO8

PC22
0.01U_0603_50V7K

+1.2VSP

PL3
5UH_SPC_06704-5R0A

PC14
0.1U_0805_25V7K
1
PQ2

D1
G1
D1 S1/D2
G2 S1/D2
S2 S1/D2

GND

BOOT2

1
2
3
4

1 PR5
2
0_0603_5%

BOOT1

1 PR4
2
0_0603_5%

PQ1
PC17
4.7U_0805_6.3V6K

PC15
150U_D2_6.3VM
2
1

PC16
150U_D2_6.3VM

PR3
0_0603_5%

23

PC19
@150U_D2_6.3VM

SOFT2

PC228
100U_6.3V

PC12
4.7U_0805_6.3V6K

17

PC18
4.7U_0805_6.3V6K
2
1

VCC

PC13
0.1U_0805_25V7K
2
1

4.7U_SPC-1204P4R7_5.7A_20%
2
1

VIN

PL2
+1.5VALWP

PC11
0.01U_0603_50V7K
2
1 12
SOFT1

VR_ON <29,34,41>

PC8
0.1U_0805_25V7K

PR256
1
1K_0603_5%

PC5
2.2U_0805_10V6K

PC7
2200P_0603_50V7K

PR2
2.2_0603_5%

PC6
0.1U_0805_25V7K

PD1
DAP202U_SOT323

PC3
4.7U_1210_25V6K
2
1

PC2
0.1U_0805_25V7K
1
2

PC1
2200P_0603_50V7K
2
1

CPUB++

1
PR19
0_0603_5%

+1.5VALWP

PR224
0_0603_5%

PQ40
SI3442DV

+3VALWP

PC167
68P_0603_50V8J

PC166
220U_D2_2M_R9

2
2
2
1

1
PR227
5.1K_0603_5%

PQ41

2.5VREF

DTC115EUA

100K

VR_ON# <34>
A

100K

+
0

PU17A
LM358A_SO8

PR21
@10K_0603_5%

PC165
560P_0603_50V7K

PR228
100K_0603_1%

4
7

1
-

PR229
137K_0603_1%
2
1

PC168
0.01U_0603_50V7K
2
1

1
2
3

8
P

PC169
0.1U_0603_16V7K

+5VALWP

PR225
5.1K_0603_5%

1
2

PC164
4.7U_1206_25VFZ

1
PR226
0_0603_5%

+1.05VSP

6
5
2
1

PU17B
LM358A_SO8

Compal Electronics, Inc.


Title

1.2V / 1.5V / 1.05V


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS
CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 12, 2003

Rev

1.0

LA-1701

Sheet
1

39

of

49

+3VALWP

+3VALWP
PR264
5.1_0603_5%
2
1

8
7
6
5

PQ54
2N7002_SOT23

FB_VDD+

2
G
S

SUSP

PR263
100K_0402_5%

CM3718

2
1

PR262
100K_0603_0.5%

PVIN
LX
PGND
VFB

+1.25VSP

1
PR265
100K_0603_5%
1
2

PR261
100K_0603_0.5%

PC215
1U_0603_10V6K

+2.5VP

VIN
GND
SD
VREF

PL20
5UH_SPC_06704-5R0A

PU22

1
2
3
4

PQ53
2N7002_SOT23

PC218
4.7U_1210_25V6K

1
2
1
2
PR266
1K_0603_5%
PC216
470P_0603_50V8J

PC219
0.1U_0603_16V7K

2
G

D
PC220
0.1U_0603_16V7K
1
2

1
SUSP

PC217
1U_0603_10V6K
1
2

PR260
0_0402_5%

1
+

PC221
220U_D_6.3M_R55

2
C

REMOTE SENSE

VS

+2.5VP

1
PR257
10K_0603_0.5%

0
4

PU20A
LM358A_SO8

PR258
10K_0603_0.5%

PC203
0.1U_0402_16V4Z

PC204
10U_1206_10V4Z

PR254
0_0603_5%
1
2

(1.25V)
+SDREF

PC206
0.1U_0402_16V4Z

PC205
0.1U_0603_50V4Z

SDREF_L
PQ45

2
G

2N7002_SOT23

+
0
-

PR291

2 @0_0402_5%

SUSP <34>

PR292

2 0_0402_5%

SYSON# <34>

5
6

PU20B
LM358A_SO8

Compal Electronics, Inc.


Title

1.2V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS
CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

Rev

1.0

LA-1701

Date:
5

Monday, May 12, 2003

Sheet
1

40

of

49

CPU-CORE

+5VDRIVE

1
2

PC207
0.1U_0805_25V7K
2
1

PC88
4.7U_1210_25V6K

PC87
4.7U_1210_25V6K
2
1

PC86
4.7U_1210_25V6K
2
1

PQ27
@IRF7821_S08

5
6
7
8
D
D
D
D
G
S
S
S
4
3
2
1

D
D
D
D
G
S
S
S

PQ26
IRF7821_S08

PC209
220U_D2_2M_R9

2
1

EC31QS04

1
2

PQ29
IRF7832_SO8

5
6
7
8
D
D
D
D
G
S
S
S
4
3
2
1

PQ28
@IRF7832_SO8

2
PR294
2.2_0603_5%

4
3
2
1

1
2

1
2

PC103
4.7U_1210_25V6K
2
1

PC102
4.7U_1210_25V6K

1
2

1
2

PL11
0.6U_HK_AE26A0R6_26A_25%
2
1

PU9
ADP3415

PC101
4.7U_1210_25V6K

5
6
7
8
D
D
D
D

PQ31
@IRF7821_S08

PR141
0.002_2512_5%
2
1
PR142
10_0603_1%

PD20
EC31QS04

PC107
0.01U_0603_50V7K

DRVL

PR140
10_0603_5% 2

DLY

10
9

BST

DRVLSD SW

PR143
0_0603_5%

PR136
2.2_0603_5%

DRVH

SD

PC105
1U_0805_25V4Z

IN

PR145
2.7_0603_5%

1
2

VSS

PC108
4.7U_1206_16V4Z

MCH_PWRGD

PC109
0.1U_0805_25V7K

PC110
1000P_0603_50V7K

4
3
2
1
G
S
S
S

1
PR144
47K_0603_5%

3205_VCC

PWDOUT

PC93
0.01U_0603_50V7K

+3VS

VDDIN

CPUB+
PD19
EP10QY03
2
1

PQ33
@IRF7832_SO8

2
1

+3VS

+1.8VSP

5
6
7
8

21

PC106
0.1U_0402_16V4Z

XC61CN0902MR

+5VDRIVE
PR134
3.32K_0402_1%

G
S
S
S

GND

2.7_0402_5%

PR138
3K_0603_5%

PD16
EC31QS04

4
3
2
1

CLAMP

1 PR133

5
6
7
8

22

D
D
D
D

VCC

G
S
S
S

SS

4
3
2
1

23

19

0_0603_5%

PU10

PR114
13.7_0603_1%

PQ30
IRF7821_S08

COREFB

PC98
0.047U_0603_25V7M

RB751V_SOD323

D
D
D
D

24

SD

ADP3205

3205_VCC

PR111
0.002_2512_5%
+CPU_CORE
2
1

PR130
270_0402_1%

PQ32
IRF7832_SO8

DACREFFB

1 PR131 2
200_0402_1%

5
6
7
8

DACREF

DPWRGD

PR129 604K _0402_1%


1
2

25

D
D
D
D

TPWRGD

27
26

G
S
S
S

DPSHIFT

4
3
2
1

REG

CLKEN

5
6
7
8

PWRGD

+3VS

4
3
2
1

29
28

D
D
D
D

RAMP

G
S
S
S

DPSLP

56 _0402_1%
1

CS-

PR123
PC94
2
10P_0402_50V8K

DPRSLP

B+

31
30

18

20

2
PR110
0_0603_5%
1

CS+

32

3205_VCC

DPRSET

PL10
0.6U_HK_AE26A0R6_26A_25%
1
2

VCCP_PWGD 2 PR137

MCH_PWRGD 2 PR135 1
0_0603_5%

PR283
3.3K_0402_5%

CS1

+CPU_CORE

17
<29,34,39> VR_ON

CS2

BOOTSET

2
PR293
2.2_0603_5%

2
1
PD43
RB751V_SOD323

16

13205_SD#

CS3

VREF

0_0402_5%
1
@0_0402_5%
1

PC100
4.7U_0805_10V4Z
5

RB751V_SOD323

VR_ON 2 PR132
0_0603_5%

VID0

PR119
2
PR284
2

VCC

15

PU7
ADP3415

GND

DRVL

PR105
0_0603_5%
2

34
33

14

<12,16,32> VGATE

DRVLSD1

DLY

13

PD41

<12> CLKEN#

VID1

DRVLSD SW

35

1
PC95
0.01U_0603_50V7K

12

DRV1

2 PR125 1
0_0603_5%
2 PR127 1
0_0603_5%

<16> PM_DPRSLPVR
<12,16> STP_CPU#

VID2

DRVH

10
9

36

PR124
6.34K_0603_1%

DRVLSD2

PR126

11

VID3

38
37

BST

PL9
FBM-L18-453215-900LMA90T_1812

330K_0402_5%

10

DRV2

<5> CPU_VID0
PR120
3.9K_0603_1%

PR121
300K_0603_5%
2

<5> CPU_VID1

DRVLSD3

VID4

39

<5> CPU_VID2

VID5

40

PR139
5.36K_0402_1%

1
2

<5> CPU_VID3

DRV3

PC96
2
1
PC97
470P_0402_50V7K 10P_0402_50V8K
2
1
2
1

PC92
0.01U_0603_50V7K

<5> CPU_VID4

TSYNC

HYSSET

PC99
0.1U_0402_16V4Z
2
1

1
2

<5> CPU_VID5

PR112
5.36K_0603_1%

PSI

PR107
1
1
0_0603_5%
PR108
2
2
23.7K_0603_1%
3
2 PR109 1
0_0603_5%
2 PR113 1
4
0_0603_5%
2 PR115 1
5
0_0603_5%
2 PR116 1
6
0_0603_5%
2 PR117 1
7
0_0603_5%
2 PR118 1
8
0_0603_5%
9

SD

GND

PU8

<5> PSI#

3205_SD#

PD42

IN

1
2

PC91
100P_0603_50V8J

2
PR106
15K_0603_1%

PR295
33K_0603_5%

PR122
PD18
300K_0603_5% 1SS355_SOD323
1
21
2

VCC

1
+3VS
1

2
1
PC90
1U_0805_25V4Z

2
PR104
2.2_0603_5%

1
PC85
4.7U_0805_10V4Z

+5VS

PD15
EP10QY03
2
1

5
6
7
8

CPUB+
PR103
0_1206_5%
2
1

PD17

PC89
2200P_0603_50V7K
2
1

PC104
2200P_0603_50V7K

PC208
0.1U_0805_25V7K

+3VS

PR222
0_0603_5%
1
2
PR146
47K_0603_5%

PU11
XC61CN0902MR

VCCP_PWGD

PWDOUT

PC111
1000P_0603_50V7K

VDDIN

VSS

+1.05VSP
4

Compal Electronics, Inc.


Title

+VCC_H_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS
CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, May 12, 2003
A

Rev

LA-1701

1.0
Sheet

41
H

of

49

PH1 under CPU botten side :


CPU thermal protection at 90 +-3 degree C
Recovery at 50 +-3 degree C

VMB
PL16
FBM-L18-453215-900LMA90T_1812
1
2

PR193
@1K_0603_5%
2
1

VL
VS
PC151
0.01U_0603_50V7K

PC152
@0.1U_0402_10V6K

CPU
1

LM393M_SO8

PR207
100K_0402_1%

OTP_C

PD29
1SS355_SOD323

MAINPWON

PR205
2.74K_0603_1%

PU15A

REV

VL

PC156
0.22U_0805_16V7K

PR198
100K_0402_1%

3
PD30
@BAS40-04

PR203
16.9K_0402_1%
1
2

L_10T

+3VALWP

PR204
1K_0603_5%

PR200
47K_0402_1%

PR201
0_0402_5%

2
PR202
25.5K_0603_1%

LI/NIMH# <29>

VL

PR199
47K_0402_1%
1
2

L_10

PTH1
10K_1%

PR195
PR196
100_0603_5% 100_0603_5%

PC153
0.1U_0603_50V4Z

PC154
1000P_0603_50V7K

BATT_TEMP <29>
EC_SMD_1

EC_SMC_1 <29,30,33>

PH2 near main Battery CONN :


BAT. thermal protection at 84 +-3 degree C
Recovery at 45 +-3 degree C

PD32
@BAS40-04

PD31
@BAS40-04

EC_SMD_1 <29,30,33>

EC_SMC_1

<4,35,37>

PD28
@BAS40-04

PC150
1000P_0603_50V7K

EC_SMC
EC_SMD

SUYIN_25133A-08G1-01_8P

BATT+

+3VALWP

PR194
@47K_0603_5%
1
2

ALI/NIMH#_PWR
AB/I
TS_A

PR197
1K_0603_5%

1
2
3
4
5
6
7
8

PCN3

100K

100K
PQ39

+5VALWP

VL

DTC115EKA_SOT23

BATTERY

PC157
@0.1U_0402_10V6K

VL

PTH2
10K_1%

2
1

O
-

OTP_B2

1
PD33
1SS355_SOD323

PU15B
LM393M_SO8

REV
PR214
3.32K_0603_1%

PC160
0.22U_0805_16V7K

PR211
47K_0402_1%

PR212
16.9K_0402_1%
1
2

L_11T

PR210
0_0402_5%

L_11

PR208
47K_0402_1%
1
2

Title

BATTERY CONN / OTP/1.8V


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Monday, May 12, 2003

Rev

LA-1701

0.1
Sheet
D

42

of

49

REV: 0.1A

1. Update PCI resource table. (Page 3)


2. Change U41 power source form +12VS to +5VS for correcting error. (Page 4)
3. Remove DVI signals. (Page 13)
4. Add Video board ID and Mother board ID for HP requirement. (Page 16)
5. Change LAN controller from RTL8100BL to RTL8139CL+ for HP requirement. (Page 19)
6. Change audio CODEC from ALC202A to AD1981B and modify relational components for HP requirement. (Page 23,24)
7. Change USB power protector from Poly switch to RT9701-CBL for meet HP's specification. (Page 27)
8. Add CP9, CP10 (100P_1206_8P4C) for EMI requirement. (Page 28)
9. Add a power button LED (D34) for HP requirement. (Page28)
9. Add a power button LED (D34) for HP requirement. (Page28)

REV: 0.1B

1. U33,U34,U56 combine to U33 (74HCT08 TSSOP14).(Page 18)


2. Add Q81,C892,C891 for +3VAUX turn on/off.(Page 25)
3. Add R91,R1132,C893 for correcting error. (Page 26)
4. U12 pin9,10 contact to GND. (Page 30)
5. Change U47D,U47E,U47F to U14A,U14B,U14C. (Page 32)
6. Add L57,C894,C895,C896,C897 for HPQ request to add SPR GNDA.
7. Add U57 and relation components for AD1981B's AVDD power source. (Page 23)
8. Change U23 and relation components to reserve. (Page 23)
9. Add R1137, 0_1206_5% resistor for optional AMP. power source of +5VS. (Page 24)
10. Add L58~L61 on AMP.(U53) output trace. (Page 24)
11. Delete TVS41~TVS44 and change C863~C866 to 47PF. (Page 24)
12. Modify JP8's pin define for using switched jacks on the headphone audio. (Page 28)
13. Change audio amplifier from TPA0202 to TPA0312. (Page 24)
14. Connecting the pin97 of JP28 and JP29 to GND for HP's requirement. (Page9,10)
15. Install a 0 ohm (R703) between ITP_DBRESET# and SYSRST# then de-populate U51,R704 and C833. (Page 16)
16. Modify USB routing method for HP's requirement. (Page 16)
i. USB0 and USB 1 (U45.C20/D20, U45.A21/B21) to the two ganged system USB ports.
ii. USB2 and USB3 (U45.C18/D18, U45.A19/B19) to the docking connector.
iii. USB4 (U45.C16/D16) to single USB.
iv. USB5 (U45.A17/B17) to MDC.
17. Delete net MBAY_DISABLE from JP1 pin A49 for HP's requirement. (Page 29,33)
18. Change powerm source of D10,D11 and D12 from CRTVDD to +3VS for HP's requirement. (Page 14)
19. Add an IO buffer (U56) for supporting EVO600's keyboard. (Page 30)

REV: 0.1C

1. Re-location all parts.


Compal Electronics, Inc.
Title

E/E(1) PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

LA-1701

Date:

Monday, May 12, 2003

Sheet
1

43

of

49

REV: 0.1D

1. Change U20 to AT24C16N and change power source to +3VALW. (Page 30)
2. Change U49 EC_SMC_1/EC_SMD_1 to EC_SMC_2/EC_SMD_2. (Page 4)
3. Change Battery EC_SMC_2/EC_SMD_2 to EC_SMC_1/EC_SMD_2. (Page 42)
4. Modify SD controller to M/B. (Page 31)

REV: 0.2A (For DB-1 SMT)

1.For solving FAN can't work properly issue. (Page 4)


a. Change U14's power plan from +5VS to +12VS.
b. Change U14 from LMV321M5X to LM321MF.
2. For solving system boot fail issue. (Page 12)
a. Del Q29.
b. Add PD41 RV751V.
3. For EMI requirement. (Page 14)
Change L1,L2,L3,L18,L19 from FBM-11-160808-121 to FCM1608C-121T.
4. For solving main battery only, system can't boot on issue. (Page 15,16)
a. Change ACIN signal connection from GPI11(U8.AA5) to GPIO27.(U8.W1)
b. Pull high GPI11 to +3VALW.
5. Pull high U19.8 to +5VS for solving SUSP# signal don't well issue. (Page 23)
6. Del L10,C155,C204,C477,C474 for HP requirement. (Page 23)
7. Change R363,R365 to 1K_0402_5% for solving CODEC can't be detected issue. (Page 23)
8. Add voltage divider R413,R414,R416,R419 for HP requirement. (Page 24)
9. Change AMP. gain from 6dB to 10dB for HP requirement. (Page 24)
10. Add R420 100K_0402_5% for solving headphone plug fail issue. (Page 24)
11. Change JP20.27 and JP20.28's power plan from +5VS to +5V for supporting touch pad wake up from S3 function. (Page 28)
12. Change U15.161's power plan from +RTCVCC to RTCVREF from increasing RTC battery life. (Page 29)
13. Add U29 for supporting 8Mbits BIOS. (Page 30)
14. Change D6,D7 to HSMB-C172 for HP requirement. (Page 30)
15. For supporting SD avtive LED function. (Page 31)
a. Connection JP17.13 to SDLED.
b. Change JP17.15's power plan from +3VS to +5VS.
16. Add JP32 for supporting BT module. (Page 31)

REV: 0.2B (For DB-2 gerber)


Add R427 20K ohm resister for solving PC-beep is too loud issue. (Page 23)

REV: 0.2C (For DB-2 SMT)


A

1. Phase-in EMI solution.


a. Add R35,R344,R58,R142,R301,R408 10_0402_5%.
b. Add C42 22PF_0402_NPO.
c. Add C447 15PF_0402_NPO.
d. Add C73,C153,C319,C560 10PF_0402_NPO.

Compal Electronics, Inc.


Title

E/E(2) PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

Rev
1.0

LA-1701

Date:
5

Monday, May 12, 2003

Sheet
1

44

of

49

REV: 0.2D
1. To change the mute circuitry for SI build.
a. Connect EAPD (pin U22.47) to JP24.2 and reserve a 0_0402_5% (R431) resistor for testing.
b. Install R162 (0_0402_5%) and no install R163.
c. Add R432 (100K_0402_5%) and Q51 (2N7002) to invert EAPD signal for amplifier and mute LED.
D

REV: 0.2E

1. For EMI requirement.


Add C204 0.1U_0402_16V4Z
2. To exchange TP and PS2 signals for EC requirement.
3. For cost down plan.
To exchange the capacitor of C83,C136 from 150U_D2_6.3VM to 100U_6.3V_M.

REV: 0.2F
1. For cost down plan.
Move audio line-out BLOCK capacitor from TP to MB. To add C565,C566 100U_6.3V_M.
2. For solving audio noise when IR active. (A2C039)
a. Del C206.
b. To change C492 from 150U_D2_6.3VM to 10U_1206_6.3V7K.
3. For EMI requirement.
Add R435~R440 0_0402_5%.
C

REV: 0.2G

1. For solving power LED signal wrong on PR/APR side.


a. Add R441 1K_0402_5%.
b. Q52 2N7002.
2. For solving power button must be pressed twice issue.
1. Add D27 RB751V.
2. Add R330 4.7K_0402_5%.
3. Change R345 from 10K_0402_5% to 100K_0402_5%.
3. Per HPQ requirement to change audio component.
To change C174 and C201 to 0.022U_0603_25V7K.

REV: 0.2H (For SI gerber)


1. Per HPQ requirement to change audio component.
To change R427 from 20K_0402_5% to 39.2K_0402_1%.

REV: 0.3 (For SI SMT)


B

1. Per HPQ requirement to change LED color from BLUE to GREEN.


a. Change D5,D6,D7,D26 from HSMB-C172_BLUE_0805 to HSMG-C170_GRN_0805.
b. Change R9,R10,R11,R421 from 140_0402_1% to 330_0402_5%.
2. To improve RTC crystal accuracy.
Change C190,C203 from 12P_0402_50V8J to 15P_0402_50V8J.

REV: 0.3A (For PV Build)

1. Per HPQ requirement to add FET to shut off power to the Bluethumb module.
a. Add Q53 SI2301DS.
b. Add C568 1U_0603_10V6K.
c. Add C570 0.01U_0402_16V7K.
d. Add C571 0.1U_0402_16V7K.
e. Add C569 4.7U_0805_6.3V6K.
f. Add Q54 2N7002.
g. Add R442 100K_0402_5%.
h. Del R424.
i. Change Q16.2 signal source from Wireless_OFF# to Wireless_OFF.
2. For supporting WLAN and BT devices exist in the same system.
a. Connect Mini-PCI JP28-36 to Bluethumb JP32-7 using a series resistor of 1K_0402_5% (R72).
b. Connect Mini-PCI JP28-43 to Bluethumb JP32-6 using a series resistor of 1K_0402_5% (R298).

Compal Electronics, Inc.


Title

E/E(3) PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

Rev
1.0

LA-1701

Date:
5

Monday, May 12, 2003

Sheet
1

45

of

49

REV: 0.3B
1. Exchange signals NUMLED# and CAPSLED# of Q31 and Q33 for solving BC022.
2. Rotate JP20 180 degree for solving PCP assembly issue.
3. Change JP18 & JP19's pin1 signal from SPKR+ and SKPL+ to SPKR+_C and SPKL+_C for solving audio noise issue.

REV: 0.4 (For PV gerber)


D

1. Connection LPC_DRQ#0 to U42.2 through R147 0_0402_5% for support SD controller DMA function.
2. For EMI requirement.
a. Add L10 0_1206_5% and exchange layout position with C204.
b. Add L36 FBM-L10-160808-301-T_0603 on EAPD signal and closed to audio CODEC.
c. Add L37 FBM-L10-160808-301-T_0603 on +3VS power line of audio CODEC.
d. Change R406 from 10_0402_5% to 33_0402_5%.
3. Per ME team Tony Liu request, change LED type and current limit resistor for increasing luminous intensity.
a. Change D5, D6, D7 and D26 from HSMG-C170 to 17-21SYGC/S530-E1/TR8.
b. Change R9, R421 from 330_0402_5% to 150_0402_1%.
4. Del C567 layout pad for solving DFX issue.
5. Reserve 1U_0603_10V6K (C572) pad and connection to U15.21 for supporting PC97591L/V in the further.
6. Do not install R72 and R298 (1K_0402_5%) for HP requirement.
7. For solving OTS#95452 which are HSYNC and VSYNC out of specification.
a. Add C573 0.1UF_0402_5%.
b. Add U43 SN74AHCT126PWR.
c. Del Q3, Q4, R263, R268, R267, R255, R254.
d. Change C3, C5 from 68P_0402_50V8K to 10P_0402_50V8K.
8. Base on HPQ Robert's command to do some audio's design change.
a. Install R433, R434 0_0603_5%
b. No install C565, C566 100UF_6.3V_M.
c. Correct the left channel input voltage divider, connect R419.1 to LINE_OUTL and R416.1 to analog GND.
d. Change C562 from 0.1U_0402_16V4Z to 0.1U_0603_16V7K.
e. Change R387 from 4.7K_0402_5% to 10K_0402_5%.
f. Change D24 from 1N4148 to R444 4.7K_0402_5%.
g. Del R416 0_0402_5%.
h. Add R419 0_0402_5%.
9. Change some component's value as HPQ Darrell's request.
a. Change C330, C334 from 0.01UF to 0.1UF.
b. Change R354 from 100Kohm to 330Kohm.

REV: 0.4A (For PV SMT)


1. Add C482 0.1UF_0402_16V4Z for solving OTS#96542.
2. For solving OTS#95994.
a. Change R428, R429 from 0_0402_5% to 4.7K_0402_5%.
b. Add R413, R416 4.7K_0402_5%.

REV: 0.4B
1. Add R445 511_0603_1% to limit RTC battery discharge current for meeting OSM 4.3.8 specification.

REV: 0.4C

1. Per HPQ David request to do some audio components change.


a. Change R428, R429 from 4.7K_0402_5% to 0_0402_5%.
b. No install R413, R416, R433, R434.
c. Install C565 and C566 100uF CV-AX.
2. Delete reserved layout pad for solving DFX issue.
Del C83, C136, R433 and R434.
3. No install R59 10K_0402_5% for solving double pull high issue.

Compal Electronics, Inc.


Title

E/E(4) PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Date:
Monday, May 12, 2003

Rev
1.0

LA-1701

Sheet
1

46

of

49

4. Change R406 from 33_0402_5% to FBM-11-100505-600T to solve EMI issue.


5. Del R9 and D5 for ME team request.

REV: 0.4D
D

1. For solving HSYNC and VSYNC waveform undershoot over specification issue.
Change L18,L19 from FCM1608C-121T to FBM-L10-160808-300LM-T.
2. Per ME (Tony Liu) request, change D6,D7,D26 from 17-21SYGC/S530-E1/TR8 to 17-21/GVC-AMPB/3T for solving lightness not enough issue.
3. Reserve R447,R448,R449 layout pad for support CB1410 B0 version chip in the further.
4. Add D29 SM05 for solving ESD test fail issue.
5. For solving "BoBo" audio noise from HLDS and TEAC ODD.
a. Change R214,R216 from 4.7K_0402_5% to 1.3K_0402_5%.
b. Change R210 from 2.7K_0402_5% to 1.1K_0402_5%.

Compal Electronics, Inc.


Title

E/E(5) PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Date:
Monday, May 12, 2003

Rev
1.0

LA-1701

Sheet
1

47

of

49

Version change list (P.I.R. List)


Item
1

Power section

Reason for change

PG#

RTC battery doesn't need to charge

35

Page 1 of 2

Modify List

Date

B.Ver#

PR190 and PR191 change to @200

2002.10.15

PR188 change to 34K, add PR259 (66.5K)

2002.10.15

change reference voltage, because VL build up fast then


RTCVREF

35

adapter change from 75W to 65W. So, the power limiter


must to reduce with adapter

36

PR83 change to 31.6K, PR84 change to 10K

2002.10.15

the current rating of the new BEAD is 9A, the old one
is 8A.

37

PL5 change to FBM-L18-453215-900-LMA90T

2002.10.15

modify circuit for aircraft power

36

add PD38,PD39,PD40,PQ46,PQ47,PQ48,PQ49,PQ50,PQ51,
PQ52,PU21,PR267,PR268,PR269,PR270,PR271,PR272,
PR273,PR274,PR275,PR276,PR277,PR278,PR279,PR280,
PR281,PC210,PC211,PC212,PC213,PC214,PZD8

2002.10.23

delete PD35,PD36,PQ44,PR250,PR251,PR252,PR253,
PC194,PC195,PC196,PC197,PC198,PC199,
PC200,PC201,PU19

modify circuit for DDR, change CM8500 to CM3718

40

2002.10.23

change VIN detector voltage and Precharge deterctor


voltage

35

PR167 change to 60.4K, PR166 change to 604K,


PR184 change to 604K, PR185 change to 301K,
PR187 change to 402K

2002.10.23

modify circuit for aircraft power, when use aircraft power,


battery can discharge

36

delete PU21,PQ47,PQ48,PQ49,PQ51,PD40,PZD8,PQ16,
PR267~PR276,PR280~PR281,PC210~PC214,PC223,PD38,PD39

2002.12.04

add PR260,PR261,PR262,PR263,PR264,PR265,PR266
PC215,PC216,PC217,PC218,PC219,PC220,PC221,
PU22

add PD40,PD41,PQ50,PZD6,PR285,PR286

for EMI solution

10

to solve noise issue

11

to prevent leakage current

12

modify circuit form dual phase to single phase at CPU-CORE

36

PC62 and PC63 change to 10U_1210_25V

2002.12.04

37

add PQ51(2N7002) and PR287 (2.7K_1206_5%)


change PC33 to 2.2U_1210_25V

2002.12.04

40

change PR45 from DTC115EUA to 2N7002

2002.12.04

41

delete PQ26~PQ29,PU7,PD15,PD16,PC85~PC90,PC93,
PL10,PR104,PR105,PR110,PR111
add PC223

2002.12.04

change PR129
PR134
PR126
PR141
PC107

to
to
to
to
to

604K_0402_5%,
3.32K_0402_1%,
120K_0402_5%,
0.001_2512_5%,
0.01U_0603_25V

13

to prevent leakage current

41

change PR128 to PD41 (RB751V)

2002.12.04

14

change CPU thermal protect to 90 degree C

42

change PR205 form 3.32K_0603_1% to 2.74K_0603_1%

2002.12.18

15

to reduce tolerance on CPU CORE voltage feedback

41

change PR126 form 120K_0402_5% to 120K_0402_1%

2002.12.18

Compal Electronics, Inc.


Title

PWR PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Date:
Monday, May 12, 2003

Rev
1.0

LA-1701

Sheet
1

48

of

49

Version change list (P.I.R. List)


Item
16
D

Power section

Reason for change

PG#

the component is too high (2.5mm), so change to 1206


size(1.6mm)

41

Page 2 of 2

Modify List

Date

chang PC101,PC102,PC103 to 10U_25V_X5R_1206


(SE142106M00)

B.Ver#

2002,12,30
D

change PR123 to 47_0402_1% (SD034470A00)


PC96 to 22P_0402_50V (SE071220J00)
PR126 to 240K_0402_5% (SD028240300)
PR129 TO 1M_0402_1% (SD034100400)
delete PC97

17

to adjust CPU CORE load line

41

18

the component is too high (5.2mm), so change to 1210


size(2.0mm)

36

chang PC74 to 4.7U_25V_X5R_1210 (SE065475K00)

2002,12,30

to reduce inrush current for 1.25V

40

change PR261,PR262 to 100K_0603_0.5% (SD019100309)


PR260 to 100K_0603_5% (SD0131003T1)
add PQ53,PQ54 2N7002 (SB7700200T5)

2002,12,30

to reduce power consumption and inrush current

35

change PR223,PR176,PR178,PR181 to 1.5K_1206_5%


(SD0111501T6)

2002,12,30

19
20
21

2002,12,30

35

delete PR165 and PZD1

2002,12,30

22

to speed up response time

39

change PC165 to 560P_0603_50V_X7R (SE025561K00)

2002,12,30

23

to solve noise issue

36

add PC224,PC225 47U_25V_EC

2003,01,05

40

change PC218 to 4.7U_1210_25V (SE065475K00) from


100U_6.3V (SG017101310)

24

25

to solve noise issue (A2C021)

41

(SF04704M000)

add PQ26,PQ29,PU7,PD15,PD16,PC85~PC90,PC93,PC97
PL10,PR104,PR105,PR110,PR111,PR114,PC230,PC231
delete PC223

2003,01,05

2003,01,23

change PR129 to 604K_0402_5%,


PR134 to 3.32K_0402_1%,
PR126 to 330K_0402_5%,
PR123 to56_0402_1%,
PC96 to 10P_0402_50V

26

to reduce negative voltage at High-side GATE


for ADP3415 (A2C014,A2C098)

41

add PD42,PD43
change PR105 and PR140 to 2.2_0603_5%

2003,01,23

27

to limit RTC battery discharge current for meeting OSM 4.3.8


specification.

35

change PR290 from 200_0805_5% to 511_0603_1%

2003,05,02

28

adjust ripple voltage and ripple current when charger battery

36

delete PC79 and PC80


change PR91 from 330K_0603_5% to 47K_0603_5%

2003,05,02

29

to solve noise issue (OTS:97258)

37

change PC33 from 2.2U_1206 to 4.7U_1210

2003,05,02

30

Modify battery connector layout foorprint for support has


lock pin type battery connector.

42

2003,05,02

31

Modify DC-IN jack library for solving AC jack plug-in


loose issue.

35

2003,05,02

Compal Electronics, Inc.


Title

PWR PIR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.Date:
Monday, May 12, 2003

Rev
1.0

LA-1661

Sheet
1

49

of

49

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