Problem 1

Fig. Vm=Vdd/2 with K(Wp/Wn)=3.9285

Fig: VTC vs Wp/Wn Sweep

Fig. Vm vs Wp/Wn Sweep

* HPSICE Netlist for Sweeping Vm vs Wp/Wn
.param pvdd = 1.2v
.param lmin = .12u
.param Wn = .28u
.param Wp = 'K*Wn'
.include "/home/cad/vlsi/models/hspice/cmos0.13um.model"
*MT1 OUT IN VDD! VDD! PFET L=120E-9 W=Wp M=1 AD=124E-15
*+AS=124E-15 PD=1.525E-6 PS=1.525E-6
*MT0 OUT IN 0 0 NFET L=120E-9 W=Wn M=1 AD=124E-15
*+AS=124E-15 PD=1.525E-6 PS=1.525E-6
MTinvN
OUT
IN
gnd!
gnd! nfet L=0.12U W=Wn AD=0.112P
+
AS=0.0924P PD=1.36U PS=1.22U wt=2.8e-07 rf=0 nrs=0.93617
+
nrd=0.93617 ngcon=1 nf=1 mSwitch=0 m=1
+
blockParasiticsBetween="PC sub" PWORIENT=1 PLORIENT=1
MTinvP
OUT
IN
vdd!
vdd! pfet L=0.12U W=Wp AD=0.352P
+
AS=0.352P PD=2.84U PS=2.84U wt=1.1e-06 rf=0 nrs=0.208531
+
nrd=0.208531 ngcon=1 nf=1 mSwitch=0 m=1
+
blockParasiticsBetween="PC sub" PWORIENT=1 PLORIENT=1
vvdd vdd! 0 1.2v
vgnd gnd! 0 0v
Vi1 in gnd! PWL 0ns 0 5ns 'pvdd' 10ns 0 15ns 'pvdd'
.dc Vi1 0 1.2 .01 sweep K LIN 50 1 10
.measure dc Vm FIND v(OUT) WHEN v(IN)= v(OUT)
.options post=1
.print tran v(in out)
.end
SWEEP OUTPUTS
.TITLE '* netlist output for hspices.'

vm
1.0000
1.1837
1.3673
1.5510
1.7347
1.9184
2.1020
2.2857
2.4694
2.6531
2.8367
3.0204
3.2041
3.3878
3.5714
3.7551
3.9388
4.1224
4.3061
4.4898
4.6735
4.8571
5.0408
5.2245
5.4082
5.5918
5.7755
5.9592
6.1429
6.3265
6.5102
6.6939
6.8776
7.0612
7.2449
7.4286
7.6122
7.7959
7.9796
8.1633
8.3469
8.5306
8.7143
8.8980
9.0816
9.2653
9.4490
9.6327
9.8163
10.0000

0.4982
0.5103
0.5207
0.5299
0.5381
0.5457
0.5526
0.5589
0.5649
0.5704
0.5756
0.5805
0.5850
0.5894
0.5935
0.5974
0.6011
0.6046
0.6080
0.6113
0.6143
0.6173
0.6202
0.6229
0.6255
0.6280
0.6305
0.6328
0.6350
0.6372
0.6393
0.6414
0.6433
0.6452
0.6471
0.6489
0.6507
0.6524
0.6540
0.6556
0.6572
0.6587
0.6603
0.6617
0.6631
0.6645
0.6658
0.6671
0.6684
0.6697

temper
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000
25.0000

alter#
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000
1.0000

HSPICE Netlist
* NETLIST OUTPUT FOR HSPICES.
.include "/home/cad/vlsi/models/hspice/cmos0.13um.model"
.GLOBAL gnd! Vdd
.OPTIONS POST=1
.OPTIONS SCALE=1
.param pvdd = 1.2V
*==============Power Supply Connections==================
VVdd
Vdd 0 pvdd
VVdd1 Vdd1 0 pvdd

* For the circuit to be characterized

* For the drivers and Loads

*=======Subcircuit definition for an inverter========

.SUBCKT INV IN OUT Vdd gnd!
MTinvN
OUT
IN
gnd!
gnd! nfet L=0.12U W=0.28U AD=0.112P
+
AS=0.0924P PD=1.36U PS=1.22U wt=2.8e-07 rf=0 nrs=0.93617
+
nrd=0.93617 ngcon=1 nf=1 mSwitch=0 m=1
+
blockParasiticsBetween="PC sub" PWORIENT=1 PLORIENT=1
MTinvP
OUT
IN
Vdd
Vdd pfet L=0.12U W=1.1U AD=0.352P
+
AS=0.352P PD=2.84U PS=2.84U wt=1.1e-06 rf=0 nrs=0.208531
+
nrd=0.208531 ngcon=1 nf=1 mSwitch=0 m=1
+
blockParasiticsBetween="PC sub" PWORIENT=1 PLORIENT=1
C1
IN
gnd! 4.846E-16
C2
OUT
gnd! 3.139E-16
C3
vdd!
gnd! 2.423E-16
.ENDS
*====Subcircuit definition for Driver (1x&4x inverter)===========
.SUBCKT DRIVER IN OUT Vdd gnd!
MTdrN1x
dr_mid
IN
gnd!
gnd! nfet L=0.12U W=0.28U
AD=0.112P
+
AS=0.0924P PD=1.36U PS=1.22U wt=2.8e-07 rf=0 nrs=0.93617
+
nrd=0.93617 ngcon=1 nf=1 mSwitch=0 m=1
+
blockParasiticsBetween="PC sub" PWORIENT=1 PLORIENT=1
MTdrP1x
dr_mid
IN
Vdd
Vdd pfet L=0.12U W=1.1U
AD=0.352P
+
AS=0.352P PD=2.84U PS=2.84U wt=1.1e-06 rf=0 nrs=0.208531
+
nrd=0.208531 ngcon=1 nf=1 mSwitch=0 m=1
+
blockParasiticsBetween="PC sub" PWORIENT=1 PLORIENT=1
MTdrN4x
OUT
dr_mid
gnd!
gnd! nfet L=0.12U W=0.28U
AD=0.112P
+
AS=0.0924P PD=1.36U PS=1.22U wt=2.8e-07 rf=0 nrs=0.93617
+
nrd=0.93617 ngcon=1 nf=1 mSwitch=0 m=1
+
blockParasiticsBetween="PC sub" PWORIENT=1 PLORIENT=1
MTdrP4x
OUT
dr_mid
Vdd
Vdd pfet L=0.12U W=1.1U
AD=0.352P
+
AS=0.352P PD=2.84U PS=2.84U wt=1.1e-06 rf=0 nrs=0.208531
+
nrd=0.208531 ngcon=1 nf=1 mSwitch=0 m=1

+
blockParasiticsBetween="PC sub" PWORIENT=1 PLORIENT=1
.ENDS
*===========Subcircuit definition for a Load============
.SUBCKT LOAD IN OUT Vdd gnd!
MTldN1
ld_mid
IN
gnd!
gnd! nfet L=0.12U W=0.28U
AD=0.112P
+
AS=0.0924P PD=1.36U PS=1.22U wt=2.8e-07 rf=0 nrs=0.93617
+
nrd=0.93617 ngcon=1 nf=1 mSwitch=0 m=1
+
blockParasiticsBetween="PC sub" PWORIENT=1 PLORIENT=1
MTldP1
ld_mid
IN
Vdd
Vdd pfet L=0.12U W=1.1U AD=0.352P
+
AS=0.352P PD=2.84U PS=2.84U wt=1.1e-06 rf=0 nrs=0.208531
+
nrd=0.208531 ngcon=1 nf=1 mSwitch=0 m=1
+
blockParasiticsBetween="PC sub" PWORIENT=1 PLORIENT=1
MTldN2
OUT
ld_mid
gnd!
gnd! nfet L=0.12U W=0.28U
AD=0.112P
+
AS=0.0924P PD=1.36U PS=1.22U wt=2.8e-07 rf=0 nrs=0.93617
+
nrd=0.93617 ngcon=1 nf=1 mSwitch=0 m=1
+
blockParasiticsBetween="PC sub" PWORIENT=1 PLORIENT=1
MTldP2
OUT
ld_mid
Vdd
Vdd pfet L=0.12U W=1.1U
AD=0.352P
+
AS=0.352P PD=2.84U PS=2.84U wt=1.1e-06 rf=0 nrs=0.208531
+
nrd=0.208531 ngcon=1 nf=1 mSwitch=0 m=1
+
blockParasiticsBetween="PC sub" PWORIENT=1 PLORIENT=1
.ENDS
*=====Highest Netlist (driver/dut/load)================
XDr1 IN A Vdd1 gnd! DRIVER
X1 A OUT Vdd gnd! INV
* Fanout
XLd1 OUT
XLd2 OUT
XLd3 OUT
XLd4 OUT

of 4
out1
out2
out3
out4

Vdd1
Vdd1
Vdd1
Vdd1

gnd!
gnd!
gnd!
gnd!

LOAD
LOAD
LOAD
LOAD

*==================INPUT PULSE==============
*Vpulse A 0 PULSE(0 1.2 0 30ps 30ps 2ns 4ns)
Vin A gnd! PULSE(0 pvdd 50p 30ps 30ps 1.970ns 4ns)
*==================ANALYSIS==============
.tran 0.1ns 8ns
*.TRAN 0.005ns 20ns *sweep beta 1 10 1
*==================MEASURE PROPAGATION DELAY=========
.measure tran Tphl_out
+trig v(A) val='pvdd/2' rise=1
+targ v(OUT) val='pvdd/2' fall=1
.measure tran Tplh_out
+trig v(A) val='pvdd/2' fall=1
+targ v(OUT) val='pvdd/2' rise=1
*===================Rise and Fall Time=======================

* .measure tran trise trig v(OUT) val='0.1*pvdd' rise=4 targ v(OUT)

val='0.9*pvdd' rise=4
* .measure tran tfall trig v(OUT) val='0.9*pvdd' fall=4 targ v(OUT)
val='0.1*pvdd' fall=4
*====================Propagation Delay========================
*.measure tran Tphl_out trig v(A) val='pvdd/2' rise=3 targ v(OUT)
val='pvdd/2' fall=3
*.measure tran Tplh_out trig v(A) val='pvdd/2' fall=4 targ v(OUT)
val='pvdd/2' rise=4
.measure tran T_avg_delay param = '(tplh_out + tphl_out)/2'
*.measure tran T_diff param = 'ABS(tplh_out-tphl_out'
*==================ENERGY DELAY PRODUCT (EDP) =========
.param Vvdd=1.2v
.measure charge INTEGRAL I(VVdd) FROM=0ns TO=4ns
.measure energy param='charge*pvdd'
.measure EDP param='energy*T_avg_delay'
.END

Fig. INV Output with Fan out 4

Fig: EDP, Tphl & Tplh values for Fan out 4

Table listing EDP
.TITLE '* netlist
tphl_out
energy
3.674e-11
-1.354e-14

and Tphl & Tplh for Fan out 4:

output for hspices.'
tplh_out
t_avg_delay
edp
temper
3.163e-11
3.418e-11
-4.629e-25
25.0000

FAN OUT 1:

Fig: INV Output with Fan out 1

charge
alter#
-1.128e-14
1.0000

Fig: EDP, Tphl & Tplh values for Fan out 1

Table listing EDP
.TITLE '* netlist
tphl_out
edp
4.020e-11
-1.015e-24

and Tphl & Tplh for Fan out 1:

output for hspices.'
tplh_out
charge
temper
alter#
3.516e-11
-1.122e-14
25.0000
1.0000

FAN OUT 0:

Fig: INV Output with Fan out 0

energy
-1.347e-14

Fig: EDP, Tphl & Tplh values for Fan out 1

Table listing EDP and Tphl & Tplh for Fan out 0:
tphl_out
tplh_out
t_avg_delay
energy
edp
temper
1.584e-11
1.357e-11
1.471e-11
-3.012e-15
-4.429e-26
25.0000

charge
alter#
-2.510e-15
1.0000