ACTIVE_HDL_8.3_README_RIZVI_SP12.txt 1) RUN ActiveHDL8.3_main_installation.exe TO INSTALL ACTIVE-HDL 8.3. IT IS IN EDA\SIMULATORS\ALDEC\ACTIVE_HDL\8.3\ACTIVE_HDL_8.3 FOLDER.

2) NEAR THE END OF YOUR INSTALLATION PROCESS, YOU WILL SEE A "CHOOSE LICENSE ENVIRONMENT" WINDOW. SELECT "NO CHANGES,ALREADY HAVE LICENSE". 3) COPY ibfs32.dll AND PASTE IT INTO Aldec\bin FOLDER INSIDE INSTALLATION DIRECTORY. IT IS IN EDA\SIMULATORS\ALDEC\ACTIVE_HDL\8.3\LICENSING_INSTALLATION_INSTRUCTIONS FOLDER. 4) COPY license_ActiveHDL82.dat PROVIDED IN EDA\SIMULATORS\ALDEC\ACTIVE_HDL\8.3\LICENSING_INSTALLATION_INSTRUCTIONS FOLDER AND PASTE IT SOMEWHERE IN THE HARD DISC AND UPDATE THE LM_LICENSE_FILE ENVIRONMENT VARIABLE. TO DO THIS, GO TO CONTROL PANEL--SYSTEM--SYSTEM--ADVANCED SYSTEM SETTINGS--ENVIRONMENT VARIABLES.CLICK NEW IN THE USER VARIABLE FIELD. WRITE LM_LICENSE_FILE IN THE VARIABLE NAME AND THE PATH FOR THE LICENSE FILE (WHERE YOU SAVED IT) IN THE VARIABLE VALUE. FOR EXAMPLE, SAY YOU HAVE INSTALLED ACTIVE-HDL 8.3 IN c:/ALDEC FOLDER AND SAVED THE LICENSE FILE IN THE SAME FOLDER, VARIABLE NAME WOULD BE LM_LICENSE_FILE AND VARIABLE NAME WOULD BE c:/ALDEC/license_ActiveHDL82.dat. 5) RUN ActiveHDL83sp1_incremental.exe FIRST AND THEN ActiveHDL83.2120.sp1_Update3_2011_06_10.exe TO RUN SERVICE PACKS AND UPDATES. THEY ARE IN EDA\SIMULATORS\ALDEC\ACTIVE_HDL\8.3\SERVICE_PACKS_&_UPDATE FOLDER. 6) RUN ActiveHDL83sp1_XilinxISE_8.2sp3_update2_VHDLLibraries.exe TO COMPILE VHDL GATE LEVEL LIBRARIES FOR XILINX (COMPATIBLE WITH XILINX 8.2) TO ENSURE PROPER POST-FIT SIMULATION FOR VHDL DESIGNS. IT IS IN EDA\SIMULATORS\ALDEC\ACTIVE_HDL\8.3\VENDOR_LIBRARIES_GATE_LEVEL\XILINX FOLDER. RUN ActiveHDL83sp1_XilinxISE_8.2sp3_update2_VerilogLibraries.exe TO COMPILE VERILOG HDL GATE LEVEL LIBRARIES FOR XILINX (COMPATIBLE WITH XILINX 8.2) TO ENSURE PROPER POST-FIT SIMULATION FOR VERILOG HDL DESIGNS. 7) RUN ActiveHDL83sp1_SYNOPSYS_FPGA_PRODUCTS_E-2010.09_VHDLLibraries.exe TO COMPILE VHDL GATE LEVEL LIBRARIES FOR SYNOPSYS. IT IS IN EDA\SIMULATORS\ALDEC\ACTIVE_HDL\8.3\VENDOR_LIBRARIES_GATE_LEVEL\SYNOPSYS FOLDER. OPTIONAL: 1. RUN ActiveHDL83sp1_XilinxISE_132_VHDLLibraries.exe TO COMPILE VHDL GATE LEVEL LIBRARIES FOR XILINX (COMPATIBLE WITH XILINX 13.1) TO ENSURE PROPER POST-FIT SIMULATION FOR VHDL DESIGNS. 2. RUN ActiveHDL83sp1_XilinxISE_132_VerilogLibraries.exe TO COMPILE VERILOG HDL GATE LEVEL LIBRARIES FOR XILINX (COMPATIBLE WITH XILINX 13.1) TO ENSURE PROPER POST-FIT SIMULATION FOR VERILOG HDL DESIGNS. 3. RUN ActiveHDL83sp1_XilinxISE_13.2_SCHLibraries.exe TO COMPILE XILINX SCHEMATIC LIBRARIES (COMPATIBLE WITH XILINX 13.1) TO ENSURE PROPER POST-FIT SIMULATION FOR SCHEMATIC DESIGNS. 4.RUN ActiveHDL83sp1_Altera_Quartus11.0_VHDLLibraries.exe TO COMPILE VHDL GATE LEVEL LIBRARIES FOR ALTERA (COMPATIBLE WITH QUARTUS II WEB EDITION 11.0) TO ENSURE PROPER Page 1

ACTIVE_HDL_8.3_README_RIZVI_SP12.txt POST-FIT SIMULATION FOR VHDL DESIGNS. 5. RUN ActiveHDL83sp1_Altera_Quartus11.0_VerilogLibraries.exe TO COMPILE VERILOG HDL GATE LEVEL LIBRARIES FOR ALTERA (COMPATIBLE WITH QUARTUS II WEB EDITION 11.0) TO ENSURE PROPER POST-FIT SIMULATION FOR VERILOG HDL DESIGNS. Page 2

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