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6.012 Electronic Devices and Circuits Formula Sheet for Final Exam, Fall 2003 Parameter Values: q = 1.

6x10 19 Coul 14 F/cm, o = 8.854 x10


Si

Periodic Table:
r,Si

= 11.7,
13

r,SiO 2

= 3.9

10

12

F/cm,
10

n i [ Si@R.T ] 10 cm kT /q 0.025 V ; (kT /q) ln10 1 m = 1x10 4 cm


3

SiO 2

3.5 x10

F/cm

0.06 V

III B Al Ga In

IV C Si Ge Sn

V N
P
As Sb

Drift/Diffusion:
Drift velocity : Conductivity : Diffusion flux : Einstein relation : sx =
m

Electrostatics:
Ex
dE(x) = (x) dx d ( x) = E (x) dx d 2 ( x) = (x) dx 2 E (x) = ( x) = (x) = 1 1 ( x)dx E (x)dx (x)dxdx

= q( e n + h p) C Fm = Dm m x Dm kT = q m

The Five Basic Equations:

Electron concentration : Hole concentraton : Electron current density : Hole current density : Poisson's equation :

n ( x, t ) 1 J e ( x, t) = gL (x, t) t q x p( x, t) 1 Jh (x,t) + = gL ( x, t) t q x

[n( x,t) p( x,t) [n(x,t) p(x,t)

n i2 ] r(T) n i2 ] r(T)

J e (x, t) = q e n( x, t)E (x,t) + qDe

n(x, t) x p(x, t) J h (x, t) = q h p( x, t)E (x,t) qDh x E (x, t) q + = [ p(x, t) n(x, t) + N d (x) N a (x)] x

Uniform doping, full ionization, TE

n - type, N d >> N a no Nd Na ND, po = n i2 n o ,


n

kT N D ln q ni kT N A ln q ni
dn' = gl (t) dt

p - type, N a >> N d po Na Nd NA , n o = n i2 po ,
p

Uniform optical excitation, uniform doping


n = n o + n' p = po + p' n' = p'

( po + n o + n') n' r
min

Low level injection, n',p' << p o + n o :

n' dn' + = gl (t) dt min

with

( po r)

Flow problems (uniformly doped quasineutral regions with quasi-static excitation and low level injection; p-type example): n'(x) 1 d 2 n'(x) = gL ( x) Minority carrier excess : Le De e 2 2 dx De Le dn'(t) Minority carrier current density : J e (x) qDe dx
Majority carrier current density : J h (x) = JTot J e ( x)
1 Dh Electric field : E x (x) J h (x) J e (x) q h po De dE x (x) Majority carrier excess : p'(x) n'( x) + q dx Non-uniformly doped semiconductor sample in thermal equilibrium

d 2 (x) q = {n i [e q ( x) kT e q (x ) kT ] [N d ( x) N a ( x)]} 2 dx n o ( x) = n ie q (x ) kT , po (x) = n ie q (x) kT , po (x)n o ( x) = n i2


Depletion approximation for abrupt p-n junction:
0 qN Ap ( x) = qN Dn 0 for for for for x < xp xp < x < 0 0 < x < xn xn < x N Ap x p = N Dn x n = kT N Dn N Ap ln q n i2 v AB )
Si

w(v AB ) =

Si

v AB ) (N Ap + N Dn ) q N Ap N Dn
b

E pk =

2q (

(N

N Ap N Dn
Ap

+ N Dn )

qDP (v AB ) = AqN Ap x p (v AB ) = A 2q

Si

v AB )

(N

N Ap N Dn
Ap

+ N Dn )

Ideal p-n junction diode i-v relation: n2 n2 n(-x p ) = i e qv AB / kT , n'(-x p ) = i (e qv AB / kT 1); N Ap N Ap


iD = A q n i2 Dh De + N Dn w n,eff N Ap w p,eff
-x p

p(x n ) = w m,eff =

[e

qv AB / kT

-1]
wn

Lm tanh [( w m x m ) Lm ] Lm Note : p'(x)

n i2 qv AB / kT n2 e , p'(x n ) = i (e qv AB / kT 1) N Dn N Dn wm x m if L m >> w m if L m ~ w m if L m << w m

qQNR,p -side = Aq
-w p

n'(x)dx,

qQNR,n -side = Aq p'(x)dx,


xn

n'(x) in QNRs

Ebers-Moll Model for Bipolar Junction Transistor (BJT) characterisitics (npn example;
no base width modulation):
w ihE D N De Dh = h AB B,eff iE = ihE + ieE = Aqn i2 + E [e qVBE / kT 1] ieE De N DE w E,eff N DE w E ,eff N AB w B,eff 2 2 w B ,eff w B ,eff De qV BE / kT 2 iC ieE (1 B ) = Aqn i 1](1 B ) with = [e B 2L2 N AB w B,eff 2De e e De iC (1 B ) iB ihE + B ieE = ieE ( E + B ) = Aqn i2 = [e qVBE / kT 1]( E + B ) F N AB w B ,eff iB ( E + B) Large Signal BJT Model in Forward Active Region (FAR) (npn; with base width mod):

iB (v BE ,vCE ) = IBS [e qv BE iC (v BE ,vCE ) =


o

kT

1]

with

I BS
o BS

[1+

vCE ] iB (v BE ,vCE ) = v BE,on

[e

1 DhE 1 DeB IES = Aqn i2 + w B ,eff N AB w E ,eff N DE ( o + 1) o + 1)


qv BE kT

1][1+ vCE ]

Break - point model :


MOS Capacitor:

0.6V , vCE ,sat

0.2V

Flat - band voltage : VFB vGB at which VFB =


p Si m
Threshold voltage : VT vGC at which VT (v BC ) = VFB 2
p Si

(0) = (0) =

p Si

p Si

+ v BC

Si

2 1/ 2 1 2 Si qN A 2 p Si v BC x DT (v BC ) = * Cox * Inversion layer sheet charge density : q* = Cox [vGC VT (v BC )] N * Accumulation layer sheet charge density : q* = Cox [vGB VFB (v BC )] P +

]}

[2

p Si

v BC

qN A

Gradual Channel Approx. for MOSFET characteristics (n-channel; no channel length mod.):

Valid for v BS 0, and v DS 0 :


iG (vGS ,v DS ,v BS )
= 0 and iB (vGS ,v DS ,v BS ) = 0
0 iD (vGS ,v DS ,v BS ) = W L with 1 W 2 L

e e * Cox [vGS VT (v BS )] 2

for for for


p Si

[vGS
1

VT (v BS )] < 0 < v DS VT (v BS )] < v DS 1

0<

[vGS

*
Cox vGS VT (v BS ) Si +

v DS v DS 2

0 < v DS < v BS

[vGS

VT (v BS )]

VT (v BS ) VFB 1+

1 2 SiqN A 2 * Cox
1/ 2

]}

1/ 2

1 * Cox 2 2

Si

qN A v BS

p Si

C* ox

ox

t ox

Large Signal MOSFET Model in Saturation (FAR) (n-channel; with base width mod.):
iG (vGS ,v DS ,v BS ) = 0 iB (vGS ,v DS ,v BS ) 0 2 K iD (vGS ,v DS ,v BS ) = [vGS VT (v BS )] [1+ v DS ] 2 1 W * 2 p Si + * 2 SiqN A 2 with K e C ox and VT = VFB L Cox

p Si

v BS

]}

1/ 2

Small signal linear equivalent circuits: p-n Diode

gd =

q IBS e
qVAB / kT kT

q ID kT
q Si N Ap 2(
d b

Cd = Cdp + Cdf , where Cdp (VAB ) = A q I [w p x p ] Cdf (VAB ) = D = gd kT 2De


2

VAB )
d

and

with

[w

xp]

2De
IC VA

BJT (in FAR)


gm q IC kT
b

g =

gm
o

go

IC
b

or
2 wB = 2 Dminority .in base

C = gm

+ B - E depletion capacitance, where

C = B - C depletion capacitance

MOSFET (in saturation)

gm

2K ID = K VGS - VT = gmb = gm = 2 K ID

2ID (VGS - VT ) with = 1 * Cox

go
Si

ID

or

ID VA

qN A q p VBS

Cgs =

2 * W L Cox Csb , Cgb , Cdb : depletion region capacitances 3 * * Cgd = W Cgd where Cgd is the gate - to - drain fringing and overlap capacitance per unit gate width

Single transistor analog circuit building block stages Bipolar:-based stages

Voltage gain, Av gm Common emitter (= gm rl ') [ go + gl ] gm Common base (= gm rl ') [go + gl ] [ gm + g ] Emitter follower 1 [ gm + g + go + gl ] Emitter degeneration r - l (series feedback) RF [ gm G F ] g R Shunt feedback m F [ go + G F ]
MOSFET-based stages
Voltage gain, Av Common source Common gate Source follower Source degeneration (series feedback) Shunt feedback gm rl '

Current gain, Ai gl [ go + gl ] 1 gl [ go + gl ]

Input resistance, R i r

Output resistance, R o 1 ro = go

r + 1]

+ 1] ro rt + r [ + 1] ro

r + [ + 1] rl ' r + [ + 1] RF

gl GF

1 g + GF [1 Av ]

ro RF =

1 [go + GF ]

Current gain, Ai 1 gl GF

Input resistance, R i 1 [ gm + gmb ] RF GF [1 Av ]

[ gm + gmb ] rl '
gm 1 [ gm + go + gl ] r - l
RF [ gm GF ] g R m F [ go + GF ]

Output resistance, R o 1 ro = go [ g + gmb + go ] ro 1+ m gt 1 1 [ gm + go + gl ] gm


ro ro RF = 1 [go + GF ]

OCTC/SCTC
1 1

OCTC estimation of

HI

HI i

[ i]

=
i

RiCi

with R i defined as the equivalent resistance in parallel with Ci , with all other parasitic device C's (C 's, C 's, C gs 's, C gd 's, etc.) open circuited.
1

SCTC estimation of

LO

LO

=
j

[R C ]
j j

with R j defined as the equivalent resistance in parallel with Cj, with all other biasing and coupling C's (C I 's, CO 's, C E 's, CS 's, etc.) short circuited.

Difference- and Common-mode signals Given two signals, v1 and v2, we can decompose them into two new signals, one (vC) that is common to both v1 and v2, and one (vD) that makes an equal, but opposite polarity, contribution to v1 and v2: vD v [v + v ] v D v1 v 2 and vC 1 2 v1 = vC + D and v 2 = vC 2 2 2 CMOS performance Transfer characteristic
VLO = 0, V HI = VDD , ION = 0, IOFF = 0 V Symmetry : VM = DD and N ML = N MH K n = K p and VTp = VTn 2 Minimum size gate : Ln = L p = Lmin , W p = ( n p )W n , W n = W min In general :

Switching trimes and Gate delay


Ch arg e

Disch arg e

* * CL = n (W n Ln + W p L p ) Cox = 3nW min Lmin Cox Min.Cycle

2VDD CL 2 K n [VDD VTn ]

assumes

=2

Ch arg e

Disch arg e

12nL VDD 2 VTn ] e [VDD

2 min

:Power disippation
Pave @ Max. f = CLV PDave @ Max. f =

2 DD

f max CLV

2 DD

Min.Cycle

* W min CoxVDD [VDD VTn ] Lmin e ox

Pave @ Max. f Inverter area

Pave @ Max. f W min Lmin

VDD [VDD VTn ] t ox L2 min