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  • Assignment 1

    Transféré par

    Nidhi Gandhi
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    The document is an assignment for a VLSI Technology & Design course that contains 10 questions covering topics such as the Y chart, VLSI design styles, FPGA architecture, design quality criteria, testing vs. verification, PLA, PAL, CPLD definitions and structure, gate array vs standard cell design, hierarchy, regularity, modularity, locality, Moore's Law in chip design, and advantages of VLSI technology. Students are asked to answer the questions and submit their responses by February 5th, 2012.

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    The document is an assignment for a VLSI Technology & Design course that contains 10 questions covering topics such as the Y chart, VLSI design styles, FPGA architecture, design quality criteria, testing vs. verification, PLA, PAL, CPLD definitions and structure, gate array vs standard cell design, hierarchy, regularity, modularity, locality, Moore's Law in chip design, and advantages of VLSI technology. Students are asked to answer the questions and submit their responses by February 5th, 2012.

    Droits d'auteur :

    Attribution Non-Commercial (BY-NC)
    Téléchargez comme PDF, TXT ou lisez en ligne sur Scribd
    Signaler comme contenu inapproprié
    24 vues1 page

    Assignment 1

    Transféré par

    Nidhi Gandhi
    The document is an assignment for a VLSI Technology & Design course that contains 10 questions covering topics such as the Y chart, VLSI design styles, FPGA architecture, design quality criteria, testing vs. verification, PLA, PAL, CPLD definitions and structure, gate array vs standard cell design, hierarchy, regularity, modularity, locality, Moore's Law in chip design, and advantages of VLSI technology. Students are asked to answer the questions and submit their responses by February 5th, 2012.

    Droits d'auteur :

    Attribution Non-Commercial (BY-NC)
    Téléchargez comme PDF, TXT ou lisez en ligne sur Scribd
    Signaler comme contenu inapproprié
    sur 1

    CHAROTAR UNIVERSITY OF SCIENCE AND TECHNOLOGY Faculty of Technology and Engineering

    Assignment-1
    Subject: VLSI Technology & Design (EC311) Year: 2012 Neetirajsinh Chhasatia Sem: VI (E&C)

    1. Explain the Y chart (D Gajski chart). 2. Discuss the impact of different VLSI design styles upon the design cycle time and the achievable circuit performances. 3. Explain the architecture of FPGA. 4. Which are the different criteria to measure the design quality? 5. What is the difference between testing and verification?

    6. 7. 8. 9.

    Define terms: PLA, PAL, CPLD, and FPGA. Draw & Explain basic structure of CPLD also explains PAL like block in brief. Compare Gate array design and standard cell based design. Define the following a. Hierarchy b. Regularity c. Modularity d. Locality e. Moores Law

    10. List out advantages of VLSI technology.

    Last date of submission: 5/2/2012

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