ICCA Volume 3

I nt er nat i onal Conf er ence on Comput er Appl i cat i ons 2012
Volume 3

I nt er nat i onal Conf er ence on Comput er Appl i cat i ons 2012
Volume 3
In association with
Association of Scientists, Developers and Faculties (ASDF), India
Association of Computer Machinery(ACM)
Science & Engineering Research Support society (SERSC), Korea

Digital Computing Systems, Electronic Data Systems, Embedded Control Systems

27-31 January 2012
Pondicherry, India

Editor-in-Chief
K. Kokula Krishna Hari

Editors:
E Saikishore, T R Srinivasan, D Loganathan,
K Bomannaraja and R Ponnusamy

Published by

Association of Scientists, Developers and Faculties
Address: 27, 3
rd
main road, Kumaran Nagar Extn., Lawspet, Pondicherry-65008
Email: admin@asdf.org.in || www.asdf.org.in

International Conference on Computer Applications (ICCA 2012)
VOLUME 3

Editor-in-Chief: K. Kokula Krishna Hari
Editors: E Saikishore, T R Srinivasan, D Loganathan, K Bomannaraja and R Ponnusamy

Copyright 2012 ICCA 2012 Organizers. All rights Reserved

This book, or parts thereof, may not be reproduced in any form or by any means, electronic or mechanical, including
photocopying, recording or any information storage and retrieval system now known or to be invented, without written
permission from the ICCA 2012 Organizers or the Publisher.

Disclaimer:
No responsibility is assumed by the ICCA 2012 Organizers/Publisher for any injury and/ or damage to persons or
property as a matter of products liability, negligence or otherwise, or from any use or operation of any methods, products
or ideas contained in the material herein. Contents, used in the papers and how it is submitted and approved by the
contributors after changes in the formatting. Whilst every attempt made to ensure that all aspects of the paper are uniform
in style, the ICCA 2012 Organizers, Publisher or the Editor(s) will not be responsible whatsoever for the accuracy,
correctness or representation of any statements or documents presented in the papers.

ISBN-13: 978-81-920575-6-9
ISBN-10: 81-920575-6-9

PREFACE

This proceeding is a part of International Conference on Computer Applications 2012 which was
held in Pondicherry, India from 27-Dec-2012 and 31-Dec-2012. This conference was hosted by
Techno Forum Research and Development Centre, Pondicherry in association with Association of
Computer Machinery(ACM), Association of Scientists, Developers and Faculties (ASDF), India,
British Computer Society (BCS), UK and Science and Engineering Supporting Society (Society),
Korea.
The world is changing. From shopping malls to transport terminals, aircraft to passenger ships, the
infrastructure of society has to cope with ever more intense and complex flows of people. Today,
more than ever, safety, efficiency and comfort are issues that must be addressed by all designers. The
World Trade Centre disaster brought into tragic focus the need for well-designed evacuation systems.
The new regulatory framework in the marine industry, acknowledges not only the importance of
ensuring that the built environment is safe, but also the central role that evacuation simulation can
play in achieving this.
An additional need is to design spaces for efficiency ensuring that maximum throughput can be
achieved during normal operations and comfort ensuring that the resulting flows offer little
opportunity for needless queuing or excessive congestion. These complex demands challenge
traditional prescriptive design guides and regulations. Designers and regulators are consequently
turning to performance-based analysis and regulations facilitated by the new generation of people
movement models.
When a greater changes are achieved these past years, still more is to be achieved which still seems
to be blue sky of 1970s. But for all the challenges, capabilities continue to advance at phenomenal
speed. Even three years ago it may have been considered a challenge to perform a network design
involving the evacuation of 45,000 people from a 120 story building, but with todays sophisticated
modelling tools and high-end PCs, this is now possible. Todays challenges are much more ambitious
and involve simulating the movement and behaviour of over one million people in city-sized
geometries. The management of these network is also easy and more specifically all the 45,000
people can be monitored by a single person sitting in his cabin. This has been the evidence of the
development these days.
As such, the conference represents a unique opportunity for experts and beginners to gain insight into
the rapidly.
Also I would like to thank all the co-operators for bringing out these proceedings for you which
majorly includes my mom Mrs. K. Lakshmi and my dad Mr. J. Kunasekaran. Apart from them my
biggest worthy gang of friends including Dr. S. Prithiv Rajan, Chairman of this conference, Dr. R. S.
Sudhakar, Patron of this Conference, Dr. A. Manikandan and Dr. S. Avinash, Convener of this
conference, Dr. E. Sai Kishore, Organizing Secretary of this Conference and the entire team which
worked along with me for the rapid success of the conference for past 1 year from the date of
initiating this Conference. Also I need to appreciate Prof. T. R. Srinivasan and his team of Vidyaa
Vikas College of Engineering and Technology for helping to make the publication job easy.
Finally, I thank my family, friends, students and colleagues for their constant encouragement and
support for making this type of conference.
-- K. Kokula Krishna Hari
Editor-in-Chief

Organizing Committee

Chief Patron
Kokula Krishna Hari K, Founder & President, Techno Forum Group, Pondicherry, India

Patron
Sudhakar R S, Chief Executive Officer(CEO), Techno Forum Group, Pondicherry, India

Chairman
Prithiv Rajan S, Chairman & Advisor, Techno Forum Group, Pondicherry, India

Convener
Manikandan A, Chief Human Resources Officer(CHRO), Techno Forum Group, India

Organizing Secretary
Sai Kishore E Chief Information Officer, Techno Forum Group, India.
Operations Chair
G S Tomar Director, MIR Labs, Gwalior, India

International Chair
Maaruf Ali Executive Director, (ASDF) - Europe, Europe

Hospitality
Muthualagan R Alagappa College of Technology, Chennai

Industry Liaison Chair
Manikandan S Executive Secretary, Techno Forum Group, India

Technical Panels Chair
Debnath Bhattacharyya, Executive Director, (ASDF) - West Bengal, India

Technical Chair
Samir Kumar Bandyopadhyay Former Registrar, University of Calcutta, India
Ponnusamy R President, Artificial Intelligence Association of India, India
Srinivasan T R,Vice-Principal, Vidyaa Vikas College of Engineering and Technology

Workshops Panel Chair
Loganathan D Department of Computer Science and Engineering, Pondicherry
Engineering College, India

MIS Co-Ordinator
Harish G Trustee, Techno Forum Research and Development Centre, Pondicherry

Academic Chair
Bommanna Raja K, Principal, Excel College of Engineering for Women, India
Tai-Hoon Kim Professor & Chairman, Dept. of Multimedia, Hanmam University, Korea

TECHNICAL REVIEWERS
Adethya Sudarsanan Cognizant Technology Solutions, India
Ainuddin University of Malaya, Malaysia
Ajay Chakravarthy University of Southampton, UK
Alessandro Rizzi University of Milan, Italy
Al-Sakib Khan Pathan International Islamic University, Malaysia
Angelina Geetha B S Abdur Rahman University, Chennai
Aramudhan M PKIET, Karaikal, India
Arivazhagan S Mepco Schlenk Engineering College, India
Arokiasamy A Anjalai Ammal Mahalingam Engineering College, India
Arul Lawrence Selvakumar A Adhiparasakthi Engineering College, India
Arulmurugan V Pondicherry University, India
Aruna Deoskar Institute of Industrial & Computer Management and Research, Pune
Ashish Chaurasia Gyan Ganga Institute of Technology & Sciences, Jabalpur, India
Ashish Rastogi Guru Ghasidas University, India
Ashutosh Kumar Dubey Trinity Institute of Technology & Research, India
Avadhani P S Andhra University, India
Bhavana Gupta All Saints College of Technology, India
Bing Shi University of Southampton, UK
C Arun R. M. K. College of Engineering and Technology, India
Chandrasekaran M Government College of Engineering, Salem, India
Chandrasekaran S Rajalakshmi Engineering College, Chennai, India
Chaudhari A L University of Pune, India
Ching-Hsien Hsu Chung Hua University, Taiwan
Chitra Krishnamoorthy St Josephs College of Engineering and Technology, India
Christian Esteve Rothenberg CPqD (Telecom Research Center), Brazil
Chun-Chieh Huang Minghsin University of Science and Technology, Taiwan
Darshan M Golla Andhra University, India
Elvinia Riccobene University of Milan, Italy
Fazidah Othman University of Malaya, Malaysia
Fulvio Frati University of Milan, Italy
G Jeyakumar Amrita School of Engineering, India
Geetharamani R Rajalakshmi Engineering College, Chennai, India
Gemikonakli O Middlesex University, UK
Ghassemlooy Z Northumbria University, UK
Gregorio Martinez Perez University of Murcia, Spain
Hamid Abdulla University of Malaya, Malaysia
Hanumantha Reddy T Rao Bahadur Y Mahabaleswarappa Engineerng College, Bellary
Hari Mohan Pandey NMIMS University, India
Helge Langseth Norwegian University of Science and Technology, Norway
Ion Tutanescu University of Pitesti, Romania
Jaime Lloret Universidad Politecnica de Valencia, Spain
Jeya Mala D Thiagarajar College of Engineering, India
Jinjun Chen University of Technology Sydney, Australia
Joel Rodrigues University of Beira Interior, Portugal
John Sanjeev Kumar A Thiagarajar College of Engineering, India
Joseph M Mother Terasa College of Engineering & Technology, India
K Gopalan Professor, Purdue University Calumet, US
K N Rao Andhra University, India
Kachwala T NMIMS University, India
Kannan Balasubramanian Mepco Schlenk Engineering College, India
Kannan N Jayaram College of Engineering and Technology, Trichy, India
Kasturi Dewi Varathan University of Malaya, Malaysia
Kathirvel A Karpaga Vinayaga College of Engineering & Technology, India
Kavita Singh University of Delhi, India
Kiran Kumari Patil Reva Institute of Technology and Management, Bangalore, India
Krishnamachar Sreenivasan IIT-KG, India
Kumar D Periyar Maniammai University, Thanjavur, India
Lajos Hanzo Chair of Telecommunications, University of Southampton, UK
Longbing Cao University of Technology, Sydney
Lugmayr Artur Texas State University, United States
M HariHaraSudhan Pondicherry University, India
Maheswaran R Mepco Schlenk Engineering College, India
Malmurugan N Kalaignar Karunanidhi Institute of Technology, India
Manju Lata Agarwal University of Delhi, India
Mazliza Othman University of Malaya, Malaysia
Mohammad M Banat Jordan University of Science and Technology
Moni S NIC - GoI, India
Mnica Aguilar Igartua Universitat Politcnica de Catalunya, Spain
Mukesh D. Patil Indian Institute of Technology, Mumbai, India
Murthy B K Department of Information and Technology - GoI, India
Nagarajan S K Annamalai University, India
Nilanjan Chattopadhyay S P Jain Institute of Management & Research, Mumbai, India
Niloy Ganguly IIT-KG, India
Nornazlita Hussin University of Malaya, Malaysia
Panchanatham N Annamalai University, India
Parvatha Varthini B St Josephs College of Engineering, India
Parveen Begam MAM College of Engineering and Technology, Trichy
Pascal Hitzler Wright State University, Dayton, US
Pijush Kanti Bhattacharjee Assam University, Assam, India
Ponnammal Natarajan Rajalakshmi Engineering College, Chennai, India
Poorna Balakrishnan Easwari Engineering College, India
Poornachandra S RMD Engineering College, India
Pradip Kumar Bala IIT, Roorkee
Prasanna N TMG College, India
Prem Shankar Goel Chairman - RAE, DRDO-GoI, India
Priyesh Kanungo Patel Group of Institutions, India
Radha S SSN College of Engineering, Chennai, India
Radhakrishnan V Mookamibigai College of Engineering, India
Raja K Narasu's Sarathy Institute of Technology, India
Ram Shanmugam Texas State University, United States
Ramkumar J VLB Janakiammal college of Arts & Science, India
Rao D H Jain College of Engineering, India
Ravichandran C G R V S College of Engineering and Technology, India
Ravikant Swami Arni University, India
Raviraja S University of Malaya, Malaysia
Rishad A Shafik University of Southampton, UK
Rudra P Pradhan IIT-KGP, India
Sahaaya Arul Mary S A Jayaram College of Engineering & Technology, India
Sanjay Chaudhary DA-IICT, India
Sanjay K Jain University of Delhi, India
Satheesh Kumar KG Asian School of Business, Trivandrum, India
Saurabh Dutta Dr B C Roy Engineering College, Durgapur, India
Senthamarai Kannan S Thiagarajar College of Engineering, India
Senthil Arasu B National Institute of Technology - Trichy, India
Senthil Kumar A V Hindustan College, Coimbatore, India
Shanmugam A Bannari Amman Institute of Technology, Erode, India
Sharon Pande NMIMS University, India
Sheila Anand Rajalakshmi Engineering College, Chennai, India
Shenbagaraj R Mepco Schlenk Engineering College, India
Shilpa Bhalerao FCA Acropolis Institute of Technology and Research
Singaravel G K. S. R. College of Engineering, India
Sivabalan A SMK Fomra Institute of Technology, India
Sivakumar D Anna University, Chennai
Sivakumar V J National Institute of Technology - Trichy, India
Sivasubramanian A St Josephs College of Engineering and Technology, India
Sreenivasa Reddy E Acharya Nagarjuna University, India
Sri Devi Ravana University of Malaya, Malaysia
Srinivasan A MNM Jain Engineering College, Chennai
Srinivasan K S Easwari Engineering College, Chennai, India
Stefanos Gritzalis University of the Aegean, Greece
Stelvio Cimato University of Milan, Italy
Subramanian K IGNOU, India
Suresh G R DMI College of Engineering, Chennai, India
Tulika Pandey Department of Information and Technology - GoI, India
Vasudha Bhatnagar University of Delhi, India
Venkataramani Y Saranathan College of Engineering, India
Verma R S Joint Director, Department of Information and Technology - GoI, India
Vijayalakshmi K Mepco Schlenk Engineering College, India
Vijayalakshmi S Vellore Institute of Technology, India
Ville Luotonen Hermia Limited, Spain
Vimala Balakrishnan University of Malaya, Malaysia
Vishnuprasad Nagadevara Indian Institute of Management - Bangalore, India
Wang Wei University of Nottingham, Malaysia
Yulei Wu Chinese Academy of Sciences, China

Part I
Proceedings of the Second International Conference on
Computer Applications 2012
ICCA 12
Volume 3
Proc. of the Second International Conference on Computer Applications 2012 [ICCA 2012] 1
www.asdf.org.in 2012 :: Techno Forum Research and Development Centre, Pondicherry, India www.icca.org.in
Proc. of the Intl. Conf. on Computer Applications
Volume 1. Copyright 2012 Techno Forum Group, India.
ISBN: 978-81-920575-6-9 :: doi: 10.73494/ISBN_0768
ACM #: dber.imera.10.73494
Understanding the Digital Forensics: A Review

Shipra Maurya
Shri Ramswaroop Memorial Group of Professional Colleges
Lucknow.
Abstract-- Digital Forensics is a discipline that involves several

techniques and tools used for analyzing the digital devices to
find evidences. Digital Forensics differ from network forensics
in the way that former deals with the data residing on a stand
alone system whereas latter operate on data spread over
network. Computer forensic requires experience, competence
and vast expertise to determine what to find, where to find
what is sought and what indicators to look for that suggest
what is hidden and where. Digital Forensics has marked its
position mainly because of the variety of computer crimes
taking place on small scale as well as large scale. The
sensitivity of computer data or information for which crime
was committed measures the loss caused.
The forensic science involves process of utilizing the
scientific knowledge for gathering, analyzing, preserving and
reporting the digital evidence.

Keywords: Digital Devices; Forensics Process; Acquisition
and Seizure; Presentation; Forensics investigation Tools and
Methodologies;
I. INTRODUCTION
In the current scenario Digital Forensics is holding its
position due to the computer crimes taking place. Computer
crimes that occur are on small scale as well as large scale. It
is dependent on the sensitivity of information or data for
which the crime has been committed about the loss caused.
Digital Forensics helps deal in with digital frauds,
investigation of digital devices, forgeries and a wide variety
of crimes. It uses scientific knowledge to collect analyze and
present the evidence to the court. So we can define the
Digital Forensics as - A process that involves capturing and
processing, then preserving and analyzing the information
obtained from evidence this may be a system, network
,application or other computing resources. Digital
Forensics deals with determining the source of an attack on
these resources and also determining the crimes happening
to a system against law.
There is another term used to counter part forensics
Anti-forensics. Anti-Forensics deals in with hiding the
computer crime being committed. It can be understood in
one sentence as Making it difficult for anyone find you and
impossible for them to prove the found you.
This paper deals in with Digital Forensics only.
Structural engineering, Pathology, serology or analysis of
digital device are all methods used in forensic science.
Digital Forensics involves investigation of evidence into
several steps. It includes: Acquisition, Authentication,
Analysis, Documentation and Presentation. However, these
steps are broadly categorized into three categories:
Acquisition, Analysis and Reporting.
A. Acquisition
In the process of Digital Forensics acquisition of the
evidence is the foremost step to be carried out. This is also
sometimes, referred to as Imaging. This step involves
acquiring the evidence, its recognition, collection and
documentation. This phase saves the state of a digital system
or creates an image of the digital evidence so that it can be
later analyzed. To acquire information from evidence
several forensic tools are used. Digital evidence is searched
and seizure to investigate information / data from it.
B. Authentication & Analysis
Analysis phase of forensics investigation identifies the
pieces of evidence from the acquired data. This involves
examining the contents and recovering information.
Authentication of digital evidence is also involved in digital
forensics process. This aims at verifying integrity of digital
evidence. A cryptographic hash algorithm for authentication
is used. The functions performed in the acquisition and
analysis phases are somewhat similar because of the
technological issued involved. This phase was referred to as
an in-depth systematic search of evidence related to
suspected crime by International Journal of Digital
Evidence (in 2002) [1] [2] [3].
Various analysis tools are used by investigators to aid
with viewing and recovering information. This analysis can
be live analysis, analysis for deleted files, cross drive
analysis and others. During the analysis phase investigator
recovers information from the digital evidence using
numerous techniques and tools. For example EnCase
Forensics Edition by Guidance Software delivers advanced
features for conducting large scale and complex
investigations with accuracy and efficiency. The tools
provided with this support

analysis of deleted files,
unallocated space, file slack etc for a Hard Drive. F.I.R.E.
(Forensics and Incident Response Environment) by DMZ
Services Inc. also provides an immediate environment to
perform forensics analysis, incident response, data recovery
etc and supports live forensics/Analysis on win32, sparc
Solaris and x86 Linux hosts.
Access Data Forensics Toolkit (FTK) by AccessData
Corporation, Forensics Server Project (FSP) by Harlan
Carvey, FoRK (Forensics or Rescue Kit) by Vital Data etc.
are some examples of Forensics/Analysis tools. However,
numerous others exist.
C. Documentation & Reporting
Digital Forensics deals with forensics/analysis of digital
evidence and reporting this analysis as a Document is the
most essential task. So, this Reporting phase involves two
sub tasks: Documentation and Reporting. After the analysis
is being performed on the digital device and evidences are
generated, all the evidences being recovered are documented
(in the form of Report).The Documented Reports are then
presented to the court.
II. NEED FOR FORENSICS
Digital Forensics is for those people who who got to like
law enforcement, are very curious and want to follow leads
when things just dont look right. Its also a job that requires
Mental toughness to deal with darker, sometimes intensely
graphic side of crime. There has been imposed various laws
to check out crimes but still the crime exists and it is hard to
find who committed the crime. Digital forensics help
overcome such difficulties. Digital forensics includes all its
major areas mobile forensics, computer forensics network
forensics etc.
Forensics is demanded in its various branches:
Computer Forensics, Mobile Forensics and network
forensics. These branches need the forensics due to
following reasons:
Digital Fraud
Unauthorized Data Duplication
Bankruptcy Data Investigation
Private Investigation of Personal Computer
Private Investigation of Cell phone/Mobile Phone
Forgeries
IP Theft
Industrial Espionage
Breach of Contract
Computer Break-ins
Phone Phreaking'
Digital Pornography
Inappropriate Internet Usage
Internet Abuse
Inappropriate Email Usage
E-Stalking
III. PRIMARY GOALS OF FORENSIC COMPUTING
The primary goals of forensics can be understood as follows:
Forensics computing help participants determine what
undesirable events occurred, if any.
This field of investigation aims to gather, process, store,
and preserve evidence to support the prosecution of the
culprit(s), if desired and to use that knowledge to
prevent future occurrences[9].
Forensics investigation also focuses to determine the
motivation and intent of the attackers.
IV. DIGITAL FORENSIC TOOLS
There exists thousands of Forensics tools available based on
Platform, type of Usage etc. Some of the tools are listed
below:
a.ENCASE FORENSIC Edition by Guidance Software
EnCase Forensic Edition is an intuitive GUI based tool for
digital forensics and investigations. Its Deluxe edition is also
available that provide its user with a complete packages of
tools like Fastbloc Software Edition (A write-blocking
solution for acquisition of USB, IDE, SCSI media etc.),
EnCase Decryption Suite (to search and collect evidence
from encrypted volumes, drives and files), EnCase Physical
Disk Emulator (to support mount evidence as local disk for
further examination using third party tools) and many others
tools.
b.AccessData Forensic Toolkit (FTK) by Access Data
Corporation
AccessData Forensic ToolKit also called FTK
features complete and thorough examination of the evidence
and allows filtering and search functionality [10]. It is also
recognized by law enforcement and corporate professionals
as the leading forensic too for email analysis. It provides us
with user interface, Decryption, bookmarking, reporting etc.
It recovers instant messaging chat logs and supports instant
messaging applications.
c.Autopsy Forensic Browser by Brian Carrier
Autopsy Forensics Browser provides GUI to the
command line investigation analysis tools. It is an open
source tool. This tool can connect you to the Autopsy Server
using any platform. This tool allows dead analysis, live
analysis of the evidence. It is written in Perl and runs on
Linux, Mac OS X, and Solaris etc.
d.Computer Incident Response Suite, by New
Technology, Inc.

This tool is compiled to aid corporate and government
computer specialist deal with the potential risks involving
malicious attacks, criminal attacks and corporate policy
abuses. This suite includes many things within it: CopyQM
(A tested & certified tool from US DoD used to create
duplicates of frequently used floppy diskettes in incident
responses, CRCMd5 (A file hashing program for
authentication),Filter N (Used to identify patterns in data
source using Fuzzy Logic), Seized tool (Used to lock and
secure evidence computers) and many other tools[7][8].
a.Data Elimination Suite by New Technology, Inc.
This tool provides supports in dealing with elimination
of sensitive data and to validate that the data was securely
erased. This suite also compile within it tools like CopyQM,
DiskScrub (For elimination of Data), GetFree (to identify
data stored in Unallocated (erased) file spaces, TextSearch
NT (To identify graphics, compressed Files on Windows
NT/XP based systems) etc.
b.Microsoft Sysinternal Suite by Microsoft Technet
This suite is developed by Microsoft Technet. This suite
bundles various troubleshooting utilities: AccessChk,
LiveKd, LoadOrder, LogonSessions, NTFSInfo, Autoruns,
TCPView, VolumeID, PsKill, PsInfo, PsExec, ProcDump,
Handle and many more.
c.MicroSystementaion XRY/XACT
This tool is used for Mobile Forensics. This tool can be
used on any Windows PC. XRY can recover Data from
thousands of different mobile devices (SmartPhones, GPS
navigation units, 3G Modems, Portable music players,
Tablet processors etc) including deleted information. It also
allows configuring reports of the analysis.

d.FoRK by Vital Data
This toolkit i.e. Forensics and Rescue Toolkit is a
LiveCD that has been created by Knoppix. This tool is used
for Linux based Systems. It provides its investigators with
an imaging mode environment and a preview mode
environment.
eF.I.R.E by DMZ Services
The Forensics and Incident Response Environment is a
portable CDROM based tool. It provides an immediate
environment to perform the forensic analysis, data recovery
and incident response. It also supports live forensic on
Solaris, Win32 and x86 Linux Hosts.
f.Forensic Server Project by Harlan Carvey
The Forensic Server Project is a concept tool that
retrieves volatile data from potentially Compromised
Systems. The FSP consists of Perl scripts and other third
party utilities [6]. The Server component of the FSP run on
an investigator or administrators system, and handles all
data storage and activity logging. The client components are
burned to a CD and run from CD drive of victim system.
The FSP is designed to be used for forensic audits of
Windows based Systems.
V. SUMMARY
Digital Data is fragile, complex but must be preserved and
authenticated. To take the compromised System out of box
Digital Forensics help. Also to determine things those have
potentially being put on system forensics provides
methodologies. Forensics also investigates what additional
files other than usual are there and reviews unexpected
things and as a result it documents and reports these
investigations.
Digital forensics is a new discipline which is used
for criminal and civil investigations. There are researches
going on to develop the new and best tools and procedures.
In this technologically growing era digital forensics is being
modified with new advancements and methodologies so that
forensics and Investigation of the digital evidence can be
made using best practices.
REFERENCES
[1] Brian Carrier. Open Source Digital Forensics Tools. The legal
Argument.
http://www.digitalevidence.org/papers/opensrc_legal.pdf
[2] Allen C. Johnston. Mississippi University. Computer Forensics
Using EnCase for Forensics Investigations.
http://www.informationinstitute.org/security/3rdConf/Proceedi
ngs/19.pdf
[3] Kellan Alley. Computer Forensics. Login Magazine Article
.Volume 27. http://www.usenix.org/publications/login/2002-
08/pdfs/kenneally.pdf
[4] Access Data Inc. Forensic Toolkit: Sales Promotion Summary.
http://accessdata.com/media/en_us/print/techdocs/Forensic%20
Toolkit.pdf
[5] http://www.cyberlawsindia.net/computer-forensics.html
[6] Pedro Aarn Hernndez valos, Claudia Feregrino Uribe,
Roger Luis Velzquez, Ren A. Cumplido Parra. Watermarking
Based on Iterated Function Systems. IEEE Proceedings of the
Magnum Conference on Computing. Por aparecer. 2007.
[7] D. R. Stinson. Cryptography: Theory and Practice. CRC Press.
2006.
[8] Forte B., Vrscay E.R. Theory of Generalized Fractal
Transforms. Fractal Image Encoding and Analysis, July, 1995.
[9] Gilbert J.W. Modern Algebra with Application. John Wiley and
Sons. 1976.
[10] Neal Koblitz. A Course in Number Theory and Cryptography.
Springer, 1994.
ISBN: 978-81-920575-6-9 :: doi: 10.73501/ISBN_0768
Design Of Parallel Vector/Scalar Floating Point Co-Processor For Reconfigurable
Architecture
E.MANIKANDAN
Pg scholar
veltech multitech dr.rangarajanr dr.sakunthala engg college
chennai,tamilnadu-600 054 india

Abstract- Current FPGA soft processor systems use
dedicated hardware modules or accelerators to speed up data-
parallel applications. This work explores an alternative
approach of using a soft vector processor as a general-
purpose accelerator. Due to the complexity and expense of
floating point hardware, these algorithms are usually
converted to fixed point operations or implemented using
floating-point emulation in software. As the technology
advances, more and more homogeneous computational
resources and fixed function embedded blocks are added to
FPGAs and hence implementation of floating point hardware
becomes a feasible option. In this research we have
implemented a high performance, autonomous floating point
vector co-processor (FPVC) that works independently within
an embedded processor system. We have presented a unified
approach to vector and scalar computation, using a single
register file for both scalar operands and vector elements. The
FPVC is completely autonomous from the embedded
processor(Softcore), exploiting parallelism and exhibiting
greater speedup than alternative vector processors. The
FPVC supports scalar computation so that loops can be
executed independently of the main embedded processor.

Keyworrds: Co-Processor, Parallelism Floating Point Unit,
FPGA, Softcore

I INTRODUCTION
Reconfigurable hardware bridges a gap between
ASICs (Application Specific Integrated Circuits) and
microprocessor based systems. Recently, there has been an
increased interest in using reconfigurable hardware for
multimedia, signal processing and other computationally
intensive embedded processing applications. These
applications perform floating point arithmetic computation
for high data accuracy and high performance.
Reconfigurable hardware allows the designer to customize
the computational units in order to best match application
requirements and at the same time, optimize device
resource utilization. Because of these advantages,
extensive research has been done to efficiently implement
floating point computations on the reconfigurable
hardware. Floating point (FP) computations can be
categorized in three classes:

1. Software library
2. General purpose floating point unit
3. Application specific floating point data path
Embedded RAMs in FPGAs provide large storage
structures. While the capacity of a given block RAM is
fixed, multiple block RAMs can be connected through the
interconnection network to form larger capacity RAM
storage. A key limitation of block RAMs is they have only
two access ports allowing just two simultaneous reads or
writes. The multiply-accumulate blocks, also referred to as
DSP blocks, have dedicated circuitry for performing
multiply and accumulate operations. These DSP blocks can
also perform addition, subtraction and barrel shifter
functions
The major FPGA companies provide embedded cores, both
hard and soft, for use with their processors. Altera has the
Nios II soft core and Xilinx offers the MicroBlaze soft
and PowerPC hard cores on their FPGAs. All these large
embedded logic blocks make more efficient use of on-chip
FPGA resources. However, they can also waste on-chip
resources if they are not being used. In this work, we will
explore the utilization of these embedded blocks on Xilinx
Virtex FPGAs in implementing floating-point operations
and vector processing

II RELATED WORK

The implementation of a floating point unit in general
purpose computing is extremely common but it makes an
interesting case study for an FPGA based reconfigurable
computing system. Up to now there have been many
research efforts applied to the implementation of an FPGA
based Floating point unit. This research can be categorized
based on the type of communication with main processor,
precision support, number of computation units and level
of autonomy.
One of the earliest works in this area is done by Fagin et
al.[1] They have implemented IEEE-754 standard
compliant floating point adder and multiplier function on
the FPGA for design space exploration. They found that
the floating point unit substantially improves performance,
but technology limitations made it difficult to implement
floating point units at that time.
Recently, Pittman et[2] al.have implemented a custom
floating point unit (CFPU) which is compliant with the
IEEE 754 standard and improves floating-point intensive
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The Xilinx
precision floa
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implements
comparison. F
available as
integers to flo
instantiated,
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has a floating
floating-point
precision. Flo
add, subtract
multiply-add
the PowerPC
Unit (APU)
floating point
a.Vector proc
Most curr
sets. A scala
separate opco
operation to
vector instruc
chapter review
used in the res
execution arch
b.Vector Opera
The code
which forms
Subprograms
vectors and x
SAXPY/DAX
for (i=0; i
Y[i] = A[i
1. Load elemen
2. Load elemen
3. Load scalar
4. Multiply A
5. Add result o
6. Store result
For a sca
performed in
instruction set
on multiple d
value. This ve
a vector leng
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is equal to the
then the SAXP
performance.
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various trade
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xs MicroBlaz
ating point un
he embedded
addition, su
Floating poin
an extension,
oating point an
floating poin
e Xilinxs Po
g point unit av
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, multiply, d
instructions.
processor cor
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registers.
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ar instruction
ode and relate
be performe
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st of the thesis
hitecture
ation
shown here
the inner loo
library [42]. F
x is a scalar
XPY loop, perf
< n; i++)
] * x + Y[i];
nt from vector
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value x
s element with
of multiplicatio
back in vector
alar processo
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t support for o
data elements
ector instructio
th, and an op
vector operan
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The CFPU is
based eMIPS
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ware profiling
PU.
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nit in hardwa
processor pi
ubtraction, m
nt division an
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nd vice versa.
nt operations
owerPC hardc
vailable that s
operations in
instructions s
divide, square
The FPU is t
re with the Au
The Xilinx
ew
cessors have
set is one
ed operand sp
ed. Vector pr
tion to scalar
cessing in gen
s and lists rece
is called SAX
op of the Bas
For the above
r value. Each
forms below s
r A
r Y
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on to element
r Y
or, these op
Vector process
operations on
rather than o
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elements in ea
operation can b
s implemente
platform whi
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, power and s
g and run
supports a si
are that is tig
ipeline. The
multiplication
d square root
conversions
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are emulate
core processor
supports IEEE
single or do
supported inc
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tightly couple
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FPU include
scalar instruc
which requir
pecifiers for e
rocessors pro
instructions.
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XPY/DAXPY
ic Linear Alg
code, A and Y
h iteration of
six steps.
of Y
perations will
or provides d
whole vectors
on a single s
perand vectors
e applied elem
g the vector le
ach vector reg
be performed
d on
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They
speed
time
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ghtly
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and
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ntil run time.
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an the natural
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vector lanes,
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n unit, the res
D RESULTS
ss as well as
mented in VHD
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FPVC
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Figure 4.

The co
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d Processor
- Assebly View

CONCLUSION
autonomous
r exhibits spee
when co
most practi
by Xilinx. The
of a decrease
datapath. H
d in the rang
oint. The FPV
e PowerPC
algorithm(Me
processor, w
ansfers the co
available in FP
process execu
t.
ults also obta
w
N
floating p
edup on impo
mpared to
ioners: embe
FPVC is easi
e in perform
Hence the F
ge of designs
VC is compl
can be d
edian
when
ontrol
PGA
ution
ained

point
ortant
the
dded
ier to
mance
PVC
that
etely
doing
in
p
T
s
an
V
R
n
h
2
h
fp
Im
S
fo
P
C
h
g
ndependent w
point solutions
The number o
izes can be co

[1] B. Fagin a
nd Floating Poin
Volume 2, Septem
[2] Zhanpeng
Reconfigurable Cu
no. MSR-TR-2009
[3] Embed
http://www.xilinx.
2009.
[4] Virte
http://www.xilinx.
pu virtex5.pdf, Ap
[5] C. Brun
mplementation o
System, Internati

[6] T. Rodolf
or Embedded Pr
Performance and
Computing and FP
[7] Mic
http://www.xilinx.
guide.pdf, 2008.
work while the
s. The FPVC i
of lanes, size
onfigured to fit
REFE
and Cyril Renard
nt Arithmetic, IE
mber 1994.
g Jin, Richard N
ustom Floating-Po
9-157, August 200
dded Processor
.com/support/ do
ex-5 APU
.com/support/ d
pril 2009. Data Sh
nelli, F. Garzia
of an Open S
on Symposium on
fo, N. L. V. Calaz
rocessors in FPG
Area, Internati
PGAs, 2009.
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REFERENCES
[1] http://en.wikipedia.org/wiki/Document_management_system
[2] http://www.contentmanager.eu.com/dmsbens.htm
[3] http://en.wikipedia.org/wiki/Optical_character_recognition
[4] http://www.geekinterview.com/question_details/12799
[5] http://www.roseindia.net/struts/mvc-architecture.shtml
[6] IEEE Paper: Intranet document management systems as knowledge
ecologies
[7] TopBitS.com: http://www.tech-faq.com/document-management-
system.html
[8] http://wiki.alfresco.com/wiki/File:Alfresco_Repository_Architecture
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[9] http://www.roseindia.net/hibernate/hibernate_architecture.shtml

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ger
signal at another pair of terminals. This property is called
gain. A transistor can control its output in proportion to the
input signal; that is, it can act as an amplifier.
Alternatively, the transistor can be used to turn current on
or off in a circuit as an electrically controlled switch,
where the amount of current is determined by other circuit
elements.
c. Transformers
Here, we used Transformer to step-down the high
voltage to low voltage since our device runs with 5volts.

V. EMBEDED C

The C programming language is perhaps the most
popular programming language for programming
embedded systems. Most C programmers are spoiled
because they program in environments where not only
there is a standard library implementation, but there are
frequently a number of other libraries available for use.
The cold fact is, that in embedded systems, there rarely are
many of the libraries that programmers have grown used
to, but occasionally an embedded system might not have a
complete standard library, if there is a standard library at
all. Few embedded systems have capability for dynamic
linking, so if standard library functions are to be available
at all, they often need to be directly linked into the
executable. Oftentimes, because of space concerns, it is not
possible to link in an entire library file, and programmers
are often forced to "brew their own" standard c library
implementations if they want to use them at all. While
some libraries are bulky and not well suited for use on
microcontrollers, many development systems still include
the standard libraries which are the most common for C
programmers.
C remains a very popular language for micro-controller
developers due to the code efficiency and reduced
overhead and development time. C offers low-level control
and is considered more readable than assembly. Many free
C compilers are available for a wide variety of
development platforms. The compilers are part of an IDEs
with ICD support, breakpoints, single-stepping and an
assembly window. The performance of C compilers has
improved considerably in recent years, and they are
claimed to be more or less as good as assembly, depending
on who you ask. Most tools now offer options for
customizing the compiler optimization. Additionally, using
C increases portability, since C code can be compiled for
different types of processors.
a.special feature
The C language is standardized, and there are a certain
number of operators available that everybody knows and
loves. However, many microprocessors have capabilities
that are either beyond what C can do, or are faster than the
way C does it. For instance, the 8051 and PIC
microcontrollers both have assembly instructions for
setting and checking individual bits in a byte. C can affect
bits individually using clunky structures known as "bit
fields", but bit field implementations are rarely as fast as
the bit-at-a-time operations on some microprocessors.
b.C Compiler for Embedded System
Perhaps the biggest difference between C compilers for
embedded systems and C compilers for desktop computers
is the distinction between the "platform" and the "target".
The "platform" is where the C compiler runs -- perhaps a
laptop running Linux or a desktop running Windows. The
"target" is where the executable code generated by the C
compiler will run -- the CPU in the embedded system,
often without any underlying operating system.
The GCC compiler is

the most popular C compiler for
embedded systems. GCC was originally developed for 32-
bit Princeton architecture CPUs. So it was relatively easily
ported to target ARM core microcontrollers such as XScale
and Atmel AT91RM9200; Atmel AVR32 AP7 family;
MIPS core microcontrollers such as the Microchip PIC32;
and Freescale 68k/ColdFire processors.
The people who write compilers have also (with more
difficulty) ported GCC to target the Texas Instruments
MSP430 16-bit MCUs; the Microchip PIC24 and dsPIC
16-bit Microcontrollers; the 8-bit Atmel AVR
microcontrollers; the 8-bit Freescale 68HC11
microcontrollers.
Other microcontrollers are very different from a 32-bit
Princeton architecture CPU. Many compiler writers have
decided it would be better to develop an independent C
compiler rather than try to force the round peg of GCC into
the square hole of 8-bit Harvard architecture
microcontroller targets:
SDCC - Small Device C Compiler for the Intel 8051,
Maxim 80DS390, Zilog Z80, Motorola 68HC08,
Microchip PIC16, Microchip PIC18
There are some highly respected companies that sell
commercial C compilers. You can find such a commercial
C compiler for practically every microcontroller, including
the above-listed microcontrollers. Popular microcontrollers
not already listed (i.e., microcontrollers for which the only
known C compiler is a commercial C compiler) include the
Cypress M8C MCUs; Microchip PIC10 and Microchip
PIC12 MCUs; etc.

VI. CONCLUSION

Once every educational institution implemented
this device, the following benefits can be attained.
1. For 4 years, a single student spends
(4000 rupees per year for buying books and)
16000rupees for buying books. This device costs
only 5000 and once if he afford this device he can
sustain it for years. So that every student can save
11000 rupees.

2. Our device is very compact and portable.
The weight age of the books are easily getting
reduced. It easy to copy any book from everyone
at any time.

3. The notable feature of this device is
notepad through which the students can make
hints and notes during class hours and it can be
retrieved when necessary.

4. The most significant advantage of our
project is to prevent deforestation since papers are
manufactured by cutting trees. The total area of
the forest is only 6% of the earth, and its exactly
the right time to save our planet. If every student
uses this device, we can minimize global warming
which is adverse effect of deforestation and
thereby support for green India.

REFERENCES
1. Berndt, T. J. (2002). Friendship quality and social
development.Current Directions in Psychological Science,
11, 7-10.
2. Wegener, D. T., & Petty, R. E. (1994). Mood management
across affective states: The hedonic contingency
hypothesis. Journal of Personality & Social Psychology, 66,
1034-1048.
3. SMBus specification
http://www.smbus.org/specs/smbus110.pdf

4. Smart Battery Data Specification
http://www.sbs-forum.org/specs/sbdat110.pdf

5. Smart Battery Charger Specification
http://www.sbs-forum.org/specs/sbc110.pdf

ISBN: 978-81-920575-6-9 :: doi: 10.73536/ISBN_0768
Node Localization in Wireless Sensor Networks
Using Mobile Anchor

Harshada Barde
Computer Department, PG Student,
Datta Meghe College of Engineering, Airoli,
Navi Mumbai, India

AbstractNode localization is required to report the
origin of events, assist group querying of sensors, and to
answer questions on the network coverage. So, one of the
fundamental challenges in wireless sensor network is node
localization. In this paper, we propose a cooperative
localization algorithm that considers the existence of obstacles
in wireless sensor networks (WSNs) which are mobility
assisted. In this scheme, a mobile anchor (MA) node
cooperates with static sensor nodes and moves actively to
refine location performance. By changing the transmission
range of mobile anchor node, the localization accuracy of the
proposed algorithm can be improved further. The algorithm
takes advantage of cooperation between MAs and static
sensors while, at the same time, taking into account the relay
node availability to make the best use of beacon signals. For
achieving high localization accuracy and coverage, a novel
convex position estimation algorithm is proposed, which can
effectively solve the localization problem when infeasible
points occur due to the effects of radio irregularity and
obstacles. It is the range-free based convex method to solve
the localization problem when the feasible set of localization
inequalities is empty. The effectiveness of this approach is
validated by extensive simulations.
Keywords-Beacon; Localization; Mobile Anchor;
Wireless Sensor Networks
I. INTRODUCTION
Localization algorithms for wireless sensor networks
(WSNs) have been designed to find sensor location
information, which is a key requirement in many
applications of WSNs. Generally speaking, based on the
type of information required for localization, protocols can
be divided into two categories: (i) range-based and (ii)
range-free protocols.
The Range-based protocol is defined by protocols that
use absolute point-to-point distance estimates or angle
estimates for calculating location. They require special
hardware to find the distance between anchors and sensors,
which may become very expensive for large networks. The
Range free protocol makes no assumption about the
availability or validity of such information. Because of the
hardware limitations of WSN devices, solutions in range-
free localization are being pursued as a cost-effective
alternative.
In the Range free protocol, the anchor informs its own
position through message passing [1] to other sensors.
After finishing the distance-from-anchor estimation
process, a regular sensor can determine its own position,
through variety of methods, such as multilateration,
triangulation, etc. If necessary, an optional step is
performed, in which regular sensors exchange messages
among them to refine their locations. Due to the hardware
limitations and power constraints of sensors, solutions of
range-free localization are often preferable and can be
considered as cost-effective options.
In this paper, we focus on the investigation of range
free localization algorithms for mobility-assisted WSNs.
An obstacle can be dynamically formed due to unbalanced
deployment, failure or power exhaustion of sensor nodes,
damaging interference, or physical obstacles such as
mountains or buildings. In this paper, we consider only
physical obstacles. Most previous algorithms cannot work
well in anisotropic networks, where obstacles appear
among sensor nodes, changing according to direction.
Nonetheless, anisotropic networks with obstacles are more
likely to exist in real world for several reasons: (i) a
uniform node distribution cannot always be achieved
because of random distribution of sensor nodes, which
means some regions might not contain any sensor node, (ii)
physical obstacles such as mountains or buildings will
naturally exist in many networks and (iii) unbalanced
power consumption among nodes results in some regions
without functionality of sensing and communication.
In this work, we propose a multi-power level mobile
anchor assisted range-free algorithm for WSNs with
obstacles. By using a relay node, our scheme can
effectively reduce the effects of obstacles on node
localization. The relay nodes will ensure optimal coverage
while simultaneously performing backhaul and access
functions. Furthermore, our scheme can calculate the
positions of infeasible points caused by a complex radio
t
p
i
l
t
f
p
d
t
b
a
t
b
m
p
d
I
h
T
d
e
A
a
n
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r
t
T
c
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s
transmission
problem when
is empty.
II. SY
In this s
localization a
technical preli
formulation o
problem and
decreasing the
A.
In WSNs,
transmission
beacon signa
anchor node
the transmissi
beacon can r
mobile beaco
possible locati
For examp
designed to e
IEEE 802.15.
has 31 transm
The exper
TelosB mote
demonstrate th
efficiently cha
Assume that
anchor node,
node is R
i
, w
assumed to
receiver and k
the MA transm
Transmission
current positio
After receivin
sensor can con
environment,
n the feasible
YNERGETIC
MOBIL
section, we
approach usin
iminaries of o
f the localizat
(iii) Subsectio
e impact of ob
Backgrou
, a node can
radius of an
al received fr
can adjust its
ion power [3]
recognize that
on. Combine
ions of the sen
ple; the TelosB
enable experim
.4 compliant
mission power l
riment is cond
es. As show
hat the transm
anged by tunin
there are N l
and related
where i = 1, 2
have a glob
knows its posi
mits beacon s
parameters o
on, transmissi
ng these beaco
nstruct an effe
, which is
set for locali
LOCALIZAT
E ANCHOR
propose a c
ng the MA: (
our algorithm,
tion problem a
on C- propose
bstacles.
und
determine wh
anchor node
rom the one-
s transmission
]. A sensor n
t it is in the
ed with the
nsor node can
B mote, an ope
mentation is
Chipcon CC2
levels between
ducted on a tes
wn in Fig.1,
mission radius
ng the transmi
evels of trans
transmission
2, . . .N. Nor
bal positionin
ition. During t
signals at vary
of the beacon
ion power, tra
on signals, an
ective constrai
recognized a
zation inequa
TION USING
co-operative
(i) Subsection
(ii) Subsectio
as an optimiza
e an algorithm
hether it is in
according to
-hop anchor.
n radius by tu
node receiving
e area around
RSSI techn
be estimated.
en source plat
equipped wit
2420 radio, w
n -25 and 0 dB
stbed compose
the experim
of a sensor ca
ission power l
smission powe
range of an
rmally, the M
ng system (G
the moving pe
ying power le
n signal are
ansmission rad
unknown-pos
int on its posit
as a
alities
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node
n A-
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ation
m for
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The
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sition
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Fig.

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For example
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||x c
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ansmission po

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roblem based o
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).
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ethods all ass
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nonempty) an
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quares represen
.1 Experiment
localization sc
The feasible se
e, assume that
mission radius
, at position x
ude that the d
c|| R.
c|| > R.
der the various
ifferent positi
in a set of ineq
c
i
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,
of MA at time
can be zero.
dii for that tim
alid constraint
nds, for the tig
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can successfu
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m of solving a
zation scenar
The feasibl
sume that the
utions. But in
s complicate
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equalities has a
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., the feasible
on the figure
nt the unknow
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cenarios: (a) T
et is empty
t current posi
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x, receives the
distance betw

s transmission
ions. The un
qualities on x:
where i =
e i, r
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me.
t radii gives th
ghtest constra
constructed
mobile anchor
ully convert
th variable tran
a set of quadr
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le set is em
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as shown in F
a solution (i.e.
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e set is empty
represent the
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If the unknow
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the localizati
nsmission pow
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feasible set
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hm using Conv
sotropic prope
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see that,
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i
T
]

notes the inne
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the equivalent
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ave the foll
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case
.
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onlinear equal
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to y
t Y is a positi
ment theorem [
ex optimizati

m of
) is

the
lity
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ive
[2].
ion

m
p
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f
w
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o
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r
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b
i
t
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w
d
c
r
n
n
g
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a
t
l
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w
w
o
m
o
b
i
n
r
where Y
matrix. The
programming
efficient inter
value of Y, w
for the unkno
where Y
2:3,1:1
elements of th
of the matrix Y
C.
In this pap
the obstacle
recognition a
discovers inne
location info
information. T
boundary nod
in contention
their rebroadc
Fig. 4. Hearin
will compete
distributed co
candidate no
remaining en
neighboring se
node is given
greater numbe
The select
following sche
Receiving
a back off tim
time that the
location inform
= ( (use
/n
(10)
where a
weights for di
The specif
which propert
or coverage ef
We can
maximum num
off time. If a
beacon signal
it will rebroa
nodes will ca
rebroadcast of
0 indicates th
resulting p
problem wh
rior-point algo
we can further
own-position
1
denotes the
he second and
Y.
Algorithm
O
per, we assum
have been
algorithm [12
er and outer
ormation. It
Thus each sen
de or not. Only
for relaying
casts may cove
ng a beacon
to relay this
ontention pro
ode wins the
nergy of the
ensors. Highe
to a node wit
er of neighbor
tion of the o
eme:
a beacon from
mer. This back
node must w
mation. The b
ed energy/initi
num n
and are coe
ifferent param
fic values of
ty is more imp
fficiency. In to
see that a m
mber of neigh
candidate bo
l from other s
dcast the bea
ancel their c
f the beacon.
hat Y is a pos
problem is
hich can be
orithms [2]. A
r calculate the
sensor x, nam
e vector cons
d third rows fo
m for Decreas
Obstacles
me that bound
discovered b
]. This alg
boundary cyc
uses only
nsor node kno
y boundary nod
beacons from
er some blind
from the MA
location infor
ocess. The p
e contention
e node and
r priority to be
th greater rem
s.
optimal relay
m the MA, a b
off timer defi
wait before r
ack off time is
ial energy) +
neighbours)*
efficients that
meters.
and can be
portant for use
otal, + = 1
more remainin
hbors will lead
undary node
ensors during
acon signal an
ontentions if
sitive semi def
a convex
solved by u
After obtaining
e position esti
mely, x = Y
2
structed from
or the first col
sing the Impac
dary nodes aro
by the boun
gorithm accur
cles without u
the connect
ows whether it
des can partic
m the MA bec
areas as show
A, boundary n
rmation throu
probability th
depends on
the number
e the optimal r
maining energy
node is given
boundary node
fines the amou
rebroadcasting
s calculated as
max_d
t provide diffe
e set dependin
ers: energy bal
.
ng energy an
d to a shorter
does not hear
g its back off t
nd other boun
they receive
finite
cone
using
g the
mate
2:3,1:1
,
m the
lumn
ct of
ound
ndary
rately
using
tivity
t is a
ipate
cause
wn in
nodes
ugh a
hat a
the
r of
relay
y and
n by
e sets
unt of
g the
s
delay
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ng on
lance
nd a
back
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time,
ndary
e the
reb
fo
in
dir
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r
i
<
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ac
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10
po
W
pe
no
In
sit
(D
su
ne
ev
Lo
es
ab
an
the
in

Fig.
As a result
broadcast firs
r the beacon s
In this wa
formation to
rect communi
Similarly to
pecial areas can
< ||xc
i
|| R
i
+
where R
relay
lay node. W
calization algo
is scheme, we
bstacle on no
ccuracy.
I
In this sect
nalyzed. The
osition estima
We consider a 2
00 m. We ass
ower with the
We perform ev
erformance co
odes randomly
n subsection A
tuation. Then
DOI) and ob
ubsection B. A
etwork scenari
valuate the pe
ocalization err
where xi is
timated positi
bsolute localiz
n error of 20%
e radio range.
a.Performan
We consider
the sensing a
4 A sensor ne
t, the node w
t and win the
signal of mobi
ay, we can
some areas t
ication.
o (3), the unkn
n obtain a set
+ R
relay
, i = 1
is the curren
We can also
orithm to solv
e can efficient
ode localizatio
II. NUM
tion, simulatio
performance
ation accuracy
2 dimensional
sume the MA
transmission r
valuation with
omparisons. F
y and the trans
A, we simulat
we discuss ef
bstacle on l
All simulation
ios. The avera
erformance fo
ror is defined a
the actual po
ion of node i
zation error us
% means that th
nce in Ideal En
r ideal situatio
area. We use
etwork with an
with the highe
competition t
le anchor.
deliver the
that cannot re
nown-position
of inequality
, 2, ..., n (11)
nt transmissio
use the pr
ve the problem
tly decrease th
on and impro
MERICAL RE
on results are
e evaluation
y of the prop
region with a
A has two lev
radii r and R=
h our propose
First, we dep
smission radiu
te our algorit
ffects of degre
localization p
results are av
age localization
or our localiz
as follows:
sition for nod
. Note that w
sing radio rang
he localization
nvironment
on, when ther
the DOI to in

n obstacle
est priority w
to serve as rel
MAs locati
eceive the MA
n sensor in the
constraints on
)
on radius for t
roposed conv
m (11). Based
he impact of t
ove the locati
ESULTS
e presented a
focuses on t
posed algorith
a size of 100 m
vel transmissi
=2r, respective
ed algorithm
ploy 100 sen
us r = 15 mete
thm in the id
ee of irregular
performance
veraged over 1
n error is used
zation algorith
de i and xi is t
we normalize t
ge. For instan
n error is 20%
re is no obsta
ndicate the rad
will
lay
ion
As
ese
n x:
the
vex
on
the
ion
and
the
hm.
m x
ion
ely.
for
sor
ers.
deal
rity
in
100
d to
hm.

the
the
nce,
% of
acle
dio
i
s
n
d
a
f
t
e
c
b
g
t
p
s
m
e
n
a
i
t
l
l
f
c
m
C
f
M
w
I
w
I
M
O
U
C
w
C
l
I
4
irregularity ch
simulation re
nodes are den
denoted by as
and the estima
from Fig. 5.1
the algorithm
error.
b.Performa
For the n
coefficient (f)
beacon points
given time. T
the sensing a
points that can
We have
scheme that
mobility-assis
exist. Consid
namely, the f
algorithm has
ideal transmis
the simulatio
localization
localization a
future work, w
cooperative lo
mobility assis
This work
Computer De
from Datta M
Mumbai, Indi
[1] M. Si
wireless sens
IEEE MASS,
[2] K.-F. S
with mobile a
IEEE Trans. V
May 2005.
[3] S.
Optimization,
UK, 2004.
[4] G. Xin
C. So, Mob
wireless senso
China, Jun. 20
[5] Q. Shi
localization in
Int. Conf. Com
4214-4218.
haracteristic.
sults in the i
noted by circ
sterisks, and th
ates represent
and 5.2 that o
of [11] in te
ance in Non-id
next set of e
that represent
s that cannot
This will mod
rea that limit
n be heard at a
IV.
presented a
can achieve
sted wireless s
dering the c
feasible set is
been presente
ssion of radio
on results th
scheme can
accuracy by in
we intend to v
ocalization sc
ted wireless se
V. A
k is supported
epartment and
Meghe Colleg
a.
VI.
ichitiu and V
sor networks w
Philadelphia,
Ssu, C.-H. Ou
anchor points
Veh. Technol
Boyd and
Cambridge
ng, J. Wang, K
bility- assiste
or networks,
008, pp.103-11
i and C. He,
n wireless sen
mmunications
Fig. 5(a) and
ideal situation
cles, the posit
he lines that l
the estimation
our algorithm
rms of the av
deal Environm
experiments,
ts the percenta
be heard by
el the obstacl
t the number
any point.
CONCLUS
new cooper
high localiza
sensor networ
complex loca
s empty; a co
ed to address
o signals. It h
hat the prop
n significant
ncluding a m
verify and imp
cheme using
ensor network
CKNOWLED
by The HOD,
d The Princip
e of Enginee
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ISBN: 978-81-920575-6-9 :: doi: 10. 73543/ISBN_0768
ACM #: dber.imera.10. 73543
Design and Implementation of Sensor Network Using CAN Bus

Prof.R.P. Deshmukh
1
Electronics & Telecom Dept.
, Y.C.C.E Nagpur

Abstract: - The number of sensors in module is monitored by
centralized system that may be used for controlling and
monitoring industrial parameters (Temp, Pressure, Speed,
and Torque) by using CAN BUS. In this paper we present a
comprehensive overview of controller area networks, their
architecture, protocol, and standards. Also, this paper gives
an overview of CAN applications, in both the industrial and
non-industrial fields. Due to CAN reliability, efficiency and
robustness, we also propose the extension of CAN
applications to sensor network.
Keywords-communication, CAN bus, CAN Trans
receiver SN651050, AVR

I. INTRODUCTION

Major communication networks can be divided into
four types, namely: IP Core Network/Internet, Wireless
LAN, 3G/4G Cellular Network [1]. The common usage
for these networks is to carry text, audio and video
content. Recently, some of these networks have been
utilized in industrial automation to monitor and control
industrial plants. Another type of networks is the
Controller Area Network. CAN is intended as a
communication network between the control units in
vehicles. Nowadays, CAN applications are gaining ground
and it is extending to industrial automation including
marine and aircrafts electronics, factories, cars, trucks and
many others The backbone of the Controller Area
Network is a fast serial bus that is designed to provide a
reliable, efficient and a very economical link between
sensors and actuators. CAN use a twisted-pair cable to
communicate at speeds up to 1 Mbits/sec, with up to 40
devices. CAN was originally developed to simplify the
wiring in automobiles. In the past, automobile
manufacturers used to connect devices in vehicles using
point-to-point wiring systems. As more electronics and
controllers are deployed to monitor and control vehicles,
wiring started to become more complex, bulky, heavy and
expensive. Automotive industry starts to reduce massive
wires complexity with dedicated CAN link that provides
low-cost, robust network, and multi-master
communication system. Figure 1 shows the efficiency and
the wiring-reduction caused by implementing CAN
among multiple devices. Thus causing wiring-reduction,
cost reduction with CAN.

II Hardware
Three major elements can be found in the sensor
network prototype: a sensor node module, a computer
server module and a computer client module. Each
element is discussed below. a) Sensor node module:
hardware block diagram of the sensor node module is
shown in Fig. 2. Each module consists of a free scale 8bit
AVR processor with built-in CAN I/O controller, an
SPI connected analog to digital circuit, which digitizes
the signals from a series of temperature sensors. All
sensor nodes are interconnected to a differential two-wire
physical CAN bus (CAN High and CAN Low), which is
controlled by a central PC computer
CAN Architecture, Standards and Protocol
CAN was originally developed by Robert Bosch
(Germany, 1986) when Mercedes requested a
communication system between three electronic control
units in vehicles. Point to point communication was not
suitable anymore, and the need of using a multi-master
communication system became imperative. Although this
origin can be traced to automotive industry, industrial
automation rapidly showed the need of using such a
popular bus system.[2-3] CAN port is a two-wire, half
duplex, high-speed network system that can reach a
throughput up to 1 Mbits/sec. Data, control commands
and devices status can be transmitted and/or received in
well structured frames. Theoretically, CAN is capable of
linking up to 2032 devices on a single


Fig 1 Reduction in wiring with CAN

Fig 2 A hardware block diagram of the sensor node
module

network; due to hardware limitation, only 110 nodes
can be linked-up to construct a single network.[2] Similar
to the traditional OSI model and IP model CAN have a 4-
layer protocol: physical layer, transfer layer, object layer,
and application layer as shown in figure 3.[3]. Fig.3.
Layered Architecture of a CAN node .The physical layer
defines how the signals are transmitted. The transfer layer
defines the Kernel of the CAN protocol. It is responsible
for presenting and accepting the received/transmitted
messages to/from the upper layer. These messages are
sent and received using the following properties: bit
timing, message framing and arbitration,
acknowledgment, error detection and signaling, in
addition to fault confinement. The object layer is
responsible for message filtering and handling. The
object layer and the transfer layer are both combined as
the data link layer defined by the ISO/OSI model. The
application layer is the upper layer, through which the
user interferes. CAN (Version 2.0) has two different
standards: CAN 2.0 A, standard CAN, using 11 bits for
node identification; and the other standard is CAN 2.0 B
or extended CAN, using 29 bits for node identification.
With 11 bits, 2,048 unique messages are possible,
whereas 536 million unique messages are possible with
29-bit identifier In a controller area network, all nodes -
recipients - can see all messages and can accept or ignore
any messages according to the system design. There are
two ISO standards classifying the two CAN's physical
layer in terms of data rate; ISO 11898 which can handle
speed up to 1 Mbit /sec and ISO 11519 that can handle
speed up to 125 Kbit /sec, as shown in table 1.

Fig 3, four layer protocol of CAN

III SYSTEM SUMMARIZATION
First of all, it should be defined function of each node,
in order to sure the number, type, signal characters of
node control quantity. This is the first step of preceding
the control system to realize networking. Secondly, it
should be chosen node controller and relevant CAN
components. For the functions of every node are single
comparatively, and the quantities of data are also small,
the demand of CPU is reduced greatly, which could be
DeviceA
DeviceB
Device
Master
EDU/PC
DeviceD
DeviceC
WITHOUT CAN
DeviceA
DeviceB
Device
Master
EDU/PC
DeviceD
DeviceC
WITH CAN
CAN BUS
RS 232 Port
Display
CPU CAN Driver
Keypad
Sensor CPU CAN Driver
Control CKT
CAN BUS
fulfilled by AVR processor. The parts of CAN bus are
mainly constructed by controller port, bus transceiver and
parts of I /O. Finally, according to agreement of physical
layer in CAN bus to choose the medium of bus, design
the wiring project, and connect it to be control network.
A. Capability Comparison between RS-232 and CAN
Bus
Industry facilities communication often related to a lot
of hardware and soft ware product. It is used to connect
the protocol between standard computer flat and industry
automatic application facilities. Moreover, the facilities
and protocols in which were used are various. Therefore,
it is hoped that most automatic application facilities can
perform simple serial orders, especially hoped that these
orders are compatible with the standard serial ports in PC
or accessional serial port boards. RS-232 which has
widest application in PC and communication industry is
one of the serial ports. RS-232 is defined as a sort of
single end standard which could increase the
communication distance in serial communication with
low-velocity. With the communal signal ground between
sending port and sink of RS-232, it can not use signal
with two ports. Otherwise, the common mode noise will
be coupling into signal system.
CAN is one of the field bus which is widest
application internationally full named Controller Area
Network. As a sort of serial communication bus with
multi-mainframe mode, the basic design criterion of CAN
demands high-velocity and better capability of
contradicting electromagnetism disturb, even demands to
check any mistakes which are produced in
communication bus. When the distance of signal
communication reached 10km, CAN still provide digital
communication velocity with 50kbit/s [5].
B. System Composition of CAN and RS-232 Convertor
It is used single chip AT89C51 as microprocessor,
SJA1000 as microcontroller of CAN in designing the
transition equipment which change RS-232 into CAN. As
shown in Fig. 1. SJA1000 could process the frame in
communication data for integrating the function in
physical layer and data link layer of CAN protocol [5].
As an interface between CAN controller and physical
bus, PCA82C250 is used to provide the differential
sending of bus and the differential receiving of CAN
controller. There are three different working could be
chosen through the Pin3 of PCA82C250 (high speed,
slope
Control, readiness). When Pin3 connects to earth, it is
working in high speed. Max is used to complete the level
transition from RS-232 to interface chip in micro-
controller.
Circuit Design Of System Hardware:-

Fig 4
Hardware circuit of system is mainly constructed by
level transition circuit of RS-232, controller and
transceiver of CAN. The collective circuit PCB of
hardware design is followed as Fig. 2.
a. Detailed Design of Every Part As an unattached
level transition controller, this brainpower transducer
relates to fetch temperature, brainpower switch in the
mode of sending and receivable, setting of
communication mode, level transition of RS-232 and
some other aspects. Material description shown as:
b. Level transition circuit of RS-232: In definition of
normal RS-232 interface, TXD, TRS and DTR are the
level output of RS-232. In the system facilities of
computer data collection and
Industry, RS-232 interface is the most familiar
communication standard. It is prescribed the meanings of
am bipolar level data 0 and 1 were expressed
together by voltage amplitude and level polarity in RS-
232 standard interface. Through fair and foul, the
maximum value is 15v; it is defined 4 logical levels in
RS-232 standard interface. For input, it is prescribed
+3v~+15v as data 0 and control line level in connection
State, while -3v~-15v as data 1 and control line
level in disconnection state. When level absolute value
under 3v, it is
Uncertain state. For fan-out, it is prescribed
+5v~+15v as data 0 and control line level in connection
state, while -5v~-15v as data 1 and control line level in
disconnection state. When level absolute value under 5v,
it is uncertain state. The prescriptive logical level of RS-
232 was different from the current microprocessors and
single chip. Therefore, it is should be converted the level
between microprocessor and RS-232 in actual
application. This conversion should be completed by
Max232 in design.
a. Receival and sending: Processor AVR is a core of
the module, which could complete the function of
application layer in CAN bus. It is chosen AVR as main
controller with which SRAM 1 K bytes, FLASH ROM
16K byte in system self programmable,512 bytes,
external & internal interrupt sources, 32 programmable
I/O lines. For the message queue quoted in program, it is
extended static state RAM with 1k,
CAN controller with Basic work module. It is chosen
SN651051 as CAN transceiver which could connected
CAN controller to CAN physical network belongs to the
interface of control circuit and physical transfers circuit.
MAX232 is an apparatus for conversion between
TTL/COMS level and EIA-232 level which could
connect single chips UART and microcomputers COM
to realize the full duplex communication of the both.
b. Realization of node circuit in CAN bus: Node
message in network could be divided into different PRI to
fulfill different real time demanding.
CAN with multi-mainframe mode, any nodes in the
network could send message to other nodes forwardly in
any time, without the difference of principal and
subordinate node.
When many nodes send message to bus
simultaneously, CAN choose the non destructive bus
arbitration technique. Node with low priority will be sent
in turn, while node with high priority will be sent
normally without any influences to save the time of
conflict arbitrage. In time of sending, the losing arbitrage
or the frame which go to pot by making mistakes will be
resent automatically. The direct communication distance
of CAN will be 10km (velocity under 5kbps),
communication velocity will maximize 1 Mbps (here,
communication distance maximize 40m). Message of
every frame in CAN all have CRC checkout and other
debug measures to insure low error rate. In the condition
of serious errors, CAN nodes have function of closing
and existing bus automatically to make other nodes
without any influences.
B. Problems Should Be Settled in Hardware Design
Some problems would be appeared in design of
hardware circuit. It is shown as follow.
a. Connection circuit between MAX232 and serial-
port: Fig.5 is the connection circuit between MAX232
and computer
Serial-port. The second pin of serial-port is sink
which connects to 14 or 9 pin of MAX, the third pin is
sending terminal which connects to 13 or 8 pin of MAX.
The data terminal of wireless sending module connects to
10 or 11 pin.
c) Connection of AVR receiver:
Temperature sensors are connected to PA0,PA1
inputs of AVR ,which is converted to its digital
equivalent through inbuilt 10 bit ADC ,RX0 and TX0 of
AVR Processor connected to SN 651050.

Fig. 5 Connection circuit between MAX232 and computer serial-
port
SN 651050 as CAN bus transceiver is an interface
apparatus between CAN controller and CAN bus which
send it with different mode for CAN
Four switches are connected to PB0 to PB3 input
pins of AVR. Depending upon status of 4 switches, the
required temperature of the system is monitored There is
only used the first data channel in the design Pin no 14 is
RxD,pin no 15 is TxD of AVR used to communicate data
It is shown as Fig. 7.

Fig. 6 Connection from RS-232 to MAX 32

Fig 7 Circuit diagram for sensor network
The experimental results demonstrate the efficiency
and accuracy of the applied
Method. Table 1 lists acquired data

Table 1 acquired data for 1 hour
Test no
Set temperat
in degree
Measured tempera
in degree
01
20.00 20.01
02 22.50 22.50
03
23.00 22.99
04 25.30 25.30
05
30.00 30.01
06 16.00 16.01
07
19.50 19.49
08 22.00 22.01
Sum
178.30 178.32

We can see that temperature measuring error is 0.02
degree centigrade and the temperature accuracy is 0.02
% relative to the temperature scale of 100 degree
centigrade

IV CONCLUSION

These sensor networks referred in the paper are just
used some cheap and universal components, like AVR,
MAX232, SN 651050 etc. For circuit design having the
advantages of briefness and integrity, it has the characters
of simple configuration and low-cost which compared to
some similar industrial products.
There are some excellences of choosing CAN bus
technique: (1) Speedy response, better anti-jamming
capability; (2)lowest malfunction rate, high
communication baud rate, great data transfer with
network which was constructed by two twisted-pairs; (3)
simple configuration, great scalability, high security and
convenient setting, servicing [6]. The system based on
field bus CAN has a very nicer application foreground in
control system domain for a good many excellences of
CAN.
Switched RS-232communication network to CAN
communication network could realize to construct
network with multidrop of RS-232 and long-distance-
communication conveniently. Moreover, it could
substitute the CAN interface card with costly price in
current market to realize data communication between PC
serial interfaces and CAN bus fleetly and exactly. The
configuration of hardware or software and the codes of
this design were all debugged and passed, which have
nicer transplant and expansibility.

REFERENCES

[1] Th. Zahariadis,"Evolution of the
Wireless PAN and LAN standards, Computer Standards & Interfaces,
Vol. 26,No. 3, May 2004, Pp 175-185.
[2] "Controller Area Network - CAN
Information,"http://www.algonet.se/-
staffanun/developer/CAN.htm,3November 2005
[3] Bosch, R. "CAN SPECIFICATION (Version 2.0),"
Germany: Stuttgart, 1991
[4] "CAN Application Fields," http:Hwww.
[5] Lin Qing, Yang Xianhui et al. Field Bus and Network Integration,
Test Control Technique, 1999, 18(5), 24-26
[6] GAO Jun, Design of the Intelligent Measuring & Controlling
System Based on CAN Field Bus, Light Industry Machinery, Vol.24,
No. 2,2006, pp.103~106.

Volume 1. Copyright 2012 Techno Forum Group,
India.
ISBN: 978-81-920575-6-9 :: doi: 10. 73550/ISBN_0768

Praful Saxena
Research Scholar
Manav Bharti University
Solan (H.P.)

Abstract In this paper, we review the Data Encryption
Standard and its types. Also we improve the efficiency of Data
Encryption standard with implementation of pseudo random
number generator and try to avoid meet-in-middle attack in
double data encryption standard (DES).

Keywords Encryption, Decryption, DES, Triple DES, Pseudo
Random Number Generator, meet-in-middle attack.

I. INTRODUCTION
DES is block cipher and Symmetric key encryption that
uses only one key for encryption and decryption; it encrypts
data in blocks of size 64 bits each. That is, 64 bits of plain
text goes as the input to DES, which produce 64 bits of
cipher text. The same algorithm and key are used for
encryption and decryption, with minor differences. The key
length is 56 bits. The initial key consists of 64 bits. Before
the DES process even starts, every eighth bit of the key is
discarded to produce a 56 bit key. That is, bit positions
8,16,24,32,40,48,56 and 64 are discarded. Before discarding,
these bits can be used for parity checking to ensures that the
key does not contain any errors.
II. PRELIMINARIES
DES is based on the two fundamental attributes of
cryptography: Substitution (confusion) and transposition
(diffusion). It consists of 16 rounds
each of which performs the steps of Substitution and
transposition.
Encrypts by series of substitution and transpositions.
Based on Feistel Structure
Use P-Boxes, S-boxes, and XOR to create confusion
and diffusion
Iterative structure easy to implement in hardware
Phase 1: The 64-bit plaintext block is bit permuted and
stored in two 32-bit registers L (Left) and R (Right).
Phase 2: A round operation composed of function f and
exclusive-ored is performed 16 times. In the i
th
round, the
32-bit R and the 48-bit round key K
i
are inputs to the f
function. The output of the f function is exclusive-ored with
L to form R for the round i+1. The R used in round i
becomes the L for round i+1. Function f shaded in Figure.1
performs following operations to generate a 32-bit output.

1. 32-bit value r is expanded into 48-bit value a by E.
2. Value a is exclusive-ored with the 48-bit round key
and output value b.
3. Value b is partitioned into 8 groups with 6-bit for each
group. Each group is input to an s- box, which substitutes a
6-bit input with a 4-bit output. All the eight 4-bit outputs are
combined to form value c.
4. Value c is permuted to generate the 32-bit output of f
function, value d by P.
A NASCENT APPROACH FOR SYMMETRIC KEY ENCRYPTION USING
DOUBLE DES

Figure 1: Functionality of one round in DES.
Phase 3: In this phase the two 32-bit outputs of round 16
are concatenated and permuted using the inverse
permutation and loaded into the output register.
Round key generation: Since each of the sixteen rounds
uses a 48-bit round key, a round key generation algorithm is
used to generate the sixteen round keys K1, K2 K16 from
the 56-bit user key. The round key generation uses simple
bit-permutation and shift operations. Each round key
contains 48 bits of the 56-bit user key.
2.1 Double Data Encryption Standard: Double DES uses
a "key bundle" which comprises two DES keys, K1 and K2,
each of 56 bits (excluding parity bits). The encryption
algorithm is:
Ciphertext = EK1 (DK2 (EK1 (Plaintext)))
I.e., DES encrypt with K1, DES decrypt with K2, then
DES encrypt with K3.
Decryption is the reverse:
Plaintext = DK1 (EK2 (DK1 (Ciphertext)))
I.e., decrypt with K1, encrypt with K2, then again
decrypt with K1.
Each double encryption encrypts one block of 64 bits of
data.
2.1.1 Meet-in-themiddle attack on double encryption
Meet-in-the-middle attacks can be used against
cryptographic algorithms that use multiple keys for
encryption. An example of a successful meet-in-the-middle
attack is the attack versus Double DES. To improve the
strength of 56-bit DES, Double DES (two rounds of DES
encryption using two different keys, for a total key length of
112 bits) was suggested.
The meet-in-the-middle attack is a known plaintext
attack; the cryptanalyst has access to both the plaintext and
resulting ciphertext. Assume the plaintext is "Cat," and the
resulting double DES ciphertext is "BzX." The cryptanalyst
wants to recover the two keys (called Key1 and Key2) used
for encryption.
The cryptanalyst first conducts a brute force attack on
Key1 using all 2
56
different Single-DES keys to encrypt the
plaintext of "Cat" and saves each key and the resulting
intermediate ciphertext in a table. The analyst then brute
forces Key2, decrypting "BzX" up to 2
56
times.
When the 2
nd
brute force attack decrypts an intermediate
ciphertext that is in the table, the attack is complete and both
keys are known to the cryptanalyst. The attack takes 2
56
plus
at most 2
56
attempts, or a maximum of 2
57
total attempts.
This is far easier than 2
112
attempts.
2.2 Pseudo Random Number Generators:
PRNGs: the mechanisms used by real-world secure
systems to generate cryptographic keys, initialization
vectors, random" nonces, and other values assumed to be
random.
PRNG is a cryptographic algorithm used to generate
numbers that must appear random. A PRNG has a secret
state, S. Upon request, it must generate outputs that are
indistinguishable from random numbers to an attacker who
doesn't know and cannot guess S. In this, it is very similar to
a stream cipher. Additionally, however, a PRNG must be
able to alter its secret state by processing input values that
may be unpredictable to an attacker. A PRNG often starts in
an state that is guessable to an attacker (usually
unintentionally), and must process many inputs to reach a
secure state. Sometimes, the input samples are processed
each time an output is generated.
PRNGs are typically constructed from other
cryptographic primitives, such as block ciphers, hash
functions, and stream ciphers. There is a natural tendency to
assume that the security of these underlying primitives will
translate to security for the PRNG.
2.3 Enumerating the Classes of Attacks:
2.3.1 Direct Cryptanalytic Attack:
When an attacker is directly able to distinguish between
PRNG outputs and random outputs, this is a direct
cryptanalytic attack. This kind of attack is applicable to
most, but not all, uses of PRNGs. For example, a PRNG used
only to generate triple-DES keys may never be vulnerable to
this kind of attack, since the PRNG outputs are never directly
seen.
2.3.2. Input-Based Attacks:
An input attack occurs when an attacker is able to use
knowledge or control of the PRNG inputs to cryptanalyze the
PRNG, i.e., to distinguish between PRNG output and random
values. Input attacks may be further divided into known-
input, replayed-input, and chosen-input attacks. Chosen input
attacks may be practical against smartcards and other
tamper-resistant tokens under a physical/cryptanalytic attack;

they may also be practical for applications that feed
incoming messages, user-selected passwords, network
statistics, etc., into their PRNG as entropy samples.
Replayed-input attacks are likely to be practical in the same
situations, but require slightly less control or sophistication
on the part of the attacker. Known-input attacks may be
practical in any situation in which some of the PRNG inputs,
intended by the system designer to be hard to predict, turn
out to be easily predicted in some special cases. (An obvious
example of this is an application which uses hard-drive
latency for some of its PRNG inputs, but is being run using a
network drive whose timings are observable to the attacker.)
2.3.3. State Compromise Extension Attacks:
A state compromise extension attack attempts to extend
the advantages of a previously-successful effort that has
recovered S as far as possible. Suppose that, for whatever
reason - a temporary penetration of computer security, an
inadvertent leak, a cryptanalytic success, etc.- the adversary
manages to learn the internal state, S, at some point in time.
A state compromise extension attack succeeds when the
attacker is able to recover unknown PRNG outputs (or
distinguish those PRNG outputs from random values) from
before S was compromised, or recover outputs from after the
PRNG has collected a sequence of inputs which the attacker
cannot guess. State compromise extension attacks are most
likely to work when a PRNG is started in an insecure
(guessable) state due to insecure client starting entropy. They
can also work when S has been compromised by any of the
attacks in this list, or by any other method. In practice, it is
prudent to assume
that occasional compromises of the state S may happen;
to preserve the robustness of the system, PRNGs should
resist state compromise extension attacks as thoroughly as
possible.

II. OUR APPROACH

As . Nascent approach for enhance the security of
Double DES:
In this article, we approach to improve the security level
of Data Encryption Standard using a random number
generator. We use a random no. generator for modify the
key. As we know key size is 56 bits are used, first generate a
random number through random number generator and
according this generated number we modify our secret key
on both side for encryption and decryption. The details of
our approach are
1. First, Generate a random number using PRNG.
R
1 From
Pseudo

Random Number Generator
(PRNG)
2. Implement a function F on our secret key. Where K
1
=
K
2
in both encryption and decryption in Double DES.

K
11
F(K
1
and R
1
)
3. Now, we encrypt and decrypt our plain text using this
new generated key K
11
.
For Encryption
C.T. = K
11
(P.T.) Two times in double DES

For Decryption
P.T. = K
11
(C.T.) Two times in double DES

III. ACKNOWLEDGEMENT

I would like to thank my official supervisors and
Professor Dr. Prashant Kumar Pandey for all their help,
advice and encouragement.

IV. CONCLUSION
The proposed scheme is to explore the use of symmetric
key in double data encryption standard (D-DES)
Cryptosystem. We will use a new key generation scheme
and optimized the use of generated symmetric key in double
data encryption standard for removing the meet-in-middle
attack. When we use a different key in each block, the
attacker can take more or more time to decrypt the complete
message. As we know, the various cryptosystem are working
on symmetric key using different mode of encryption with
different symmetric key combination in our day to day life
for secure communication, the success in this modern era.

REFERENCES
[1]. P.C. van Oorschot and M.J. Wiener, Improving implementable
meetin- the-middle attacks by orders of magnitude, CRYPTO
'96, Springer- Verlag, 1996.
[2]. M. Santha and U.V. Vazirani, Generating Quasi-Random
Sequences from Slightly Random Sources, Journal of Computer
and System Sciences, v. 33, 1986, pp. 75{87.
[3]. M.Matsui: The First Experimental Cryptanalysis of the Data
Encryption Standard, Crypto'94, LNCS 839,Springer, pp. 1-
11, 1994.
[4]. Eli Biham and Adi Shamir: Differential Cryptanalysis of DES-
like Cryptosystems. Journal of Cryptology, vol. 4, pp. 3-72,
IACR, 1991.
[5]. M. Matsui: Linear Cryptanalysis Method for DES Cipher,
Eurocrypt'93, LNCS 765,Springer, pp. 386-397, 1993.
[6]. Orr Dunkelman, Gautham Sekar, and Bart Preneel:Improved
Meet-in-the-Middle Attacks on Reduced-Round DES, To
appear in Indocrypt 2007.
[7]. DATA ENCRYPTION STANDARD (DES), Federal Information
processing standards, Publication 46-3,1999 October 25.
[8]. Alejandro Hevia, Marcos Kiwi, Strength of two data encryption
standard implementation under timing attacks,ACM Transactions
on Information and System Security (TISSEC), Volume 2,Issue 4
(November 1999) Pages: 416 437.

V
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REFER
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l. 35, December 2
, Fabien A.P. Peti
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2000.
Jajodia, Explor
Computer, Februa
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ration chromo
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Genetic algori
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NCLUSION
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t all known
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teganography
n in which the
image. The
od works pr
optimum solu
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al Value a
2007, pp. 487-520
itcolas,Informatio
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ring Steganograph
ary 1998, pp.26-3
munications Illus
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ented in Java
ithm package
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ntium 4 CPU
less than half a
l test image
hem converged
tions. Table
set for ou
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process. Thi
e message is to
experimenta
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ution. VI.
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.

ISBN: 978-81-920575-6-9 :: doi: 10.73564/ISBN_0768
Literature Survey on LEACH Protocol in Wireless Sensor Network
Aishwary Agrawal (Author)
M. Tech. Scholar (CSE)
BIST
Bhopal, India

AbstractWireless sensor networks have explored to many
new protocols specifically designed for sensor networks where
energy consideration is very crucial. Most of importance, given
to hierarchical routing protocols based on clustering has better
scalability. The common goals of designing a routing algorithm
is not only to reduce control packet overhead, maximize
throughput and minimize the end-to-end delay, but also take
into consideration the energy consumption. Scalability is an
important factor in designing an efficient routing protocol for
wireless sensor networks (WSNs). In this paper we are
proposing a concept of selection of equal energy cluster head
through Equal Energy Routing-LEACH Protocol (EER-
LEACH). Three metrics (power consumption, time of
transmission and packet loss rate) are used in order to
compare three routing protocols LEACH, ER-LEACH and
EER-LEACH.

Keywords-LEACH; ER-LEACH; ERR-LEACH
I. INTRODUCTION
Advances in wireless communication made it possible to
develop wireless sensor networks (WSN) consisting of
small devices, which collect information by cooperating
with each other. These small sensing devices are called
nodes and consist of CPU (for data processing), memory
(for data storage), battery (for energy) and transceiver (for
receiving and sending signals or data from one node to
another). The size of each sensor node varies with
applications. For example, in some military or surveillance
applications it might be microscopically small. Its cost
depends on its parameters like memory size, processing
speed and battery [7]. Today, wireless sensor networks are
widely used in the commercial and industrial areas such as
for e.g. environmental monitoring, habitat monitoring,
healthcare, process monitoring and surveillance. For
example, in a military area, we can use wireless sensor
networks to monitor an activity. If an event is triggered,
these sensor nodes sense it and send the information to the
base station (called sink) by communicating with other
nodes.
We have known that all the protocols which has
designed and implemented for WSN should provide some
real-time support as they are applied in areas where data is
sensed, processed and transmitted based on an activity for
further immediate action. Specialty of real-time protocol is
fast and reliable in its reactions to the changes prevailing in
the network. It should provide redundant data to the base
station or sink using the data that is collected among all the
sensing nodes in the network. The delay in transmission of
data to the sink from the sensing nodes should be short,
which leads to a fast response.
My research area is on Equal Energy Routing Adaptive
Clustering "EER-LEACH" is a routing protocol which is
integrated with clustering and a simple routing protocol in
wireless sensor networks (WSNs). In another term the
LEACH protocol is an effective sensor network routing
protocol. It is one of the most common routing protocols in
hierarchical routing. The goal of LEACH is to provide data
aggregation for sensor networks while providing energy
efficient communication that does not predictably deplete
some nodes more than others.
LEACH (Low Energy Adaptive Clustering Hierarchy) is
designed for sensor networks where an end-user wants to
remotely monitor the environment. In such a situation, the
data from the individual nodes must be sent to a central base
station, often located far from the sensor network, through
which the end-user can access the data. There are several
desirable properties for protocols on these networks:
Use 100's - 1000's of nodes
Maximize system lifetime
Maximize network coverage
Use uniform, battery-operated nodes
Conventional network protocols, such as direct
transmission, minimum transmission energy, multi-hop
routing, and clustering all have drawbacks that don't allow
them to achieve all the desirable properties. LEACH
includes distributed cluster formation, local processing to
reduce global communication, and randomized rotation of
the cluster-heads. Together, these features allow LEACH to
achieve the desired properties. We have already known that
LEACH is a hierarchical protocol in which most nodes
transmit to cluster heads, and the cluster heads aggregate
and compress the data and forward it to the base station.
Each node uses a stochastic algorithm at each round to
determine whether it will become a cluster head in this
round. LEACH assumes that each node has a radio powerful
enough to directly reach the base station or the nearest
cluster head, but that using this radio at full power all the
time would waste energy.
The LEACH algorithm divides the network life time into
a number of rounds, where each round has two phases:
Setup phase (clusters formation) and Steady State Phase
(operating phase). In the Setup phase the clusters are formed
autonomously. Each node selects a random number between
0 and 1; if this random number is greater than a threshold T
then the node will be selected as a cluster head and
broadcasts an advertisement message containing its Id. Due
to the random nature of the selection the cluster heads can
be any node randomly scattered throughout the network.
Nodes which have already been a cluster head from the
process. Other nodes (non-cluster head) decide to join a
cluster depending on the signal strength of the received
advertisements in the form of energy of nodes, and then the
nodes send a Join-Request message to the selected CH.
After the CH receives the joining messages from other
nodes which decided to join this cluster; the CH creates a
schedule and broadcasts this schedule to all the cluster
members.
This paper is organized as follows: in section II we
present a brief survey on various research papers on
LEACH, section III includes a description of our proposed
idea. Finally, section IV provides concluding remarks and
highlights our proposed work.
II. LITERATURE SURVEY
Here a newly developed technique named, Adaptive
Cluster Management for Energy Efficient Sensor Networks
[2] is discussed. In this paper they considers ways to
improve the prolong life time of the wireless sensor
networks. Power consumption during communication
phases is the greatest limiting factor to sensor network
lifetime. Basically the main aim of this paper is to increase
the lifetime or data communication capacity of cluster based
schemes. This paper they have used a technique of routing
protocol to enhance the hieratical routing protocol LEACH-
C. In this technique they used an adaptive method to control
the communication phase depending upon network state.
Here another newly developed technique named,
Evaluation of LEACH Protocol Subject to Different Traffic
Models [6] is discussed. In this paper author introducing
different traffic models to LEACH protocol for wireless
sensor network. Network performance of LEACH with
these traffic models is analyzed. Results of this paper is
trying to provide design guidelines for LEACH
implementation under a realistic traffic model in which each
node has a range of transmission probabilities and for a
range of network sizes. Furthermore, by incorporating
realistic energy model from Crossbow MICA2 motes. In
this paper simulation results show that LEACH has
promising performance when implemented with Crossbow
MICA2 motes.
Energy Efficient Communication Protocols for Wireless
Sensor Networks [1] is discussed. In this paper author
presents Energy saving is a paramount issue in wireless
sensor networks (WSNs). WSN distributed autonomous
devices using sensors to cooperatively monitor physical or
environmental conditions, such as temperature, sound,
vibration, pressure, motion or pollutants. One of the
limitations of wireless sensor nodes is their inherent limited
energy resource. Since these devices rely on battery power
and may be placed in hostile environments replacing them
becomes a tedious task. Besides maximizing the lifetime of
the sensor node, it is preferable to distribute the energy
dissipated throughout the wireless sensor network in order
to minimize maintenance and maximize overall system
performance [1]. In this paper various energy-efficient
routing protocols are using to compare among themselves
and analyze the energy-efficiency of the system on the basis
of the network lifetime. Results show that study the LEACH
minimizes energy dissipation by exploiting the data-
gathering aspect of micro sensor networks.
Efficient Routing LEACH (ER-LEACH) Enhanced on
LEACH Protocol in Wireless Sensor Networks [3] is
discussed. In this paper, author introducing an Efficient
Routing LEACH (ER-LEACH) which is a modified version
of the well known LEACH protocol; ER-LEACH proposes
vital solutions to some shortcomings of the pure LEACH.
ER-LEACH is expected to perform well especially when the
mobility is high and will prolong the overall network
lifetime through load balancing. In this paper author is try to
improved LEACH protocol by ER-LEACH.
III. PROBLEM FORMULATION
In paper [1] only show the performance of LEACH
protocol under certain constraints like:
Probability of transmission
Network size
Hardware used of crossbow technology
In this paper, the author studies the behavior of leach
protocol on certain condition and presents a comparative
study on that basis. Factors used in this paper are:
Probability of transmission
Network size
Hardware used of crossbow technology
In Paper [5] author presents only the comparative study
of the LEACH, LEACH-C and Static clustering. No new
work performed. This paper is basically presents the study
of three protocols of WSN.LEACH, LEACH-C and Static
clustering and shows that LEACH and LEACH-C
performance is same in some conditions whereas static
clustering performance is poor in these conditions.
In paper [3] author doesnt tell the method to determine
CH (Cluster Head) in case of equal residual power nodes.
This paper presents enhancement in the LEACH protocol by
considering the following factors:
Cluster head selection: on the basis of residual
energy remaining in the node
Selecting alternate cluster head: the enhanced
version will check for an ACH after the setup
phase
Grouping zones: By making zone better
communication can be achieved with low power
consumption, this zoning can be done on the basis
of geographical location
IV. PROPOSED WORK
For [6] we can use more number of factors for finding
optimal condition for the network design which provide
minimum power consumption. In [1] we can study some
more protocols that are helpful to be used in WSN that are
more optimal than the LEACH, Whereas in [3] we can
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ice (QoS). W
forming cluste
S) factor is kep
ailed in transm
he lost data p
ing in figure 1
power
of the
sensor
outing
of the
otocol
some
EACH.
of the
EACH
large
gh of
on and
H and
CH is
nd the
(CH)
y-state
ace. In
select
ection
tween
to find
EER-
of the
tween
ng the
reduce
hanced
oad in
e load
er the
m cost
(BS)
he BS.
when
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d idea
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tency.
ntation
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mitting
packet.
.

of
LEA
pha
pre
pro
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wil
Tra
Thi
larg
imp
from
to
futu
app
clos
[1]
[2]
[3]
Figure 1: Flow
In this section
wireless sens
ACH, ER-LE
ases of cluste
sented in det
oposed mec
rformance eva
l save energ
ansmission for
is advantage b
ge number of
prove quality
m all sensors
compute the
ure to desc
plication for th
sely with effic
Rakesh Poonia
Efficient Comm
published in Ra
Computer Scien
1697-1699.
Ahmed Ghneim
Management fo
ISBN: 978-1-90
Hasan Al-Refa
Yehia M. El.
Enhanced on
w chart of cluster
V. CON
n, we are conc
sor networks
EACH and the
ering, routing
tail. Its comp
chanisms w
aluation will p
gy over com
r small areas
becomes more
nodes. Our pr
of service (Q
in a network
data gatherin
cribed securit
hat. Enhancing
cient way.
VI. RE
a,Amit Kumar Sa
munication Proto
akesh Poonia et a
nce and Informat
mat, John Mellor
for Energy Effici
02560-25-0 20
ai, Ali Al-Awneh
Rahman Effici
LEACH Protoc
head selection in
NCLUSION
cluding our re
(WSN). Th
e complete pr
g, and schedu
plexity was an
were present
roved that our
mpared protoc
and small nu
e significant fo
roposed work
QoS) required
by utilizing s
ng schedule.
ty issues an
g security issu
EFERENCES
anghi and Dharm
cols for Wireles
al, / (IJCSIT) Inte
tion Technologie
r and Ping Jiang
ient Sensor Netw
11 PGNet.
h, Khaldoun Bati
ient Routing LE
col in Wireless
EER-LEACH
esearch. We ha
e novel featu
otocol includi
uling have be
nalyzed and t
ted. Propos
r proposed wo
col, and Dir
umbers of nod
for large areas
will also grea
d to gather d
some extra eff
We will try
nd a potent
ues, and worki
m Singh 3 Ene
s Sensor Networ
ernational Journa
s, Vol. 2 (4) , 20
g Adaptive Clu
works published
iha, Amer Abu A
EACH (ER-LEAC
Sensor Networ
ave
ure
ing
een
the
sed
ork
rect
des.
s or
atly
data
fort
in
tial
ing
ergy
rks
al of
011,
uster
d in
Ali,
CH)
rks
published in International Journal of Academic Research Vol. 3. No.
3. May, 2011, I Part.
[4] M. Hadjila & M. Feham A Comparative study of the Wireless
Sensor Networks Routing protocols scalability Published in
International Journal of Distributed and Parallel Systems (IJDPS)
Vol.2, No.4, July 2011.
[5] M. Bani Yassein, A. Al-zou'bi, Y. Khamayseh, W. Mardini
Improvement on LEACH Protocol of Wireless Sensor Network
(VLEACH) published in International Journal of Digital Content
Technology and its Applications Volume 3, Number 2, June 2009.
[6] Guofeng Hou, K. Wendy Tang Evaluation of LEACH Protocol
Subject to Different Traffic Models Published in The 1 st
International Conference on Next Generation Network Hyatt Regency
Jeju, Korea / July 9 - 13, 2006.
[7] Rmer, Kay; Friedemann Mattern "The Design Space of Wireless
Sensor Networks IEEE Wireless Communications, Dec. 2004.
[8] http://en.wikipedia.org/wiki/Low_Energy_Adaptive_Clustering_Hier
archy


Proc. of th
Volume 1. Co
ISBN: 978-8
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s,
s,
c
s
n,
o
Extemporaneous
Extemporaneous presentation is far by most popular &
effective method when carefully prepared
Enough time, Flexible in language, Material help you
clearly, Rapport with the audience, Preparation is
inadequate, Note cards.
Manuscript
Manuscript presentation, material is written out & you
are supposed to read it out aloud verbatim. Read a
speech, you should know what is written where. Its a
permanent & accurate record of whatever you say, No
change of tampering with the facts & figures , Material is
organized, Language gets polished , Less time for
making eye contact, You cant talk to them because u are
reading, Adaptation is rather difficult , Loss of audience
attenuations.
Impromptu
You have to deliver an informal speech, dont panic &
babble, State your topic & then preview the points you
are to make. U sound very natural, Get a chance to
express your thoughts, Spontaneous, Lacks organized
development, No supplementary material.
Memorization
Only a handful of u can memorize an entire speech,
writing key words, Very easy for speaker to maintain eye
contact, Move & non verbal communication, Allotted
time to finish topic, It requires too much time, No
flexibility or adoption , Forget .
Kinesics
Kinesics is the name given to the study of the bodys
physical movements. Personal appearance, Posture,
Gesture, Facial expression, Eye contact.
Proxemics
It is the study of physical space in interpersonal
relations.
Intimate (contact to 18 inches), Personal (18 inches to 4
feet), Social (4 to 12 feet), Public (12 feet to range of
sight), our behavior in each is determined by our culture.
We need to be sensitive to the space conditioning of
others.
Paralinguistic
Its are the feature of non-verbal vocal cues that help
you to give urgency to your voice.
Quality, Volume, Pace/Rate, Pitch, Articulation,
Pronunciation, Voice modulation, pauses.
Chronemics
Its all the time management.
IV Group Communication
Importance to all teamwork and group communication,
Businesses enterprise, government, educational institutes,
Team as become integral part, Groups are developing
into teams. The group communication is distributed like
Group Discussion, Organizational Group discussion,
Group discussion as part of selection process.
To share & exchange information and ideas, to collect
the information or feedback, to arrive at a decision on
important factors, to solve problem, to discuss the issues,
to elaborate upon any work.
a.Group Discussion
Face to face, Oral interaction, Share & discuss ideas,
Decision making, Problem solving, short list the
candidates.
Organizational Group discussion
Its is used mainly group decision making, Reduces the
many problems, Techniques
b.Brainstorming
Brainstorming is a method for generating a variety of
ideas and perspectives. The steps include like
1. A group of 6 or 12 people sit around a
table
2. The group leader states the problem in
clear manner so that all participated can
understand
3. Members then suggest as many
alternates as they can give in oral or write or on
paper or white board
No criticism is allowed, and all the alternatives are
recorded
Nominal Group Technique
The group persons present in traditionally, the steps like
1. Members meet as a group each person
write ideas on the problem
2. Each member will take his turn around
the table
3. The group now discuss on the idea for
clarity
4. Each group members silently and
independently rank-order the list
5. The finally decision is determined by
the highest aggregate rank

C.Delphi Technique
Its is more complex and time consuming, Similar to
nominal technique but does not require physical presence
of the group members. The steps are
1. The problem techniques is identified
and members are asked to provide potential
solution through series of carefully designed
questionnaires
2. Each member anonymously and
independently complete the first questionnaires
3. The results of the first are compiled at
center location & reproduced
4. Each member receives a copy of the
results
5. After viewing the results, the members
are asked for their solutions
6. Steps 4 & 5 are repeated as often as
necessary until consensus is reached.

Group discussion as part of selection process
Judging the personality of candidates, their
communication skills, knowledge and their ability to
work as a team, it is conducted for selection processes,
some topic or case for discussion, normally 8-10 time
limit 20-30 minutes, Circle or block or u-shape, Team
playing skill.

Evaluation Components
Knowledge, Communication skill, Group behavior,
Leadership potential.

Knowledge
The depth & range of your knowledge as well as your
analytical & organizational abilities.
Remember you are being evaluated on how you think
and not what you think.
Communication skill
You will be assessed in terms of, Active listening,
Clarity of thought & expression, Tone, Voice,
Articulation, Fluency, Modulation, Good delivery, Apt
language, Appropriateness of body language.
Group behavior
Emotional maturity & balance promotes good
interpersonal relationships
Leadership potential
The candidates who possesses both functional ability &
co-coordinating ability will emerge as the leader
1. Approach to topic & case studies
2. Group discussion based on a topic
3. Group discussion based on a case study
V Interviews
An interview is a psychological and sociological
instrument; it is an interaction between two or more
persons for a specific purpose. The interviews are
classified into Objectives, Types of Interviews, and Job
Interviews.
a.Objectives
The conduct of interview depends very much on the
reason behind it., Interviews are conducted achieve,
some of the following objective, To select the person for
a specific task, To collect information, To exchange
information, To counsel, To monitor performance.

Types of Interviews
Depending upon the objective & nature, interview can
be categorized into following types Job, Information,
Persuasive, Exit, Evaluation, Counseling, Conflict-
resolution, Disciplinary, and Termination.

a.Job Interviews
It can be classified either face to face or telephonic
Disposition, Career objective, Subject knowledge,
General knowledge , Communication skill, Mental
agility ,Consistency ,Self confidence.
b.Success Factor
Positive attitude towards work, Proficiency in the field
of study, Communication skills, Interpersonal skills,
Confidence, Critical thinking & problem solving skills,
Flexibility, Self motivation , Leader ship, Teamwork.
c.Failure Factor
Arrogance, Apathy , Uninhibited nervousness ,
Equivocation, Lack of concentration, Lack of crispness,
Lack of social skills, Lack of firmness, Qualitative skills
,Unsuitable personality .
Preparation
Go through a mock interview, Gather adequate inside
information, Dress appropriately, be prepared to ask
questions, Memorize your resume, be punctual, Relax.
Types of questions
Exprience questions, Credential questions, Options
questions, Dumb questions, Behavioral questions,
Difficult questions.
Process
Establishing rapport, Gathering information, closing.
Tips for Success
Be well prepared, Brush up your subject & general
knowledge, Memorize resume, Know about the
company, Dress appropriate, Carry a neat folder
contenting all the things, Be polite, Never chew gum or
smoke during interviews, Do not answer a question you
did not understand, Show a real interest in job, Speak
clearly and positive, Smile and say thank you, Shake
hands firmly.

CONCLUSIONS
In this article I am going to explain the concept of the
technical communication has been explained, from the
literature survey & from the experience of the author.
The process like basic communication, including barriers
communication. Effective presentation, interviews, and
group discussion are present to upcoming students to
identify their weakness and make them to improve the
best skills and improve the communication gap in
respective areas. Is highly recommended because it is
proved to be more effective, practical, ensures
confidence in students life deployment. It is the first most
important to identified the requirement and quality
standards and finally the review and analysis result is
very accurate.

REFERENCES

[1] Technical communication by Meenakashi Raman and Sangeeta
Sharma, Fact Book, Second Edition, 2001.

[2] Ethics in information technology by George Reynolds.

[3] Business communication by Raymond V Lesikar, Marie E Flately,
Karthryn Rentz, Neerja Pande.


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III. DATA REDUNDENCY & INCONSISTENCY

Data redundancy occurs in database systems which
have a field that is repeated in two or more tables. Data
redundancy leads to data anomalies and corruption and
generally should be avoided by design. Database
normalization prevents redundancy and makes the best
possible usage of storage. Proper use of foreign keys
can minimize data redundancy and chance of
destructive anomalies. However sometimes concerns of
efficiency and convenience can result redundant data
design despite the risk of corrupting the data. Different
files may have different formats and the programs may
be written in different programming languages as they
are developed by different programmers. The same
information may be duplicated in several places (files).
For example, the address and telephone number of a
particular customer may appear in a file that consist of
saving-account records and in a file that consists
checking account records. This redundancy leads to
higher storage and access cost. It may lead data
inconsistency; that is, the various copies of the same
data may no longer agree.
IV. DATA ISOLATION
Since data is scattered in the various files, which
might be in different formats thus, it is difficult to write
a new application to retrieve appropriate data.
Generally the terms security and integrity are
considered to be same, but these two concepts are quite
distinct. Security refers to the protection of data against
unauthorized disclosure, alteration or destruction;
integrity refers to the accuracy or validity of data. In
other words,
Security involves ensuring that users are allowed to
do the things they are trying to do.
Integrity involves ensuring that the things are trying
to do correct.

Why do we need security?
The very obvious reason for the security is to
prevent misuse of the database by international and
accidental causes.
Crashes during transaction processing;
Anomalies caused by concurrent access to the
database;
Anomalies caused by distribution of data over
several computers;
Logical errors that violate the assumption that
transaction preserve the database consistency
constraints.

The various aspects to the security problem are:
1. Legal, social and ethical aspects e. g does the
person making the request, say for withdrawing money
from a bank, has legal rights for making the requested
transaction?
2. Physical controls e. g is the computer or terminal
room always locked or otherwise guarded.
3. Policy questions e. g how does the enterprise
owning the system decide who should be allowed and
to what?
4. Operational problems e. g is a password schema
is used, how are the passwords themselves kept secret?
How often are they changed?
5. Hardware controls e.g. does the processing unit
provide any security features, such as the storage
protection keys or a privileged operation mode?
6. Operating system security e.g. does the
underlying operating system erase the contents of
storage and data files when they are finished with?
Integrity problems:
The data values stored in the database must satisfy
certain types of consistency constraint. For example, the
balance of a bank account may never fall below a
prescribed amount (say, Rs.500). Developers enforce
these constraints in the system through hard coding
these conditions. When new constraints are added, it is
difficult to ensure this property in a conventional file-
processing system.
Security problems:
Every person should not be allowed to access the
database for security purposes. Since application
programs are added to the system in an ad-hoc manner,
it is difficult to ensure such security constraints.

V. FILE
A file is organized logically as a sequence of
records. These records are mapped onto disk blocks. is
usually a tight coupling between the operating system
and the file system. Files are provided as a basic
construct in operating system, so we shall assume the
existence of an underlying file system. A file is durable
in the sense that it remains available for programs to use
after the current program has finished. Computer files
can be considered as the modern counterpart of paper
documents which traditionally are kept in offices and
libraries files. Information in a computer file can
consist of smaller packets of information (often called
"records" or "lines") that are individually different but
share some trait in common.
BLOCKS
A Block is a sequence of bytes or bits, having a
nominal length (a block size). Hence blocks are the
small area where data is stored. Although blocks are of
fixed size, determined by the physical properties of the
disk but by the operating system, record size varies.
Most file systems are based on a block device, which is
a level of abstraction for the hardware responsible for
storing and retrieving specified blocks of data, though
the block size in file systems may be a multiple of the
physical block size.

VI. TRADITIONAL FILE ORIENTED
APPROACH

The traditional file-oriented approach to information
processing for each application has a separate master
file and its own set of personal files. An organization
needs flow of information across these applications
also, and this requires sharing of data, which is
significantly lacking in the traditional approach. One
major limitation of such a file-based approach is that
the programs become dependent upon the programs.
Although such file-based approaches which came
into being with the first commercial applications of
computers did provide an increased efficiency in the
data processing compared to earlier manual paper
record-based system as the demand for efficiency an
speed increased processing started suffering from the
following significant disadvantages.

VII. FIXED AND VARIABLE LENGTH FILE

One approach to mapping the database to files is to
use several files, and to store records of only fixed
length in any given file. An alternative is to structure
our files such that we can accommodate multip0le
length of file records. Files of fixed-length records are
easier to implement then are files of variable length
records. Many of techniques used for the former can be
applied to the variable length case. Thus we begin by
considering a file of fixed-length records.
Keeping the data in the variable length records file
is advisable because it save space , which is being
wasted in the fixed-length files. And if the data goes out
of the fixed limit then also it can be summed up in that
length.

VIII. EXPLANATION OF THE DATABASE
STORAGE IN THE FILE SYSTEM

A database system is partitioned into modules that
deals with each of the responsibility of the overall
system. Computer's operating system provides most of
the basic services and the database system must build
on that base.
The functional component of the database system
can be broadly divided into 2 categories: Query
processor component and Storage manager component.
IX. OS FILE SYSTEM

The main purpose of computers is to create,
manipulate, store, and retrieve data. A file system
provides the machinery to support these tasks. At the
highest level a file system is a way to organize, store,
retrieve, and manage information on a permanent
storage medium such as a disk. File systems manage
permanent storage and form an integral part of all
operating systems.
There are many different approaches to the task of
managing permanent storage. At one end of the
spectrum are simple file systems that impose enough
restrictions to inconvenience users and make using the
file system difficult. At the other end of the spectrum
are persistent object stores and object-oriented
databases that abstract the whole notion of permanent
storage so that the user and programmer never even
need to be aware of it. The problem of storing,
retrieving, and manipulating information on a computer
is of a general-enough nature that there are many
solutions to the problem. There is no correct way to
write a file system. In deciding what type
of filing system is appropriate for a particular
operating system, we must weigh the needs of the
problem with the other constraints of the project. For
example, a flash-ROM card as used in some game
consoles has little need for an advanced query interface
or support for attributes. Reliability of data writes to the
medium, however, are critical, and so a file system that
supports journaling may be a equirement. Likewise, a
file system for a high-end mainframe computer needs
extremely fast throughput in many areas but little in the
way of user-friendly features, and so techniques that
enable more transactions per second would gain favor
over those that make it easier for a user to locate
obscure files. It is important to keep in mind the
abstract goal of what a file system must achieve: to
store, retrieve, locate, and manipulate information.
Keeping the goal stated in general terms frees us to
think of alternative implementations and possibilities
that might not otherwise occur if we were to only think
of a file system as a typical, strictly hierarchical, disk-
based structure.

X. FILE SYSTEM
A file system (filesystem) is means to organize data
expected to be retained after a program terminates by
providing procedures to store, retrieve and update data,
as well as manage the available space on the device(s)
which contain it. A file system organizes data in an
efficient manner and is tuned to the specific
characteristics of the device. Structure represents the
way of summarizing the information. There are two
ways viz.: "Stream of bytes", "records".
Without a filesystem programs would not be able to
access data by file name or directory and would need to
be able to directly access data regions on a storage
device.
File systems are used on data storage devices such
as magnetic storage disks or optical discs to maintain
the physical location of the computer files
When we put our data in the unorganized way, then
it is known as the "raw data" or "Stream of bytes". In
this type, no size and file structure is decided. User can
read from 1 to 17 words at a unit time. Alignment and
the size of the I/O request is also not specified.
A managed and organized way of representation is
known as "record". Here user specifies the size and
format of the record, and then all I/O to that file must
happen on record boundaries and be a multiple of the
record length.
After storing the next work is to fetch the file. This
requires some techniques for the fast tracking:
1.Put the name of the file in some meaningful way.
2.Do indexing.
3.Sequencialize the data.
4. Store data at a proper place.

XI. PROPOSED SYSTEM

In our model we will built the database which
during the installation ask the Operating System to
specify the amount of memory or the disk which can be
allotted to the database. After specifying the allotted
space the database will do the clustering the space and
organized it according to the need of the Database. In
this proposed database there is a separate File system
interpreter is used which translate the address location
of the files created by the Database system into the
address location specified by the Operating System File
system. The operating system addresses again translate
back into the address specified by the database file
system. The TLB or the page table is automatically
updated by the Operating System in order to maintain
the homogeneity of the file system.
The TLB contains a set of entries, each of which
contains a page number, the corresponding page frame
number, and the protection bits. There is special
hardware to search the TLB for an entry matching a
given page number. If the TLB contains a matching
entry, it is found very quickly and nothing more needs
to be done. Otherwise we have a TLB miss and have to
fall back on one of the other techniques to find the
translation. However, we can take that translation we
found the hard way and put it into the TLB so that we
find it much more quickly the next time. The TLB has a
limited size, so to add a new entry, we usually have to
throw out an old entry. The usual technique is to throw
out the entry that hasn't been used the longest. This
strategy, called LRU (least-recently used) replacement
is also implemented in hardware.

ADVANTAGES OF PROPOSED SYSTEM
1. Increased integrity.
2. Less seeking time.
3. Work on a specific kind of data.
4.Save from the external threats, as the location of
the space is encrypted in the O.S..
5. Lesser page faults.
6. Fast searching Operation.
7. Fast query processing.
8. Resolves delay problem.
9. Better memory management.
10. The optimization of the memory will take place
as it reduces the problem of Holes or segments.

XII. CONCLUSION

Hence the file system proposed by us will work with
conjunction with portaging file system will increase the
speed of various quires and commands. As compare to
the file system of operating system the files manage by
the file system of the database the searching is easy and
fast and it also reduces the page fault which occur due
to the non availability of the page frame.

REFERENCES

[1] Alex Szalay, Science Magazine, Vol 323, 6 March, 2009 Podcast
[2] http://podaac.jpl.nasa.gov/WEB_INFO/glossary.html#DDD
[3] Gray et al. Scientific Data Management in the Coming Decade
[4] NSF - Workshop on the Challenges of Scientific Workflows May
12, 2006 Arlington, VA
[5] http://nasascience.nasa.gov/researchers
[6] LUSTRE File System: High Performance Storage and Scalable
File System. Sun, Dec 2007
[7] Olsen, Zimmerman, Bos Scientific Collaboration on the Internet
[8] http://www.w3.org/TR/owl-guide/#OWLGlossary
[9] The Semantic Web in Action, Scientific American Dec. 2007
[10]Ganesh, et al. http://www.vldb.org/pvldb/1/1454170.pdf
ISBN: 978-81-920575-6-9 :: doi: 10. 73487/ISBN_0768
An FPGA Based Framework for Exploitation of Multinode Architecture

Yasodai.A,
Dept of ECE
Vickram college of Engg,
Enathi,
Sivagangai, India
Abstract-With the growing complexity in consumer
embedded products and the improvements in process
technology, Multi-Core architectures have become
widespread. These new systems are very complex to design
as they must execute multiple complex real-time
applications (e.g. video processing, or videogames), while
meeting several additional design constraints (e.g. energy
consumption or time-to-market). Thus, in order to explore
all the possible HW-SW configurations in multi- Core,
simulation is not practical anymore due to the large
overhead in time of cycle-accurate simulators. The cycle
accurate software simulators do not provide a feasible way
to handle the modern embedded multi core architectures.
The interest has recently shifted from well established cycle
accurate full system simulators to the adoption of Field
Programmable Gate Array (FPGA) based hardware
emulation platforms, whose trends in integration capability,
speed and price propose them as a candidate to speed up
the exploration of large multi-core architectures .Execution
of multiprocessors in embedded system does not provide a
speed accuracy tradeoff. Therefore, our project aims to
achieve speed accuracy and power consumption through
VLSI implementation by VHDL coding. For our easy
implementation and reduce the complexities, we have
consider each processor as a node.

I. INTRODUCTION
II.
Manufactures have given up attempting to extract
ever more performance from a single core and instead
have turned to multi-processors designs. While
programmed into a single FPGA. With multiple FPGAs
on a board and multiple boards in a system, large
complex architectures can be explored. Such a system
would not just invigorate multiprocessors research in the
architecture community. Since processors can run at 100
to 200 MHz, a large scale multiprocessor would be fast
enough to run operating systems and large programs at
speeds sufficient to support software research.
Simulation has been adequate for single-processor
research, significant use of simplified modeling and
statistical sampling is required to work with 216
processors. Today, one to two dozen processors can be
some of practical approach of multi-processor is editing
a photo while recording a TV show through a digital
video recorder, Downloading software while running an
anti-virus program. But some of the applications are
difficult to parallelize. For such parallel software
development, cycle accurate simulator in embedded
system does not give a speed accuracy tradeoff. To
overcome this, in a IEEE letter (Vol.2) Paolo Meloni,
Simone Secchi and Luigi Raffo proposed an FPGA
based framework for Multi core architectures .A Cycle
Accurate Simulator (CAS) is a computer program that
simulates a micro architecture cycle-accurate. CAS is
used when designing new microprocessors - they can be
tested, and benchmarked accurately (including running
full operating system, or compilers) without actually
building physical chip, and easily change design many
times to meet expected plan. Cycle Accurate Simulator,
must ensure that all operations are executed in the proper
virtual (or real if it is possible) time - branch prediction,
cache misses, fetches, pipeline stalls, thread context
switching, and many other subtle aspects of
microprocessors.
Cycle Accurate Simulators
Cycle-accurate simulators are one of the
prevailing simulation tool in computer architecture
research. Unfortunately, the results generated by Cycle-
accurate simulators can be misleading due to unknown
amount of error. There are a number of problems with
cycle accurate simulator, in general:
Speed:
Simulators are slow, often multiple
orders of magnitude slower than native execution. Many
researchers commonly use reduced-execution methods
can compound simulation errors, if not carefully applied.
Generalization:
Simulators are often highly
configurable, since the authors often want to create a tool
can be used to model a multitude of different situations.
The end result is that a single simulators can model all
architecture, built it may model them all in equally poor
manner. Another problem is that the more configurable a
simulator, the easier it is to configure it improperly often
in non obvious ways. This has been one of the biggest
problems for these simulators.
Validation:
Most simulators are not validated
against real hardware and when they are, the results are
rarely within 10% errors, even after extensive effort has
been taken to attempt to model a known architecture.
Documentation:
Simulators use often poorly
documentation both at a high level and at the source
code level. This alone probably accounts for more errors
in simulation than any other overt programming bugs.
Code forks:
Since few people are using the
simulator at any given time, the code base quickly
becomes unmaintained and fragmented among the group
using it. Bugs may be fixed at different times and at
different institutions.
The source code diverge so much that
when one people claims it are a particular simulator that
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REFERE
P. Meloni, S. C
a NoC and a tra
ness, in Proc. D
many, 2006.
sanovic, C. Kozy
ch Accelerator
Vision for a Share
.
Sunwoo, J. Kim
Keefe, and H
hnologies (FAST)
in Proc. 40
th

ture, Washington,
K. Compton,
computing resea
p. 17, 2006.
Loi, F. Angiolini
, Area and pow
wareness, VLSI-D
. Bertozzi, A. B
ARM: Exploring
stemC, J. VLSI
2, 2005.
ccurare simulatio
Sally M.MC kee
NCLUSION
he drawbacks
e accuracy. In
is 0.8 sec
on time for tr
500ns.Apart
ws other advan
r consumptio
nvironment ,i
ation, tool sup
fications can b
even in the fiel
ENCES
Carta, L. Benin
aditional intercon
Design, Autom.,
zyrakis, S. L. Lu
for Multiple
ed Experimental
m, N. A. Patil, W
H. Angepat, F
T): Fast, full-syste
Annu. IEEE/A
, DC, 2007, pp. 2
A simulatio
arch, FPLFie
i, S. Carta, M. B
wer modeling for
Design J., 2007.
Bogliolo, F. Me
g the multi-proce
Signal Process.
on a waste of
e.
in embedded
the proposed
but in ou
ransfer of task
from that the
ntages like les
on ,long term
ip integration
pport(EDI),low
be made it any
ld.
ni, and L. Raffo
nnect fabric with
Test Eur. Conf
u, and M. Oskin
e ProcessorsA
Parallel HW/SW
W. Reinhart, D. E
FPGA-accelerate
em, cycle-accurat
ACM Int. Symp
249261.
on platform fo
eld Programmabl
Barbaro, L. Raffo
networks-on-chip
enichelli, and M
essor SoC design
Syst., vol. 41, no
time byVincen

d
d
ur
k
e
s
m
n,
w
y
o,
h
f.,
n,
A
W
E.
d
te
p.
or
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o,
p
M.
n
o.
nt


ISBN: 9788192057569 :: doi: 10. 73529/ISBN_0768
Universally Compatible DSP Based Wire Feeder Controller for MIG Welding
System

Abstract This work presents the real time implementation of
DSP based wire feeder controller which discloses details on
Universally Compatible DSP Based Wire Feeder Controller for
MIG Welding System. This universal compatible DSP based
electrode wire feeding interface controller includes all welding
functions that are placed in the power source, which is
compatible with any power supplies with wire feeders which
reduces the inventory and increases commonality. To improve
the weld quality, it is required to have optimum values of
electrical parameter setting in the welding power supply. For
this purpose, it is necessary to control the current for good
welding, which is controlled by regulating the wire electrode
feeding mechanism. In the feeder controller, a closed loop PID
control system is implemented for the electrode wire feeding
and speed control. And also many functions such as creep,
crater and mode selection have been implemented which gives
the better welding performance for different wire diameters.
Keywords- Interface, MIG Welding; PID Control; Wire
Electrode; Wire Feeder.
I. INTRODUCTION

This paper presents the novel idea for compatible wire
feeder interface controller with power source [1]. The MIG
(Metal Inert Gas) or MAG (Metal Active Gas) process is
used in the welding machine. In the controller, operator set
the optimum voltage and current for the different wire sizes.
The welding current can be controlled by adjusting the wire
electrode speed. The wire speed can be varying between 1.5
to 20 m/min for different wire dimensions from 0.8 to 1.6
mm. The pressed current allows the formation of the solder
puddle and reducing the drainage for the spray production
from this the quality of the solder depends on the control of
the current. The control of the process is accomplished by
dsPIC controller that implements a PID control algorithm
that acts in the manipulation of the speed of feeding of the
wire electrode and in the adjustment of the current supplied
by the energy source. The controller also receives different
input signals and process, to improve the performance of the
welding by avoiding initial jerk, bubble formation, steady
state welding operation, mode selection, gas test etc all are
user friendly [2].
II. TECHNICAL WORK DESCRIPTION
a.Background
The present development relates to the wire feeder
mechanism of welding devices, in certain embodiments, to
improve methods and apparatus for controlling wire
electrode advancement.
A common metal welding technique employs the
principle of heat generated by electrical arc is used to
change the state from solid state to molten state, to facilitate
a welding process [2]. One technique that employs this
arcing principle is wire feed welding.

Figure1. Gas Metal Arc Welding
In MIG, a spool of solid-steel wire is fed from the
machine, through a liner and comes out of a contact tip in
the MIG gun. The contact tip is hot or electrically charged,
when the trigger is pulled and melts the wire for the weld
puddle. This is accomplished in several ways. In short-
circuit welding, small droplets of molten wire is heated
when short-circuited, flow together to make a puddle as they
touch the base metal. Inert gas flows out of the gun and
keeps the weld puddle shielded from the atmosphere. Thus,
metal inert gas, inert gas means the gas which will not
combine with another element; so inert gases, like helium
and argon, were used. Then it was discovered that carbon
dioxide, which is not actually an inert gas also worked well.
MIG welding is a commonly used high deposition rate
welding process. Wire is continuously fed from a spool.
Srinivasan K
Sr. Engineer R&D
ESD, ESAB India Ltd
Chennai, India

Thiruvenkadam M
Sr. Engineer R&D
ESD, ESAB India Ltd
Chennai, India

Paramasivam S
R&D Head
ESD, ESAB India Ltd
Chennai, India

The diagrammatical representation of MIG welding system
illustrated in figure 1. If the welding devices properly
adjusted, the wire feed advancement and arcing cycle
progresses smoothly and provides a good weld.
For various applications, different kinds of wires are
used. The selection of the particular type of wire depends on
several factors, includes the type of materials being
wel ded, t he wel d design, material surface condition,
quality concerns and process variation concerns [3]. Due to
these considerations, the different kinds of wires have widely
varying diameter sizes were used.

Figure 2. Weld Process

During the welding operation [4], the feeder mechanism
fed the wire electrode to gun at a constant speed. This speed
is set by the operator via a variable knob no control circuit.
An operator may select between various kinds and sizes of
wire electrode. However different kind of wire electrode
performs well at different operational settings of the
welding devices. That is, the different kinds of wire
electrode perform well within different levels of voltage and
current. The figure 2 shows diagrammatical representation
of weld process.
When the operator triggered the torch, the feeder
mechanism starts to feed the electrode wire from the wire
spool through the torch gun. At the end of the torch gun
there is a nozzle, shield gas and the wire electrode are
coming out of the torch gun. When the electrode is brought
in to close proximity with the work piece, completing the
circuit and generate sufficient heat to weld the work piece.
The different kinds of agent, making various model of wire
feed mechanism, hence it will not compatible with all power
sources and also the local manufacturers are not considering
the some welding functions like preflow of gas, creep, mode
selection, burn back, post flow of gas, crater fill etc, it leads
to the initial jerk while striking the electrode wire with work
pieces, electrode wire struck with weld buddle, regenerative
breaking of wire feeder motor and bubble formation at the
end of wire electrode. Therefore, there exists a need for
new development and a method to control the wire feeder,
include all weld functions compatible with all power
sources.
A. Detailed Description
In present development, in accordance with certain
embodiments, provides a method and apparatus for
controlling the wire feed mechanism in a welding system.
In MIG welding systems incorporating the present
development can includes the universal compatibility with
wire feed mechanism that links the simple method for
adjusting the voltage and current level. Thus, in such a
system, if an operator make an adjustment in the voltage and
current through a simple knob, the wire speed would be
automatically adjusted to accommodate the new current
setting [5]. Alternatively, the selected wire feed speed can
be automatically determined by an output current level.
Advantageously, the linked relationship between the current
level control and the wire feed control can assist the
operator for obtaining the desirable performance and,
furthermore can facilitate multifunctional control of the
welding device via a single knob. The figure 3 illustrates an
exemplary welding system that includes an embodiment of
this wire feed control development [6]. Indeed, the systems
are often stationed by less-experienced operator.
Returning to the exemplary welding system, it includes a
gas setup, wire feed mechanism and welding torch that
defines the location of the welding operation with respect to
a work piece [7]. When the welding torch at a location
proximate to the work piece allows direct current provided
by a power source, which converts the incoming alternating
current (AC) power to an appropriate direct current (DC)
power flows through welding torch via a wire feed
mechanism, welding cable to arc from the welding torch to
the work piece. In summary, this arcing completes an
electrical circuit from the power source to work piece via
the welding torch cable to wire electrode and negative
terminal. Advantageously, this arcing generates a relatively
large amount of heat causing the work piece and filler metal
to transit from solid state to a molten state, facilitating the
weld.
To produce electrical arcing, the exemplary system
includes a wire feeder unit that provides a consumable wire
electrode to the welding torch cable. In this torch cable,
electrical current conducts through wire electrode via a
contact tip located in the neck assembly, leading the arcing
between the egression wire electrode and work piece.
To shield the weld area from contaminants during
welding, to enhance arc performance, and to improve the
resulting weld, the exemplary system includes a gas source
that feeds an inert shielding gas to the welding torch via
welding torch cable. A solenoid valve is used to open and
close the gas to the welding torch cable. In the exemplary
system also includes a facility for checking the availability
of gas and an operator can set the pressure of gas without
triggering the torch.

Figure 3. MIG System with Interface Controller

a.Hardware Parts of the Wire Feeder
The figure 4 shows the structure of a digital feeder with
the dsPIC30F6010A as its CPU (Central Processing Unit). The
controller is a 16-bit high performance modified RISC
(Reduced Instruction Set Computation) processor with
Harvard architecture. Its clock frequency is 30MIPS (Million
Instruction Per Second), which runs at high speed while
includes complete peripheral equipments. It covers almost all
the peripheral functions of a digital wire feeder requirement. It
has 10-bit ADC (Analog to Digital converter), 8 PWM
channels (Pulse Width Modulation), five 16-bit timer and
counter, etc.

Figure 4. Controller Block Diagram
b.Control Techniques of Wire Feeder
The closed loop PID algorithm is used in the controller of the
wire feeder for desired wire feeder speed [8]. The controller of
the wire feeder receives different analog and digital signal
through A/D converter channel for various functions, its
process and delivers PWM, digital and analog signal.
The wire feeder controller obtains set data on wire
feeding from current reference pot and exact data from the
buck converter [9]. With the set data the dsPIC30F6010A
controls the duty cycle of PWM output so as to realize the
control on the wire feeder motor speed. The wire feeding
system adopts closed loop voltage control mode, for sampling
the output voltage and fed to the controller. The PID
(Proportional Integral Derivative) control techniques used to
adjust the PWM to control the wire feeder speed. When the
torch is triggered, set data and the sampled data transmitted to
the controller and it will generate the error signal, depends
upon this error, duty cycle of the PWM is adjusted. This PWM
signal applied to the buck converter through driver circuit. The
dsPIC controller process the error and generate PWM signal
very fast and also based on analog and digital input signal it
will perform the welding functions.
B. Principle of PID Control
The principle of working of the PID controller is responds
to an error signal in a closed control loop and attempts to
adjust the controlled quantity in order to achieve the desire
system response [10]. The controlled parameter can be any
measurable quantity, such as speed, voltage or current. The
output of the PID controller can control one or more system
parameters that will affect the controlled system quantity. The
benefit of the PID controller is that it can be adjusted
empirically by adjusting one or more gain value and observing
the change in system response.
A PID algorithm block diagram is shown in figure 5. An
error signal is formed by subtracting the desired setting of the
parameter to be controlled, from the actual measured value of
that parameter. The sign of the error indicates the direction of
change required by the control input. The proportional (P)
term of the controller is formed by multiplying the error signal
by a P gain. This will cause the PID controller to produce a
control response that is a function of the error magnitude. As
the error signal becomes larger the system needs more
correction. The effect of the P term will tend to reduce the

AC Mains
DRIVER

MAIN CIRCUIT

dsPIC30F6010A

PWM
A/
D

M
O
D
U
L
E
A/
D

M
O
D
U
L
E
Crater ref
Current ref
Creep ON/OFF
Crater ON/OFF
Mode Selection
Gas Test

Figure 5. PID Control Diagram

overall error as time elapses. However, the effect of the P term will
reduce as the error approaches zero. In most systems, the error of the
controlled parameter will get very close to zero, but will not
converge. The result is a small remaining steady state error. The
Integral (I) term of the controller is used to fix small steady state
errors. The integral I term takes a continuous running total of the
error signal. Therefore, a small steady state error will accumulate
into a large error value over time. This accumulated error signal is
multiplied by an I gain factor and becomes the I output term of the
PID controller. The Differential (D) term of the PID controller is
used to enhance the speed of the controller and responds to the rate
of change of the error signal. The D term input is calculated by
subtracting the present error value from a prior value. This delta
error value is multiplied by a D gain factor that becomes the D
output term of the PID controller. The faster the system error is
changing; the D term of the controller produces more control output.
III. IMPLEMENTATION AND EXPERIMENTAL VERIFICATION

Figure 6. Hardware Interface Controller Board

The implementation of the prototype is illustrated in figure 6
and 7. All the experimental results were obtained starting from this
prototype, where the digital program and all functions were being
validated

Figure 7. Controller Board Interfaced with MIG Machine

Figure 8. Reference and Measured Output Voltage
In the experiment system adopts direct current servo print motor,
designed for wire feeder mechanism whose rated voltage is c24V;
rated current is 5A and wire diameter varies from 0.8mm to 1.6mm.
Error Controller
Output
System
Output
System Feedback
-
+

Controller
System

-

Proportional Gain
Differential Gain
Internal Gain Cumulative Error
Last Error Value
+
Set Point


In figure 8, in which the dashed lines stands for the set wire feeding
speed while the solid lines stand for the measured wire feed, shows
the experiment result. Verification from the experimental result on
the measured wire feed speed, high precision, excellent stability in
the speed under stable working condition. The elements for the
experiment are as follows, the constant voltage output from the
welding supply of 24V (it varies upon the output current), the work
piece as mild steel, the sheet thickness is 12mm, the wire speed
varies minimum 1.5m/min to maximum 20m/min (Meter Per
Minute)

Figure 9. 4T Mode Welding Function Output Waveform

Figure 10. 2T Mode Welding Function Output Waveform

The figure 9&10 illustrate the all welding functions like trigger
switch, creep, crater, mode selection, gas test etc.

A. Conclusion
According to the experimental results, the wire feeder whose
rotating speed is controlled with the closed loop PID control
technology is swift in following the set value. The control response
is fast and the motor speed can be made to excellently steady.
Its more compatible in power source with different manufactures
wire feeder and also includes all welding functions. Hence it leads to
increase the performance and also marketing. The operator can
access easily for all functions.
IV. APPENDIX
A. Mathematical Converter Model
The open loop converter model explained by author [11].In the
closed loop voltage control buck converter model, the controlling
variable is duty ratio and the controlled variable is output voltage,
generalized output impedance Z
0
.

The transfer function is derived from the following equation,
(1)

Where d is small change in

(2)

(3)
From (1) & (2)
(4)
From (4)
(5)
From (1)
Substitute

(6)
From (3)

Substitute

Since


Figure 11. Model of Buck Converter

//( +
)

The output impedance is modeled as a load resistance
R
L
, shunting the filter capacitance. It is modeled as a
capacitance C, in series with internal capacitor resistance
R
C
.

The transfer function of this circuit can be derived as
follows,
= (
1
+
)//
+ 1
(
) +1

Substitute Z
0
(5)

) +1
+1

Substitute Z
0
(6)

+1
+ 1

) +1
+1

The transfer function of output to input current,

) +1
+(
//
) + 1

; = 0
The closed loop buck converter control system as shown
figure 12

Figure 12. Closed Loop Control System
V. REFERENCE

[1] Gho, J.S , Chae.Y.M , Kim.K.S , Won.K.S ,
Mok.H.S, Choe.G.H. A study on the effect of wire
feeding speed controller in inverter arc welding
machine , Power Electronics and Drive Systems,
1999. PEDS '99. Proceedings of the IEEE 1999
International Conference on Vol.1
[2] George E. Cook, Joseph E. Maxwell, Robert Joel
Barnett, and Alvin M. Strauss , Statistical
Process Control Application to Weld Process ,
IEEE Transactions on Industry Applications VOL.
33, NO. 2, March/April 1997.
[3] Kenji Ohshima, Mituyoshi Yamamoto, Tadashi
Tanii,and Satoshi Yamane, Digital Control of
Y(s)
u(s)


Torch Position and Weld Pool in MIG Welding
Using Image Processing Device , IEEE
Transactions on Industry Application, VOL. 28,
NO. 3, May/June 1992.
[4] Welding Hand book, vol. 2, Welding Processes,
8th ed,L.P.Connor, Ed., American Welding
Society, Miami, FL, 1991.
[5] US Patent Automatic Welding Wire Feed adjuster
, Andreu P.Meckler, 2007.
[6] US Patent Welding Wire Feed Speed Control
System Method, Kenneth A.Stanzel, Appleton,WI
(US), Bernard J.Vogel, Troy Ho, (US), Chris Roehl,
Appleton, WI (US) Kelly Morrow, De Land
FL(US),2006.
[7] Jesper S. Thomsen , Feedback Linearization
based Arc Length Control for Gas Metal Arc
Welding , 2005 American Control Conference.
[8] Zhang Hongbing, Huang Shisheng, Zhou Yiqing.
Fuzzy Control of WireFeeder in Pulse Welding
System, Electronic Measurement and
Instruments, ICEMI '07.
[9] Shulin Liu , Jian Liu , Yinling Yang , Jiuming
Zhong Design of intrinsically safe buck DC/DC
converters, Electrical Machines and Systems, 2005.
ICEMS 2005 Proceedings of the 8
th
International
Conference Vol.2
[10] Hao Peng , Chin Chang . A simple nonlinear
gain scheduling method in digital PWM converter
control, Power Electronics and Motion Control
Conference, 2009 IPEMC'09. IEEE 6
th
International
conference.
[11] Practical Design of a open loop Buck Converter
by Dennis L.Feucht.

VI. BIOGRAPHIES
Srinivasan Kesavan was born in Tirupattur,
India in 1981. He received the B.E. degree
from Madras University, Chennai, in 2003,
the M.E. degree from Satyabama University,
Chennai, in 2005. He is working towards
Ph.D from Anna University, Coimbatore,
India.
His employment experience included the
Edutech NTTF India Pvt Ltd, Bangalore,
ESAB Engineering Services Ltd, Chennai.
His special fields of interest included DC-
DC converters, magnetic design.

S. Paramasivam was born in Coimbatore,
India in 1971. He received the B.E. degree
from GCT, Coimbatore, in 1995, the M.E.
degree from P.S.G College of Technology,
Coimbatore, in 1999, and the Ph.D. degree
from College of Engineering, Anna
University, Chennai, in 2004. His interests
include power electronics, AC motor drives,
DSP- and FPGA-based motor controls, power-
factor correction, magnetic design, fuzzy
logic, neural networks, and controller design for wind energy conversion
systems. He has published over 78 papers on various aspects of SRM and
induction motor drives in international journals and conferences worldwide.
Presently he is working at ESAB Group, Chennai, as the R&D Head.

M.Thiruvenkadam was born in Dharmapuri, Tamilnadu, India in 1984. He
received the B.E. degree in electrical and
electronics engineering from GCE, Salem, in
2005, the M.E. degree in control and
instrumentation from College of Engineering,
Anna University, Chennai, in 2007. He is
working towards Ph.D from Anna University,
Coimbatore, India. He has worked in welding
equipment Industries for past 3 years as an
embedded engineer. Presently he is working
at ESAB Group, Chennai, as the R&D
Engineer. His interests include DSP based application development, control
and instrumentation, power electronics, and embedded programming.

ISBN: 9788192057569 :: doi: 10. 73522/ISBN_0768
Analysis of Analog Multiplier

Prof. Arun Katara
Department of Electronics and Telecommunication Engineering
Datta Meghe Institute of Engineering, Technology and Research, Wardha, India.

Abstract A new CMOS voltage-mode Four-quadrant
analog Multiplier is proposed and analyzed. By applying
inputs signals to set of complementary diode pair
connection & to that of voltage difference circuit. The
circuit is formed by cascading the complementary diode
pair connection with the voltage difference circuit. Based on
the proposed multiplier circuit, a low voltage high
performance CMOS four quadrant analog multiplier is
designed and fabricated by using 0.35u technology. The
measured 3dB bandwidth is 15 MHz. Simple structure, low-
voltage, low power, and high performance makes the
proposed multiplier quite feasible in many applications.
I. INTRODUCTION
Analog multipliers are important circuit blocks for
many applications such as frequency mixers, variable
frequency oscillators, adaptive filters, neural networks
automatic gain control, amplitude modulation, etc. In
order to improve the overall power efficiency of such
application which is now regularly required for modern
analog and mixed signal design dedicated for portable
equipments, the analog multiplier to be used must be able
to operate under a reduced supply voltage and consume
low current.
Four quadrant analog multipliers are widely used in
contemporary VLSI chips for non-linear operations,
modulation/demodulation as well as frequency
conversion.
The basic functionality of the multiplier is to deliver
output signal v0 proportional to the product of two input
voltages Vx and Vy:
V0=km . Vx. Vy

Usually, the variable transconductance technique
which operates on Gilberts translinear circuit is widely
used for the design of multiplier circuits in Bipolar
CMOS technologies [1],[2].The square law based MOS
multiplier can be realized easily since the squaring
function can be obtained from the inherent square law of
the MOS transistor operating in the saturation region[3]-
[5].
The multiplier proposed in this paper also uses the
MOS square law characteristic, but the circuit structure is
applied from the complementary pairs of diode
connection circuit.
II. CIRCUIT DESCRIPTION
A. Complementary Pairs of diode-
connection circuit
Fig 1 shows the n-type and p-type diode
connected MOS transistors biased with constant
current source I
DD
. In the following analysis, it is
assumed that the drain current of the MOS device in
saturation is given by the following expression. Now
by applying the input voltages V
1
and V
2,
the current
flowing through the drain terminal of the MOS
transistor is given as,

(a) (b)
Fig.1 Diode pair connection

The drain current of the transistors in the saturation
region may be given as
I
d1
=K1(V
01
-V
1
-V
Tn
)
(1)
I
d2
=K1(V
01
-V
2
-V
Tn
)
(2)

Where I
d1
is the drain current flowing through
NMOS _1& I
d2
is the current flowing through
NMOS_2
,
V
01
is the output voltage, K
1
=
n
C
ox
W/2L & V
Tn
is threshold voltage of the transistor. From the circuit we
can conclude that,

I
d1
+I
d2=
I
DD

(3)
By adding equation 1 & 2, we can find the output
voltage V
01
as
V
01=
(V
1+
V
2)
/2 + V
Tn+
I
DD
/2K
1

[1+K
1
/4I
DD
(2V
1
V2- V
1
2
-V
2
2
)]
(4)

For the P-type diode-connection shown in fig1.b, the
output voltage V
02
is also given by the same way as,
V
02=
(V
1+
V
2)
/2 -V
Tp-
I
DD
/2K
3

[1+K
3
/4I
DD
(2V
1
V2- V
1
2
-V
2
2
)
(5)

where K
3
is the transconductance parameter of
PMOS_1 & PMOS_2, V
Tp is
the threshold voltage of the
PMOS transistor .Now V
1
of fig1-a is connected to V
1
of
Fig 1-b ,similarly V
2
of Fig1-a is connected to V
2
of fig
1-b, to form the circuit diagram of complementary diode
-connection. However the dc offset current I
DD
/2 is also
supplied from the input signal voltages for biasing the
PMOS & NMOS transistors, that are operated in
saturation region.

(a)

(b)
Fig.2 Complementary diode pair connection

Fig 2-a.shows the complementary diode pair
connection and its output voltage waveform is shown in
fig 2-b.The output voltages are in the form of
multiplication of the input voltages V
1
and V
2
, the sum
and the square of the input voltages. Also the common-
mode input voltage ( V
1
+V
2
)/2.

b.Voltage difference circuit

For removing the common mode input voltage from
the output equation of V
01
and V
02
of the complementary
diode-connection, the output is driven by the voltage
difference circuit shown in fig-3 .
The circuit includes matched transistors NMOS_1,
NMOS_2, PMOS_3 & PMOS_4. For having the unity
gain current mirror two identical PMOS devices are also
used.
From the circuit diagram of voltage difference circuit,
the output voltage V
od
is given as
V
od
=V
gs2
+ V
gs4
+ V
ss

(6)
Where, V
gs2
is the gate to source voltage of transistor
NMOS_2 & V
gs4
is the gate to source voltage of PMOS_4
again made to operate in saturation region. By
considering the drain current equations of the transistors
the output voltage is expressed as
V
od
=V
i1
- V
i2
+ V
ss

(7)
Equation -4 shows that the output voltage V
od
is in
the form of difference voltage between the input voltage

V
i1
and V
i2.

Fig-3 Voltage Difference Circuit
C.TWO QUADRANT MULTIPLIER
By cascading the complementary diode-connection
circuit of fig-2 and the voltage difference circuit shown
in the fig-3, i.e., the output of complementary diode-
connection is applied to the voltage difference circuit, the
two quadrant voltage-mode multiplier can be realized.
The ideal current sources I
DD
are replaced by the
transistors with a biased voltage vg1 & vg2.
The fig-4 shows the circuit for generating the biased
voltage vg1 & vg2.

Fig-4 Circuit for generating the biased voltage vg1 &
vg2.

It is assumed that the transconductance parameter K
1
& K
5
of all NMOS & PMOS are matched.
The circuit for voltage-mode analog multiplier is
shown in fig5.
From equation (4), (5) and (7), the output voltage
V
om
of the two quadrant multiplier can be given as

V
om=
V
DC
+ ( (K
1
+
K
5
)/32I
DD
) (2V
1
V
2
-
V
1
2
-V
2
2
)

(8)

Where, the dc term V
DC
is given as,
V
DC=
V
Tn
+ V
Tp
+ ( I
DD
/2)(1/K
1
+1/K
5
)
+ V
ss
To diminish

the effect of the second order term of the
input voltages, the complete circuit diagram of CMOS
voltage-mode multiplier

can be shown in fig-6.

Equation (8) indicates that the multiplication of V
1
and

V
2
is achieved. As the output voltage also includes
the components that are proportional to the square of the
input voltages V
1
and V
2 .

Finally subtracting V
om1
& V
om2
,the output voltage
of the four quadrant multiplier is given by
V
out
= V
om1
- V
om2
= ((K
1
+
K
5
) / 2 I
DD
) V
1
V
2
Which is a complete multiplier function without the
second order component of the input voltages V
1
& V
2
.
Thus the output voltage of each multiplier can
obtained as

V
om1=
V
DC
+ ( (K
1
+
K
5
)/32I
DD
) (2V
1
V
2
-
V
1
2
-V
2
2
)

V
om2=
V
DC
+ ((K
1
+
K
5
)/32I
DD
) (-2V
1
V
2
-
V
1
2
-V
2
2
)

Fig5 Two Quadrant voltage-mode multiplier

Fig-6 Four quadrant voltage-mode analog
multiplier

III. SIMULATION RESULT
The proposed four quadrant multiplier shown in fig .6
has been simulated with TSPICE using 0.35
n
level 3
process. The power supply voltage is 5V and the bias
current I
DD
=50A.
Fig.8 shows the waveform for amplitude modulation
as one of the application of a multiplier. The modulation
is performed when the input voltage v1 & v2 are 100
KHz & 1 MHz with the peak amplitude of 400mV.

The error voltage is measured within the range
400mV for V
1
, while the other input V
2
varies from
400mV. The linearity error is 0.8%. The power
consumption avg_power = 1.0468e-003. the proposed
circuit achieves the output without using the passive
component i.e. resistors.

Fig.7 Frequency response of the four quadrant
multiplier.

Fig 8: Transient response of the four quadrant
multiplier
REFERENCES
[1] B.Gilbert, A precise four-quadrant multiplier with sub-
nanosecond response, IEEE J Solid-State Circuits, vol. SC-
3,no . 4,pp. 373 1998.
[2] J.N. Badanezhad and G. C.Temes, A 20 V four quadrant CMOS
analog multiplier, IEEE J. Solid-State Circuits ,1985,sc-
20,pp.1158-1168.
[3] Zhenhua Wang, A Four-Quadrant analog multiplier Using MOS
Transistors Operating in the saturation Region, IEEE Trans .
Instrum .Meas. vol.42,no. 1,pp.75-77,Feb.1993.
[4] M.Franciotta , G.Colli, and R. Castello, A 100-MHz 4mW
Four-quadrant biCMOS Analog Multiplier, IEEE J. Solid-State
Circuits, vol.32,no.10,pp.1568-1572,Oct.1997.
[5] Sho-Yuan Hsiao and Chung-Yu Wu, A 1.2 V CMOS Four-
Quadrant analog multiplier, IEEE ISCAS05
Proceedings,pp.241-244,June 1997.
[6] Boonchai boonchu and Wanlop Surakampontorn, A New
NMOS Four-Quadrant analog Multiplier, IEEE ISCAS05
procee dings,pp.1004-1007,may 2005


Part II
ICCA 12
Volume 3

ISBN: 978-81-920575-6-9 :: doi: 10. 74243/ISBN_0768
Establishing the Relationship between Customer Relationship Management and E-
Business

Abstract

Abstract - Customer relationship management (CRM) is also
known as relationship marketing or customer management.
The goal of CRM is to aid organizations in better
understanding each customers value to the company. CRM is
a very important business initiative because during times of
economic dislocation, customer retention repeatable revenue
is a matter of survival. CRM is the method that businesses
have to deal with the newly minted customer economy.
Now-a-days, CRM is emerging as CRM e-Business. E-
Business is a term that is basically used to describe a business
that runs on the internet and that makes use of the existing
internet technologies to increase the profitability and
efficiency of the business. The need for CRM e-Business
solution has been fuelled as products have become more
commoditized and the number of competitors has soared with
pricing differences getting narrower. All this has placed
immense pressure on the company and organizations are fast
realizing that they need to achieve customer satisfaction if
they want their profits to rise.
In this paper we will try to establish a relationship between
the CRM and the E-platform. CRM, despite being one of the
most profitable customer strategies, still it has some failures.
The most important aspect of CRM problems is its excellent
ability to achieve customer retention but its failure to do so.
This is indirectly responsible for CRM collapse. What
actually is CRM failure and why does it occur? Can we meet
these challenges with BOM. Generally one of the reasons for
this failure is because most organizations that actually employ
CRM, experience a lot of confusion about its attributes and
what it really is. Some would define it as a business strategy
while others view it as something to do with technology.

Keywords: CRM, E-Commerce, BOM

I. INTRODUCTION
As we all know this is the world where every industries
boundary are not confined to the boundary of the
industries. These are extended deep in the customer. This
let to the rising of the concept called Customer
Relationship Management: Basically the need to keep
in touch with the customer increases the significant of the
CRM software. Now a day there is no companies which
like to create a great relationship with the customer. The

need of the company for such type of relationship increases
the customer satisfaction that industry or company is
thinking for them.

II. CUSTOMER RELATIONSHIP
MANAGEMENT

The so called typical customer no longer exists, and
companies have been learning this lesson the hard way.
Until very recently, business was more concerned about
the whats then about the whos. In other words,
companies were found

As sellingas many products and services as possible,
without regard to who was buying them. Most corporations
cling to this product centric view even today, basing their
organizational structure and compensation plans on the
products they sell, not the customer who buy.
Nowadays the competition is just a mouse click away.
Embattled companies are slouching towards the realization
that without customers, products dont sell and services
dont materialize. They have been forced to become
smarter about selling, and this means becoming smarter
about whos buying, companies are reading the
competitive writing on the wall looking the technology for
a leg up. This, combined with the oft quoted factoid that it
costs a company six times more to sell a product to a new
customer then it does to sell to an existing one the old
bird in the hand thus coming to roost has motivated
business to try to maximize existing customer relationship
and the main way to squeeze every drop of value from
existing customer is to know who the best customers are
motivate them to stay that way. Indeed a good starter
definition of customer relationship management is:
CRM is the seamless co-ordination between sales
customer service, marketing field support and other
customer touching functions. It integrates people, process
and technology to maximize relationship with all
customers and suppliers. CRM results in a number of
benefits to an organization like increased margins
improved customer satisfaction ratings and decreased
administrative costs. The goal of CRM is to aid
organizations in better understanding each customers
value to the company, while improving the efficiency and
effectiveness of communication. CRM captures, analysis,
and distributes all relevant data from customers and
prospect interactions to everyone in the organizations.
Mr. Rohit Joshi
Deptt. Of Computer Application (MCA)
SRMGPC, Lucknow
Mr. Ankur Shrivastav
Deptt. Of Computer Application (MCA)
SRMGPC, Lucknow


CRM emphasized customer acquisition and is recognized
as one of the most viable tools used to future a companys
success in the highly competitive business world.
There are three major areas that focus on customer
satisfaction, sales, marketing and services. The
functionality of and between these three fields is essential
to successfully connecting a companys front and back
offices to facilitate effective, enterprise wide coordination.
The professional sales force predicts and proposes the real
time analysis of information and distributes this
information to the company and business partners.
Marketing concentrates on personalizing customer
preferences and offering them satisfying experiences
service is associated with the companies call centers and
coordinate interaction between web email and other
communication Medias. These fields are developed further
with the help of CRM automation.

III. CRM CHALLENGES

CRM despite being one of the most profitable customer
strategies, still it has some failures. The most important
aspect of CRM problems is its excellent ability to achieve
customer retention but its failure to do so.

Various problems with CRM are:
A. Exorbitant costs
B. Inadequate focus on objectives
C. Inefficient Resources
D. Inappropriate matrices
E. Complex Systems.
F. No customer focus
G. Slow returns

CRM does fail in some instances. That cannot be
disputed. CRM reviews shoe that the failure rates of CRM
could reach a high of an amazing 80% in a few years time.
Thats entirely in contravention of all the highs that have
been predicted right? It just evidences the fact that if CRM
is to be employed it has to be done with the utmost caution
exercised and with full attention to implementation.
Some software companies also fails in implementing
CRM, on this front the chief mistake could be the way they
handle SFA as a component. What happens is that despite
the fact that the endeavor to help sales persons actually
gain ground in their sales efforts they wind up doing the
opposite. Since the systems are devised chiefly by people
who are not at the fore front and who know very little
about sales activities personally, this has an impact on its
user friendly attributes. Sales personnel therefore find them
quite difficult to handle and more often than not
nonproductive as well.
CRM packages tend to fail also on account of their
inflexibility or shall we say their rigidity. A CRM solution
tends view the customer as yet another transaction. But
customers are far from that. Seeing them as figures and
numbers is one of the loop holes in the CRM industry. The
human element is lost in the entire spectrum of activity.
Decisions are required to be made on a daily basis that can
not be incorporated in the CRM package itself. It has
everything to do with spontaneous, decisive choices being
made by the employees who are face to face to customers.
One reason CRM system often fail is because the
employees themselves are reluctant to use them or unable
to use them in the appropriate manner. Armed with
insufficient knowledge and misconceptions they are
hesitant and ill equipped to deal with the CRM efforts.
Disappointed with the initial implementation results
employs start to grumble. Reluctant to give it a chance they
stop giving off their best efforts only to aid CRM failure.
The hype about CRM is often to blame leaving employs
believing in the magic wand sweeping away all their
difficulties when the actual pitfalls are felt, they stop
working towards CRM goals. Result CRM failures.
CRM also fails because businesses seldom bother to
make the right choice of CRM software and often do so
after little or no deliberation. Ensuring that the chosen
solution can and will support all their business processes, is
essential and must be carried out, but it is something
businesses seldom do resulting in CRM collapse.

So whos Responsible for CRM Failure?
Actually its a combination of both Organizations
employing CRM as well as those selling them.
Organizations havent learnt how to employ its business
processes in the right manner so as to get the most out of
its CRM implementation while CRM sellers need to make
sure that their systems are user friendly and easily
adaptable and most importantly take into account the
various factors that have been so far overlooked.
Companies need to learn the golden rule. Merely installing
CRM packages does not ensure success. It is by no means
a surety of positive results. Understanding the fact that the
strategy does have its drawbacks, working on these
drawbacks and doing their best to get the most out of their
CRM implementation alone will obliterate CRM failures
and yield success. What is `highly required is the ability to
focus on the business needs, choose a CRM package that
works towards it, employ the right resources and assume
the right metrics. Adopting these measures would go a long
way in alleviating CRM problems.

IV. CUSTOMER RELATIONSHIP
MANAGEMENT AND E-BUSINESS
The phenomenon of building a relationship with
customers via internet is known as electronic CRM (e-
CRM). The objective of CRM and e-CRM are the same
the difference is the medium used for providing services to
the customer. E-CRM is a multifaceted strategy that helps
companies understand, anticipate and manage customer
needs. A major thrust of it involves segmenting customers

and offering appropriate and differentiated services for
each of these levels. It mainly uses the electronic media to
integrate and simplify customer- related business
processes, drastically reducing costs of customer- facing
operations while achieving CRMs primary goal to
enhance the customer experience. E- Business does have
its own difficulties though. It is a lot more complex than
that what people think it is. In order to succeed at e-
Business an organization needs to basically figure out just
hoe it wants top do its business, what products it wants to
sell, what are its key objectives and who are its targeted
customers.
E-Business transactions have crossed the billion marks
and are scheduled to hit $1 trillion in the year 2006. With
such astounding statistics, it is but clear that the advantages
that it offers have far surpassed company expectations and
have roped in users rapidly. Ignoring the phenomenal
growth of e-Business is futile. Companies preferring to
stick to traditional methods and processes will without a
doubt are left behind in the rat race. Since the internet
explosion globally, consumers prefer e- Business as it
smacks of ease of usage. E- Business is a term that is
basically used to describe a business that runs on the
internet and that makes use of the existing internet
technologies to increase the profitability and efficiency of
the business.

V. REASONS FOR THE GROWTH OF CRM E-
BUSINESS
5.1. The reasons for CRM e-Business growing to such
enormous heights is internet technology, benefits of
electronic technology and the easily available solutions
that exist. Companies find that availing of CRM e-
Business facilities boosts the efficiency to a great extent.
The reason e- Business has succeeded is on account of its
ability to provide cost effective solutions that require very
little time to implement.
5.2. Traditional business methods have proved
tiresome, costly and very time consuming. As a result
businesses have been looking around for a better solution.
CRM e- Business solutions proved to be just the strategy
that was required. It catered to existing business problems
and proved that it had the potential to deal with potential
difficulties as well. Flexibility and the ability to adapt to a
changing environment is something that CRM e-Business
finds easy to do.
5.3. CRM e Business includes companies that use
the internet to acquire products or supplies for in house
production. This is known as e-procurement. It ahs the
potential to actually cut down cost considerably making it
a good bet for companies looking at achieving cost
effectiveness.
5.4. It also has the added advantage of being able to
track purchases and manage the purchasing efforts
efficiently. It helps in the buying and selling of products. It
also helps the organization to use electronic chat as a
means of technical support and customer support. This
helps any company to save time and effort and at the same
time provide opportunities that the traditional system could
not. Whats advantageous here is that a virtual computer
system can be used and with the download of a program,
all the relevant information about hardware and software
specifications can be adequately sent to the support team
directly.
5.5. In addition it manages to maintain a central server
or email list as a method of distributing information, rather
than having costly and time consuming individual ones. In
the pats few years almost all companies have become to
some level or the other an e- Business. CRM e- Business is
right now increasing the chance of building sales and
increasing the sales revenue by increasing the area of
operation, reducing operating costs, increasing productivity
and thereby hiking the efficiency of the supply chain and
the CRM application as well.
5.6. CRM e- Business solutions give companies a well
planned and easily integrated e- Business strategy that
caters to both the customer needs as well as the corporate
needs. Both these need to be adequately catered to in order
that company objectives de fulfilled. The net result of
implementing CRM e Business strategies is satisfied
customers and overall productivity.

VI. CONCLUSION
Customer relationship management also known as
relationship marketing or customer management, plays a
vital role in todays competitive world and if implemented
properly, can yield very positive results in retaining the
existing customers and attracting the new ones. CRMs
goal is to aid organizations in better understanding each
customers value to the company.
CRM inspite of being so fruitful, still faces some
challenges or fails sometimes due to the improper
implantation of it or may be due to the organization those
selling it. To overcome these challenges what is highly
required is the ability to focus on business needs, choose a
CRM package that works towards it, employ the right
resources and assume the right metrics. This all can help
organization to achieve high profits and in retaining
customers.
In the same manner e-CRM is the right tool for the
present scenario as it saves time and resources of an
organization and provides good enough outcome in terms
of customer.
REFERENCES
[1]. Jill Dych, The CRM Handbook, A business guide to
customer relationship management; 7
th
Edn.2007: 28-42.
[2]. Prof.V.Sudhakar,Indian Journal Of Marketing, e-CRM;
Dec 2009; 33-39.
[3]. Jill Dych, The CRM Handbook, A business guide to
customer relationship management; 7
th
Edn.2007: 128-141.
8. Web References
I. www.destinationcrm.com.
II. www.crmcomunity.com.
III. www.searchcrm.com
ISBN: 978-81-920575-6-9 :: doi: 10. 74250/ISBN_0768
SECURE AND LIGHTWEIGHT MODEL FOR M-PAYMENT SYSTEM BASED
ON HASH CHAIN IN MOBILE NETWORK
Chitra Kiran. N
Research Scholar Dept of Electronics & Communication Engg.
UVCE
Bangalore, India

Abstract: The dynamic nature of the wireless adhoc network
imposes great deal of challenges in micropayment system
where there exists a sets of intermediate relay nodes which
might not be interested to cooperate for providing services to
other nodes in the network. This situation will pose a great
security threat in micropayment system when considering
reliable transaction. The proposed system highlights about a
new model of micropayment system in wireless adhoc
network considering the challenges of dynamic topology of its
respective network. The system stimulates the intermediate
nodes to cooperate for facilitating secure and reliable
transaction from source to destination nodes. The system
consists of high end encryption using hash function is also
independent of any Trusted Third Party when the network
topology frequency changes, thereby it is flexible, lightweight,
and reliable for secure micropayment systems.
Keywords-component; Micropayment System, Hash
Function, Wireless Adhoc Network
I. INTRODUCTION
Wireless adhoc network has become one of the prime
topics of research in the very recent years where majority of
the research work is concentrated on restricted user-groups,
where various nodes cooperate to communicate [1]. But
security and energy consumption is always a never ending
issue in wireless adhoc network. Although wireless adhoc
network can be effectively used in wireless payment system
cost effectively, but unfortunately, such technology comes
with many security flaws. One of the prominent classes of
payment found to be used in m-commerce recently is
micropayment system [2] which is based managing small
payment values. In anonymous micropayment schemes,
there is no connection between the payer and the payment
means. In this case, the payment means should be secured
by a third party vendor which is normally any financial
institutions. The financial institution should ensure the
reliability and the legitimacy of each coin in the network
which also means that every user who wants to verify a coin
should check with the financial institution. The second type
of payment is in connection to the payer, where each
payment mean or token should include the characteristics of
the first payer. Therefore, before accepting any payment
mean a node should substantiate the first payer and verify
that he owns requires the involvement of a trusted third
party. Not only this, but the payee can directly redeem the
payment means or use the similar token for another
payment, if the micropayment mechanism allows asking for
a delegation authorization. Accordingly, micropayment
schemes still requires the proper designing of efficient
security protocols, which could become problematical
according to the quantity of the payers and the environment
of the payment means and payment chains. Further, this
system does not describe any robust mechanisms allowing
concluding distributed payment or pay distributed
applications.
Abundant researches for e-payment system have been
already proposed [3, 4, 5]. The researches on payment
system over mobile network have been discussed in [6].
Such system has extensive deployment of expensive
cryptographic protocol operations. Micropayment systems
has contributed to iterative payments from a single vendor
where majority of the security policies has used one-way
hash functions [7] in order to generate a chain of hash
values. Hash functions such as MD5/SHA are more
computationally proficient in comparison to other
symmetric key algorithms such as AES or asymmetric key
algorithms such as RSA and allow for fast generation and
verification of payment tokens [8]. But maximum of the
researches comes with a security loopholes and high
costing. Use of advance cryptographic protocols in such
cases will only increase the memory and network overhead
for high requirement of maintenance of key management.
So traditional cryptography cannot be deployed in securing
the communication between one to another node in wireless
adhoc network. The problem of reliability of
communication becomes much worst when there is a
frequent changes in the network topology.
In the proposed research paper, we highlight a secure
payment policy which facilitates one node to join an
existing wireless adhoc network and thereby permits it to
pay each node that relays packets on its behalf. In section 2
we give an overview of related work which identifies all
the major research work being done in this area. Section 3
highlights about the micropayment system describing some
of the prominent payment system considered in previous
research work. Proposed system is discussed in Section 4
followed by research methodology in Section 5. Section 6
discusses about performance analysis and finally in section
5 we make some concluding remarks.
II. RELATED WORK
Zhi-Yuan Hu [9] has designed an innovative and
practical authentication system, Anonymous
Micropayments Authentication (AMA), is designed for
micropayments in mobile data network. But his work has a
relative drawback for common problems of authentication
mechanism based on symmetric key cryptography.
Xiaoling Dai [10] has researched on micropayment
protocols in offline with multiple vendors.
Min-Shiang [11] has introduced several micro-payment
schemes based on one-way hash chain and review some
literatures on supporting multiple payment. The author has
also proposed a new micropayment scheme, which achieves
the following three goals: micro-payment multiple
transactions, service providers, and anonymity.
Samad [12] has proposed a trust model from user point
of view and combined it with MR2 micropayment scheme
and called the new scheme TMR2. This trust model is
supported by micropayment provider and assures the users
that they will not be charged for in case the product is not
satisfactory or it is corrupt.
Sung-Ming e.t. al [13] has studied various probabilistic
micropayment Scheme shows that the scheme by Rivest
may reduce the administrative cost of the bank, however it
brings extensive computational overhead to the merchant.
Lih-Chyau Wuu [14] has proposed a secure and
efficient off-line micro payment scheme which uses coin
chain technique to make coin that the verification of coin
can be done quickly by hash computation. This scheme also
ensures that the coins could only be used by their owner,
and protects the privacy of the consumer.
Vivek Katiyar e.t. al. [15] has discussed about role of
Elliptical Curve Cryptography and presents a survey on the
current use of ECC in the pervasive computing
environment.
Husna Osman and Hamish Taylor [16] has discussed
three key design considerations in implementing a fully
distributed reputation system for ad hoc m-commerce
trading systems, namely relevant reputation information, its
storage and reliability.
Fouzia Mousumi and Subrun Jamil [17] has described
cost effective push pull services officering SMS based
mobile banking concept has been illustrated for 24 hours
banking convenience which helps customers stay on top of
any recent changes made in their current or deposit account
or loan through SMS.
Arogundade e.t. al. [18] propose an open network
system which can adapt to users changing needs as well as
allowing effective and secured transaction via any
customers bank account.
Partha e.t. al [19] proposes a novel approach by
utilizing cancelable biometric features for securely storing
the fingerprint template by generating Secured Feature
Matrix and keys for cryptographic techniques applied for
data Encryption or Decryption.
Mohammad Al-Fayoumi [20] discuss an important e-
payment protocol namely pay-word scheme and examine its
advantages and limitations, which encourages the authors to
improve the scheme that keeps all characteristics intact
without compromise of the security robustness
Kaylash Chaudhary e.t. al [21] have carried out an
assessment of micro-payment against a non-micro-payment
credit systems for file sharing applications.
Charles K. Ayo and Wilfred Isioma Ukpere [22]
propose a unified (single) smart card-based ATM card with
biometric-based cash dispenser for all banking transactions
Wang [23] proposes a novel payment system with smart
mobile devices, wherein customers are not limited to
purchase e-cash with the fixed face-value
Obviously it can be seen that majority of the work is
carried on wired network with much less consideration of
wireless network. The issues related to dynamic topologies
of wireless adhoc network is not discussed in detailed in
any of the researches described above.
III. MICROPAYMENT SYSTEM
A. About Miropayment System
A micropayment is a financial transaction involving a
very small amount of money and usually one that occurs
online [24]. One problem that has prevented their
emergence is a need to keep costs for individual
transactions low which is impractical when transacting such
small sums even if the transaction fee is just a few cents
[24]. Micropayments have to be appropriate for the
transaction of non-tangible merchandise over the Internet
which inflicts necessities on speed and cost of processing of
the payments: delivery occurs nearly immediately on the
Internet, and often in arbitrarily small pieces. On the other
hand, the bottleneck in sales of tangible merchandise,
management and distribution, sets a lower bound
particularly for costs to remain economical. So, the
evaluation criteria of micropayment systems should include
[25]:
Ease of use: The application must be easy to use for the
clients. There is no authorization login and PIN number
to be fed all the time. The customer only needs to click
and to buy a page in the web page with a
micropayment system in a few seconds.
Security: The aim of security in the payment
procedures is to prevent any group from cheating the
system. For customers and external adversaries the
forms of cheating security, which are detailed to
payment design, are extra expenditure of coins and
creation of false coins forgery during payment.
Anonymity: The customer anonymity should be
protected. An elementary property of physical cash is
that the association between customers and their
purchases is untraceable. This means that the payment
systems do not allow payments to be traced without
compromising the systems security. This may
encourage some potential customers to start using the
payment system.
Divisibility: The protocol supports multiple
denominations and a range of payment values.
Performance: The protocol provides high-volume
payment support.
Robustness: The protocol is tolerant of network
bottlenecks and broker/authorizer down-time.
Table 1. Comparison of E-commerce payment methods
Property CyberCas
h
[25]
MPay
[25]
PayWo
rd
[25]
NetPay
[25]
Ease of
Use
Low High Medium High
Security High Medium Low Medium+
Anonymi
ty
Low Low Low Medium+
Divisibili
ty
Very High Very
High
High High
Performa
nce
Very Low High Medium Very
High
Robustne
ss
Low High High High

There is a growing need for an effective, efficient
micro-payment technology for high-volume, low-value E-
commerce products and services. Current macro-payment
approaches do not scale to such a domain. Most existing
micro-payment technologies proposed or prototyped to date
suffer from problems with security, lack of anonymity and
performance.
IV. PROPOSED SYSTEM
The proposed system highlights a secure micropayment
system by which the system allocates a payment to all those
nodes which permits relaying of the packets thereby
providing service. Such types of the nodes implicate the
payment agreement to pay. The payment agreement can be
governed along with the uniqueness of each node in the
mobile network. This can also be verified by the Trusted
Third Party (TTP). Unfortunately wireless adhoc network
will not support these long-lived service (payment)
agreements among the nodes due to the dynamic topology
of the wireless adhoc network, where it is very difficult to
predict the position of the nodes in next sequence of time.
Therefore, there is a need of extensible as well as secure
policy which allows the user to make payment to all nodes
in the network without any dependency on TTP or any
financial institutions to issue a new payment agreement.
The main aim of the research work to design a secure
protocol which stimulates the nodes for packet forwarding
in wireless adhoc network. The objectives of the proposed
scheme are:
Verification: The system should allow both online as
well as offline validation of the payment tokens
independent from any need of intermediate relay
nodes.
Route Flexibility: The scheme should permit selection
of an most favorable route towards its destination and
initiate payment to all nodes in its network. In case of
route diversion, the system is independent from TTP to
create a new payment agreement.
Cost-Effective: Cost effective cryptographic
mechanism to be applied allowing all the intermediate
nodes to be able to validate the security information
related to payment events in the packet.
Higher Security: The system seeks to diminish all the
fraudulent activities by blacklisting all the illicit users
in the network.
V. RESEARCH METHODOLOGY
The entire proposed model is design in specific set of
operations to be performed by the entities involved in the
secure micropayment schema using wireless adhoc
network. The proposed steps are broker agreement, cost and
endorsement delivery, initiating payments, new route
consideration, transferring tokens, and broker approval. The
proposed research methodology can be explained in brief
steps as following:
1. Broker Agreement: A broker supplies its registered and
authorized user will a secure and tamper-proof token
with public key pair along with highly encrypted user
identity. Any micropayment schemes like credit card
can be used for designing the application. The user then
sends a signature message consisting of hash value and
payment information which is encrypted with public
key of broker.
Fig 1. Broker Agreement Policy
The broker generates (agreement) secret
endorsement data which consists of a random number,
an anchor value, length of hash chain, user-identity,
and expiry of chain. These set of information is secured
by private keys of broker. Therefore the broker
agreement can only be deciphered by users token.
However, the security of tokens (smart cards) are not
reliable as it can be deciphered, so the broker private
information is appended with expiry date in order to
restrict an unauthorized user in the range of mobile
network to have an access on the confidential
information transacted between user and broker.
2. Cost and Endorsement Delivery:
A sender node P sends the cost request message
encrypted with digital signature using their private keys
to query the route of recipient node Q. All intermediate
nodes attaches an certificates so that the origin node will
be able to validate the digital certificates on the cost
details. The data for cost reply message is returned to P.
After estimating the cost involvement in routing, the
encrypted broker endorsement is sent to all relay nodes
in the network. These endorsements are private data, so
each user encrypt with their public key, which can be
received from cost reply message. This scheme pays the
intermediate routers for forwarding the packets.
Cost Request
Cost Reply
Endorsements
P
Q
Intermediate Relay Nodes
Sender
Recipient
{Signatures, Certificates}
{Encrypt with public key}

Fig 2. Endorsement-Distribution
3. Initiating Payment: This step is about initiating
payments in the system by the user. P transmits message
in his network and appends a hash token from sub-
chains. The payment scheme in independent of
increased used of hash values for multiple payments by
the user ensuring much less network overhead. In case
the intermediate relay nodes have captivated the hash
values, they will not be able to decipher them without
broker agreement and its respective signature.
4. New Route Consideration: This step is performed as
wireless adhoc network quite often changes their
topology dynamically. In case of new route, the system
needs not to contact the any TTP. Overhead is reduced
by observing the new nodes in the route and using only
them for the distributing the secure endorsement.
5. Transferring Tokens: Here the intermediate relay node
transmits the greater hash values in one chain that has
spent it by the node. The user token then transmit the
hash value to the consecutive broker with their
endorsement digitally signed. The message and its
highly encrypted contents are validated by the broker as
well as issues an acknowledgement.
6. Broker Approval: The proposed system does support
multiple brokers for reliable communication which
allows any user to get associated with any broker
available in the network. The user in the first network
receives payment chain from the broker in that network,
it assist the same user for validating the digital
certificates generated by the nodes in new network
when the network topology changes. The assumption to
this step is that the user, broker and all the entities
involved should first get themselves registered and then
perform the task.
VI. PERFORMANCE ANALYSIS
The proposed system facilitates secure and reliable sets
of communication with offline verification from sender to
recipient node in wireless adhoc network thereby
permitting a secure micropayment schemes for multiple
nodes in the network by using hash functions. For
providing successive endorsement distribution securely,
asymmetric key are used. The proposed system is
completely free from any underlying routing protocol in
the wireless scenario which is very vital as routing
protocols are quite dependent upon the network topologies.
The long-term micropayment agreements have been
eliminated because of its unsuitability in wireless adhoc
network environment. Inspite of this, the cost details are
securely extracted from each node in relay path to estimate
a cumulative cost for forwarding the data through wireless
adhoc network.
Another uniqueness in the proposed design is when a node
do not have sufficient hash values for one session, then the
node can be directed to some unused sub-chains by
transferring a new set of endorsement. But there is a
probability of loss of connection, if the system runs out of
sub-chains. This phenomenon is applicable to all protocols
related to micropayment system where the user registration
priviledge is limited for access on the resources. The
proposed system is highly favorable to the dynamic
topology of wireless adhoc network as every instance the
topology changes, the broker endorsement will need to be
transferred to all the new nodes come across in the path.
But however, it has been seen that the node mobility in
such scenario as well as chain length contributes to
wastage of time. However chains of higher length can be
used for extreme high mobility in the network.
VII. CONCLUSION
The proposed system has highlighted a unique security
scheme for micropayment which is completely
independent of any trusted third party vendor. The
proposed system has signified some of the instance of the
non-cooperation of the nodes for providing services for
micropayment system. The secured transaction adopted by
the proposed system will allow the real-world
micropayment system for guaranteed forwarding of the
packets with highest reliability. The proposed system
facilitates the routers to levy cost for each packet and also
adapts to the dynamic network topology of the wireless
adhoc network. The multiple routes to the recipient node
with secure and encrypted cost of the packet is received by
the node, depending on which appropriate direction and
disseminated values of endorsement can be selected to
each intermediate relay node. The intermediate node
validates and initiates receiving tokens for forwarding the
packets. The application concept is free from any
dependency of the TTP in order to receive tokens for new
route by intermediate routers. Using extra chains, it is able
to initiate payments to the new node in the new network.
Our future direction of research will include considering
the trust and reputation management for providing more
safe and more reliable operation in micropayments in
wireless adhoc network.
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2011]
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ISBN: 978-81-920575-6-9 :: doi: 10. 74257/ISBN_0768
DESIGN & DEVLOPMENT OF DIGITAL FREQUENCY MULTIPLIER
Prof. Sandip D.Ramteke

Department of Electronics Engineering

Datta Meghe Institute Of Engineering,
Technology and Research,
Wardha, India

Abstract The concept of frequency multiplier has been
routinely used in many communication systems. An early
frequency multiplier used a PLL (Phase Locked Loop) for
this purpose. The initial VCO frequency is set at the desired
value of frequency which is an integral multiple of N of the
input frequency. A divider chain of appropriate Mod n
divider then converts the VCO frequency back to a value
close to that of input frequency. After tracking and locking
the VCO frequency then represents desired output. The
above method has the typical drawback of delay caused by
loop filter and several input cycle are usually required
before the VCO output settles down to its final value. These
drawbacks are removed in a Digital Frequency Multiplier.
Keywords
I. INTRODUCTION
In Digital Frequency Multiplier Usually master
clock is required to obtain the count of the time period of
the input signal frequency. This count is latched into a
registers and is used as one of the input s of an n bit
digital comparator. The other input of the comparator is
now made available as the output of another counter
which is run by his frequency clock whose frequency is an
integral multiple of the master clock. When the
comparator output indicates equality of the two input
numbers the counter is reset to zero and immediately start
running again. it can be show that the comparator output
represents a signal of frequency which is an integral
multiple of the input frequency .
II. BLOCK SCHEMATIC OF DIGITAL FREQUENCY
MULTIPLIER
The schematic diagram of the Digital frequency
multiplier is given in the figure 1. The input period Ti is
counted by the master clock period of Tc1 seconds. It is
assumed that Ti >> Tc1. The count is latched into a buffer
register, at the end of every input period . The register
output is thus a static number Ni . The number Ni serves
as one input to the magnitude comparator. A second
counter is now run at a high speed using a second master
clock of period Tc2. The period Tc2 is smaller than Tc1
such that Tc1/Tc1 = k = integer.
The magnitude of comparator gives an output
whenever the two input numbers are equal. This output is
used to drive a
Figure1: Schematic diagram of the Digital
frequency multiplier
mono stable to obtain the output pulse train whose
frequency is fo . The period To = Ti/k or fo=kfi.
A Digital frequency multiplier which includes a first
counter for counting the number of clock pulses received
from generator having first been divided by N in a
divider. The counter establishes the number of these
pulses which occurs during a cycle of the incoming
frequency and this number is compared in a comparator
with the count from a further clock counter. Typically
when coincidence occurs a change of state of comparator
results and as this coincidence will occur N times during a
cycle of incoming frequency, the output repetition
frequency from the comparator will be N times the
incoming frequency . although division can be provided
prior to the first counter this can be alternatively be
provided after this counter by using an arithmetic divider.

Figure 2:- Block diagram of DFM1
A first path and a second path, A first source of clock
pulses and a second source of clock pulses for supplying
said first and second paths respectively, divider means in
said first path for dividing the first clock pulses relative to
the incoming rate, first counter means in said first path,
said first counter means having a first input for receiving
an incoming frequency and for determining the number of
pulses occuring from said first source during the period
between sequential cycles of said incoming frequency,
holding means for periodically holding the count
determined by said first counter means updated at a rate
dependant on the incoming
Second counter means in said second
path for counting the number of clock pulses from said
second source, comparator means connected to receive the
outputs of the first and second paths respectively to
produce an output signal having a repetition frequency
which is a multiple of the incoming frequency, and inhibit
means for momentarily inhibiting a change in the count
provided by said second counter means whenever the
holding means is being updated.
.

frequency multipliers are extensively used in the field of digital
signal processing. Ideally, such a device generates N equidistant
output pulses during any given period of an input signal. In practice,
the period of the input signal is measured as a function of the
number of cycles of a master clock, occurring between two
successive input signal cycles. Similarly, the period of the output
pulses is restrained to be an integer number of master clock periods.
Clearly, the precision of the frequency multiplier is limited by the
resolution of the input period measurement, as well by the fact that,
in general, the result of dividing the master clock frequency by the
multiplying factor is not an integer value.
If the restriction of the output pulses to be
equidistant during any given input signal period is removed, the
second source of error can be exactly compensated. Many
designs of digital frequency multipliers have been reported in
literature, deferring both in operation principle and in the manner
the error correction is performed .Two main operating principles
may be distinguished
1.- The input signal period is measured as an integer number of
master clock cycles. The result is divided by the multiplying factor.
The integer part of the quotient is the minimum number of
master clock periods between consecutive output pulses. The
remainder of the division is the basis for error correction.

2.- The master clock frequency is divided by the multiplying
factor. The resulting clock signal is used to measure the input period.
The integer part of the measurement is the minimum number of
master clock periods between successive output pulses, and the
fraction is the basis for error correction.

A pure sinewave at frequency f has no harmonics. If it
goes through a linear amplifier, the result continues to be
pure (but may acquire a phase shift).
If the sinewave is run through a stateless nonlinear
circuit (transcribing function), the resulting distortion
creates harmonics. The distorted signal can be described
by a Fourier series in f.

The nonzero c
k
represent the generated
harmonics. The Fourier coefficients are given by
integrating over the fundamental period T:

These harmonics can be selected by a band pass filter.
The power in the distorted signal is spread across all
the resulting harmonics.
[1]
An ideal half wave rectifier, for
example, has all nonzero coefficients. An approximate
circuit could use a diode.
From a conversion efficiency standpoint, the nonlinear
circuit should maximize the coefficient for the desired
harmonic and minimize the others. Consequently, the
transcribing function is often specially chosen. Easy
choices are to use an even function to generate even
harmonics or an odd function to for odd harmonics. See
Even and odd functions Harmonics. A full wave rectifier,
for example, is good for making a double. On the other
hand, a Tripler may over drive an amplifier to
symmetrically distort the positive and negative peaks.
YIG multipliers often want to select an arbitrary
harmonic, so they use a stateful distortion circuit that
converts the input sine wave into an approximate impulse
train. The ideal (but impractical) impulse train generates
an infinite number of (weak) harmonics. In practice, an
impulse train generated by a monostable circuit will have
many usable harmonics. YIG multipliers using step
recovery diodes may, for example, take an input
frequency of 1 to 2 GHz and produce outputs up to 18
GHz.. Sometimes the frequency multiplier circuit will
adjust the width of the impulses to improve conversion
efficiency for a specific harmonic.

In digital electronics, frequency multipliers are often
used along with frequency dividers and phase-locked
loops to generate any desired frequency from an external
reference frequency. The frequency multiplication is
carried out in the phase-locked loop's feedback loop, by
using a frequency divider on the output of the voltage
controlled oscillator (VCO). This divided-down output is
fed-back to the input comparator and compared to the
reference frequency. Since the divided down frequency is
smaller than the reference frequency, the comparator
generates a voltage signal to the VCO, telling it to
increase the output frequency. It continues to do this via
the feedback loop, raising the VCO output frequency,
until the divided-down frequency from the VCO output is
equal to the reference frequency. At this point the
comparator stabilizes and generates no more signals to the
VCO, or only minor changes to maintain stability. The
output frequency from the VCO will be stable at the input
reference frequency multiplied by the value of the
feedback divider.
A PLL with a frequency divider in its feedback loop
acts as a frequency multiplier and is a type of frequency
synthesizer
Frequency multipliers have much in common wit
frequency, and some of the same nonlinear devices are
used for both: transistors operated in Class C and diodes.
In transmitting circuits many of the amplifying devices
(vacuum tubes or transistors) operate nonlinearly and
create harmonics, so an amplifier stage can be made a
multiplier by tuning the tuned circuit at the output to a
multiple of the input frequency. Usually the power (gain)
produced by the nonlinear device drops off rapidly at the
higher harmonics, so most frequency multipliers just
double or triple the frequency, and multiplication by
higher factors is accomplished by cascading doubler and
trippers stages.
Frequency multipliers use circuits tuned to a harmonic
of the input frequency. Non-linear elements such as
diodes may be added to enhance the production of
harmonic frequencies. Since the power in the harmonics
declines rapidly, usually a frequency multiplier is tuned to
only a small multiple (twice, three times, or five times) of
the input frequency. Usually amplifiers are inserted in a
chain of frequency multipliers to ensure adequate signal
level at the final frequency.
Since the tuned circuits have a limited bandwidth, if
the base frequency is changed significantly (more than
one percent or so), the multiplier stages may have to be
adjusted
as frequency synthesis, digital communications, and
data clock recovery [1]. Due to the advance in digital
integrated circuit (IC) technologies, the ADPLL has been
implemented and used in various applications [2]. The
architecture of an ADPLL is depicted in Fig. 1 [3], where
the main components are a digital phase (or phase-
frequency) detector (DPD), a digital loop filter (DLF), and
a digitally-controlled oscillator (DCO). A digital
frequency divider is also included in Fig. 1 for general
applications. Compared to the analog PLL, the ADPLL
has many merits such as lower frequency/phase jitters as
well as lower cost, and a higher yield. In addition, the
ADPLL has scalability and redesign flexibility with
changing processes, and also easy to integrate with
baseband communication circuits. For the ADPLL design
with the consideration of noise impact, the loop noise
bandwidth (i.e. loop bandwidth), lock-in (or settling) time,
and lock range are important performance factors.
The loop bandwidth, lock-in time, and lock range are
related to the natural frequency of a PLL system.
However, the loop bandwidth is proportional to the
natural frequency, and the lock-in time is inversely
proportional to it [1]. Thus, if the lock-in time is smaller,
the loop bandwidth is wider and leads to a poor noise
suppression. On the other hand, a narrower loop
bandwidth will lead to longer lock-in time. To design an
ADPLL with a fast lock-in time and a satisfied capability
of noise suppression, the digital loop filter must be
carefully designed.
Many design methods of an ADPLL system have
been reported in literatures. In [3], the ADPLL was
designed via a sampled system of the analog PLL, where
the substitution
between the corresponding Laplace and z-transforms
of the closed-loop transfer function for first-order and
second-order systems was employed. In [1], a counter-
based sequential loop filter was analyzed with computer-
aided design. In [3], the design procedure of an ADPLL
system using a cha rgepump analogy of an analog PLL is
addressed. To the best of our knowledge, the balance
between the lock-in time and the noise suppression
capability issues have not been explored for the ADPLL,
where an ADB-ADPLL is required.
III. BACKGROUND TO THE DESIGNE
DFM
The design digital frequency multiplier relates to a
frequency multiplier system and more particularly to a
digital frequency multiplier system suitable for handling a
varying input frequency signal typically at relatively low
frequencies.
In known frequency multiplication systems use is
made of phase locked loops or voltage to frequency and
frequency to voltage conversion. Phase locked loop (PLL)
techniques commonly used for frequency multiplication
have certain drawbacks. The principle drawback at low
frequencies is the loop response time due to the low pass
filter used in the feedback loop of the PLL. This
effectively means that at very low input frequencies the
frequency produced by the PLL may drift considerably.
Also phase locked loops cannot readily cope with high
dynamic ranges coupled with high multiplication factors.
For these to be correctly implemented high response times
are required which are unacceptable. The further
disadvantage is that the phase locked loop is essentially an
analogue system and this gives a poor performance when
the temperature of the system is subject to change.
The other common method of frequency multiplying is
to convert the input frequency to an analogue voltage,
process this voltage, probably with an op-amp, and then
convert this voltage to a higher frequency using a V/F
converter. Again problems occur at low frequencies--the
Frequency to Voltage (F/V) converter cannot produce a
steady voltage output. A large amount of ripple is
produced which may be easily eliminated using some
form of DC filter technique. In so doing the response time
of the system becomes too high and again this is
unacceptable. This system is also an analogue system and
thus suffers in the same way as PLL's.
IV. SUMMARY OF THE DESIGN DFM
According to the design part there is provided a digital
frequency multiplier comprising: a first path and a second
path, a first source of clock pulses and a second source of
clock pulses for supplying said first and second paths
respectively, first counter means in said first path, said
first counter means having a first input for receiving an
incoming frequency and for determining the number of
pulses occurring from said first source during the period
between sequential cycles of said incoming frequency,
divider means in said first path for dividing the first clock
pulses relative to the incoming rate, second counter means
in said second path for counting the number of clock
pulses from said second source, and comparator means
connected to receive the outputs of the first and second
paths respectively to produce an output signal having a
repetition frequency which is a multiple of the incoming
frequency.
The digital frequency multiplier overcomes
the difficulties incurred in the conventional methods of
frequency multiplication, and two principle advantages
are:
Fast response time: 1/input frequency
Negligible degradation in performance with
changing temperature.
The digital technique also offers predictability in
that the performance of the system may be repeated.
All the parameters relevant to the system's
operation may be readily calculated, including output
jitter (which is a function of the clock frequency), at all
times.
Systems performance does not drift with time--as
occurs in the analogue cases.
The system to be described typically can accept
any input frequencies from approximately 1 Hz to 10 KHz
and multiply these by an integer from 2 to N to produce
an output frequency in the range 2 Hz to 1 MHz (practical
value).
V. APPLICATION
The important applications of the Digital Frequency
Multiplier are mention below.
1) Fast and Accurate frequency measurement of
low frequency signals.
2) Accurate phase measurement of low frequency
signals.
3) Generation of real time output at present phase
on power line waveform.
The application 1 and 2are conventional. The
application no.3 is very useful in putting ON or putting
OFF a device or system at a predetermined angle on the
power line waveform. This is extremely useful in the
study of transients. It can be used to study behavior of
circuit breakers, transformers or Rotating machine when
put ON or OFF on the point on wave of the power line
waveform.
REFERENCES
[1]. Syed Masud Mahmud. "A programmable Self-Adaptlve
Digital Frequency Multiplier". IEEE Trans. Inshun Means.,
vol37 no. 2, pp.237-240, June 1988.
[2]. H.-Y. Lo and J.-H. Lu. A simple design for a digital
programmable frequency multiplier, Inr. J. Elri.rron.. vol.
46. no. 5. pp. 535-542. Dec. 1979.
[3]. Bilgic, A synchronous frequency multiplier using phase-
locked loop, Int. J. Electron., vol. 52, pp. 569-573. 1982.
.

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when mobile phones reached the market. By 2000, landline
telephones and wired computers were beginning to be
replaced by wireless technologies. The whole world was
literally going mobile as the turn of the millennium
approached. Apart from mobile phones, other wireless and
mobile computational devices such as Laptops, Palmtops,
PDAs (Personal Digital Assistants) and Tablets also rapidly
entered the market some devices of course with more
success than others for particular markets. Currently 1
billion mobile phones are in use throughout the world,
compared to 400 million Internet users. It is only since the
turn of the millennium that educational institutions started to
experiment with wireless and mobile technologies and that
the concept of M-learning started to emerge. Desmond
Keegan in 2003 published his latest book called: The
Future of Learning: From E-learning to M-learning. In
chapter four of this book, Keegan presents and analyses no
less than 30 M-learning initiatives across the globe in 2001.
In these initiatives much has already been done about the
experimental use of wireless technologies including wireless
Internet environments and wireless classrooms and various
mobile devices for teaching and learning. In further
chapters, Keegancontinues to discuss M-learning
possibilities including the capabilities and limitations of
mobile devices. With his book, Keegan demonstrates the
emergence and growing importance of M-learning.
Following statistical report gives the usage of mobile.
Figure 3 shows the use of mobile devices over the past
years. Figure 4 gives some examples of mobile technology
tools.
7.3 billion mobile subscriptions (May 2011)
Access to mobile networks available to 90% of the
world population
83% of total mobile subscriptions are in developing
countries
74% penetration rate in developing countries
250 000 SMS sent every second!
typesofdevicesstudentshaveaccessto
Source:SpeakUp 2009: Creating OurFuture:Students Speak Up abouttheirvision for21st Learning

Fig 3: M-learning devices
SomeExamplesofMobileTechnology
Tools
Wheredoyoubegin??
Zirada Kallisto
Impatica CTAD

Fig 4: Mobile Technology Tools
III. QUALITY OF LIFE OF ELDERS
According to brain research, age alters the structure of
the brain: overall brain mass shrinks modestly in some
people beginning around the age of 60 or 70. The cortex
also undergoes modest thinning and the brains white matter
decreases, influencing the transmission of signals between
different regions of the brain. Neurotransmitters, the
chemicals that relay messages from neuron to neuron in the
brain, become less available with age and this may play a
role in declining memory among older adults. The good
news is that age-related brain function loss is not a
necessary outcome of aging: the effects of changes within
the brain can be moderated by environmental factors, such
as intellectual stimulation. Formal education, leisure
activities, and professional pursuits can all contribute to
keeping the mind stimulated and healthy. We can make the
brain work better simply by accumulating more knowledge,
which builds more networks of connections in the
brainthe wisdom that we acquire can compensate for the
decline that may be gradually occurring, says
neurobiologist Dr. James McGaugh.
Active learning carries benefits that go beyond
alleviating age-related loss of brain function. Engaging in
active learning also provides a means for remaining actively
involved in the community, for developing new interests
and for keeping up with younger generations. In short,
people feel healthier, happier, more respected and more
independent when they pursue active learning in their senior
years.
IV. SPECIFIC NEEDS OF SENIOR CITIZENS
Overall it can be pointed out that older people can
hardly avoid using ICT in their everyday lives and they
are eager to learn how to use it, if they find them useful or if
there is any perceived personal benefit. Communication,
leisure, mobility, entertainment, social contacts are the most
important topics that need to be covered by ICT in general.
Technology and therefore all sorts of computer systems,
internet applications etc. are going to be integrated into
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rning should n
perts, new idea
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gnoscenti of m
adopt discover
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nships
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are inherently
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size and key si
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as mobile learn
nd not yet ta
does it remain
e into a serio
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figure in these
seem to be hi
g attention tod
evelopments i
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not be left beh
as and inventi
and invention
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enue stream
rgent need for
ile project
ons operators
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IX. CON
ucationists, w
ing possibilit
will provide e
nments are id
approaches
between lec
mong membe
ulfills the gro
failure becaus
riven: M-lear
ncept.
market usage.
ries in Cyber
flow and le
onal Analysi
entrenched
ultures of
eflect gover
consumer tech
y dissatisfying
sed need for th
ndards to ov
tandards are
dly regulating
unications tech
tery life.
ize.
multiple screen
ng E-learning
S OF MOBILE LE
ning not yet e
aken its place
n at the resea
ous form of
lications are b
walks of life
e development
igh on the list
day. It is esse
in education
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hind. As relaye
ions only beco
s are adopted
e learning is
for the tele
r mobile learn
status and
that it represe
NCLUSION
we should em
ties that M-l
even more so
deal for conte
where in
turers and l
ers of COPs
owing deman
se as a learni
rning alone is
psychology: W
earning networ
is of Mob
institutionaliz
education a
rnment cont
hnology: Mob
g by never qu
he consumer.
vercome cultu
slow to emer
g and limiting t
hnology.
n sizes, multip
g materials
EARNING
emerged from
e in mainstre
rch project lev
provision? T
being develop
e. Learning a
ts. Learning a
t of applicatio
ential for mob
keep pace w
tant that mob
ed by innovati
ome innovatio
d and utilized
s not seen as
ecommunicatio
ning is to emer
convince t
ents a viable a
mbrace the ri
learning alrea
o in future. M
emporary soc
nteraction a
learners, amo
is needed. M
nds for life-lo
ing
s a
We
rks
bile
zed
and
trol
bile
uite
ural
rge
the
ple
for
its
am
vel
The
ped
and
and
ons
bile
with
bile
ion
ons
by
s a
ons
rge
the
and
ich
ady
M-
cial
and
ong
M-
ong
learning opportunities that enable you to learn while you
earn on-the-go. The challenge is to design and develop
relevant learning environments, based on sound didactical
principles that will ensure the optimizing of learning in the
M-learning environment. M-learning increases the
confidences for senior citizens and motivates them to
continue their education.
REFERENCES
[1]. Mfkk Invention and Research Center Services Co. Ltd., Web 2.0
Best practice for senior citizens , 2011. 04. 28 Canadian council on
learning lessons in learning, August 22, 2006.
[2]. Paul Muyinda , Ezr , Kathy Lynch, M-Learning: The Educational
Use of Mobile Communication Devices,
[3]. Dr Tom H Brown, Towards a model for m-learning in Africa,Title
of article submitted to the South African Journal for Higher
Education.
[4]. Kristiansen, T 2001. M-learning: Experiences from the use of WAP as
a supplement in learning. Unpublished report on a pilot project in co-
operation between Insite, Ericsson, Telenor Mobil and It Fornebu
Knowation.April 2001, Norway. 11
ISBN: 978-81-920575-6-9 :: doi: 10. 74271/ISBN_0768
THE RECENT ADVANCES & FUTURE TRENDS IN WIRELESS
BIOTELEMETRY SYSTEM

MadhupriyaSenapati
B tech(Electronics &communicatin)
JayotiVidyapeethWomens University, Jaipur, Rajasthan, India

Abstract- The Telehealth field is currently an extremely active
interdisciplinary research area. The research includes
modeling physical, link, and network layer protocol
development, and the creation of new applications for healthy
and sick people.
This paper gives you a complete description on firstly, what is
the Wireless Medical Telemetry system, its various areas of
applications & how this idea was first generated. It also
explains the electromagnetic spectrum involved in the
working of a wireless medical telemetry system. Then is the
state-of the art and future trends in the low power telemetry
system, as energy harvesting and its consumption becomes a
very concerning issue.
Technical advancements in embedded systems, wireless
communications and physiological sensing allow small size,
light weight, ultra low power, and intelligent monitoring
devices. A number of these devices can be integrated into
energy efficient biotelemetry system with Nano IP, a new
enabling technology for health monitoring, sports and
military applications.
Finally, keeping in mind, the present day and future concern
for Energy, this paper focuses on Energy harvesting system
with Nano IP.

Keywords- telemetry, Energy harvesting, Energy scavenging

I. INTRODUCTION

The development of wireless medical telemetry has
become an increasingly popular application in recent years.
As the elderly population continues to increase, healthcare
costs also continue to rise. Systems that are developed for
monitoring diseases at home provide several benefits.
First, by monitoring a person at home the disease
progression or fluctuation can be monitored continuously
instead of only obtaining a snapshot in the doctors office.
Secondly, healthcare costs can decrease since the
monitoring may be done outside of the clinic. Finally, the
quality of life for the patient may increase since they can
be monitored in the comfort of their own homes.
A wireless ECG system can monitor a patients heart
activity (electrocardiography), electrical brain activity
(electroencephalography), pulse oximetry, and many
others. while allowing him to live a normal life at home &
the patient can upload the data recorded by the device to
the hospital via internet. Electrodes and transducers
connect to a small radio transmitter worn by the
patient. Their physiological data is transmitted from the
user worn unit to a computer over a radio link. Telemetry
systems not only make the patient more comfortable but
may reduce costs for hospitals by allowing them to monitor
any patient in any room, minimizing the costs of
transferring data to a single location, and minimize the
amount of equipment that must be kept in the patient room.
Given the hectic hospital environment, wireless
medical telemetry has become and will continue to be an
important technological innovation.
Wireless communication systems are envisioned to be
used for:[1]
-implantable pacemakers and defibrillators
-glucose monitors
-insulin pumps
-hearing aids
-health care facility communication
-medical and emergency equipment
tracking
-remote patient monitoring

II. BACKGROUND

Wireless medical telemetry was first used in hospitals
for fetal heart rate monitoring more than 30 years ago.
Originally developed by NASA engineers to monitor the
physiological parameters of astronauts, wireless medical
telemetry has since been utilized to monitor everything
from oxygen saturation to orthopedic device loading.
In order to understand how a wireless medical
telemetry device works, one must be familiar with the
electromagnetic spectrum. Electromagnetic energy is
composed of alternating electric and magnetic fields
traveling through space. The energy carried in these fields
can manifest when it interacts with a certain type of matter.
What differentiates different types of electromagnetic
energy is the wavelength of the fields. Wavelengths can
vary dramatically, as can their effects. For example, x-ray
and gamma ray energy have wavelengths (10
-10
10
-14
m) so
small that they can fit between individual atoms. Radio
waves, on the other hand, have much longer wavelengths
(1 -10
4
m) and are most commonly used for communication
purposes.
typical wireless medical telemetry system is composed
of a small, battery-operated radio transmitter that is
connected to electrodes placed on the patient. The signal is
t
s
i
m
m
r
s
t
s
s
i
c
p
i
s
e
o
h
i
T
f
f
o
s
n
transmitted to
signal for furth
The first s
is to amplify t
modulate the
modulated RF
radiating ante
small battery
the electrical h
At the rec
signal and am
signal is dem
information fr
commonly po
permanent loc

One prob
integrate tele
signal interfe
example, as y
often a sign n
have major im
integration, th
Telemetry Ser
for wireless
frequencies ar
1432 MHz. D
operate prote
sources such
networks (WL
o a remotely lo
her processing
step in the wir
the bio-signal
RF carrier g
F signal can
nna. The tran
pack operatin
hazards and ri
ceiver, an ante
mplifies it thro
modulated in
from the trans
owered by a
cation in an iso
blem hospital
emetry techno
erence from
you may have
not to use cell
mplications o
he FCC has d
rvice (WMTS
medical te
re 608-614 MH
Devices transm
cted from int
as wireless p
LAN).
ocated receive
g.
reless medical
. Once amplif
generated by
then be direc
nsmitter is usu
ng at a low vo
isks to the pati
enna receives
ough a RF am
order to rec
mitter. Receiv
a wall outlet
olated location
s are facing
ology into th
other wirele
seen in many
phones. Signa
on patient saf
developed the
), a set of RF
elemetry app
Hz, 1395-140
mitting in thes
terference cau
phones and w
er that recover
l telemetry pro
fied, the signa
an oscillator.
ctly applied to
ually powered
oltage, minimi
ient.[2]
the modulated
mplifier. Next
cover the orig
ver units are
because of
n from the pat
while tryin
heir operation
ess devices.
y hospitals, the
al interference
fety. To ease
Wireless Me
bands used so
plications. T
0 MHz, and 1
se frequencies
used by other
wireless local
rs the
ocess
l can
The
o the
by a
izing
d RF
t, the
ginal
most
their
ient.

g to
ns is
For
ere is
e can
this
dical
olely
These
1427-
s can
r RF
area
ba
eq
rel
ba
tra
T
wi
in
di
de
di
(S
ap
as
me
im
The WMTS
ands dedicated
quipment. Thi
liable twowa
ands are ve
ansmission vir

III. R
TRENDS IN L
M

Wireless sy
ired alternativ
fection, redu
scomfort, enh
elivery. Appl
sciplines, sug
SoC) or System

IV. DES
An examina
pplications re
sociated with
edical field
mplementation
bands offer th
d solely for t
is, in turn,
ay communic
ery narrow,
rtually imposs
RECENT ADV
LOW POWER
MEDICAL AP
ystems hold a
ves, including
uced risk o
hanced mobil
lications dem
ggesting oppo
m-in- Package
SIGN CRITER
ation of wirel
eveals two
the deployme
and those
n.
he advantage o
the use of m
allows for fa
cation. Howev
making vid
sible.
VANCES AND
RWIRELESS S
PPLICATION
a number of a
: ease of use,
of failure, r
lity, and low
mand experti
ortunity for
(SiP) integrat
RIA AND CH
less technolog
sets of ch
ent of a new te
associated
of being the fi
medical teleme
faster and mo
ver, the WM
deo and vo
D FUTURE
SYSTEMS FO
NS
advantages ov
reduced risk
reduced pati
wer cost of c
se in multip
System-on-Ch
tion.[3]
HALLENGES
gies for medi
hallenges: tho
echnology in t
with techni
first
etry
ore
MTS
ice
OR
ver
of
ent
are
ple
hip
ical
ose
the
ical
m
c
m
a
w
a
l
s
s
o
r
i
m
e
h
w
I
p
s
v
T
For a wire
must provide
compromising
must be both
authorized per
The techn
wireless me
application. D
limited proce
simpler comm
Systems m
size and weig
or battery bas
required to av
in replaceme
material use
environmenta
human body.
while less rest
In addition,
problems such

V

A number
systems for m
vitro monitor
Table I.
eless medical
efficient, reli
g patient saf
private and s
rsons.
nical challeng
dical system
Devices in viv
essing and m
munication pro
must be highly
ght. Sources o
sed; in the la
void the cost, r
ent surgical
ed should
lly friendly
Applications
trictive, still d
in vitro tec
h as interferen
V. EXISTIN
TECHN
r of existing r
medical appli
ring, and tel
system to be
able, and accu
fety. Transm
secure, yet rem
es inherent in
m depend o
vo (inside the
emory capabi
otocols.
y integrated to
f power can b
atter case, max
risk, and patie
procedures.
be both b
for biocompa
s in vitro (o
demand low po
chnologies su
nce and noise.
NG AND EME
NOLOGIES
research-based
ications inclu
emedicine, a
widely adopte
urate data wit
mitted informa
main accessib
n the design
on the inte
e body) may
ilities, deman
minimize imp
be either indu
ximum lifetim
ent trauma inhe
Furthermore,
biologically
atibility with
outside the bo
ower consump
uffer exposur
ERGING
d and comme
uding implant
re highlighte
ed, it
thout
ation
ble to
of a
nded
have
nding
plant
uctive
me is
erent
the
and
h the
ody),
ption.
re to
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s, in
d in
wi
low
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de
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ex
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tec

1. Techno
A number
ireless capabil
w carrier fre
ubQore radio
onsumes a pea
ycle at 400kb
asonably size
evices, and ha
ansmission t
pplications fo
anagement,
imulators, and
2. Narro
Internal ima
agnosis, parti
GI) tract. A nu
apsule have b
tra low-pow
ansmission to
tro applicatio
Wireless Med
edicated spectr
3. Potenti
In terms of c
UWB) is exp
chnology for w
The FCC a
quires that UW
andwidth (BW
he FCC also
xceedingly sm
PSD). There
chnology wh
chnologies in
ology for Impl
of recent wo
lities of induc
equencies. Th
architecture
ak current less
bps. This ban
ed antennas, a
as propagation
through the
or the radio
glucose met
d vascular bloo
wband Applic
aging is a w
cularly for di
umber of desig
been reported.
wer wireless
a receiver w
ons, numerous
ical Telemet
rum for medic
ial for Ultra-W
communicatio
periencing a
wireless medic
also redefines
WB devices o
W) or with a -
ensures that
mall, with very
are several
hen compare
n the medical
lants
orks focus on
ctively powere
he recently an
from Cambri
than 1.7mA f
d allows the
avoids interfe
n characteristi
human b
o include c
ters, insulin
od pressure mo
cations
widely used to
iseases of the
gns for a wire
. Given Imag
s link for
worn around th
s low power
try Systems
cal telemetry e
Wideband
on standards, U
rebirth a
cal application
the definitio
occupy more t
-10dB BW gr
t UWB emis
y low Power S
advantages
d with trad
l area. Due t
n improving t
ed implants w
nnounced MI
dge Consulta
for a 0.05% du
construction
rence with IS
ics conducive
ody. Propos
cardiac rhyth
pumps, ner
onitors.
ool for medi
Gastrointestin
eless endoscop
ging employs
r non-invasi
he waist. For
examples ex
(WMTS) u
equipment.
Ultra- Wideba
s an emergi
ns.
on of UWB a
than 500MHz
reater than 20
ssion levels a
Spectral Dens
of the UW
itional wirel
o its low EIR
the
with
CS
ants
uty
of
SM
to
sed
hm
rve
ical
nal
pic
an
ive
r in
ist.
use
and
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and
of
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are
sity
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ess
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o
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m
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a
t
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a
t
m
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n
c
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other radio sy
interception
medical data)
UWBs 7.5GH
ultra high da
resolution me
detection syste
4. Tele
Multiple B
are appearing
typically rel
transceivers.
environment,
connected to
continuous
connecting th
has been inves
5. MEM
Micro-Ele
important role
building the
implementatio
ends. Pressur
world, and ha
For example,
across heart v
to measure ca
glaucoma di
diagnosis of u
Features
attractive for
ability to integ
functions in an
manufacturing

The succ
networks will
low power w
maintenance f
may in the
environment.
approaches to
temperature v
mechanical vi
human body,
hundreds of m

The great
networks is en
can no longer
replenished. T
of a wireless s
t, a UWB sign
ystems, which
and detectio
), and less in
Hz unlicensed
ata rate medi
edical imaging
ems.
emedicine
Bluetooth-bas
g in the liter
ly on the
Applicable to
data gathere
o PDAs or
patient mon
hese piconets t
stigated.
MS Technolog
ectromechanica
e in wireless
e critical m
on of ultra lo
re sensors ar
ave the highes
they are used
alves accurate
ardiac output
sease progre
urological diso
that make
next generati
grate mechani
n SoC/SiP env
g.
VI. ENERG
cessful prolif
l in part depen
wireless nod
free. The ener
future be
In addition to
o scavenge ene
variations, ind
ibrations, fluid
and solar ener
microwatts or m
VII. ENERG
est problem f
nergy. When a
r fulfill its role
Therefore, it is
sensors expire
nal behaves a
h results in l
n (i.e. enha
nterference. F
d bandwidth,
ical applicatio
g, virtual sur
sed medical t
rature. To da
connection
o both the h
ed from these
to the intern
nitoring. The
to cell phones
gy
al systems (
medical syste
mechanical
ow power RF
e very matur
st potential in
d to measure
ely to help ass
and complian
ession, and t
orders.
the MEMS
on medical d
ical, sensory, a
vironment wit
GY SCAVEN
feration of
nd on the dev
des that are
rgy required f
scavenged d
o MEMS, a nu
ergy have bee
ductively pow
d flow, energy
rgy have been
more.
GY HARVES
faced by mos
a sensor is dep
e unless the s
s generally acc
s when its bat
as a noise sign
low probabilit
anced privacy
Furthermore,
it can be used
ons such as
rgery, and can
telemetry sys
ate, these sys
of off-the-
ospital and h
e devices can
net via PCs
e capability
s for telemed
(MEMS) play
ems, ranging
sensors to
transceiver f
re in the ME
the medical f
pressure grad
ess valve dise
nce, to unders
to assist in
technology
evices include
and computati
th very low co
NGING
medical wir
velopment of u
autonomous
for their opera
directly from
umber of diffe
en studied. Na
wered smart c
y produced by
n proven to de
STING:
st wireless se
pleted of energ
ource of energ
cepted that the
ttery run out.
nal to
ty of
y of
with
d for
high
ncer-
stems
stems
shelf
home
n be
s for
of
dicine
y an
from
the
front-
EMS
field.
dients
eases,
stand
the
very
e the
ional
ost of
reless
ultra-
and
ation
the
ferent
atural
cards,
y the
eliver
ensor
gy, it
gy is
e use
the
en
so
pr
so
is
lim
lif
ha
so
ex
en
ha
an
se
wi
req
de
rep
of
Ha
en
all
se
ac
ch
tec
thr
the
ge
en
vib
to
A solution t
e power con
nergy harvesti
ources such as
roduced from t
olar energy. On
through the u

A wireless s
mited power so
fetime. Much
as assumed th
ource, namely
xtending the
nergy usage. F
ardware dama
nd network r
arch for an
ireless sensor
quire sensors
ecades) or e
placement is
f ambient ene
arvesting.
Following ar

Reduce d
nergy may be s
Reduce m
lows for devi
rvice visits to
Providing
ccess hazardou
Reduce
hemicals.
The more
chnology is th
rough the use
e safest and
enerated from
nergy is not s
bration based
scavenge bo
to extend the b
nsumption th
ing. This can
s vibrational e
the body mov
ne method of
se of piezoele
sensor networ
ource (like a b
of the research
he use of a
batteries, to p
lifetime of
Failure due to
age) can be ov
re-configuratio
alternative s
r networks es
to be install
embedded in
impractical. T
ergy into a u
re the some be
ependency on
sufficient to el
maintenance
ices to functio
replace batter
sensing and ac
us environmen
environmen
efficient and
he energy harv
e of piezoelect
efficient meth
m vibration is
safe at all ins
harvesting, m
ody vibrations
battery lifetim
hrough a tech
n be achieve
energy, kineti
ements, body
f harvesting vi
ctric crystal.
rk that is not
battery) essent
h on wireless
portable and
power sensors
the network
o other causes
vercome by s
on. This has
source of en
pecially for a
led for long d
n structures
The harnessin
useful form is
enefits of Ener
n battery pow
liminate batter
costs as En
on unattended
ries.
ctuation capab
nts on a contin
ntal impact
d safety ene
vesting from v
tric capacitor.
hod in the se
s not harmful
stances to hu
micro power g
s for use in t
me and to redu
hnology nam
ed from vario
ic energy that
temperature a
ibrational ener
dependent on
tially has infin
sensor networ
d limited ener
s and focused
by minimizi
s (like structu
self organizati
s motivated t
nergy to pow
applications th
durations (up
where batte
g and collecti
s called Ener
rgy Harvesting
wer as harvest
ry completely
nergy harvesti
d and elimina
bilities in hard
nuous basis.
of hazardo
ergy harvesti
vibration ener
. This method
ense, this pow
l as even so
man body. In
generator is us
the sensor no
uce
med
ous
t is
and
rgy
n a
nite
rks
rgy
on
ing
ural
ion
the
wer
hat
to
ery
ion
rgy
g:
ted
.
ing
ates
d-to
ous
ing
rgy
d is
wer
olar
n a
sed
de.
Experimental results have shown that when a piezoelectric
crystal in The Bio-Telemetry system consists of body
sensor networks in which slave sensor nodes can be used
for bio-medical information acquisition; signal
preprocessing, data storage, and wireless transmission
(sometimes direct transmission without any preprocessing).
These body sensors are used to sense the various bio-
medical parameters such as breath rate, temperature of the
body, motion of body parts, glucose level in the blood and
also heart beat rate. The sensed analog signals are
converted to digital signals appropriate for transmission.
This type of slave sensor node is called as the sensing
node. In addition, the function of sensor nodes can be
expanded to monitoring, diagnosing and for treatment
purpose and this type of slave sensor node is called as the
stimulating node. The sensed signals are driven to master
node through the slave node. Then the master node
transmits the sensed signals to the desired computer system
at where monitoring of patient has been done. This
transmission can be performed through Nano IP module.

Energy harvesting is achieved by placing piezoelectric
crystal to the moving body parts. Piezoelectric crystal
works on the principal of piezoelectric effect, through
which vibrational energy produced by the body parts is
converted to electrical energy that gives sufficient
additional energy for the sensor unit. Energy harvesting
technology increases the life time of all the sensors, and
also reduces the power consumption.

VIII. NANO IP
In our system, the communication will be made
through the Nano IP. Nano IP stands for the Nano Internet
Protocol which is a concept that was created to bring
internet- like networking services to embedded and sensor
devices, without the overhead of TCP/IP. Nano IP was
designed with minimal overheads, wireless networking and
local addressing in mind.
The protocol actually consists of two transport
techniques, nanoUDP, which is an unreliable simple
transport, and nanoTCP, which provides retransmissions
and flow control. A socket-compatible API is provided
which makes the use of the protocols very similar to that of
IP protocols. The only difference is in addressing and the
port range. NanoIP makes use of the MAC address of
underlying network technology rather than IP addresses,
which are not needed for local networks. The port range is
8-bits, 256 ports each for source and destination.
With the Nano Socket family, only a few hours are
required to add full-featured Internet access functionality
over LAN or WiFi to an embedded device, including TCP
sockets, SSL encryption, routing, e-mail, and file transfers.
The logical interface between the host application and the
modules is AT+i Protocol, a simple text-based API that
enables fast and easy implementation of Internet
networking and security protocols. The Nano Socket
family includes a plethora of security features. The
modules serve as a communications offload engine and
inherent firewall, protecting the embedded device from the
Internet attacks.[4]

IX. CONCLUSION
State-of-the-art research on low power wireless systems
for medical applications has been presented. A review of l
design criteria reveals that not only must technical
challenges be considered, but those issues associated with
reliable and secure operation in a medical setting must be
addressed as well. Several examples of current research-
based devices and commercial products are described.
Emerging techniques to realize low power systems have
been addressed. Energy scavenging is examined as a
possible power source.

Also, as Energy is a matter of concern these days,
implementation of the bio telemetry system using Nano IP
has been proposed. Compared to the conventional
protocols used in bio-telemetry systems, the proposed
Nano Internet Protocol suit gives efficient and reliable
transmission of bio-medical parameters to the monitoring
location.

REFERENCES

[1]. Emerging technologies-wireless communication systems for
implantable devices By DorinPanescu

[2]. Wireless medical telemetry laboratory.-2006 Cleveland
Medical Devices Inc., Cleveland, OH

[3]. Recent advances and future trends in low power wireless
systems By-Kenneth A.Townsend, Tommy K.K Tsang,
Krzysztof Iniewski.

[4]. Energy efficient biotelemetry system with Nano IP By-
R.Mohan, R.Banaridaran, K. Sudha


ISBN: 978-81-920575-6-9 :: doi: 10. 74278/ISBN_0768
Design Issues of Bus Arbitration Schemes in Shared Bus Multiprocessor(MPSoC)
Prof.Neeta Doifode
Department of Electronics and Telecommunication
Datta Meghe Institute of Engineering, Technology and Research, Wardha, India

Abstract The multiprocessor SoC designs have more than
one processor and huge memory on the same chip. SoC
consists of hardware cores and software cores ,multiple
processors, embedded DRAM and connectors between cores .A
wide range of MPSOC architectures have been developed over
the past decade. This paper surveys the history of various On-
Chip communication architectures present in the design of
MPSoC. This acts as a primary factor of overall performance
in complex SoC designs. Some of the various techniques that
have driven the design of MPSoC has been discussed.
Dynamically configurable communication architectures are
found to improve the system performance. Currently On-chip
interconnection networks are mostly implemented using
shared buses which are the most common medium. The
arbitration plays a crucial role in determining performance of
bus-based system, as it assigns priorities, with which processor
is granted the access to the shared communication resources.
In the conventional arbitration algorithms there are some
drawbacks such as bus starvation problem and low system
performance. The bus should provide each component a
flexible and atmost share of on-chip communication bandwidth
and should improve the latency in access of the shared bus.
The performance of SoC is improved using the probabilistic
round robin algorithm with regard to the parameters, latency.
Thus in this paper various issues related to bus arbitration
related to design of MPSoC is analysed.
Keywords: MultiProcessor System-on Chip (MPSoC),Shared
Bus, OnChip Network, Latency
I. INTRODUCTION
Shrinking process technologies and increasing design
sizes have led to highly complex billion transistor integrated
circuits (ICs).As a consequence, manufacturers are
integrating increasing number of components on a chip. A
heterogeneous SoC might include one or more
programmable components such as general purpose
processor cores, digital signal processor cores, or
application-specific intellectual property cores (IPs) as well
as an analog front end, On-chip memory, I/O devices and
other application specific components. In other words, SoC
is an IC that implements most or all the functions of a
complete electronic system.
Modern System-on-Chip (SoC) architectures comprise
several components such as master and slave modules.

Masters are active modules that send read requests or
data to memories. Typical masters are CPUs and hardware
accelerators such as DMAs,hash generators ,or graphics
engines. Slave modules are passive components that react
on requests and store data or respond to master requests
with appropriate data. Slave modules are typically
memories, on-chip buses, or simple register banks. Some of
the bus architectures of various MPSoC has been reviewed
.Memories can be distinguished into on-chip and off-chip
memories. On-Chip memories feature low latencies but
small capacities whereas the off-chip memories exhibit high
latency with high capacities. Figure 1 shows an SoC
example.

Fig 1: Shared Memory Multiprocessor System
Building an SoC requires a communication infrastructure
that supports a large number of transaction masters and a
large number of slaves, each of which can be arbitrated
between the masters that needs to access that slave.
Traditionally, multi-master buses like the Advanced High-
performance Bus (AHB) have been used for the task. The
bus arbiter resolves access conflicts by the masters to the
single shared resource of the bus, which implicitly prevents
multiple masters to access the same slave at the same time.
A single shared bus does not allow any communication to
happen in parallel between different masters and different
slaves at the same time.
Concurrent requests at a slave are resolved using a simple
arbiter. However simple arbitration lead to poor
performance with regard to throughput and latency of the
overall system .Hence it is necessary to judiciously select a
communication architecture that best suits or optimally suits
the communication traffic generated for particular
application. In addition to selecting communication
architecture from a variety of alternatives, it is necessary to
customize the selected architecture for the specific
application or domain. Both these factors make it critical for
a designer to be aware of, and to evaluate the trade-offs
involved in the selection of an optimal system level
communication architecture.

Fig:2 Traditional Shared Bus Topology

In this paper, we present a detailed survey and analysis of
the performance of various commonly used SoC
communication architectures, under several conditions. The
architectures we consider in this paper includes Static
Priority based shared system bus, hierarchical bus, TDMA
based architecture and a ring based architecture. Efficient
methodology has been developed to study the performance
of various architectures.

II. REVIEW ON SHARED BUS
ARBITRATION ALGORITHMS

In this section, concepts and terminology associated with
on-chip communication architectures has been introduced.
Some popular communication architectures used in
commercial SoC design is described. The communication
architecture topology consists of a network of shared and
dedicated communication channels, to which various SoC
components are connected. These include (i) masters, which
initiate a data transaction (e.g., CPUs, DSPs, DMA
controllers etc.), and (ii) slaves, components that merely
respond to transactions initiated by a master (e.g., on-chip
memories). Fig (2). When the topology consists of multiple
channels, bridges are used to interconnect the necessary
channels. Since buses are often shared by several SoC
masters, bus architectures require protocols to manage
access to the bus, which are implemented in (centralized or
distributed)bus arbiters. Currently used communication
architecture protocols includes round-robin, priority based
and time division multiplexing .In addition to arbitration,
the communication Protocol handles other communication
functions like to limit the maximum number of bus cycles
by setting maximum transfer length.
2.1. Static Fixed Priority:
It is a common scheduling mechanism [2]. In this scheme
each master is assigned a fixed priority value. When several
masters request simultaneously, the master with highest
priority will be granted. This is achieved by employing a
centralized arbiter. (Fig.2.).If masters with high priority
requests frequently, it will lead to the starvation of the
elements with lowest priority. But its advantage is its simple
implementation and small area cost, flexibility and faster
arbitration time. This protocol is used in shared bus
communication architectures. (Fig. 2). This protocol is used
by bus architectures like AMBA, Core Connect
2.2. Time Division Multiple Access (TDMA):
Time division multiplexed scheduling divides execution
time on the bus into time slots and allocates the time slots to
adapters requesting the use of buses [4]. A request for use of
the bus might require multiple slot times to perform all
required transfers. If the master associated with current time
slot has pending request ,the arbiter grants the transaction
immediately and time wheel is rotated to next slot.

Fig 3: Schematic Diagram of TDMA Architecture

Advantage of this algorithm is that it is easy to
implement. Disadvantage in this method is that it leads to
the mistake of data transfer and poor response latency.
However in this architecture, the components are provided
access to communication channel in an interleaved manager,
using two level arbitration protocols. To alleviate the
problem of wasted slots, second level of arbitration is
supported to permit the bus grant to other requesting
masters. For e.g.. The current slot is reserved for M1, which
has no pending request. As a result arbitration pointer is
incremented from its current position to next pending
request. (Fig 3). The major drawback is its poor bandwidth.
2.3.Round Robin Algorithm:
Round Robin algorithm can reallocate the available slots
to other requesting master. It is a fair arbitration style when
used with a limited transfer length. Whenever a turn ends,
either unused or because of end of transfer or limited
transfer length, the turn is passed to next component in
order. Maximum access time and equal bandwidth can be
achieved with limited transfer length. However it provides
poor performance if requests are varied dynamically.
2.4. Lottery Bus Architecture:
In this protocol a centralized lottery manager accumulates
request for ownership of shared communication resources
from one or more masters, each of which has assigned static
or dynamic lottery tickets. Master owning the maximum
number of tickets will be granted the access of bus.


2.5 Token passing Architecture:
This protocol is used in ring based architectures. A
special data word, called token, circulates on the ring .An
interface that receives a token is allowed to initiate a
transaction. When the transaction is completed, the interface
releases the token and sends it to the neighboring element.
Ring based architectures have also been used in high speed
ATM switches. The Fig.4. Shows the model of ring based
architectures with 8 components attached to the ring through
ring interfaces.
The advantage of the ring based architecture is that the
channel is connected to all the components, but is point-to-
point and therefore can support higher clock rates than the
previously described architectures. An important parameter
is the maximum token holding time, which bounds the
maximum number of words, a ring interface can send or
receive each time it seizes the token.

2.6 Code Division Multiple Access (CDMA):
This protocol has been proposed for sharing on-chip
communication channel. In a sharing medium it provides
better resilience to noise/ interference and has an ability to
support simultaneous transfer of data streams. But this
protocol requires implementation of complex special direct
sequence Spread spectrum coding schemes, and
energy/battery inefficient systems such as pseudorandom
code generators, modulation and demodulation circuits at
the component bus interfaces and signaling .

Fig 4: Ring based communication architecture

As a conclusion we can say that on-chip-bus-design and
on-chip-core-based design methodologies are integration
approaches that depend on standardized component or bus
interfaces. They allow the integration of homogeneous IP
components that follow these standards to be directly
connected to each other, without requiring the development
of complex wrappers. Let us note that on-chip buses rely on
shared communication resources and on arbitration
mechanism that is in charge of serializing bus access
requests. This widely adopted solution unfortunately suffers
from power and performance scalability limitations, and
restricted sharing of resources between communicating
entities. For bus networks, the bus is occupied by a single
communication even if multiple communications could
operate simultaneously on different portions on the bus.
Therefore a lot of effort has been devoted to the
development of advanced bus topologies (e.g. partial or full
crossbar, bridged buses) and protocols for better support of
route-ability, flexibility, reliability, and reconfigure-ability.
Therefore, a systematic way of designing networks with
possibly arbitrary topology is gaining the importance.
In the long run, a more aggressive approach is needed.
For particular needs, the SoC may be built around a
sophisticated and dedicated network-on-chip that may
deliver very high performance for connecting a large
number of components. It seems that this design paradigm
shifts towards packetized on-chip communication based on
micro-networks of interconnects or networks-on-chip [1].

III. SHARED BUS ARCHITECTURES

Various SoC buses are overviewed and its construction
are discussed by[1].Shared bus communication architectures
like AMBA, WISHBONE, Core Connect , and PCI are most
popular choices among the system designers due to their
extensive features. AMBA arbiter design is simple enough
to handle master and slave communication. Wishbone and
Core connect arbiters and its design for communication
between masters and slaves consume more area. The
structure of the AMBA AHB is illustrated in the Fig.5.

3.1 AMBA BUS:
AMBA is the most widely used bus communication in the
emerging SoC applications .AMBA AHB developed by
ARM consists of arbiter, masters and slaves. It allows
arbiter to be designed to suit the application needs, the best.
This specifies a hierarchy of bus types, tailored to differing
priorities found across the interconnect structure of SoC
designs .It minimizes silicon infrastructure required to
support efficient on-chip and off-chip communication for
both operation and manufacturing test.

Fig 5: AMBA AHB Based SoC

3.2. Wish Bone BUS:
The Wishbone bus architecture is shown in Fig.6.It shows
a simple application of wishbone SoC Bus involving master
slave communication..Wishbone uses master/slave
architecture. Functional modules with master interfaces
initiate data transactions to participating slave interfaces.
There are four different types of interconnection in this
architecture which includes Point-to-point, Data flow,
Shared Bus and Crossbar switch. Arbiter selects the master
that will own the slave, based on the arbitration technique.
which can be chosen by the designer and implements it
based on the application needs.
The Wishbone bus architecture is shown in Fig.6.It shows
a simple application of wishbone SoC Bus involving master
slave communication..Wishbone uses master/slave
architecture. Functional modules with master interfaces
initiate data transactions to participating slave interfaces.
There are four different types of interconnection in this
architecture which includes Point-to-point, Data flow,
Shared Bus and Crossbar switch. Arbiter selects the master
that will own the slave, based on the arbitration technique.
which can be chosen by the designer and implements it
based on the application needs.

Fig 6: Wishbone so C Bus
Wishbone doesnt have separate interfaces for low speed
and high speed peripherals like AMBA. It appears to be the
simplest of other buses reviewed.

IV. EXISTING ON-CHIP BUS ARCHITECTURES

4.1. Lottery bus Communication Architecture
Lahiri et al (2001) presents a flexible and scalable
algorithm for the multiprocessor SoC.The core of the
LOTTERYBUS architecture is a probabilistic arbitration
algorithm implemented in a centralized lotterymanager
for each bus in the communication architecture. The
architecture does not presume any fixed communication
topology. Hence, the various SoC components may be
interconnected by an arbitrary network of shared channels
or a flat, system-wide bus.
The lottery manager accumulates requests for ownership
of the bus from one or more masters, each of which is
(statically or dynamically) assigned a number of lottery
tickets, as shown in Fig. 7. The manager pseudo-randomly
chooses one of the contending masters to be the winner of
the lottery, favoring masters that have a larger number of
tickets, and grants access to the chosen master for a certain
number of bus cycles. Multiple word requests may be
allowed to complete without incurring the overhead of a
lottery drawing for each bus word. However, to prevent a
master from monopolizing the bus, a maximum transfer size
is used to limit the number of bus cycles for which the
granted master can utilize the bus Also, the architecture
pipelines lottery manager operations with actual data
transfers, to minimize idle bus cycles. The inputs to the
lottery manager are a set of requests (one per master) and
the number of tickets held by each master. The output is a
set of grant lines (again one per master) that indicate the
number of words that the currently chosen master is allowed

Figure 7: Lottery manager for a bus in a Lottery bus-based
communication architecture
transfer across the bus. The arbitration decision is based on
a lottery. The lottery manager periodically (typically, once
every bus cycle) polls the incoming request lines to see if
there are any pending requests. If there is only one request, a
trivial lottery results in granting the bus to the requesting
master. If there are two or more pending requests, then the
master to be granted access is chosen using the tickets
t0,t1,t2 and t3 for the respective masters.
4.2 Dynamic Lottery bus architecture:
In this architecture (fig 8), the inputs to the lottery
manager consist of a set of request lines (r0r1r2r3), and the
number of tickets currently possessed by each
corresponding master that are generated by ticket generated
by ticket generator[8]. Therefore, under this architecture,
not only can Range of current tickets vary dynamically, it
can take on any arbitrary value. Therefore at each lottery,
the lottery manager needs to calculate for each
component , the partial sum This is implemented
using a bit wise AND operation and tree of adder, as shown
in Fig 8.The final result, T=r0t0+r1t1+r2t2+r3t3, defines the
range in which the random number must lie. A limitation of
this implementation is that distribution of the resulting
random number is not uniform. The rest of the architecture
consists of comparison and grant hardware, and follows
directly from the design of the static lottery manager.
Figure 8: Lottery manager architecture with dynamically varying tickets
Advantages of Static lottery Bus architecture is that all
the masters that are requesting gain the control of bus.
Disadvantages of dynamic lottery bus architecture is that if
the pseudo random number is greater than total ticket value
then none of the masters will get the grant signal. Master
having low ticket value has a large average latency.
4.3. ATM switch architecture:
In this arbitration algorithm, it accepts three parameters
(Requests, Tickets, Adaptive signal) for the input of arbiter.
Adaptive signal value is used as an additional input to
improve the probability of the bus grant. This adaptive
signal value is transmitted from the master that requires the
bus grant more than another master because of the stressful
traffic. Since we do not know which IP is used for the
shared bus in advance of the SOC design, the adaptive
signal can be fixed by the specific parameter. In this paper,
the master counts the buffer position storing the ATM cell
and if the data approaches to the limited amount, the
adaptive signal is generated to improve the drawing
probability.
The current pending request and ticket value is used to
obtain the shared probability of Ci .In order to improve the
probability of the master .Ai values are obtained from the
look up table and two of the master requests accomplish the
bit-wise AND operation by the values. ai is the additional
ticket value to solve the problem of random value. [Fig.9].
We assume that the data approaches to the limited buffer
capacity in C4 then master generates the adaptive signal.
For the input adaptive signal, the MUX control signal is
generated by the fixed value of the look up table and the
pending request value. In case C4 generates the adaptive
signal and the adaptive request is 0001 from the lookup-
table, the pending request value from the master is 1011 and
the bitwise AND operation with 0001 from look-up table
generates 0001.Therefore the total ticket value
is At the same time, the determined ticket value
0004 is generated and the existing ticket value 1034
assigned to the master operates with the adder to get the
ticket value 1038. The adaptive ticket value is used to solve
the problem that the characteristics of LFSR are
disappeared.

Figure 9: ATM Switch architecture
If the pseudo random value is bigger than , the
control signal of MUX generates the enable of the request
bit from the master. The partial summation value of each
master is obtained by the bit-wise AND operation between
the request values and the ticket value. If the pseudo random
value from LFSR and the total ticket value generates
modulo , C4 is assigned to use the bus,
because the pending request value is 0001.The advantage of
ATM switch architecture is that the adaptive signal is used
to solve the problem that the characteristics of LFSR are
disappeared if pseudo random number is bigger than total
ticket value.

V. CONCLUSION

In this paper, we have discussed some of the issues
related to the design of SoC with regard to the
interprocessor communication .Various bus architectures
and protocols have been reviewed. Currently on-chip
communication networks are mostly implemented using
shared interconnects like buses. Shared bus communication
architectures like AMBA, Wishbone. AMBA is the most
widely used bus communication in the emerging SoC
applications. By power analysis between various
architectures it is found that Core connect consumes more
power due to presence of various gates in the
interconnection . Wishbone requires more area due to more
interconnections in the architecture. Core connect consumes
more latency due to gated signals from master to arbiter and
from master to slave. Hence the designers should select the
right arbitration technique to meet the requirements with
improved performance for various shared bus architectures.
Hence in the future research it is focused to design an arbiter
that dynamically schedules the requests by various masters,
occurring simultaneously and thus improving the
performance of a multiprocessor with respect to latency and
bandwidth.

REFERENCES

[1]. Sorren Sonntag and Helmut Reinig (2008 ) , An Efficient-
Weighted-Round Robin algorithm for Multiprocessor
Architectures, Proc. 41st Annual Simulation Symposium, IEEE
Computer Society of India..

[2]. Bu-chung Lin, Geeng-Wei Lee, Juninn DarHuang and Jing-
Yang Jou (2007), A Precise Bandwidth Control Arbitration
Algorithm for Hard Real Time SOC Buses, DAC 2007, pp
165-170.

[3]. Prakash Srinivasan ,Ali Ahmadinia Ahmet ,T Erdogan Tughrul
Arslan (2007), Power Evaluation of the Arbitration policy for
different On-Chip Bus based SoC platform ,IEEE SOC
Conference, Taiwan, Volume, Issue, 26-29 Sept. 2007 pp:159
162.
ISBN: 978-81-920575-6-9 :: doi: 10. 74285/ISBN_0768
An Context Aware Document Clustering Using Data Fusion
P.VenkateshKumar
Research Scholor,
Anna University of Technology
Coimbatore,Tamil nadu

Abstract Information is better utilized when it is organized
and easier to find. The tremendous growth in the volume of
unstructured text data in the internet and various other
sources including digital libraries, news has led to
development of techniques to organize the information as per
the user's requirement. Context of the selected word in the
document plays a very important role in achieving the desired
search goal. Document clustering helps organizing data
collection and enhance information retrieval. In this paper, it
is proposed to cluster documents by computing the term
frequency of the document collection and fuse contexts based
terms. The feature extracted data is clustered using
agglomerative clustering and Bisecting K-Means methods.
Keywords: Document clustering, term frequency,
Agglomerative clustering, Bisecting K-means.
I. INTRODUCTION
Document clustering enhances information retrieval.
Information is better utilized when it is better organized,
and easier to find. Document clustering is based on the
clustering hypothesis, that documents having similar
contents are relevant to the same query [1]. Cluster
analysis is a statistical tool for automatic classification that
groups similar entities in a multi-dimensional space [2].
Document clustering is unsupervised grouping of text
documents into groups or clusters sharing common topic or
have overlapping content. The unsupervised method makes
it possible to organize information without any prior
knowledge about the classification of documents.
Hierarchical clustering algorithms like single link,
complete link, group average, Ward's method, and
weighted average were primarily used in document
clustering [3]. These methods were developed during the
earlier days, but with the exponential growth of document
collections, these techniques cannot be scaled due to their
computational overhead.
Document clustering has many applications, widely
used for enhancing search engine results, web crawling,
document organizing and in information retrieval. The
main applications of clustering in information retrieval are
search result clustering, scatter-gather, collection
clustering, language modeling and cluster-based retrieval.
In search result clustering, the search results are clustered
so that similar documents appear together. In Scatter-
Gather clustering, the user selected groups are merged and
this collection is once again clustered. Effective
information presentation for exploratory browsing is
achieved by collection clustering. Document clustering in
language modeling results in increased precision and/or
recall. Clustering speeds up the retrieval process, as
document matching the query will contain all the similar
documents in the same cluster.

There are different methodologies for clustering; some
most commonly used methods are partitioning algorithms,
hierarchical method, graph-based, density and grid based
clustering [4, 5]. Clustering algorithms for document
clustering are broadly classified as Hierarchical algorithms
and Partitional algorithms.

Hierarchical algorithms: The documents in hierarchical
methods are represented in multi-level and tree-like
structure [6]. These methods achieve better quality
clustering results but reallocation of documents is not
possible [7] and time complexity is quadratic.

Partitional algorithms: The documents are clustered in
single level. Partitional algorithms are applied to large
collection of documents due to its low computational
requirements [8]. The clusters may overlap in this method.
The most popular partitional algorithm is the K-means
algorithm. This algorithm performs in linear time
complexity.
II. LITERATURE REVIEW
Smeaton, et al., [9] proposed architecture for efficient
document clustering and retrieval from a dynamic
collection of documents. The key problem faced by
document clustering is the computational overhead, as
creating clusters requires an NXN similarity matrix. With
the collection of documents growing in size, it is not
feasible to generate a similarity matrix for information
retrieval. The proposed architecture the clustering process
is implemented in an efficient way by applying several
thresholds within the cluster generation process. This leads
to a clustering architecture which is scalable to large
collections. The proposed architecture is capable of
catering to dynamic updates and additions to the database
and re-generate clusters in a reasonable time frame. The
proposed method used complete link clustering and was
experimented using the database of a newspaper.

Jones, et al., [10] proposed using a genetic algorithm
(GA) for document clustering. The GA provides an
efficient solution for combinatorial optimization problems
in reasonable time when compared with the deterministic
algorithm like non-hierarchic clustering. The experiments
used three document test collection. The collection was
clustered using GA. The effectiveness of the resulting
clusters for searches was evaluated. The performance
measure used was E-measure, smaller the E values better
the retrieval performance. The GA results obtained were
compared with that of nearest-neighbor clusters.
Experimental results concluded that the value of E was
smaller for the nearest-neighbor than the GA.
Mahdavi, et al., [11] proposed a Harmony K-means
algorithm (HKA) based on Harmony search optimization
method. The proposed method converges to the global
optimum using theory of Markov chains. The documents
are represented in a vector space model, and the HKA
algorithm is applied. Experiments are conducted using five
datasets. Stop words are removed, and Porters algorithm is
used to reduce different types of words. The proposed
algorithm was evaluated for quality and speed of
convergence using different datasets. The proposed
algorithm is compared with K-means algorithm.
Experimental results proved conclusively that the proposed
HKA algorithm produces better solutions with high
quality.
In this paper, it is proposed to cluster documents by
computing the term frequency of the document collection
and cluster documents using agglomerative clustering and
K-Means bisect methods with similarity measures like
cosine function and correlation coefficient function. The
paper is organized as follows: Section I deals with the
introduction of document clustering, its applications and
related works with respect to different types of clustering
algorithm. Section II consists of literature review with
section III explaining the methodology, followed by results
and discussion in section IV and conclusion in section V.

III. METHODOLOGY
Term frequency is a statistical measure used to
determine the most essential terms in documents. The raw
term frequency is equal to the number of times a term
appears in a document. The raw term frequency does not
take into account the relative importance of the term, thus a
weighted term frequency is used and given as
,
,
,
0 0
1 log
t d
t d
t d
if tf
wf
tf otherwise
=
=

+

The term frequency weighs words inverse of frequency,
that is, higher the frequency of a word in a document lower
is its weights, thus the measure is called term frequency-
inverse document frequency (tf-idf). The documents and
query are represented in a vector space model [12]. In this
model, each document d is considered to be a vector in the
term-space and it-idf is represented by the vector as:

, 1 2
1 2
log , log ,...., log
tfidf i d m
m
n n n
d orw tf tf tf
df df df
| | | | | | | |
=
| | | |
\ . \ . \ . \ .

where
i
tf
is the term frequency of the ith term , n is the
total number of documents, and
i
df
is the document
frequency. The length of each document vector is
normalized to that of a unit length.

The similarity between two documents
i
d
and
j
d
is
computed by cosine function [12]. The distance between the
documents are given by the cosine of the angle between
them. A vector is normalized by dividing each of its
components by its length-

2
2
i
i
x x =

This maps the vectors in unit sphere:

,
1
1
n
j i j
i
d w
=
= =

The similarity is given as:

( )
.
,
j k
j k
j k
d d
sim d d
d d
=

For normalized vectors, the cosine is the dot product

( )
cos , .
j k j k
d d d d =

Pearsons correlation coefficient is another popular
similarity measure used to measure the extent of relation
between two vectors. The measure ranges from +1 to -1.
For a term set
{ }
1
,..,
m
T t t =
, the coefficient is given by
( )
, ,
1
2 2 2 2
, ,
1 1
,
m
t a t b a b
t
a b
m m
t a a t b b
t t
m w xw TF xTF
PCC t t
m w TF m w TF
=
= =
=
( (

where
,
1
m
i t a
t
TF w
=
=


The correlation coefficient selects terms that are highly
indicative of membership in a category. Correlation
coefficient is given by:

( )
( )
( )( ) ( ) ( )
* *
,
TP TN FN FP
Co T C
TP FN FP TN TP FP FN TN
=
+ + + +

where TP is true positive, FP is false positive, FN is
false negative and TN is true negative.
Agglomerative hierarchical clustering is a bottom-up
clustering method; wherein starting with a single entity or
small cluster, it agglomerates or merges to form the next
higher level clusters. Thus clusters have sub-clusters, which
in turn have sub-clusters and so on. Agglomerative
hierarchical cluster algorithm in successive iteration
agglomerates the closest pair of clusters by satisfying some
similarity criteria, until all the data is in one cluster. These
steps can be repeated until the desired number of clusters is
obtained or the distance between two closest clusters is
above a certain threshold distance. The cluster similarity is
computed using any one of the distance measurement such
as Euclidean, Euclidean squared, Pearson correlation, or
Spearman method. The drawback in this method is that an
entity cannot be relocated, and use of different distance
metrics may result in different results.

The process followed by agglomerative clustering is as
follows:
- Each object is assigned to a separate
cluster.
- Distances between the clusters are
measured.
- A distance matrix is constructed using the
distance values.
- Pair of clusters with the shortest distance
is selected.
- The selected pair is merged and removed
from the matrix.
- The distances from the new cluster to all
other clusters is calculated and updated in the
matrix.
- Repeat until the distance matrix is
reduced to a single cluster.

Basic K-means Algorithm is a centroid-based approach.
It generates k number disjoint and flat clusters. The K-
means method is an unsupervised and iterative method. The
K-mean follows the process for clustering:
- Selects K points randomly as the initial
centroids.
- Assign all entities to the closet centroid.
- The centroid of each cluster is
recalculated.
- Repeats above two steps until the
centroids dont change.

The disadvantage of K-means method is that the quality
of the clusters produced is difficult to compare and the size
of the clusters varies widely. These problems are addressed
by Bisecting K-means method. The bisecting K-means
algorithm starts with a single cluster of all the documents
and works in the following manner:
- Pick a cluster to split.
- Basic K-means algorithm is used to find
2 sub-clusters.
- Repeat the above bisecting step for a
fixed number of times and take the split that
produces the clustering with the highest overall
similarity.
- Repeat the above steps until the desired
number of clusters is reached.

Using the concept of Hypernym words represented as a
two level tree are fused and the TDF computed.

IV. RESULTS AND DISCUSSION

The transcribed Reuters dataset consisting of 10 class
labels is used in this experiment. The obtained feature set is
reduced based on the importance of the word with respect
to the class label. Table I and Figure 1 Shows the
classification accuracy of the clusters using Nearest
neighbor and Agglomerative clustering.

TABLE I : CLASSIFICATION ACCURACY

Num
ber of
clusters
K Nearest
Neighbor
Agglomerative
clustering
5 73.47 77.55
10 76.53 78.57
15 75.51 82.65
20 75.51 80.61

From table I it is seen that the classification accuracy
obtained is comparable with other techniques available in
literature. Figure 1 shows the plots obtained.


Figure I : The classification accuracy for different number of clusters.

V. CONCLUSION
In this paper it is proposed to investigate a novel
method of word fusion based on word context using
hypernymn. The transcribed reuters dataset is used to test
the hypothesis. The results obtained are promising with
classification accuracy of up to 82.65%. Further work
needs to be done to prune data and think of multi word
fusion.

REFERENCES

[1]. Van Rijsbergen, C. J. Informationretrieval Butterworths, 1979.
[2]. Everitt, B.S. Cluster Analysis. London: Edward Arnold, 1993.
[3]. Willett, Peter. Recent Trends in Hierarchic Document
Clustering: A Critical Review.Information Processing and
Management Vol. 24, No 5, p. 577-597, 1988.
[4]. Grira N, Crucianu M, Boujemaa N (2005) Unsupervised and
semi-supervised clustering: a brief survey. In: 7th ACM
SIGMM international workshop on multimedia information
retrieval, pp 916.
[5]. Jain AK, Murty MN, Flynn PJ (1999) Data clustering: a
review. ACM Comput Surv 264323.
[6]. Zhao Y, Karypis G (2005) Hierarchical clustering algorithms
for document datasets. Data Min Knowl Discov 10:141168.
[7]. Jain AK, Murty MN, Flynn PJ (1999) Data clustering: a
review. ACM Comput Surv 264323.
[8]. Steinbach M, Karypis G, Kumar V (2000a) A comparison of
document clustering techniques. KDD2000. Technical report
of University of Minnesota
A. Smeaton, M. Burnett, F. Crimmins, and G. Quinn. An architecture
for efficient document clustering and retrieval on a dynamic
collection of newspaper texts. In BCS-IRSG Annual Colloquium on
IR Research, Workshops in Computing, 1998.

V
A
p
Proc. of th
Volume 1. Co
ISBN: 978-8
APC-

AbstractTh
operationin si
consume much
small ROMS
The proposed
odd-multiple
(LUT) for me
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results in the
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he Intl. Conf. o
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he multiplica
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multipliers to
ons. Each of
the LUT size b
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proposed com
LUT size to o
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pple carry add
compiler for
decrease in a
used CSD bas
carry additio
Verilog using
SYS design co
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multiply-accu
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Applications
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4306/ISBN_07
306
D LUT FO
De
Ka
Co
major arithm
Us. The multipl
nted design util
some basic ga
oding (APC)
for lookup-t
be used in dig
these techniq
by a factor of t
d OMS schem
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mbined appro
one fourth of
is coded for 5
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area and d
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Xilinx version
ompiler version
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umulate struct
tation time. T
speed devices
mory has beco
cient. It has
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ntages as gre
d low late
wer consump
ctures reduces
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elay[2] .

ndia.
768
OR MEM
Eldho John
epartment of E
arunya Univer
oimbatore, Ind
metic
liers
lizes
ates.
and
table
gital
ques
two.
me is
mory-
oach
the
5 bit,
and
delay
y as
r in
The
n 92i
n B-
duct
delay
ture,
This
s. In
ome
also
mory
fast
uting
ulate
eater
ency
ption
s the
king.
plex
mu
coe
be
bin
val
val
mu
com
val
.X
i
if a
LU
ava
opt
hav
onl
req
mu
ant
size
are
brie

A.A
Thi
hal
MORY BA
ECE
rsity
dia

Figur

A conven
ultiplier is sh
efficient, havin
multiplied w
nary number o
lues of X, an
lues of produc
ultiplication, a
mputed produ
lues of X, is c
is stored at th
an L-bit binar
UT, then the
ailable at its ou
However,
timization for
ve presented
ly the odd m
quired to be s
ultiple storage
tisymmetric pr
e can also be
e recorded as a
II PROPOSED
MEM
In this sect
efly.
APC FOR LU
The APC c
is method sto
lf data is obtai
ASED CO
re 1 Conventio
ntional look
own in Figu
ng word lengt
ith A [1]. As
of word length
d accordingly
ct C= A.X. Th
an LUT of 2
L
uct values cor
onventionally
he location X
i
ry value of X
correspondin
utput [1].
do not find an
memory base
a new approa
multiples of
stored, which
e (OMS) sch
roduct coding
e reduced half
antisymmetric
D APC-OMS
MORY BASED
tion we will se
UT OPTIMIZA
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OMPUTA

onal LUT ba
up table
ure 1, where
th and X is an
ssuming X to
h L, there can
y, there can b
herefore, for m
L
words, con
rresponding t
y used. The pr
i
for 0 x
i
2
X
i
is used as a
ng product v
ny significant
ed multiplicat
ach to LUT
the fixed c
has referred
heme [7]. In
g (APC) appro
f, where the p
c pairs [8].
COMBINED
D MULTIPLI
ee about the te
ATION
educes the da
first half dat
g the 2s comp
1
ATION

ased multiplier
(LUT) based
A is a fixed
n input word to
be a positive
be 2
L
possible
be 2
L
possible
memory based
nsisting of pre
to all possible
roduct word A
2
L
-1, such tha
address for the
value A.X
i
i
work on LUT
tion. Recently
design, where
coefficient are
to as the odd
addition, the
oach, the LUT
product word
D LUT FOR
IER
echniques
ata size to half
a. The second
plement
1
r
d
d
o
e
e
e
d
e
e
A
at
e
s
T
y,
e
e
d
e
T
s
f.
d
2
Table I
APC words for different input values for L=5
Input
, X
Prodc
t
value
s
Input
,X
Prodc
t
value
s
Address
x
3
x
2
x
1
x
0

APC
Word
s
0000
1
A 1111
1
31A 1111 15A
0001
0
2A 1111
0
30A 1110 14A
0001
1
3A 1110
1
29A 1101 13A
0010
0
4A 1110
0
28A 1100 12A
0010
1
5A 1101
1
27A 1011 11A
0011
0
6A 1101
0
26A 1010 10A
0011
1
7A 1100
1
25A 1001 9A
0100
0
8A 1100
0
24A 1000 8A
0100
1
9A 1011
1
23A 0111 7A
0101
0
10A 1011
0
22A 0110 6A
0101
1
11A 1010
1
21A 0101 5A
0110
0
12A 1010
0
20A 0100 4A
0110
1
13A 1001
1
19A 0011 3A
0111
0
14A 1001
0
18A 0010 2A
0111
1
15A 1000
1
17A 0001 1A
1000
0
16A 1000
0
16A 0000 0A

The product words for different values of x for L=5
are shown in Table I. The first column in the table is the
2s complement of that on the third column of the same
row [1]. In addition, the sum of product values
corresponding to these two input values on the same row
is 32A. Let the product values on the second and fourth
columns of a row be u and v, respectively. Since can
write

u = [(u + v)/2 (v u)/2] (1)

v = [(u + v)/2 + (v u)/2] (2)

for (u + v) = 32A, soequation (1) and (2) modified
to,
u=16A-[(v-u)/2] (3)

v=16A+ [(v-u)/2] (4)

From equation (3) and (4), instead of storing u and
v only [(u-v)/2] is stored for a pair of input on a given
row. Since the representation of the product is derived
from the antisymmetric behaviour of the products, it can
name asantisymmetric product code [8]. The 4-bit
address X=(x
3
x
2
x
1
x
0
) of the APC word is given by
[1]

X= {X
L
, if x
4
=1}
{X
L
, if x
4
=0} (5)

In equation (5), X
L
= (x
3
x
2
x
1
x
0
) is the four less
significant bits of X, and X
L
is the twos complement of
X
L
is the twos complement of X
L
. The desired product
could be obtained by adding or subtracting the stored
value (v u) to or from the fixed value 16A when x
4
is 1
or 0, respectively [1], i.e.

Product word = 16A + (sign value) (APC word) (6)

In equation (6) sign value = 1 for x
4
= 1 and sign
value = 1 for x
4
= 0. The product value for X = (10000)
corresponds to APC value zero, which could be
derived by resetting the LUT output, instead of storing
that in the LUT [8]. The main application of LUT is in
various filter structure [3]-[6].

B. MODIFIED OMS FOR LUT OPTIMIZATION

Table II
OMS based design of the LUT of APC words for L=5

Input X
x
3
x
2
x
1
x
0

Produc
t value
No
of
shift
s
Shifte
d
input,
X
Store
d
APC
word
Addres
s
d
3
d
2
d
1
d
0
0001 A 0 0001 A 0000
0010 2A 1 0001 A 0000
0100 4A 2 0001 A 0000
1000 8A 3 0001 A 0000
0011 3A 0 0011 3A 0001
0110 6A 1 0011 3A 0001
1100 12A 2 0011 3A 0001
0101 5A 0 0101 5A 0010
1010 10A 1 0101 5A 0010
0111 7A 0 0111 7A 0011
1110 14A 1 0111 7A 0011
1001 9A 0 1001 9A 0100
1011 11A 0 1011 11A 0101
1101 13A 0 1101 13A 0110
1111 15A 0 1111 15A 0111

The OMS approach is shown in Table II. In the
OMS, instead of storing all the values of all 2
L
possible
values of the multiplication C=A.X, only (2
L
/2) words
corresponding to the odd multiples of A may be stored in
the LUT, while all the even multiples of A could be
derived by th
[7]. The even
shifting 3A,
shifting 5A a
using for prod
is derived fro
is not derived
is required. A
be implement
but the imple
stage barrel
efficient strat
that the produ
left shifts, it
APC word 0
an active high

X can be
the equation (
d
i =
x
i+1
, for
and
d

Where
shifting out al

For 16A only

X= { Y
L
, i

Where Y
all the leading
These m
below.
OMS based
Input X
x
4
x
3
x
2
x
1
x
0
P
v
10000
00000
III
COMB
The imp
combined LU
techniques, A
supposed to r
uses four blo
he left-shift op
n multiples 2A
while 10A a
and 7A respec
ducing the sh
m A, need a f
d from A, only
A maximum o
ted by a two s
ementation of
shifter. Ther
tegy to store
uct 16A can b
is shown in
0 is derived b
h RESET sign
RESET=(x
0
+
e mapped into
(8)
i =0,1,2...
d
3
=(x
0
)
X=(x
3
x
2
ll the leading
y
if x
4
=1 }
Y
L
is firmed b
g zeros in X
L
methods are de
Ta
design of the
1000
Produc
t
values
Enco
d wo
16A 0
0 16
IMPLEMEN
BINED LUT F
MUL
plementation
UT for memo
APC and OM
reduce the area
ocks. The bl
perations of t
A, 4A, 8A ar
and 14A are
ctively [7]. A
ift operation.
four left shift
y a maximum
of three left sh
stage logarithm
f four shifts
refore, it wo
2A for input
be derived by
Table III. F
by resetting th
nal given by th
x
1
+x
2
+x
3
).x
4
o a LUT addr

x
1
x
0
) is f
right zeros of
(9
y circularly ri

escribed in the
able III
LUT of APC
00, 00000

ode
ords
Store
d
value
s
0 ----
A 2A

NTATION OF
FOR MEMOR
LTIPLIER
of the prop
ory based mu
MS method.
a to one fourth
lock a conve
the odd multip
re derived by
derived by
A barrel shifte
However, if 1
operation. If 1
of three left s
hift operation
mic barrel shif
requires a th
ould be a m
X = (00000)
y three arithm
or X=10000,
e LUT output
he equation (7

(
ess (d
3
d
2
d
1
d
0
)
(8)
formed by r
f X
9)
ight shifting o
e Table III sho
words for inp
# of
shift
s
Add
s
d
3
d
2
0
---- --
3 10
F APC-OMS
RY BASED
posed APC-O
ultiplier uses
This method
h. This multip
erts our input
ples
left
left
er is
16A
16A
shift
can
fter,
hree-
more
), so
metic
the
t, by
7).
(7)
), by
)
right
out
own
puts
dres
s
2
d
1
d
0

---
000
OMS
two
d is
plier
ut to
add
the
add
and
out
Fig
con
in F
con
one
val
OM
thu
A.
pro
inp
use
pro
and
elem
A
dress d
0
d
1
d
2
d
3
e APC and O
dress d
0
d
1
d
2
d
3
d block d co
tput.
gure 2 APC-OMS
The propos
ntrol signal (s
Figure 2. This
ntrol circuit, 4
e barrel shifter
In this cir
lues, which o
MS method, th
us Area Delay
The Address g
The addres
oduce the addr
put to a 4 To
ed to produce
oceeding bloc
d correspond
ments are sho
ddress genera
I
(x
4
x
0
0
0
0
0
0
0
0
3
, which is pr
OMS method.
to LUT addr
onverts the L
S combined LUT
of 2-bit A with
sed method i
0,
s
1
) is obtain
s method uses
4-to-9 address
r and adder/su
cuit, thus sto
btained by ap
hus can reduc
Product.
generator and
s generation a
ress d
0
d
1
d
2
d
3
.
9 address dec
e the controls
ks. The diffe
ding values
own in the Tab
Table
ation and contr
L=5
Input
x
3
x
2
x
1
x
0

S
1

0000 1
0001 0
0010 0
0011 0
0100 1
0101 0
0110 0
0111 0
roduced by co
The block b
ress. The bloc
LUT output t
design for the
h 5-bit input X
is shown in F
ned from the
s one address
s decoder, 9
ubstractor unit
oring only so
pplying both
ce the area of
d Control circ
and control cir
This address
coder. The co
s
0
,s
1
which
erent combina
of address
ble IV.
e IV
rol outputs for
5
S
0
reset
1 0
0 0
1 0
0 0
0 0
0 0
1 0
0 0
3
ombining both
b converts the
ck c is an LUT
to the desired
multiplication
Figure 2. The
circuit shown
generator and
x 6 LUT and
t as shown.
ome specified
our APC and
f the LUT and
cuit
rcuit is used to
is given as the
ntrol circuit i
is used in the
ations of inpu
and contro
r input length
t Address
(d
3
d
2
d
1
d
0
)
1000
0111
0011
0110
0001
0101
0010
0100
3
h
e
T
d
n
e
n
d
d
d
d
d
o
e
s
e
ut
ol
)
In the a
possibilities o
control circui
Accordin
combined me
designed as
Reset=x
4
and
The ba
according to
gates to prod
the barrel shif
use in the nex
The add
shifter and so
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
above Table I
of input and
ts for easy ref
ng to the requ
ethod, the cont
S
0
=x
S
1
=(x
x
3
x
2
x
1

arrel shifter
the control v
duce the cont
fter, thus prod
xt sections.
dress generato
ome basic gate
1 1
0 0
0 1
0 0
1 0
0 0
0 1
0 0
1 1
0 0
0 1
0 0
1 0
0 0
0 1
0 0
1 1
0 0
0 1
0 0
1 0
0 0
0 1
0 0

IV, it has bee
its correspond
ferences.
uirement of AP
trol and reset
x
0
+(x
1
+x
2
)
x
0
+x
1
)
(12)
will right
values (s
0
s
1
),
trol elements
ducing the add
or circuit con
es, which con
0 0000
0 001
0 000
0 0010
0 0000
0 000
0 0000
0 0000
1 Reset
0 0000
0 0000
0 000
0 0000
0 0010
0 000
0 001
0 0000
0 0100
0 0010
0 010
0 000
0 0110
0 001
0 011
en shown the
ding address
PC and OMS
circuit can be
(
(
shift circul
, using the b
reset,s
0
,s
1
. Fr
dress (d
0
d
1
d
2
d
3
nsists of a ba
verts our inpu
0
1
1
0
0
1
0
0
ted
0
0
1
0
0
1
1
0
0
0
1
1
0
1
1
e all
and

(10)
(11)
larly
basic
rom
3
) to
arrel
ut to
an
bot
mu
a b
Fig
stan
inp
inp
inp
act

address d
0
d
1
th of our m
ultiple storage

The addres
barrel shifter
gure 3 and 4.

B. T
A 4-to-9 a
ndard 3-to-8
puts 0000 to
puts it will ac
put 1000, the
ivated. The de
d
2
d
3
, which
methods antis
(OMS).
s generator an
and some bas
Figure 3 Cont
Figure 4 A
The 4 To 9 Ad
address decod
decoder. This
1000.For 00
ct as a norm
ninth output
esign is shown
is obtained b
symetric (AP
nd control cir
sic circuit as
ntrol circuit
Address generator
ddress Decode
der is a deco
s decoder wil
000-0111 com
mal 3-to-8 dec
line of the de
n in Figure 5.
4
by combining
PC) and odd
rcuit consist o
shown in the

circuit
er
oder from the
l work for the
mbinations o
coder. For the
ecoder will be
4
g
d
of
e

e
e
of
e
e
C.The 9*6 Lo
A Look
an array or as
runtime com
operation. Th
significant, si
faster than
or input/outpu
D. The Barrel
In this u
output of Loo
reset signals.
with inserting
signals s
1
, s
0
.
the input (x
4
/subtract 16A
from the LUT

Word
size

8 Bit
Figure 5 The
ook Up Table
k up table
ssociative arr
mputation wit
he savings in te
ince retrieving
undergoing
ut operation.
l shifter and A
unit, producin
ok Up Table.
The outputs f
g zero on LSB
The output w
x
3
x
2
x
1
x
0
) i
A ie (110000)
T output.

Addition
Scheme
M

Ripple
Carry

Wallace
Tree
e 4 To 9 Decoder
is a data st
ay, often us
th a simpler
erms of proce
g a value from
an 'expensi
Adder unit
ng the correct
For this usin
from the LUT
B side accordi
will be resete
is 10000. Th
) to the outpu

CSD
Based
Multipli
er
Pro
Mu
ADP A

2201.1 20

1856.7 16
r
tructure, usu
ed to replac
r array index
essing time can
m memory is o
ve' computa
t output from
g the control
T are shifted r
ing to the con
d in this bloc
e adder will
ut of the LUT

oposed
ultiplie
r

AD
sav
ADP
9.8

005.34

639.03 9.6

ually
ce a
xing
n be
often
ation
m the
and
right
ntrol
ck if
add
T or
nd
an
m
se
mu
mu
sch
com
is i
the
into
me
pro
size
[5]
Sy
arch

DP
ving

8%

67%
F
IV
The coding
ISE 9.2i too
Compiler u
understand
work, the
commonly u
d ripple carry
nd the compa
measured in u
econds.

Com
V CO
The area a
ultiplier is com
ultiplier in bot
hemes. The a
mpared to the
increasing for
e LUT size ag
o this method
thods such as
ocessing appli
e.
[1]. P.K. Meh
computat
285289.
[2]. Internatio
Semicond
[3]. J.-I. Guo,
based VL
Circuits S
10, pp. 72
[4]. H.-C. Ch
memory-e
applicatio
Circuits S
Mar. 200
D. F. Chiper, M
ystolic algorithms
hitecture for the
Figure 6 Barrel sh
RESULTS
g of the propos
ol and synthe
using the T
the better per
performanc
used CSD mu
addition sche
arison is sho
um
2
and del
Table
mparison with
ONCLUSION
and delay of
mpared with c
th ripple carry
area delay pr
CSD based m
higher bits. I
gain by applyi
d. This method
s in IIR filter
ications.In fu
REFERE
her, LUT Base
ion in Circuits
onal Techn
ductors.[Online].A
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efcient realizati
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M. N. S. Swamy,
and a memory-b
e computation o
hifter and Adder u
S AND DISCU
sed work don
esized by Syn
TSMC 90-nm
erformance of
ce has com
ultiplier with
eme. The anal
own in Tabl
lay is measu
e V
CSD multipli
AND FUTUR
f the propose
commonly use
y and Wallace
roduct (ADP)
multipliers. Th
In future work
ing compressi
d can be appl
r and FIR fil
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of DCT/DST/IDC
5
unit
USSIONS
e in the Xilinx
nopsys Design
m library. To
f the proposed
mpared with
wallace tree a
lysis summary
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ured in nano
ier
RE WORK
d LUT based
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then it should
but the scan
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The V
to be applied
circuit will be
and analyze
conventional
technique w
compression t
data compres
reduction.
[1] Chul-k
and Ja
Low-P
[2] Sudip
Intelli
Dynam
19- 21
[3] S. Wa
Labor
Perfor

Scan",
directly applied
lating the pow
the Xilinx IS
esign Compil
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t for Benchmar
CONCLUSIO
project is i
1] during sh
rdering scan c
is much redu
several block
patterns, and t
entire pattern
d show better
cells becom
simple to im
veral scan chai
VHDL descrip
to a ITC 99 B
e simulated in
e the powe
patterns. The
ill be more
technique. In f
ssion techniqu
REFE
kiBaek, Insoo Ki
ae-Hoon Lee A
Power VLSI Testi
Roy, Ajit
gence Approach
mic Power Reduc
1, 2008.
ang, NEC Labor
atories America,
rmance of Broadc
, Proceedings of A
d to ITC 99 b
wer.The coding
E 9.2i tool an
ler using the
rk circuits

ON AND FUTU
intended t
hift operations
chains dynami
uced by grou
ks by using
then reorder a
ns is divide in
power consum
me even more
mplement, an
in[1] based tes
ption of reord
Bench mark cir
n synopsis des
er reduction
coding done
e efficient b
future it will b
ue for achiev
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URE WORK
to reduce po
s of scan ch
cally. Test po
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the correlati
again within e
nto more grou
mption reducti
e complex. T
d can be ea
st circuits.
dered patterns
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e in VHDL. T
by adding d
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engupta, "Artif
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[4] Y. Bon
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[6] D. Gho
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[7] Sying-J
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ST
ISBN: 978-81-920575-6-9 :: doi: 10.74236/ISBN_0768
CHECKPOINTS FOR CABS USING CELLULAR QUAD BAND MODULE
WITH GP
Pughazendi.N Srivatsan.S
Associate Professor / Department of M.C.A, PG Scholar, Department of M.C.A,
Panimalar Engineering College Panimalar Engineering College
Chennai, India Chennai, India

Abstract -- LBS are the mobile services in which the user
location information is used to provide a service. Providing
Location Based Service (LBS) using Global Positioning
System (GPS) as a location provider.

The main objective of this work is to design and
implement a client server system that helps cab service
providers to locate their cabs and to receive alerts when
there is any problem such as speed limit violations , taking the
unspecified route,etc..It was developed mainly to be used in
navigation tracking systems. Because of the reduction in the
size of the GPS receivers and because of the integration of
GPS with some mobiles; GPS became one of the most
important service providers in the LBS. The GM862-GPS
combines the powerful GSM engine of the GM862 with a
SiRF III 20-channel high sensitivity GPS receiver. Call up the
module, issue the GPS query command, and you'll have
NMEA data!

Keywords-component: Location based service, Global
positioning system, GM862-GPS.

I. INTRODUCTION
The cab location information consists of X-Y
coordinates generated by any given positioning technique
such as Cell-ID, GPS, etc. The GPS is the most efficient
positioning technique.
The location , the time and the speed of the cab etc are
retrieved and refreshed much frequently to check for any
violations and to make sure of the safety condition.

II. PROPOSED SYSTEM
This system tracks the movement of the cab and there
are some constraints to make the journey safe and short.
When the data (location,speed,time,checkpoint reach) are
constantly refreshed and updated in the database so as to
check whether the cab travels in the specified speed and
route . Whenever there is any violation or mismatch of the
condition , the system alerts the concerned incharge of the
cab so that necessary action could be taken by examining
what went wrong.
A. Advantages
The system provides the user with all the necessary
details about the cabs including start time, hours travelled ,
speed , current location , etc.. This will help the cab
providers to keep track of their cabs more effectively.
The cabs are not required to be manually monitored for
the unsafe state rather manual intervention is required only
when the tracking system raises any Alert. This minimizes
the human intervention.
All the required information about all the cabs and
about all the journey are efficiently maintained in the
database and is frequently refreshed for the uncompleted
journies. A quick view of all the details about a particular
cab or about a particular journey can be fetched from the
database based on the journey date or cab number or
location or time,etc.
This is a cost effective way of keeping track of all the
cabs of cab service provider.
GM862-GPS Advantages:
SiRF III High Sensitivity GPS Receiver
GSM Quad Band
On Board SIM Holder
Embedded TCP/IP Stack
GPRS Class 10
PYTHON Script Interpreter
Embedded FTP and SMTP Client
17mA average stand-by, 3.5mA in low-
power mode
250mA average operating current
Data, Voice, SMS, and Fax
Data speeds up to 57.6kbps
Supply voltage : 3.4-4.2V
CMOS Camera Capable
2 x MMCX Antenna Connectors
Extensive datasheets and forum support
Software and pin compatible with the
previous GM862 modules

III. SYSTEM ARCHITECTURE
The internet is the medium that will be used to transfer
user data and service request from the cab to the server and
then the requested information is processed.
There is a GPS device in each cab so that the location
of the cab can be tracked . Each cab is linked with the
server system which is inturn is mapped to the google map
inorder to locate the cab and compare with the checkpoints.
Since GPS is used to retrieve the information , we are
able to retrieve not only the latitude and longitude
(location) of the cab but also the speed of the cab , the
direction it travels which is very much useful in monitoring
the cabs more efficiently
A. Global Positioning System (GPS)
Every time the system at the cab service providers
place is updated with the cab location , it requests the
location of the cab from the GPS.
The Global Positioning System (GPS) is currently the
only fully functional Global Navigation Satellite System
(GNSS). More than two dozen GPS satellites are in
medium Earth orbit, transmitting signals allowing GPS
receivers to determine the receiver's location, speed and
direction.
We use the GM862-GPS module to receive the GPS
signals. GM862 has extended temperature tolerance and
supports GPRS class 10.
This gives high performance and high accuracy during
the process of tracking .
Jamming detection is one of the added advantage of
using this module as a GPS receiver .
Updating the Module is very simple and quick.
Updating the latest feature is via transfer of a delta file
which is faster and saves time.
B. GM862-GPS
The new GM862-GPS module is at the cutting edge of
the Telit product line. It combines superior performance in
quad-band GSM/GPRS modem functionality with the
latest 20-channel high sensitivity SiRFstarIII single-chip
GPS receiver.
Pin-to-pin compatibility to the previous GM862-GPS
module enhances and extends the functionality of new and
existing GPS applications. With its ruggedized design,
extended temperature range, integrated SIM card holder,
and industrial-grade connectors, the Telit GM862-GPS is
the ideal platform for mobile applications in areas such as
telematics, fleet management, tracking, security, and
vehicle navigation.
The new GPS receiver features low power consumption
with position resolution accuracy of less than 2.5m, SBAS
(WAAS and EGNOS) as well as high sensitivity for indoor
fixes. These features combined with the available
Python application development environment translate
into a very cost effective and feature rich platform quite
capable of becoming the total solution for the complete
customer application. Additional features including
jamming detection, integrated TCP/IP protocol stack, and
Easy Scan offer unmatched benefits to the application
developer without adding cost.
Support Over-the-Air firmware update by means Premium
FOTA Management. By embedding RedBends
vCurrent agent, a proven and battle-tested technology
powering hundreds of millions of cellular handsets world-
wide Telit is able to update its products by transmitting
only a delta file, which represents the difference between
one firmware version and another

IV. PROGRAMMING DESIGN
Cabs : c1,c2,c3,c4,..
For each Cab we have the following values to be
maintained :
LOCATION IDENTIFICATION:
1. Source Location : s
2. Destination Location : d
3. Check Points : cp1,cp2,cp3,cp4
4. Current Location of the cab: loc
SPEED:
1. Speed Limit: lim
2. Current Speed of the cab: cs
TRAVEL TIME:
1. Start Time of the journey: st
2. End Time of the journey: et
3. Maximum time to reach each checkpoint:
(HH:MM:SS): mt1, mt2, mt3, mt4
4. Minimum Time to reach each checkpoint:
(HH:MM:SS): min1, min2, min3, min4
5. Current Running Time (HH:MM:SS): ct
6. Minimum Time: min1,min2,min3,min4.
7. Checkpoint Reach time: cpt1,cpt2,cpt3,cpt4
Pseudocode :
Initialize source and destination (s and d) and
checkpoints.
Initialize speed limit , maxtime (mt1,mt2,mt3,mt4)
Get the start time : st
Get the current location : loc
if(loc!=s)
Raise ALERT (Source and Current location donot
match )
else
while(loc <= d)
{
RESET current timer to 00:00:00 [ i.e., ct=00:00:00 ]
Start the ct
Get the current speed (cs)
Checkspeed(cs)
i=1
while(i<5) // for 4checkpoints
{
Flag=false
If(ct > min
i
)
{
While( ct <= mt
i
)
{
If( loc == cp
i
)
{
Check point i Reached Set flag
i
=True
Store the cpt
i
= ct
break
}
}
}
If( flag
i
== false )
Raise ALERT (cp
i
Violated )
i++
}
}

// Total journey time calculation
If( flag == True )
{
Record the End Time et=(st+ct)
}

V. IMPLEMENTATION
The system is to be implemented by making use of the
google map facility and mapping the location of the cabs
and the checkpoints that are plotted already in the map
route so that the location of the cabs can be traced to
monitor the movement of the vehicle. The proposed system
also provides a means to consider the safety aspect of the
cabs by monitoring the speed of the cabs. When the cab
exceeds the predefined speed limit, this system will raise
an alert.
By using the GM862-GPS module as amodem and as a
GPS receiver the GPS signals are received and on the other
hand the location is fetched from google maps . Then the
module
interprets the location of the cabs and tracks the
violations of cabs if any and alerts the concerned person.
Starting the controller gives the following menu on the
terminal:

------
Beacon
v0.02
2007/07/
28
s -
Change
sms
phone
number
o - Switch modem on/off
i - Init modem
m - Send SMS
c - Cold start GPS
p - Request GPS
------
key >
Switching the modem on and off is done by pulling the
pin 17 of the GM862 to low for at least a second. The
status LED of the modem should start to blink in response.
Initializing the modem is done with the following
sequence of AT commands:
AT, say hello
AT+IPR=19200, set the baud rate to
19200
AT+CPIN=<pin>, set your PIN for the
SIM card
AT+CMEE=2, choose extended error
messages

The modem should respond with the status LED
blinking slower, if the PIN matches and the network is
reachable.
Initializing the GPS is optional, as the modul starts the
GPS on power on. You can force a cold or a warm start.
AT$GPSR=1, issue a cold start
AT$GPSR=2, issue a warm start
If you ommit the cold or warm start, you should be able
to see a fixed position within 30 seconds after you powered
up the module. This time may vary with your position and
the reachability of the satellites.
The current position is requested by sending
AT$GPSACP, read the acquired position
The response contains information about current time
and date, the position and the number of available
satellites.
To send send an SMS, send the following commands:
AT+CMGF=1, select text sms format
AT+CMGS="<phone number>", send the message to
the given phone number. This command responds with an
prompt >. Now the text of the SMS can be transmitted. The
message has to end with 0x1A.
Parsing the GPS position
The position string received from the GPS looks like
this:
GPSACP:
131924.999,5343.9291N,00954.7841E,2.6,34.0,3,29.78,0.3
2,0.17,
130707,07

VI. CONCLUSION AND FUTURE WORK
A. Limitations of the System
This system is at present developed only to track the
movement of the cab in some specified predefined
checkpoints but do not continuously track all the way
through from source to destination. This can be a limitation
to the proposed system since the checkpoints are static i.e.,
predefined only at some few areas.
B. Future Enhancements
This paper with an emerging technology of GPS in
future can be implemented to dynamically track the flow of
the cab locations so that the tracking is not based on some
few checkpoints but on the entire route from source to
destination.

REFERENCES

[1] Axel Kupper, Location-based services, fundamentals and
operation, WILEY, 2nd edition, 2005.
[2] Joel McNamara, GPS for Dummies, For Dummies,
1st edition, 1998.
[3] Rick Broida, How to Do Everything with Your GPS, McGraw-
Hill/Osborne, 2nd edition, 2004.
[4] Qusay H. Mahmoud "J2ME and Location-Based Services".
Sun Developer Network, 2004.
[5] Google Earth software. http://earth.google.com/ September
2008.
[6] http://earth.google.com/kml/
[7] http://earth.google.com/kml/kml_tut.html
[8] http://earth.google.com/products.html

ISBN: 978-81-920575-6-9 :: doi: 10. 74292/ISBN_0768
SMPS with Linear PWM Technique

Ishan S. Chintawar
M.Tech. (Electronics Engg.)
YCCE , Nagpur
Abstract: -A switched-mode power supply (switching-
mode power supply or SMPS) is an electronic Power
supply incorporates a switching regulator in order to be
highly efficient in the conversion of electrical power .In
SMPS using PWM chip , It requires hyperbolic curve of
nonlinear nature of Input voltage & on time for smooth
working . We do not get desired hyperbolic curve of
Nonlinear nature using the existing PWM chip. So
sometimes it over compensates & sometimes it under
compensates . Which causes error in the output voltage. In
this paper a review of different topologies of SMPS &
SMPS with linear PWM technique is introduced.

Keywords: Switch mode power supply, Pulse Width
Modulation, Nonlinear

I. INTRODUCTION
All electronic circuits need a power supply. A
device that transfers electric energy from a given source
to a given load using electronic circuits is referred as
power supply . Two types of DC power supply are
available in the market i.e. Switched mode power
supply & Linear power supply. SMPS is preferred over
Linear power supply by many customers as for same
power rating , SMPS is smaller, cheaper and lighter
than linear power supply especially transformer. The
high frequency switching transformer that is required in
SMPS is smaller and lighter than the transformer that is
required in linear power supply.Also the efficiency of
SMPS is better than Linear power supply. SMPS also
have better efficiency than linear power supply. In
Switch Mode Power Supply, Pulse Width Modulation
technique is used in control the closing and opening
switches. The on and off of the switch is important
because the duty cycles of the PWM is used to regulate
the DC output voltage .So the desire output voltage can
be produced by generate various duty cycle. So There is
compensation for changes in the input supply and
output load. Then the output voltage is compared to the
reference voltage which is accurately set and the error
voltage given by the comparator is used by dedicated
control logic to terminate the drive pulse to the main
power switches at the correct instance. This will provide
a very stable dc output supply if the circuit is designed
accurately. In this paper Linear PWM strategy for
SMPS is suggested . As for the smooth working of
Switch Mode Power Supply, Pulse Width modulation
Chip requires hyperbolic curve of nonlinear nature of
Input voltage & on time . The desired
hyperbolic curve of Nonlinear nature using the
existing PWM chip cannot obtained. So sometimes it
over compensates & sometimes it under compensate.
Which causes error in the DC output voltage?

II. BACKGROUND

The block diagram of S.M.P.S. shows that it is fairly
complicated circuit. shown in Fig. 1. (This
configuration assumes a 50/60Hz mains input supply is
used.) The ac supply drawn from the mains is rectified
first, and which is then filtered by the input reservoir
capacitor to produce a rough dc input supply. Due to
variations in the mains this level can fluctuate widely &
The capacitance on the input has tobe fairly large to
hold up the supply in case of a severe droop in the
mains . ( The supply is called a dc to dc converter When
the S.M.P.S. configured to operate from any suitable dc
input).The unregulated dc is given directly to the central
block of the supply, the high frequency power switching
section. Switching powersemiconductor devices such
asMOSFETs and Bipolar which are fast devices are
driven on and off, and switch the input voltage across
the primary of the power transformer. The frequency of
drive pulses are normally fixed (20 to 200kHz) and
variable duty cycle. Hence, on the transformer
secondaries a voltage pulse train ofsuitable magnitude
and duty ratio appears. Depending upon the topology
used, this voltage

pulse train is appropriately rectified, and then
smoothed by the output filter, which is either a
capacitor or capacitor / inductor arrangement . To
maintain efficiency, this power transfer has to be carried
out with the lowest losses possible. Thus, selection of
the correct power semiconductors and optimum design
of the passive and magnetic components is critical. To
provide a stabilised dc supply, regulation of the output
is carried out by the control / feedback block. Generally,
most S.M.P.S. systems worked on a fixed frequency
pulse width modulation basis, where the duration of the
on time of the drive to the power switch is varied on a
cycle by cycle basis. This compensates for variation in
the input supply and output load.Then the output
voltage is compared with the reference voltage of
comparator.An error voltage obtained from comparator
is used by control logic to terminate the drive pulse to
the main power switches at the correct instance. In this
way the Switched mode power supply works which
provide efficient use of power.

III. TOPOLOGIES OF SMPS

A. The Buck Converter

Fig. 2: Buck Converter

The forward converter family are all based on the
buck converter, which includes the push-pull and
bridge types, shown in Fig. 2. It has straightforward
operation . When switch TR1 will be turned on, the
input voltage is applied to inductor L1 and in the output
power is delivered. According to Faradays law
inductor current builds up. As pulsating input is
provided to LC filter , a smooth dc output voltage and
current, with very small ripple components is obtained.
If the circuit losses are neglected ,VinD is the average
voltage at the input side of the inductor & Vo is the
voltage at output side. Thus, for the average voltage
across the inductor to be zero, in the steady state ,
Simply the basic dc equation of the buck is :

D =
(1)

Where D is the duty cycle of transistor switch &
defined as on time devided by total time. In the buck
converter the output voltage is always less than input
voltage so it is step down type. As the duty cycle will
never become one. By varying the duty cycle of the
switch, Output voltage regulation is obtained. The
effective filtering of the inductor current is provided by
the LC arrangement. So in the buck & its derivatives
very low ripple charecterstics are observed.. Normally
the buck is always operated in continuous mode
( inductor current never falls to zero) where smoothing
capacitor requirements are smaller &also peak currents
are lower. In continuous buck ,no major control
problems are there.

B. The Boost Converter
Boost is again one of the the fundamental converter
which is more complex in nature than buck converter.
When the switch is on, Vin is applied across inductor
L1 & diode D1 becomes reverse biased & Current
building in the inductor to a peak value, either from
zero current in a discontinuous mode, or an initial value
in the continuous mode. The voltage across L1 reverses,
as soon as the switch turns off which causes the diode
voltage to rise above the input voltage. Then diode
conducts the energy stored that is in the inductor, plus
energy direct from the supply to the smoothing
capacitor and load . Hence, it is a step up converter as
Vo is always greater than Vin. The boost dc equation is
obtained by a similar process as for the buck in
continuous mode operation and is given below : In the
boost converter also the output depends only upon the
input and duty cycle. So the output regulation is
achieved by controlling the duty cycle.The boost
converter is used as capacitive load applications like
photo-flashers & battery chargers. Furthermore, the
Boost is popular choice as a pre-regulatordue to its
continuous input current that is placed before the main
converter. One of the main function is to improve the
power factor.

Fig.3 : Boost Converter

C. The Flyback Converter

The flyback converter is not derived solely from
the boost. The storedinductor energy delivered
by the flyback only during the switch off-time.
The boost, however, also delivers energy from the
input. The flyback is the combination of previous
two topologies , called the buck-boost or non
isolated flyback regulator. This topology is shown
in Fig. 4.


Step Up / down Polarity Inversion

Fig. 4: Buck-Boost Converter

Diode is reverse biased during the switch is on and
across the inductor the input is connected, which stores
energy. The inductor voltage reverses during turn off
and the stored energy is then passed to the capacitor and
load through the forward biased rectifier diode. Except
that the transistor switch now has to support the sum of
Vin and Vo across it, the waveforms are similar to that
of boost. Clearly, both the input and output currents
must be discontinuous. Polarity inversion is also present
& the output voltage generated is negative with respect
to the input. If we observe closely it reveals that the
dc transfer function in continuous mode is as shown
below :

(2)

It is found that the value of the switch duty ratio,D
can be selected such that the output voltage can either
be higher or lower than the input voltage. This provides
flexibility to the converter either to step up or step
down the supply. Like the boost ,this regulator also
suffers from the same continuous mode control
problems and discontinuous mode is usually favoured .
Since currents are pulsating in both input and output
low ripple levels are very difficult to obtain using them
buck-boost. Filter capacitors with very large output are
needed , typically up to 8 times that of a buck regulator.

SMPS With Linear PWM Technique :

The Basic equation required for Switch Mode Power
Supply is

V
T

(3)
Where , V
o
= Output Voltage ,
V
i
= Input Voltage ,
T
on
= On Time ,
T = Total Time

The existing SMPS requires hyperbolic curve of
nonlinear nature . But practically it is not possible to
obtain the required curve. So charecterstics of V
i
Vs.T
on

can be plotted using the equation given below :

T
(4)
The Plot of V
i
Vs. T
on
is shown below :

In this the nonlinear slope is obtained practically
using existing SMPS but it requires hyperbolic curve of
nonlinear nature for smooth working. As by this
chrecterstics sometimes it undercompensates &
sometimes overcompensates the inpun voltage. So there
is error in output voltage. So now we employe linear
PWM technique to SMPS in Which Integrator circuit is
used in place of PWM Chip. For that the considerations
are,

Vi*Ton = Constant (5)

So , Now Integrate Vi Over T.

V
dt
(6)
Where ,
= Time Constant of integrator

So,
V
(7)
Now, the linear charecterstics can be plotted as
shown below. By virtue of which when the input
voltage is compensated & the correct output voltage can
be obtained.

So using this technique , the efficiency of SMPS can
be improved.

IV. CONCLUSION

This paper presents a review of different topologies
that can be used for SMPS & the new Linear PWM
technique for SMPS is proposed. By using this
technique the efficiency of the SMPS can be increased
to great extent. So the ultimate goal of efficient use
electrical power can be achieved . The different types of
topologies can be used for different functions.

REFERENCE

[1]. J.Humphreys,C.J.Hammerton,D.Brown,R.Miller,L.Burley,
PowerSemiconductor Applications-Switched Mode Power
Supplies, Philips Semiconductors, Chapter 2, Hamburg,1994.
[2]. Mohd. Shahruddin Bin Harun, Design Switch Mode
Power Supply (SMPS) using Pulse Width Modulation
Controller Technique, Faculty of Electrical & Electronic
Engineering University Malaysia Pahang(UMP) ,November
2007.
[3]. Wei-Hsin Liao, Shun-Chung Wang and Yi-Hua Liu,
Generalized Simulation Model for a Switched-Mode Power
Supply Design Course Using MATLAB/SIMULINK,
Member, IEEE, 2011.
[4]. Texas Instrument, Transistor Circuit Design.
[5]. National Semiconductor, National Semiconductor Linear
Data Book.


Part III
ICCA 12
Volume 3
ISBN: 978-81-920575-6-9 :: doi: 10.73683/ISBN_0768
Design and Implementation of Low Power and Area Efficient adder and
Vedic Multiplier for FFT

D. Jaganathan M.E. (VLSI DESIGN), Dr . Rangarajan Dr. Sakunthala
Vel Tech Multi Tech Engg College,Avadi,Chennai.

Abstract - The ever increasing demand in enhancing the
ability of processors to handle the complex and challenging
processes Resulted in the integration of a number of processor
cores into one chip. This load is reduced by supplementing the
main processor with Co-Processor. The Fast Fourier
Transform (FFT) is a computationally intensive digital signal
processing (DSP) function widely used in application and the
speed of FFT depends greatly on the multiplier and adder.
Vedic Mathematics is the ancient system of mathematics which
has a unique technique of calculations based on 16 Sutras. It is
used for design a multiplier. Carry select adder (CSLA) is the
fastest adder used to perform an arithmetic functions. The
proposed design has reduced area and power as compared
with the regular Adders and Multipliers. This work evaluates
the performance of the proposed designs in terms of delay,
area, power.

Keywords FFT, CSLA,Vedic multiplier, low power, area
efficient.

I. INTRODUCTION
The increase in the popularity of portable systems
as well as the rapid growth of the power density in
integrated circuits have made power dissipation one
of the important design objectives, second thing area
& performance. So here the carry select adder and
Vedic multiplier are modified for reducing the above
factors. The Fast Fourier Transform (FFT) is a
computationally intensive digital signal processing
(DSP) function widely used in applications such as
imaging, software-defined radio, wireless
communication, instrumentation and machine
inspection. The choice of FFT sizes is decided by
different operation standards. It is desirable to make
the FFT size changeable according to the operation
environment. Achieving a successful design means
the system should be able to support different
operating modes required by diverse applications
with low power consumption requirement.
Based on the idea of sharing two adders used in
the Carry Select Adder (CSA), a new design of a
low-power high performance adder is presented. The
new adder is faster than a Ripple Carry Adder
(RCA), but slower than a CSA. On the other hand, its
area and power dissipation are smaller than those of a
CSA. In a typical processor, Multiplication is one of
the basic arithmetic operations and it requires
substantially more hardware resources and processing
time than addition and subtraction. In fact, 8.72% of
all the instruction in typical processing units is
multipliers. In computers, a typical central processing
unit devotes a considerable amount of processing
time in implementing arithmetic operations,
particularly multiplication operations. In this paper,
comparative study of different multipliers is done for
low power requirement and high speed. The paper
gives information of Urdhva Tiryakbhyam
algorithm of Ancient Indian Vedic Mathematics
which is utilized for multiplication to improve the
speed, area parameters of multipliers. Vedic
Mathematics also suggests more formulae for
multiplication i.e. Nikhilam Sutra which can
increase the speed of multiplier by reducing the
number of iterations.
The paper gives information of Urdhva
Tiryakbhyam algorithm of Ancient Indian Vedic
Mathematics which is utilized for multiplication to
improve the speed, area parameters of multipliers.
Vedic Mathematics also suggests more formulae for
multiplication i.e. Nikhilam Sutra which can
increase the speed of multiplier by reducing the
number of iterations. Increasingly huge data sets and
the need for low power in adders tend to increase.
The traditional serial adders are no longer suitable
for large adders because of its huge area and high
power. All systems tends to trade off between speed
and power. The computation time taken by the
array multiplier is comparatively less. because the
partial p
parallel.
multiplier
propagate
multiplica
for high
operation
partial ca
adder de
designed
I. CA
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data path
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work is to use
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Fig
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calculated i
associated
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In this paper
128-bit and
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not further
but, all the
verhead for pr
er many desig
gn overhead,
addressed fo
BEC with 8:4 m
G VEDIC
is of immense
sing (dsp)
nt the hardwar
tion (dft), disc
e sine transform
communicati
multipliers are
ation is perfo
ations and tw
r processing,
east significan
msb) when bi
efore, the ad
multiplications
ative method
ex number m
on based impl
sing offset
cordic (coordin
m , the quadr
d recently, th
ns) .
a technique f
where the
used. this
eal multiplica
as compared t
left to right ar
reported in 20
extended fo
above techniq
re/postprocess
gn issues lik
power consum
or fast multipl
mux
e importance
and image
re module of
crete cosine
mation (dst)
ions; large
e required.
ormed using
o additions/
carry needs
nt bit (lsb) to
nary partial
ddition and
s limit the
had so far
multiplication
lementation,
binary and
nate rotation
ratic residue
e redundant
for complex
algebraic
algebraic
ation, at the
to the direct
rray for the
005, and the
or complex
ques require
sing or long
ke as speed,
mption etc.,
lication . in

algorithm
multiplica
enhance
encounter
and/or the
but the p
all cases.
vedic
Indian ma
calculatio
tiryakbyh
crosswise
multiplica
also a sa
from 10
multiplica
adopted f
this wor
designing
transistor
i) simplic
implemen
propagati
mehta et
using "u
adopted f
sutra is s
which als
multiplier
dasatah"
2009, bu
module fo
in the gat
already
knowledg
level (a
multiplier
By em
complex
four mult
the fina
dasatah"
with less
compariso
compared
method o
approach
operation
the mul
configura
be elabo
perfonnan
dynamic
power c
method w
standard
mic and str
ation techniq
the efficienc
rs the reduc
e methods for
principle behin
c mathematic
athematics wh
ons based on
ham" is a sans
e formula is
ation. "nikhil
anskrit term in
0", formula
ation and subt
from ancient
rk we form
g the comple
r level with tw
city and modu
ntations and
ion for rapid
al. have been
urdhva-tiryakb
from the veda
similar to the
so indicating t
r design usin
sutras has be
ut he has no
for multiplicat
te level (fpga)
been reporte
ge till date th
asic) implem
r.
mploying the
number multi
tiplications fo
al product.
sutra is used
number of p
on with array
d with existin
or the streng
resulted not
ns, but also in
tiplier is fu
ation of input
rated. transis
nce parameter
leakage pow
onsumption
was calculated
cmos techno
ructural leve
ques had bee
cy of the m
tion of the
their partial p
nd multiplicat
cs is the an
hich has a uni
16 sutras (for
krit word mea
s used for
am navatasca
ndicating "all
is used for
traction. all th
indian vedic
mulate this m
ex multiplier
wo clear goals
ularity multip
ii) the elim
d additions a
n proposed a
byham" sutra
as. the formu
e modem arra
the carry prop
ng "nikhilam
een reported b
ot implemente
ion. multiplie
) using vedic
ed but to th
here is no rep
mentation of
vedic mathe
iplication was
or real and im
"nikhilam
for the multip
partial produc
y based mult
ng methods su
gth reduction
only in simp
n a regular ar
ully paramet
and output wo
stor level imp
rs such as pr
wer and dyn
calculation o
d by spice spe
ology and com
els, a lot
en developed
multiplier; wh
partial produ
products additi
tion was same
cient system
ique technique
rmulae). "urdh
ans vertically
smaller num
aramam dasat
from 9 and
r large num
hese formulas
mathematics
mathematics
r architecture
in mind such
plications for
ination of ca
and subtractio
multiplier des
as, which w
ulation using
ay multiplicati
pagation issue
navatascaram
by tiwariet. a
ed the hardw
r implementat
mathematics
he best of
port on transi
such comp
ematics, an n
transformed i
maginary terms
navatascaram
plication purpo
cts generation
tiplication. w
uch as the dir
n technique,
plified arithm
rraylike structu
terized, so
ord-lengths co
plementation
ropagation de
namic switch
of the propo
ctre using 90
mpared with
of
d to
hich
ucts
ion,
e in
of
e of
hva-
and
mber
tah"
last
mber
are
. in
for
in
h as:
vlsi
arry
ons.
sign
was
this
ion,
es. a
mam
al in
ware
tion
has
our
stor
plex
bit
into
s of
mam
ose,
n, in
when
rect
our
metic
ure.
any
ould
for
lay,
hing
osed
nm
the
o
b
b
(
p
s
o
n
fo
c
m
g
m
a
m
m
le
b
a
w
m
1
it
la
m
w
g
F
tw
fr
w
other design lik
based implem
based impleme
16,16) x(16
propagation de
witching pow
on "urdhva
navatascarama
fonnulas are be
A. "URDH
The mean
crosswise" an
multiplication
general mult
multiplication.
array multipli
multiplication
multiplicand l
ength multipl
because a larg
are involved in
we are describ
multiplication
Figure
"U
B. NIKHIL
Nikhilam
10. It is also a
t is more effi
arge. We will
multiplication
where the chos
greater than b
Fig. 5, we writ
wo rows follo
from the chose
write two colu
ke distributed
mentation and
entation. the c
6,16) comp
elay only 4ns
wer.In this pap
a-tiryakbyham
am dasatah"
eyond the scop
HVA-TIRYAK
ing of this
nd it is
operations.
tiplication pr
this procedu
cation techni
technique w
lengths are sm
lication this t
ge amount of
n these cases.
bing nikhilam
of two larger n
e 3 Multiplica
Urdhva-Tiryakb
LAM SUTRA
Sutra means
applicable to a
icient when th
illustrate this
of two decim
sen base is 10
both these two
te the multipli
owed by the di
en base, i.e., th
umns of numb
arithmetic, pa
algebraic tra
calculated resu
plex multip
s with 6.5 m
per we are co
m", and
formulas
pe of this pape
KBYHAM " SU
sutra is "ver
applicable t
Figure repr
rocedure of
ure is simply
ique . it is a
when the mu
mall, but for
technique is n
carry propaga
to overcome t
m sutra for cal
numbers.

ation procedur
byham " sutra
all from 9 an
all cases of mu
he numbers in
s Sutra by con
mal numbers
00 which is ne
o numbers. A
er and the mu
ifferences of e
heir complime
bers, one consi
arallel adder
ansfonnation
ults revealed
plier have
mw dynamic
oncentrating
"nikhilam
and other
er.
UTRA
rtically and
o all the
resents the
f the 4x4
y known as
an efficient
ultiplier and
r the larger
not suitable
ation delays
this problem
culating the
re using
a
nd last from
ultiplication;
nvolved are
nsidering the
(96 93)
earest to and
As shown in
ultiplicand in
each of them
ents. We can
isting of the
numbers
consisting
product
distribute
product w
numbers
side of th
the secon
number o
93 - 4=8
combinin

The in
as well a
integrated
of the im
performan
widely u
designing
research i

to be multipl
g of their co
also consists
ed by a vertic
will be obtain
of the Colum
he product will
nd number o
of Column 1 or
89. The fina
ng RHS and LH
Figure 4. Nik
III. PROP
CARRY S
ncrease in the
as the rapid gr
d circuits hav
mportant desig
nce. Because
used compon
g efficient add
in VLSI desig
lied (Column
ompliments (C
s of two p
cal line right
ned by simply
mn 2 (74 = 2
l be found by
of Column 2
r vice versa, i
l result will
HS (Answer =
khilam Sutra Mu
POSED FFT D

ELECT ADD
popularity of
rowth of the
e made powe
gn objectives,
adders are o
nents in int
ders has been
gn. The saying
1) and the ot
Column 2). T
parts which
hand side of
y multiplying
8). The left h
cross subtract
2 from the f
.e., 96 - 7 = 89
be obtained
= 8928).
ultiplication
DESIGN
DER
f portable syste
power density
er dissipation
second area
one of the m
egrated circu
the goal of m
g goes that if y
ther
The
are
the
the
hand
ting
first
9 or
by

ems
y in
one
a &
most
uits,
much
you
c
o
p
o
th
a
b
o
d
d
b
s
b
la
th
lo
n
(R
a
C
m
a
ti
(
th
(n
b
R
b
c
A
e
a
in
b
th
u
w
C
a
p
c
a
c
c
b
p
can count, you
operation for
processing or
operation of a
he performan
also very imp
because of the
operations suc
division. Hen
digital adder w
binary operati
uch blocks.
block is gauge
ayout area and

Based on t
he Carry Sele
ow-power hig
new adder is
RCA), but slo
area and power
CSA. While R
most compact
adders, they a
ime). On the
CLAs) are th
hey are the w
(nlog (n)) area
been considere
RCAs and CL
because they
compact area o
As a result, som
efficiency of t
area efficient a
ncrement circ
blocks which a
he idea of sha
used in the C
which is more
CSA.
Carry sele
adders used in
perform fast ar
csla, it is clea
area and power
csla adder con
can compute ti
block the pro
power as comp
u can control. A
any digital
control syste
digital system
nce of the res
portant compo
eir extensive u
ch as subtrac
nce, improvin
would greatly
ions inside a
The performa
ed by analyzi
d its operating
the idea of sh
ect Adder (C
gh performanc
s faster than
ower than a CS
r dissipation a
Ripple Carry A
design (O (n)
are the slowes
other hand, C
he fastest adde
worst from th
a). Carry Sel
ed as a comp
LAs (O (n)
offer a goo
of RCAs and
me effort has
this kind of a
adder has been
cuit instead o
add high bits.
aring the two
CSA, a new
e compact and
ct adder (csl
n many data-
rithmetic func
ar that there i
r consumption
nsists of a bin
ill 128 bits wh
oposed design
pared with the
Addition is a f
system, dig
em. A fast an
m is greatly in
ident adders.
onent in digi
use in other b
ction, multipl
ng performan
advance the e
circuit comp
ance of a dig
ing its power
g speed.
haring two add
CSA), a new
ce adder is pre
a Ripple C
SA. On the oth
are smaller tha
Adders (RCA
) area) among
st types of ad
Carry Look-ah
ers (O (log (n
he area point
ect Adders (C
promise soluti
time and O
od tradeoff b
the short dela
been done to
adder. In for e
n proposed wh
of one of the
In this researc
adders that a
architecture i
d power effici
la) is one of
-processing pr
ctions. the stru
is scope for r
n in the csla. th
nary to excess
hich replaces
n has reduce
regular sqrt c
fundamental
gital signal
nd accurate
nfluenced by
Adders are
ital systems
basic digital
lication and
nce of the
execution of
promised of
gital circuit
dissipation,
ders used in
design of a
esented. The
Carry Adder
her hand, its
an those of a
As) have the
all types of
dders (O (n)
head Adders
n) time), but
of view (O
CSAs) have
ion between
(2n) area)
between the
ay of CLAs.
improve the
example, an
hich uses an
e two adder
ch, based on
are typically
is proposed
ent than the
f the fastest
rocessors to
ucture of the
reducing the
he proposed
code and it
existing rca
ed area and
csla.

VEDI
The p
vedic mu
have been
two numb
work, app
system to
with the d

IC MULTIPLI
proposed vedi
ultiplication fo
n traditionally
bers in the de
plying the sam
o make the p
digital hardwa
IER
ic multiplier
formulae (sutr
y used for the
ecimal numbe
me ideas to th
proposed algor
are.

Reg
16-B
is based on
ras). these su
multiplication
er system. In
he binary num
rithm compat

gular 16-b SQR

BIT MODIFIE
the
utras
n of
this
mber
tible
c
p
a
RT CSLA.
ED CSLA
1.
2.
The propo
complex multi
paper I am wo
and 32
urdhva tiry
nikhilam s
osed multipli
iplier for inte
orking with 1
bit

yakbayam sutr
sutra
ier is used
ense a+ib * c
28 bit carry
of

ra
to build a
c+id. In this
select adder
multiplier.

Suppo
We m
answer. T

1

ose we have to
(i
digit
answ
(i
down
multiply 2 and
Thus 12 x 13 =

Step 1
1 3
Pe
2

R0=A0B0
o multiply 12 b
i) We multi
1 of the mul
wer
ii) We then m
n as the middle
3 vertically, g
= 156. It bears

Result
erv.Carry =
1
6
Steps involve
by 13
iply the most
ltiplier, get th
multiply 1 and
e part of the an
get 6 as their p
a simple exte

t = 6 1
= 0
1 2

Example o
6

ed in Urdhva T
significant di
eir product 1
d 3, and 1 and
nswer and
product and p
endible form in

Step 2
3 R
Perv.C

5 6
of Urdhva Tiry
Tiryakbayam
igit 1 of mult
and set it do
d 2 crosswise,
put it down as
n a similar way

Result = 5
Carry = 0
1
ryakbayam Sut
5
Sutra
tiplicand verti
own as the mo
add the two, g
the last the ri
y for multi-dig

S
5 1
P
2
1
tra

ically by most
ost significant
get 5 as the su
ight hand mos
git multiplicat

Step 3
3 Resu
Prev.Carry
1 5 6
t significant
t part of the
um and set it
st part of the
tion.
ult = 1
y = 0
1

C

C1R1=A0B
C2R2=C1+
C3R3=C2+
C4R4=C3+
C5R5=C4+
C6R6=C5+
C7R7=C6+
C8R8=C7+
C9R9=C8+
C10R10=C
C11R11=C
C12R12=C
C13R13=C
C14R14=C
C14R14R13R
CO
B1+A1B0
+A0B2+A2B0
+A3B0+A0B3
+A4B0+A0B4
+A5B0+A0B5
+A6B0+A0B6
+A7B0+A0B7
+A7B1+A1B7
+A7B2+A2B7
C9+A7B3+A3
C10+A7B4+A
C11+A7B5+A
C12+A7B6+A
C13+A7B7
R12R11R10R9
ONCLUSION
0+A1B1
3+A1B2+A2B
4+A3B1+A1B
5+A4B1+A1B
6+A5B1+A1B
7+A6B1+A1B
7+A6B2+A2B
7+A6B3+A3B
3B7+A6B4+A
A4B7+A6B5+A
A5B7+A6B6
A6B7
9R8R7R6R5R
Gener
N
B1
B3+A2B2
B4+A3B2+A2
B5+A4B2+A2
B6+A5B2+A2
B6+A5B3+A3
B6+A5B4 +A4
A4B6+A5B5
A5B6
R4R3R2R1R0 b

ral Mathemati
2B3
2B4 +A3B3
2B5 +A4B3+A
3B5+A4B4
4B5
being the fina
ical Formula

A3B4
l product.

A simple approach is proposed in this paper to
reduce the area and power of SQRT CSLA
architecture. The reduced number of gates of this
work offers the great advantage in the reduction of
area and also the total power. design of the modified
128-b SQRT CSLA proposed. The modified CSLA
architecture is therefore, low area, low power, simple
and efficient for VLSI hardware implementation.
Similarly the

multiplier is modify for 32-bit by using vedic
multiplier.

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Grid Resource Management Based On Agent Grouping
Arun Prakash.T
Department of Information Technology
B S Abdur Rahman University
Chennai, India

Abstract: A key challenge in Grid computing is the
achievement of efficient and self-organized resource
management. Grids are often large scale, heterogeneous, and
unpredictable systems. Introducing group structures can
help to distribute coordination efforts, but higher levels of
adaptation and learning in the coordination protocols are
still required in order to cope with system complexity. We
provide a solution based on a self organized and emergent
mechanism evolving congregations of resource management
agents through a Group Selection process which maximizes
utility outcomes for system-wide performance. We provide a
formalization of this process into a Group Selection pattern,
and we propose several instantiations optimizing Grid
resource management scenarios such as adaptive job
scheduling, market-based resource management, and policy
coordination in Virtual Organizations (VOs). We further
evaluate by simulation the performance of the mechanism in
those scenarios. The results support the conclusion that
Group Selection optimizes coordination by evolving small
and dynamic groups.
Keyword: Grid computing, Agent, group selection,
resource management

I. INTRODUCTION
The popularity of Grids has been growing very
rapidly, driven by the promise that they will enable
knowledge and computing resources to be
delivered to and used by citizens and organizations as
traditional utilities or in novel forms. Contrarily to other
distributed systems, Grids have many independent
resource providers with varying resource characteristics
and availability. In addition to large sizes, the dynamicity
of resources leads to a very complex coordination task
that cannot be handled manually by users. Automatic and
adaptive resource management is proposed as a solution
to these challenges. To that aim, the potential synergies
between Grids and multi-agent systems (MAS) have been

outlined. Among others, MAS have exploited group
structure to partition the population in interaction groups,
heavily impacting the coordination.
Group Selection refers to a process of natural selection
that favors characteristics in individuals that increase the
fitness of the group the individuals belong relative to
other groups. Group Selection implies that every member
of the group depends on a group characteristic that is not
isolated in a single individual. Such groups form isolated
niches where the sub-populations are allowed to evolve
behaviors independently of the rest of the populations.
The existence of niches maintains a large diversity in an
evolving population since the evolutionary paths in
separated nichs may develop in entirely eifferent ways.
This evolutionary process can promote the evolution of
individual agents characteristics benefiting the group the
agent belongs to. In several coordination scenarios, inter-
agents miss-coordination (due to ignorance, high
complexity, or other reasons) might be leading to very
suboptimal social welfare outcomes. Group Selection
guides the co-evolution of group-structured systems to
optimized configurations.
In this paper, we provide a decentralized coordination
mechanism for Grid resource management based on
Group Selection. We distribute the agents in groups.
Further agents group migrations through a Group
Selection process improve the overall population
performance. We propose formalization into an
engineering pattern and we show by simulation how it
performs optimizing several resource management tasks
in Grids: learning agents for adaptive job scheduling,
bargaining agents in a market-based resource allocation,
and policy coordination in VOs.

II. STATE OF THE ART IN MAS BASED GRID
RESOURCE MANAGEMENT
We detail in this section the state of the art in MAS
based Grid resource management mechanisms, leaving
for the next section the state of the art in group formation
mechanism in MAS and a comparison to the Group
Selection mechanism.
Conventional solutions in Grid resource management
apply manual management or, at most, centralized
mechanisms ensuring a predictable outcome. This
normally leads to important scalability limitations due to

ISBN: 978-81-920575-6-9 :: doi: 10. 73690/ISBN_0768
increased manual and computational costs, as well as
limited tolerance to changes or failure (human operators
and centralized management offer a single failure point in
the system). In Grid scheduling, conventional parallel
computer schedulers, such as PBS and LSF, address the
scheduling problem by implementing a synchronous
schedule/enactment process. The scheduling algorithm
has full knowledge of the resource properties. This
solution is not appropriate in a federated environment
where no central entity has sole authority over local
resource states. The Condor high-throughput system
avoids this problem by providing almost no delivery
guarantees; a centralized matchmaker makes simple
greedy decisions to place jobs and simply retries when it
encounters resource states in conflict with its internal
view of the environment. The Pegasus Grid workflow
mapping system includes a random job placement
behavior to spread small parts of an overall workflow into
Grid resources.
Coordination is an important topic in large scale Grid
systems management. In, different coordination
mechanisms for Grids are evaluated. From lower to
higher level, the following mechanisms are proposed:
scripting languages, shared-data spaces and middleware
agents, the later being identified as the more flexible.
However none of these solutions incorporate the notion of
self-organization capturing systems dynamics as our
mechanism does. A comprehensive survey on self-
organizing agent-based and autonomic computing
applications in Grid Computing is presented in. Market
based resource allocation has received a great deal of
attention in the last years. The GridBus Project is a
reference in Grid Economy and utility based computing,
and has proposed a great variety of market models and
tools for the trading of Grid Resources. However, its
strong emphasis on computational intensive Grids and the
hierarchical nature of some of the proposed components,
like the Grid Market Directory, diverges from the fully
decentralized resource allocation mechanisms used here.
Other centralized approaches exist such as, but scalability
issues both in size and computational requirements further
complicate its applicability to large size Grids. Tycoon is
a market-based system for managing compute resources
in distributed clusters or Grids. It uses distributed auctions
with users having a limited amount of credits. Users who
provide resources can, in turn, spend their earnings to use
resources later. A fully decentralized approach is the one
adopted with the catallactic agents. In this approach,
bilateral negotiations are established between learning
agents, and the spontaneous price coordination arises
from both the bargaining and co-evolutionary learning
processes. However, the bootstrapping and evolution of
these bargaining agents in markets is an open issue.
Grids environments are being organized in VOs,
associating heterogeneous users and resource providers to
coordinate resource sharing; a set of individuals and/or
institutions defined by their sharing rules form a Virtual
Organization. There are many projects using VOs
conceptually, but very few projects are addressing the
management of VOs themselves in Grids. While the
notion of a VO seems to be intuitive and natural, we still
lack well-defined procedures for deciding when a new
VO should be formed, who should be in that VO, what
they should do, when the VO should be changed, and
when the VO should ultimately be disbanded. In Conoise-
G project an agent system supporting robust and resilient
VOs formation and operation is presented. Another
project focusing on Trust issues is Trustcom aiming to
provide a trust and contract management framework
enabling the definition and secure enactment of
collaborative business processes within VOs that are
formed on-demand, self managing and evolve
dynamically. In both Conoise-G and Trustcom
approaches to VO management, components for helping
automated VO management are developed.

III. STATE OF THE ART IN GROUP FORMATION
MECHANISMS FOR MAS
Exploiting group structure in MAS has been proposed
in previous research. It is acknowledged that, in general,
there is no single type of organizational paradigm that is
suitable for all situations. Some claim that there is not
even perfect organization in any situation, due to the
inevitable tradeoffs that must be made and the
uncertainty, lack of global coherence and dynamics
present in any realistic population. In hierarchies the data
produced by lower level agents travels upwards to provide
a broader view, while control flows downwards as the
higher level agents provide direction to those below.
Holarchies follow a very similar pattern, but typically
include homogeneous, self-similar elements at each
hierarchical level, and the constituents of each group are
partially-autonomous.
Coalitions are formed by subsets of the population,
and in general are goal oriented and short-lived.
Coalitions have been studied in game theory community
for decades, and can be composed of both cooperative and
self-interested agents. Most of the coalition formation
literature attempt to formalize optimal grouping
mechanism for agents populations. Major limitations of
these algorithms are a high computational complexity,
and unrealistic assumptions regarding the availability of
information. Not being super-additive (the value of
unified coalitions is not necessarily greater than the sum
of the composing coalitions), markets are a very
demanding scenario for state of the art coalition

algorithms. These issues prevent practical usage of these
mechanisms in large scale scenarios such as Grids. In
contrast, Group Selection implies few or no
computational costs.
An alternative group formation mechanisms proposed
in MAS research is congregations. Congregations are
subgroups in the agent population which have a defined
purpose and organizational cost, though still releasing the
full autonomy to agents. They are applied to electronic
markets. They are proved to serve as market optimizers.
However, we identify an important limitation in the
congregation models proposed. Groups are static and
agents can trade in just a specified number of subgroups.
In contrary, Group Selection approaches enable a
dynamic view of the system, evolving the required
number of subgroups depending on the changing agents
requirements.
An important drawback in all of the group formation
mechanisms presented so far is that the dynamical view of
the system is not addressed. Normally the optimal groups
are calculated at some computational costs, and entering
in a new domain application requires a complete
recalculation of groupings from scratch. An exception to
this rule is the work, where iterative formation of multiple
coalitions is attempted in response to a dynamic task
environment. In general, the proposed solutions address
the calculation of optimal groups centrally, supposing
complete system knowledge to the central coalition-
maker, with few exceptions. This panorama contrast with
realistic present day large scale distributed systems, where
small, decentralized components need to deal
autonomously with coordinated decision making.
Group Selection is a fully decentralized mechanism
which focuses on the dynamic view of the groups,
iteratively ruling its evolution towards more optimal
configurations. It has been shown that Group Selection
can lead to the spread of group beneficial characteristics
in many different grouped settings of agents populations.
This enables the application of Group Selection processes
in any group-like structured agent population.
Applications of Group Selection have appeared in biology
and sociology and also in economic theory. In
engineering, novel socially-inspired mechanism have
been developed building to some extent on Group
Selection processes. These mechanisms use a tag (or
social label) to identify groups. Agents interactions are
biased by Tags (i.e. within the groups) and inter-group
migrations are ruled by Group Selection processes. This
has been demonstrated most notably in the
application to free-riding prevention in Peer-to-Peer
networks by Hales. Also other applications build on Tag
mechanisms such as query routing and processing for
Peer-to-Peer web search. Table I compares Group
Selection with the rest of group formation mechanism
reviewed. It can be seen that Group Selection potentially
addresses several important issues in existent group
formation mechanisms.

IV. GROUP SELECTION PATTERN
A. SOFTWARE PATTERNS
a. software engineering design pattern is a general
repeatable solution to a commonly occurring problem in
software design. This is a description or template for how
to solve a problem that can be used in many different
situations. Software patterns have their roots in
Christopher Alexanders work in architecture. He
proposed a design pattern as a three-part rule that
expresses a relation between a certain context, problem
and solution. A good pattern provides more than just the
details of these sections; it should also be generative.
Patterns are not solutions; rather patterns generate
solutions.
Software patterns became popular after the publication
of the classic book by Gamma et al. The documentation
for a design pattern should contain enough information
about the problem that the pattern addresses, the context
in which it is used, and the suggested solution. Patterns
allow developers to communicate using well-known, well
understood names for software interactions. Common
design patterns can be improved over time, making them
more robust than ad-hoc designs.
MECHANISM BENEFITS DRAWBACKS APP TO GRIDS
Hierarchies

Maps many domains;
predictable
Centralized, tends to static;
bottlenecks
Globus MDS
Holarchies Autonomy Lack of predictability in
holons organization
Holonic VO management
Coalitions Goal-oriented, potentially
optimal

Formation can be costly;
prevents applications in very
dynamic settings
A few research papers
Congregations Long lived, utility directed;
modular; can be plugged with
others (e.g. markets)
Groups may be restrictive;
restricted dynamics

To electronic markets
Group Selection Dynamic view, evolves system
towards optimal outcomes;
scalable; very generic process,
complements others

Potentially ever-evolving
suboptimal allocations;
unpredictability; needs to be
engineered as an emergent
coordination mechanism
-

Software engineering design patterns have also been
introduced in MAS, including blackboard, meeting,
master and slave, market-maker and others. Pattern
languages can help a developer to build entire MAS. For
example, an individual pattern can help also in designing
a specific aspect of an agent, such as how it models its
beliefs, but a pattern language can help to use
those beliefs to build agents that plan and learn by
putting individual patterns into context.
However, an important drawback of current software
design patterns is that their application to large and
decentralized systems suffers from manageability and
scalability issues. Blackboards, master and slave, market-
maker and other common patterns imply centralization of
agents activities. This poses strong limitations to system
scalability. As a proposed solution, engineers have started
to build on bottom up approaches to develop emergent
and self-organized design patterns.
Patterns in computer science have also been used from
other disciplines. A relevant case is for bio-inspired
computing .They state in order to motivate the proposal of
a family of design patterns coming from biology: The
motivation of the present work is that large-scale and
dynamic distributed systems have strong similarities to
some of the biological environments. This makes it
possible to abstract away design patterns from biological
systems and to apply them in distributed systems. In other
words, we do not wish to extract design patterns from
software engineering practice as it is normally done.
Instead, we wish to extract design patterns from biology,
and we argue that they can be applied fruitfully in
distributed systems. Another field which has inspired
several software design patterns is sociology.
Since Grids are naturally composed in VOs, a basic
group unit already exists. The Group Selection process
operates through natural selection in several group-
structured systems in nature: biological systems (evolving
group-advantageous behaviors); humans societies
(promoting high levels of cooperation); and economies
(promoting the emergence of leading firms). We want to
build on these good properties of the mechanism to port
the Group Selection process to an engineering pattern
usable in large scale distributed systems amenable to
group structure, such as Grids.

B. GROUP SELECTION PATTERN
Building on the experience gained by Babaoglu et al.,
we describe the following attributes for our Group
Selection pattern: name, context, problem, forces,
solution, example, and finally, design rationale. The
meaning of these attributes should be self-explanatory,
except perhaps in the case of context. The context is
defined by the system model: the participants, their
capabilities and the constraints on the way they can
interact. Our system model is a Grid composed of N
agents, structured as a variable number of groups or VOs.
Each agent maintains an action, strategy, or policy
(depending on the scenario considered) to take resource
management decisions. This property, together with group
membership, can be evolved continuously by the Group
Selection process.

Name: Group Selection pattern in MAS
Context: The basic units of the model are agents. The
population of agents is structured into functional groups.
These groups compose a very dynamic environment in
which agents may enter and leave continuously.
Problem: I want to engineer a system composed of N
agents. The structure in which these entities can be
arranged in the system is a free design parameter, and the
movement of entities from one structure to another should
not be constraint. In open MAS, the definition of an
optimal structure can be ruined at any time by the
entrance of new agents in the system. As a result of this,
self-organized emergence of the properties is a good-to-
have characteristic.
b.Forces: Entities in the system should keep the
highest autonomy level possible. Coordination
optimization should be as controllable from the
designer point of view as possible. These two forces
compose a classical dilemma when engineering self-
organizing systems.
c.Solution: By organizing the agent interaction in
subgroups, which are dynamically created, desired values
for the macroscopic variables (cooperation, coordination,
stability)can emerge from agents co-evolution in the
groups, modeled as interaction and migration phases. The
group structure determines the interaction scope of the
agents. The dynamic view considers the migration of
agents from group to group, potentially implying the
change of agent properties by evolutionary learning, i.e.,
fitness based learning. This process self-organizes into
group level selection where groups performing well
survive and groups with agents implementing poor
coordination strategies die out.
Examples: In a Grid environment the agents become
Grid users or Grid service providers. An example of
cooperative setting is job scheduling in a pool of Grid
resources by a set of decentralized co-schedulers. Another
example is a set of agents coordinating their resource
management policies in the VOs they form.
Design rationale: We provide an algorithmic approach
to the pattern which can be instantiated in different
flavours by simple variation of Interaction and
Migration rules.
The implementation of the Group Selection pattern is
depicted in Fig. 1. In the left side, we see the flowchart
for an individual agent. First, the agent performs in the
scope of its group an interaction phase (dependent on the
domain of application), which can be for example a job
submission, an economic resource allocation, or a

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and job scheduling, as well as policy coordination in Vos.
Given a general Group Selection pattern for structured
MAS, various applications to Grid Computing scenarios
are possible; regardless of how utilities are derived in
interaction phase or how migration phase is performed,
the important thing to keep inside the pattern is that
both phases must be present. By varying interaction and
migration rules we get different instantiations of the
Group Selection pattern, producing different coordination
mechanisms. We instantiate the pattern in three different
flavors accounting for applications in three Grid resource
management scenarios: adaptive job scheduling,
economic-based resource allocation based on bargaining
agents and coordination of resource management policies
in VOs.
The pattern is instantiated basically in two classes or
modalities, depending on the type of property to be
affected by the Group Selection process. The first class
consists in putting together compatible agents, without
the need of modifying their properties (actions, strategies,
etc). In this case the property being evolved is nothing but
the presence in a group. The disposition of agents in the
convenient group is what gives the agent competitive
advantage compared to agents in other groups. We show
this modality in the application to adaptive learning
schedulers, which get their learning spaces changed as a
result of new group memberships, but no strategy is
changed due to group selection. The second class of
instantiation also transmits group beneficial
characteristics. The evolution of specific agents
characteristics is managed upon migration phase by the
copy of characteristics of agents from other groups which
might be outperforming current agent utilities. We show
this modality in the Grid markets segmentation
application, when negotiation types are modified when
changing groups, with Group Selection promoting the
copy of outperforming agents type in the new group. A
similar case happens for policy coordination in VOs, with
successful resource sharing policies being imitated by
agents joining new groups.
For the three scenarios, we provide a baseline which
does not use inter-group migrations based on utilities.
These baselines are extracted from state of the art Grid
resource management. In Table II, we show how the
Group Selection optimization compares to each baseline
mechanism, and what the optimization consists of.
All the experiments in the next subsections are
conducted in an open source, generic agent-based Grid
simulator specifically built for developing agent
coordination mechanism on top of Grids. The simulator is
implemented in java, on top of a MAS discrete event
simulator, Repast. The agent based Grid simulator
leverages the excellent analysis tools of Repast and its
core, and adds a Grid model and an Agent Framework,
focusing on the development of agents for the
coordination of Grid activities. The models explained in
this paper are included as scenarios for the Grid simulator
and its source code can be inspected. The experiments are
fully repeatable by downloading the simulator in the
provided URL. We base our results here in single
simulations, without averaging over multiple runs. We
show here only sample executions of the simulations, but
we have obtained the same results on multiple runs,
confirming its validity. We refer also to prior work on
Group Selection mechanisms with averaged results over
multiple runs.

SCENARIO BASELINE (state of the
art)
GROUP SELECTION OPTIMIZATION
Adaptive job scheduling

Flat population of
adaptive job schedulers
Evolves groups of
adaptive Job schedulers. The
mechanism evolve group
memberships
Schedulers learning spaces
are shorter and converge
Quicker. System load
decreases
Market-based resource
allocation

Flat decentralized market
of bargaining agents
Evolves market segments
from the flat market. The
mechanism evolve group
memberships & negotiation
types
Increases social welfare
derived from allocation utility.
Outperforms alternatives in job
scheduling
Coordination of resource
management policies in VOs

Static VO policies with
rule-based policy management
Dynamic VOs evolved
through Group Selection. The
mechanism evolve VO agents
memberships & agents
policies
Increased coordination
trough adaptive policy
management

VI. GROUP SELECTION FOR ADAPTIVE
DISTRIBUTED GRID SCHEDULING
The adaptive Grid scheduling model builds on
Reinforcement learning (RL). RL is learning from
interaction with the environment, from the consequences
of action, rather than from explicit teaching. The general
goal of RL is to find a policy mapping observations
(which might be states) to actions which maximizes
expected reward over multiple time steps. RL has been
widely studied in agent theory, mostly in settings with one
learner in a static environment. Porting these successful
early results to MAS settings has proven a very difficult
and controversial as pointed out by researchers in the
domain.
Galstyans model of adaptive distributed Grid
scheduling is our first baseline. It applies RL to a flat
population of independent job co-schedulers. An

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move between
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performance o
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ome variabili
mplying the c
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new job submi
ate on each sim
he higher the t
both fixed size
n abstract pro
ms clearly rand
e with stocha
r the noise in
actual resourc
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w consider an
tern (depicted
y select the nex
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out resources
this segment
hrough a redu
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e. Agent mig
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to that group
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s take the follo
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ble (update Q
the set of res
he next job wil
tion rule: Ag
n groups depe
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hat is, compar
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outperforming
n is applied wi
ity is added tr
reation of a br
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ission is perfo
mulation tick.
task load on th
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astic reward
the reward in
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the previous p
optimization u
d in Fig. 2).
xt resource fro
p. This means
on their cur
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uced learning
.e., we partitio
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tiation, the RL
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sources in the
ll be submitted
gents (with
ending on the
ups with agent
re my own per
ent in a differe
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ith a migration
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rand new grou
act processing
ormed in each
The higher th
he resources. J
iable sizes (10
er required uni
n mechanism. R
information,
nformation is d
in reporting.
paragraph is o
using the Gro
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om the resourc
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rrent group. T
boost Q-tab
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by applying
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ee which value
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migration pro
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the extent to
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oduce variabil
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arting a group
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that, for a fix
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s generated
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less for groupi
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to 0.5 leads
urther increasi
mprovements a
is provoked
eter, namely t
lation. This hi
ows that a hi
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his migration
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nd adapt easier
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ion
ion
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VII. SE
R
An alterna
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Decentralized
have been pro
for Grids and
here is nothin
a central ent
participants r
as in typical c
The Catall
von Hayek. T
mechanism
decentralized
self organizat
market to be
price signaling
resource alloc
It is intuit
huge flat mar
given number
higher the he
EGMENTATI
RESOURCE M
ative resource
ning agents in
d Grid market
oposed as suit
Service Orien
g more than a
tity and does
requirements u
entralized mar
laxy mechanis
The Catallaxy
for systems
agents that m
tion approach
adjusted base
g between age
cation are expl
tively clear th
rket is not the
r of buyers and
eterogeneity a

ION IN MAR
MANAGEME
management
n a decentrali
ts based on c
table coordina
nted Architect
a communicati
s not particip
using optimiza
rkets (auction
sm was origin
y approach i
consisting
makes use of
h. It enables p
ed on constant
ents. Catallacti
lored in the CA
hat decentraliz
e most efficien
d sellers in a G
and dynamicit
RKET BASED
ENT
mechanism u
zed Grid mar
catallactic age
ation mechanis
tures. The mar
ion bus it is
pate in match
ation mechanis
s).
nally proposed
s a coordinat
of autonom
f a free-mark
prices within
t negotiation
ic agents for G
ATNETS proj
zed bidding i
nt setting for
Grid market. T
ty of the sys

uses
rket.
ents
sms
rket
not
hing
sms
d by
tion
mous
ket
the
and
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ect.
in a
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The
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id
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s
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th
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c
n
m
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ty
are, the bigg
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propose to ex
enabling the b
and the autom
optimized mar
dea of Group
norms and inst
market segme
customers and
groups to ad
trategies that
egment. Mark
his clearly doe
Group Selec
evolution in a
cale open syst
In Fig. 5 (
catallactic mar
contact service
negotiations w
mechanism fin
4). Each servic
ype, defined b
ger is the pr
ding to low sy
xtend standar
bootstrapping
matic evolutio
rket segments
p Selection as
titutions betwe
entation is id
d potential c
ddress and to
satisfy the d
kets segments
es not scale no
ction self-or
a scalable man
tems.
(left) we see
rket. Two bro
e providers in
with them. In
nds 4 Grid ser
ce provider ma
by its strategy,
robability of
ystem-wide p
rd catallactic
of the agent
on of these
s. Hayek itsel
s a transmitter
een societies.
dentifying gro
customers, to
o respond w
different pref
s can be set u
or adapt to ope
rganizes ma
nner which w
an example
okers (Client
order to enga
this example
rvices provider
aintains a diffe
, contractual i
f un-coordinat
erformance. W
c Grid marke
s in submark
groups towar
lf supported t
r of free mark
The idea behi
oups of simi
o prioritize t
with appropri
ferences of ea
up manually, b
en Grid system
arket segme
works with lar
of a typical f
1 and 2) try
age into bilate
e, the discove
rs (Services 1
erent negotiati
mplications, a
ted
We
ets,
kets
rds
the
ket
ind
ilar
the
iate
ach
but
ms.
ents
rge
flat
to
eral
ery
to
ion
and

l
n
t
o
e
s
u
s
a
s
p
s
m
d
T
m
I
c
l
p
w
a
s
I
a
a
m
legal issues
negotiation ty
to avoid chea
other agents.
example the n
S1 and S2. In
strategy S1 w
Service 4, w
using S2. Thi
spurious nego
are time and r
After one
services execu
perceived util
such as the se
metric compri
decide how to
They can co
migrating to V
In this scenar
characteristic
level. In this
preferentially
which tend to
abilities and
successful allo
In this
Interaction an

Market-ba
agent/agents
allocation util
market allocat

and so on.
ype informatio
ating agents w
In order to
negotiation typ
n this case, w
will end up ne
which are mor
is is a case of
otiations which
resource consu
market iterati
utions are der
ity as feedbac
ervice provisio
ising QoS. Th
o evolve on t
ompare fitness
VOs where th
rio, it is this
being autom
manner Clien
with Services
o be Services
goals, hence
ocations.
pattern insta
nd Migration ru
ased Interact
from my
lity and perfo
tions.
An importan
n must be kep
with incentive
simplify, w
pe space to tw
we can see th
egotiating wit
re compatib
f miss coordin
h should be av
uming.

ion, and after
rived, the user
ck. This can be
on time, up to
hen, Clients an
the different m
s with agents
hey find outpe
negotiation
matically selec
nt 1 and Clien
s belonging to
closer to the
increasing th
antiation, th
ules take the f
tion rule:
market segm
orm job subm
nt issue is
pt private in or
es to free-ride
we reduce in
wo different typ
hat Client 1 w
th Service 2
ble with Clie
nation leading
voided since t
utilities from
rs send back th
e a simple me
o more elabora
nd Services m
market segme
s in other V
erforming age
types closene
ted at the gr
nt 2 will inte
o the same gro
em in negotiat
he probability
he Market-ba
form:
Negotiate w
ment. Calcu
mission follow
that
rder
e on
the
pes,
with
and
ents
g to
they
to
p
w
ty
th
id
w
p
n
G
the
heir
etric
ated
must
ents.
VOs,
ents.
ess
roup
ract
oup,
tion
y of
ased
with
ulate
wing
r
r
o
w
o
a
o
n
m
a
n
e
p
u
s
b
p
o
c
th
w
We build o
o optimize a
performing dec
whole set of se
ypical catallac
he markets
dentified by a
with the enha
proceeds in ex
normal catallac
Grid market is
Market-bas
esources) mo
elative fitness
outperforming
with another
outperforming
agent moving
of the agent
negotiation typ
migration prob
a mutation pro
new group on i

For these e
economic base
protocol, stand
used in Grid m
tarts with a ta
buyer), which
participants (th
out by the grou
conclusion of
he set of colle
winner. On to
on automatic
an agents di
centralized se
ervices (in a si
ctic market, w
for services
a tag. Once the
anced discover
xactly the sam
ctic market. A
depicted in Fi
sed Migration
ove between
s. Agents will
them. That i
agent perform
me, then mov
to a new grou
in the target
pes in groups
bability and so
obability, imp
its own by the
experiments w
eline an implem
dardized by F
markets contex
ask announcem
h can be a
he sellers). T
up cast of a c
this first peri
ected proposa
op of this p
market segme
iscovery proc
earch and nego
ingle market),
we propose a
in specializ
e negotiation p
ry, the econo
me way as it
A minimal seg
ig. 5 (right).
n rule: Agen
groups dep
migrate to gro
is, compare ow
mance. If the
ve to its group
up copies the
group. This
s. This rule is
ome variability
plying the crea
e agent.
we have used
mentation of t
FIPA, which h
xt. The Contr
ment phase by
answered by
This announce
call for propos
iod, the initia
als the best on
protocol, we
entation in ord
cess. Instead
otiation over t
as it is done in
segmentation
zed VOs, ea
partner is chos
omic negotiati
t would do in
mentation of t
nts (with th
pending on t
oups with age
wn performan
e other agent
p. In addition, t
negotiation ty
is what alig
s applied with
y is added trou
ation of a bra
as decentraliz
the Contract-N
has already be
ract-Net protoc
the initiator (t
one or mo
ement is carri
sals (CFP). Af
ator selects fro
ne, informing t
apply a simp
der
of
the
n a
of
ach
sen
ion
n a
the
heir
the
ents
nce
is
the
ype
gns
h a
ugh
and
zed
Net
een
col
the
ore
ied
fter
om
the
ple

o
a
t
l
p
w
n
t
m
f
r
w
a
r
s
w
t
r
s
t
t
e
c
a
s
7
a
f
m
c
r
c
e
u
offer/demand-
answer the CF
the CFP does
lower its exp
price. As for t
will lower its
next CFP. Bo
their expectat
meet their ex
fixed small pr
In order t
resource alloc
with 100 agen
a fixed rate of
round issued
sending by the
with commun
to 5 Services
random eithe
scenario) or fr
the Group Sel
negotiation ty
the closeness

If we com
evolving throu
coordinate ea
accumulated a
smoothly influ
70 in the Gro
around the in
fair (Fig. 6, rig
market is sim
can conclude
resource allo
compromising
economic alg
utilities by ap
-based econom
FPs which m
s not meet its
pectations and
the buyers, if
s expectation
oth the buyers
tions in case o
xpectations. T
rice steps.
to test the pe
cations, we set
nts (50 buyers
f incoming req
per Client. Ea
e Client. In or
nication costs,
to be reached
er from the w
from agents be
lection scenar
ypes. Utility
s between ne
mpare a flat m
ugh Group Se
sier the negot
allocation util
uenced by off
oup Selection
nitial selling p
ght). The price
milar; hence w
that market se
ocation utilit
g price stabi
gorithm can
pplying a Grou
mic algorithm
meet its current
s requirement
d it will decr
a seller rejects
by increasing
s and the sell
of receiving o
The price upd
erformance of
tup in the simu
s and 50 seller
quests, 1 reque
ach request w
der to model r
we limit the s
d on each grou
whole popula
elonging to th
io).We introdu
derived by cl
egotiation type
market with a
election, we s
tiation types,
lities (Fig. 6,
fer/demand in
n scenario). Th
prices (75) ren
e evolution fo
we do not show
egmentation is
ies of the
ility. A simp
be optimize
up Selection p
m: The sellers w
t selling price
ts, the seller w
rease the sell
s the CFP, the
g the offer in
lers will incre
offers/bids wh
dating is done
f economic-ba
ulator an scena
rs). We introd
est per simulat
will trigger a C
realistic scena
scope of the C
upcast, selecte
ation (in the
he same group
uce five differ
lients is related
es. The closer
a grouped sett
ee how the la
leading to be
left). Prices v
the bounds 80
he price stabi
nders the mar
r the baseline
w the graph.
s able to incre
traders with
ple decentrali
ed in allocat
process, boost
will
e. If
will
ling
en it
the
ease
hich
e at
ased
ario
duce
tion
CFP
rios
CFP
d at
flat
p (in
rent
d to
the
ty
w
n
n
G
s
g
p
o
d
a
u
b
a
c
c
ting
atter
etter
vary
0 to
ility
rket
flat
We
ease
hout
ized
tion
ting
th
c
s
th
m
w
In
w
th
g
o
th
n
to
in
ypes are, the
with a single f
negotiation ty
negotiation typ
Group Selectio
tructured: age
groups whenev
payoffs. This
outperforming
We measur
directly propor
Given M d
are represented
utility calculat
buyer agent 1 a
agent 2. The
consider the m
cases oscillate
he convergen
compatible ne
egmented in
han for agents
We try now
migration prob
which values
ntuitively, sin
while mutation
he relation m
groups. We fix
order of magn
he Market ba
new sub-marke
o reach agreem
n this scenario
higher the ut
flat decentraliz
ypes of othe
pes of agents
on scenario, t
ents migrate w
ver they find
s migration
agent negotia
re the utility
rtional to the n
different negot
d by integers
ion, with 1 nt
and 2 nt being
exception is
maximum uti
between 0 and
nce in the
egotiation typ
groups to fin
s in the flat dec
w to vary the
bability and
are leading
nce migration
n creates bran
migration/to mu
x a mutation p
nitude smaller
sed resource
ets would affe
ments. We nee
o. Having a f
tility derived.
zed market, ag
er agents by
s outperformin
the same lear
with a high pro
other agents a
implies the
ation type.
extracted from
negotiation typ
tiation types, n
from 1 to M.
t being the neg
g the negotiati
that when 1
lity 1 achiev
d 1.
same groups
pes. It is e
nd compatibl
centralized ma
e Group Selec
mutation pro
g to a bette
tends to hom
nd new sub-ma
utation, the la
probability of 0
than in the R
allocation sce
fect traders wh
ed for a slowe
fixed mutation
In the baseli
gents try to lea
y adopting t
ng them. In t
rning process
obability to oth
achieving high
copy of t
m allocations
pe closeness.

negotiation typ
. We use (2)
gotiation type
ion type of sel
2 nt nt
ved. The rest
s of traders
asier for ag
e trade partn
arket.
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ontrolled by
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see that, fo
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to 0.7, decrea
CY BASED
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members, wh
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a
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performance.
Grid segmente
or so agents, a
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In our V
organization) h
policies. A VO
A2 (p2), A3 (p
operation. Pol
maximized by
forming each
coordination in
clusters out of
agents in eac
compatibly de
measured diffe
Fig. 8 (lef
users of any p
Fig. 8 (right)
members poli
members utility
The best con
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as shown in F
lusion as for t
ker to compati
VO model, e
has a policy
O consists of a
p3).}. The V
licy based r
coordinating
VO. The o
n each of the V
f the N agents
h cluster usi
epends on th
erently depend
ft) shows a f
policy can acc
shows a Gr
icies are co
y.
nfiguration co
5 to 20 sub-ma
Figure 7(right
the RL scenar
ible negotiatio
each agent (
A = A (p), f
set of agents.
VO defines th
resource shari
the policies
bjective is a
VOs in the sy
s in the popul
ing compatibl
he specific s
ding on it.
flat Grid with
cess provider
rid organized
ompatible, th
orresponds to
arkets, each o
t). This suppo
rio: small grou
on types.
representing
from a set of
VO = {A1 (p
he scope of ag
ing utility g
of the M age
achieving poli
ystem, forming
ation, with m
le policies. T
scenario and
hout VOs wh
s of any poli
in VOs who
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of 5
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g C
most
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Clearly, fo
scenario with
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automatic pol
Selection pat
instantiated as
Policy C
collective int
shared equally
We have im

for policy bas
h group stru
The challenge
nation in dyna
licy coordina
ttern. The tw
s follows.
Coordination
teraction insid
y between the
mplemented th
sed resource m
ucture outpe
e in this case i
amic VOs. W
ation by mean
wo rules of
Interaction
de the group
e agents comp
he simplest o
management,
erforms the
is how to man
We aim to achi
ns of the Gr
the pattern
rule: We
p, with a pay
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of the collec

the
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ieve
roup
are
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im
th
p
to
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p
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h
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w
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cenario. The p
over the whole
Policy Co
compare their
performance (
mplies the cop
his target grou
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ogether with
diversity (entro
policy alignme

Equation 3
tands for on
Minimizing th
homogeneity i
performance s
policies in the
when all presen
maximal entro
corresponding
payoff is calc
e VO.
oordination M
r performanc
(internal learn
pying of the p
up. This maps
rces optimizin
a similar pol
opy) within ea
ent possible.
implements o
ne of the po
he index is
in VOs. We re
scale from 0
group are alig
nt policy in th
opy).
to a VO p
culated on the
Migration rul
ce against t
ning). Migrat
policy of one
s VOs configu
ng their perfor
icy. The goal
ach VO, achie
our metric for
olicies in a
equivalent
everse this me
to 1: This gi
gned (minima
he group is rep
policy alignm
alignment lev
le: The age
their own p
tion to a gro
random agent
urations of lar
rmance by acti
l is to minim
eving the high
this scenario.
set of size
to maximizi
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ives 1 when
al entropy) and
presented equa
ent
vel
ents
past
oup
t in
rge
ing
mize
hest
i p
M.
ing
e a
all
d 0
ally

The total number of agents is N=100. The set of
different policies is M=10. Mutation probability is fixed
to a small value of 0.01 like in the markets segmentation
scenario. We see from Fig. 9 (left) that reaching a high
alignment (low entropy) up 0.8 is possible before 1000
rounds and maintained afterwards for a migration
probability of 0.3.Fig. 9 (right) shows that the number of
VOs oscillates in this case between 10 and 20. If we use a
higher migration probability of 0.7, this implies a higher
ration migration/mutation and consequently less number
of groups in the system in average. As we can see from
Fig. 9, larger number of small groups generates better
coordination, which recovers the same conclusion as in
precedent scenarios.

IX. CONCLUSION
In large scale Grids, system dynamicity and
uncertainty are high; automatic, decentralized and self-
organized control becomes a requirement. Our proposal is
that a simple, rather powerful coordination mechanism
based on Group Selection can be used to self-organize a
set of agents in VOs to operate more effectively on a Grid
environment. The Group Selection mechanism
complements rather than compete with much of the
existent coordination mechanisms for MAS. We have
formalized a distributed systems engineering pattern
Group Selection pattern, amenable to be instantiated in
several Grid resource management scenarios. We have
shown, by simulations in a general purpose agent-based
Grid simulator, how splitting the Grid participants (agents
and resources) in groups and further evolving those
groups based on utility can lead to optimization in several
Grid resources management tasks.
First, we have shown how to apply the pattern to
evolve congregations of independent RL schedulers,
leading to optimized operation/learning in groups,
compared with a baseline with a flat population of
schedulers. We have also analyzed which values for the
parameters of the mechanism (the group migration to
group mutation rate) achieve better performance,
concluding that generating trough this rate a population of
very dynamic and small groups achieves the best
optimization in this scenario. Evolving smaller Q-tables
allows for the RL agents to converge quicker to
coordinated resource usage, and changes or problems in
resources can be quickly addressed by migration to new
groups or creation of new groups trough mutation. In
general RL schedulers learn quicker and adapt quicker to
changes in dynamic, small groups.
In the case of plugging the mechanism into a
decentralized Grid market, each group represents a sub-
market of the market segmentation, and migration of
agents from one sub-market to another is ruled by the
Group Selection process. The results extracted by
simulations show higher profits for the society of agents
trading in decentralized Grid markets which structure the
population in sub-markets and incorporate Group
Selection, compared to the flat decentralized markets. The
performance results show that agent-based automatic fair
trading of resources at stable prices can be achieved using
the decentralized market mechanism coupled with the
Group Selection process. Studying the impact of varying
migration to mutation rate draws a similar conclusion as
in the previous scenario: agents trading in small groups
are able to converge quicker to more compatible
negotiation types.
As for plugging the mechanism into policy-based VO
management scenario, the migration of agents from one
VO to another and its policy adaptation by aligning
policies with the agents in the target groups is ruled by the
Group Selection process, achieving optimization of
policy-based resource sharing utilities. The results
extracted by simulations show how small groups of agents
can align quicker and to a higher degree (following
Shannon entropy index metric) their resource sharing
policies.
Clustering in small groups is a tendency largely
observed in all kind of human organizations. In
cooperation building scenarios, it has been shown that
smaller group sizes ease cooperation in both social-
networks based cooperation and Group Selection based
evolution of cooperation. Our results for the evaluation of
Group Selection in three different Grid coordination
scenarios suggest that the same conclusion applies in fully
cooperative domains: small and dynamic groups of
agents evolved trough Group Selection optimize better
fully cooperative coordination scenarios. In our Group
Selection pattern, the group migration to mutation rate
determines the average number of dynamic groups in the
systems. A rate tuned to evolve dynamic and small groups
achieves the best optimization in all three scenarios. In the
adaptive scheduling scenario, just group membership is
evolved in order to segment learning Q-tables of agents.
In the other two scenarios (market segmentation and VO
policy based resource sharing) an agent characteristic
(negotiation type and policy respectively) its also
evolved via imitation upon migration to new groups. For
the population of 100 agents evaluated in the simulator,
the specific migration to mutation rate (this is scenario-
dependent) dynamically generating small groups of
around 5 agents achieved the best performance in all three
cases.
Future work includes considering Grid users and
services belonging to many VOs simultaneously, mapping
more realistic scenarios. Deployment of the pattern into a
Grid prototype can add more insights into practical
feasibility of the approach.

REFERENCES
[1] I. Foster, C. Kesselman, and S. Tuecke, The anatomy of the
Grid:Enabling scalable virtual organizations, Int. J. Supercomput.
Appl.,vol. 15, no. 3, pp. 200222, 2001.

[2] I. Foster, N. R. Jennings, and C. Kesselman, Brain meets Brawn:
Why Grid and agents need each other, presented at the 3rd Int. Conf.
Autonomous Agents Multi-Agent Syst. (AAMAS), New York, 2004.
[3] D. S.Wilson, A theory of group selection, Proc. Nat. Acad. Sci.,
vol.72, pp. 143146, 1975.
[4] R. Raman, M. Livny, and M. Solomon, Resource management
through multilateral matchmaking, in Proc. 9th IEEE Symp. High
Perform. Distrib. Comput., 2000, p. 290.
[5] E. Deelman, J. Blythe, Y. Gil, C. Kesselman, G. Mehta, S. Patil, M.
H. Su, K. Vahi, and M. Livny, Pegasus: Mapping scientific workflows
onto the Grid, in Proc. Grid Comput.: 2nd Eur. Across Grids
Conf.(AxGrids), Nicosia, Cyprus, Jan. 2004, pp. 1126.
[6] X. Bai, H. Yu, G. Wang, Y. Ji, G. M. Marinescu, D. C. Marinescu,
and L. Blni, Coordination in intelligent Grid environments, Proc.
IEEE, vol. 93, no. 3, pp. 613630, Mar. 2005.
[7] S. Lynden and O. F. Rana, Coordinated learning to support resource
management in computational Grids, presented at the 2nd IEEE Int.
Conf. Peer-2-Peer Comput., Linkoping, Sweden, Sep. 2002.
[8] H. Tianfield and R. Unland, Towards self-organization in multi
agent systems and Grid computing, Multiagent Grid Syst.An Int. J.,
vol. 1, no. 2, pp. 8995, Oct. 2005.
[9] R. Buyya, D. Abramson, and S. Venugopal, The Grid economy,
Proc. IEEE, vol. 93, no. 3, pp. 698714, Mar. 2005.
[10] B. Schnizler, D. Neumann, D. Veit, and C. Weinhardt, Trading
Grid servicesA multi-attribute combinatorial approach, Eur. J.
Operat. Res., vol. 187, no. 3, pp. 943961, 2006.


ISBN: 978-81-920575-6-9 :: doi: 10.73697/ISBN_0768
Abstract: In this project, OPTIMIZED IMPLEMENTATION
OF REDUCED SIZE LUT IN BUILT IN SELF TESTING
optimizing the memory size of the look up table and
implementing it in a BIST circuit for a multiplier. Memory size
of the look up table can be optimized by controlling the storage
of repeated data's by an address decoder. Reducing the
memory size of the look up table and hence the power
dissipation reduces. Thus here in my project for a 16 bit
multiplier by reducing the repeated results of the multiplier
optimized lookup table is formed. This optimized lookup table
is then applied in the built in self test to test a multiplier circuit.
Here because of the optimized lookup table the testing speed
increases.

Index Terms:Look up table, Built in self testing

I. INTRODUCTION

Development of physics based circuit models for deep
sub-micron MOSFETs is becoming increasingly difficult as
the device dimensions are scaled down. Earlier, it had been
possible to obtain compact models with a small number of
fitting parameters for circuit simulation by understanding the
physical phenomena in the devices. This is no longer
practical as the device dimensions enter the sub 100 nm
regimes, since these devices have very complex structures
and doping profiles. To model the small geometry devices
accurately, one has to perform multidimensional analysis,
which always results in very complicated model expressions
with many empirical parameters. Further, it is generally
difficult to extract such a large number of parameters
accurately from experimental data, and parameters extracted
often produce parameters which are physically inconsistent
because of the above difficulties with analytic models. The
look-up table (LUT) approach is being considered as an
attractive alternative for circuit simulation. In this approach
the terminal currents and charges are used as Look-up table.
A suitable interpolation scheme is used to evaluate the
current or charge at any point that does not coincide with a
table point. In the LUT approach, our aim is to approximate
the behaviour of a given device using finite number of table
points with a suitable interpolation algorithm. The table
points can be obtained from measurements, device
simulations, or from existing physical models. In
semiconductor device models, the controlling variables
of the device are its terminal voltages and the dependent
physical quantities are its terminal currents and charges. The
objective is to approximate this dependent physical quantity
using an interpolation scheme. It is assumed that the device
operates in quasistatic regime, i.e., the terminal currents and
charges depend only on the instantaneous values of the
terminal voltages. As we shall see in this assumption is a
realistic one in many practical situations with sub-micron
gate lengths.

In integrated circuits, BIST is used to make faster, less-
expensive manufacturing tests. The IC has a function that
verifies all or a portion of the internal functionality of
the IC. In some cases, this is valuable to customers, as well.
For example, a BIST mechanism is provided in
advanced field bus systems to verify functionality. At a
high level this can be viewed similar to the PC BIOS's
power-on self-test (POST) that performs a self-test of the
RAM and buses on power-up. The main purpose of BIST is
to reduce the complexity, and thereby decrease the cost and
reduce reliance upon external (pattern-programmed) test
equipment. BIST reduces cost in two ways: 1. Reduces test-
cycle duration 2. Reduces the complexity of the test/probe
setup, by reducing the number of I/O signals that must be
driven/examined under tester control. Both lead to a
reduction in hourly charges for automated test equipment
(ATE) service. The BIST name and concept originated
with the idea of including a pseudorandom number
generator (PRNG) and cyclic redundancy check (CRC) on
the IC. If all the registers that hold state in an IC are on
one or more internal scan chains, then the function of the
registers and the combinational logic between them will
generate a unique CRC signature over a large enough
sample of random inputs. So all an IC need do is store the
expected CRC signature and test for it after a large enough
sample set from the PRNG. The CRC comparison with
expected signature or the actual resultant CRC signature is
typically accessed via the JTAG IEEE 1149.1 standard.
There are several specialized versions of BIST which are
differentiated according to what they do or how they are
implemented: Programmable (pBIST), Memory built-in self-
test (mBIST) - e.g. with the algorithm, Logic,Analog and
mixed-signal built-in self-test (AMBIST),Continuous built-in
self-test (CBIST),Periodic built-in self-test, Interrupt-driven
built-in self-test (IBIST) or user-initiated built-in self-test,
Power-up built-in self-test (PupBIST),Automatic built-in
self-test (ABIST).

BIST is the technique of designing additional
hardware and software features into integrated circuits to
allow them to perform self-testing, i.e., testing of their
own operation (functionally, parametrically, or both) using
their own circuits,
OPTIMIZED IMPLEMENTATION OF REDUCED SIZE LUT IN BUILT
IN SELF TESTING
Ajith kumar A., M.E.(VLSI DESIGN), ajithkmr89@gmail.com
Veltech Multitech Dr.Rangarajan Dr.Sakunthala Engineering College, Chennai
ereby reducin
ATE).BIST is
akes the elec
ss costly. The
rcuit, so its i
versity that it
r DRAMs in
rcuits for patte
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mplex device
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minating the
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IST such as,1)
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ips.3) Shorter
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test the chip
plication boar
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vices. This
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g dependence
a Design-for
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concept of BI
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built on dif
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and analog te
special tests
need to acqui
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external pin
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longer be a
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) Lower cost o
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umstances as
II. PRO

In the look
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particular ad
address is usi
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IST is applica
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adequate for
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structures ca
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OPOSED SYS
kup table the
decoder where
ddress in the
ing the addres
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ss. Here the
e LUT write
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, w3, w4, w
the lookup
m the particu
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nal automated
(DFT) techniq
ier, faster, mo
able to just ab
as widely as
e, a common
onto the chi
mode selection,
lexity of inte
vices that ha
ologies insid
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lities. BIST
tional on-chip
end testers.BI
circuits that
embedded
ture, even the
the fastest c
ution for. The
he need for ex
not eliminate
an be incorp
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er support.5)
rical testing en
ow the consum
even after th
an alternative
and increasing
ater deployme
better BIST
STEM
write operatio
e the datas ar
address dec
ss generator. T
is taken for
e control un
operation. H
d3 is the inp
w5, w6, w7 a
table. The e
ular memory
ss.
d test equipme
que, because
ore efficient, a
bout any kind
s the produ
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ip of addition
, and go-/no-g
egrated circui
ave functiona
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ers that posse
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p test circui
IST is also t
have no dir
memories us
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xternal electric
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g complexity
ent in a wid
techniques a
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re stored for t
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Thus the outp
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and
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he size of the
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reduced to
from the two
hus the addre
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shown in the
7 times and
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stores the 4
project the l
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5, no. 3, pp. 4454
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Systolic algorithm
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] P. K. Meher,
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r Video Technolo
] Synposys, De
Online]. Available
] TSMC 0.l8um
atabook, Release
003.
] J.-I. Guo, C.-M
LSI array design
nalog Digit. Sign
] H.-R. Lee, C.-W
e memory-based
onsum. Electron.,
0] D. F. Chiper,
ystolic array archi
gnal Process.,Sep
1]A.K.Sharma,A
rchitectures,Desig
003.
2] H.-C. Chen, J
circuit with th
bove diagram
s tested using
m the test
IST circuit ad
nerator. The
address de
BIST check w
or not. The
he multiplier
he test pattern
utput for the c
nerator. Here i
bit multiplier
6 bit multiplie
est. By using
ease.
REFER
Technology Road
ublic.itrs.net/
W. Jen, and C.-M
d VLSI architect
nics, vol. 39, no. 3
.-I. Guo, T.-S. C
n of cyclic convo
IEEE Trans. Ci
453, Mar. 2005.
M. N. S. Swamy
ms and a memory
he computation
st-I: Regular Pap
Systolic design
utional formulatio
ogy, vol. 16, no. 9
signWare. Found
e: http://www.syn
Process 1.8-Volt
e 4.1. Sunnyval
M. Liu, and C.-W
n for DFT and D
nal Process.,Oct. 1
W. Jen, and C.-M
d VLSI architect
, Aug. 1993
M. N. S. Swamy
itecture for the d
p. 2002.
Advanced Se
gns, and Applica
J.-I. Guo, T.-S. C
he optimized
m. Here in the
g the test pat
pattern gen
ddress generat
optimized lo
ecoder also
whether there
e comparator
circuit for t
n generator wit
corresponding
in this project
r is done. This
er will be imp
the optimize
RENCES:
dmap for Semico
M. Liu, On the d
tures for FIR fil
3, pp. 619629, A
Chang, and C.-W
olution and its ap
ircuits Syst for V
y, M. O. Ahmad
y-based design ap
of DCT/DST/I
pers, vol. 52, no
ns for DCT using
on, IEEE Trans.
9, pp. 10411050
dry Libraries, Mo
nopsys.com/
t SAGE-XTM Sta
e, CA: Artisan
W. Jen, The effic
DCT, IEEE Tran
1992.
M. Liu, On the d
tures for FIR fil
y, M. O. Ahmad,
discrete sine trans
emi conduc
ations. Piscatawa
Chang, and C.-W

lookup table
BIST circuit t
tterns which a
nerator. In t
tor is used as t
ookup table a
used in t
is fault prese
r compares t
the given inp
th the optimiz
g input from t
t optimized lo
s optimized lo
plemented in t
ed LUT testi
onductors. [Onlin
design automation
lters, IEEE Tra
Aug. 1993.
W. Jen, A memo
pplication to discr
Video Technol., v
d, and T. Stourai
pproach for a unif
DCT/IDST, IE
. 6, pp. 112511
g a low-complex
Circuits & Syste
, Sept. 2006.
ountain View, C
andard Cell Libr
Components, Se
cient memory-ba
ns. Circuits Syst.
design automation
lters, IEEE Tra
and T.Stouraitis,
sform, IEEE Tra
ctor Memor
ay, NJ: IEEE Pre
W. Jen, A memo
e is
the
are
the
the
and
the
ent
the
put
zed
the
ook
ook
the
ing
ne].
n of
ans.
ory-
rete
vol.
itis,
fied
EEE
137,
xity
ems
CA.
rary
ept.
ased
. II,
n of
ans.
A
ans.
ries:
ess,
ory-
effic
cosin
2005
[13]
Avai
[14]
VLS
Anal
1992
autom
IEEE
1993
[16]
systo
Sign
cient realization o
ne transform, I
5.
International Te
ilable: http://publ
J.-I. Guo, C.-M.
SI array design fo
log Digit. Signa
2.[15] H.-R. Lee
mation of the me
E Trans. Consu
3.
D. F. Chiper, M.
olic array architec
al Process., vol.
of cyclic convolu
IEEE Trans.Circ
echnology Roadm
lic.itrs.net/
Liu, and C.-W.
or DFT and DCT
al Process., vol.
e, C.-W. Jen, a
emory-based VL
um.Electron., vo
N. S. Swamy, M
cture for the disc
50, no. 9, pp. 234
ution and its appl
cuits Syst. Video
map for Semicon
Jen, The efficie
T, IEEE Trans.
. 39, no. 10, pp
and C.-M. Liu,
LSI architectures
ol. 39, no. 3, pp
M. O. Ahmad, and
crete sine transfor
472354, Sep.
lication to discret
o Technol., Mar
nductors. [Online]
ent memory-base
Circuits Syst. II
p. 723733, Oct
On the desig
for FIR filters
p. 619629, Aug
d T. Stouraitis,
rm, IEEE Trans
2002.
te
r.
].
d
II,
t.
gn
,
g.
A
s.
V
I
A
Proc. of th
Volume 1. Cop
ISBN: 978-81
A
Optim
Swar
#
ECE Dep

Kum

Abstract CM
Design Varian
functional req
use in self-po
CHIP solutio
PHOTO-SENS
CORE SUB
harvesting ov
VISIBLE regi

KeywordsPh
mode*, Irradia
Various m
circuits are p
cycle of suc
depends up on
the ICs. The
selected for
based on m
operating cyc
sensor curren
Zane of Colo
of Electrical
University of
with respect t

1)

R
he Intl. Conf. o
pyright 201
1-920575-6-
ACM #: dber.
mized Des
rrnna Karthik.
partment, SAS

mbakonam , T
India

MOS compatib
nts are realized
quirements ag
owering applic
ons. CMOS
SORS / PHO
B-SYSTEM
ver a wide ran
ion of the elect
hotonics, Photo
ance, Radiation
I. IN
modes of sel
presented in t
ch VLSI sys
n the power s
power sourc
integration w
matching pow
cle. For a ty
nt demand dia
orado Power E
l, Computer
f Colorado at
to a sample se
Example
Typical :
RF transceiver
Operate
on Computer A
12 Techno For
9 :: doi: 10. 7
.imera.10. 73
sign varia
.P, Student me
STRA Univer

Tanjore Dist , T
612001

ble Optoelectro
d by optimizin
ainst technolo
cations in VL
S compactible
OTO DETEC
for Environ
nge of frequen
ro-magnetic Sp
oconductive m
n damage, EMI
NTRODUCTION
lf-powering o
the journal lit
stem and its
sources that ar
ces are gener
with CMOS
wer consumpt
ypical sensor
agram arrived
Electronic Ce
r and Energ
t Boulder

[1]
ensor load requ
Sensor load R
: Low power
and analog se
with high pe
Applications
rum Group, In
3704/ISBN_0
704
ants of a s
ember, IEEE
rsity SRC Ca

Tamil Nadu ,

onic VLSI Cir
g component l
ogical barriers
LSI SYSTEM
e semi-condu
CTORS form
nmental Ene
ncy spread in
pectrum.
ode*, Photovol
I.
N
of CMOS V
terature. The
s maintainab
re integrated w
rators are larg
IC applicati
tion during
r load, measu
d by Prof. Re
entre, Departm
gy Engineer
is shown bel
uirement diag
Requirements(
micro contro
ensor inputs
eak currents

ndia.
0768
self-power
Circuit

ampus

rcuit
level
s for
ON
uctor
the
ergy
the
oltaic
VLSI
life
ility
with
gely
ions
full
ured
egan
ment
ring,
low,
gram.
(Fig
oller,
and
mo
vib
pow
ave
[2]
sou
rep
(
VIS
req
dut
ado
Env
sou
des
har
sub
lea
pow
env
ene
tim
Au
reli
gen
per
min
sou
bey
app
opt
ring CMO
Asst.

#
ECE
Kumbak
low a
vary

Often quot
odes are:
1. Piezo-elec
brations are u
wer for power
erage output p
2. RF contro
urce generatin
ported by Shan

II. ENER
(STAY LIGHT)
A
Making use
SI-Design, w
quirement of I
ty cycle of op
opted a pract
vironmental S
urces, for elect
In this con
signing and
rvesting opto
bsequent integ
ds us to Sy
wering, self-
vironmental st
ergy.
Many SOC d
me for maki
utonomous Ch
In order to in
iability for a l
neration by
rformance eff
nimize the eff
urces for pow
yond RF as an
proach is now
toelectronic ci

OS Optoe
Prof. Swamin
Department, S
Campus
onam , Tanjor
India - 61200
average power
Optimization
with the avail

ted among th
ctric transduc
used to gener
ring digital ci
power was in t
olled narrow b
ng an output
ntanu A. Bhale
RGY HARVEST
(A PERPETUAL
AUTONOMOUS
of advances
which has b
ICs to micro-
peration of the
ical design a
Stray light En
tric energy ge
text our par
Developmen
oelectronic In
gration with C
ystem- On- C
-sustaining C
tray light ener
design concep
ng the CM
ip for remote
ncrease the lif
onger-time, w
mechanical
ficiency of th
fect of EMI on
wer generation
n energy sour
-possible with
ircuit design f
electronic
nathan.S
SASTRA Un
re Dist , Tami
01
er
on: sensor o
lable power
he above pow
cers producin
rate the nece
ircuits (ICs).
the order of~4
band or ambie
D.C. Voltag
erao etal [3]
TING FROM ENV
L SOURCE OF E
S SYSTEMS).
made in ultra
brought down
-watt level, b
e CMOS ICs
approach in m
nergy as an am
eneration.
rticular appro
nt of low p
ntegrated Cir
CMOS ICs. Th
Chip solution
CMOS ICs
rgy as an amb
pts evolved ov
MOS ICs fun
applications.
fe cycle of the
we have exclu
l means. I
he IC design
n the CMOS
n which lead
rce. Hence a m
h the advancem
for VLSI appli
VLSI
niversity SRC
il Nadu ,
operation can
wer generation
ng mechanica
essary electric
The published
400microwatt
ent RF energy
ge of 0.7v

i
VIRONMENT
ENERGY FOR
a-Low- Powe
n the powe
by keeping the
low, we have
making use o
mbient energy
oach involve
power energy
rcuits and it
his integration
ns for a self
powered by
bient source o
ver a period o
nction as an
e SOCs and it
uded the powe
n terms o
n, we need to
ICs due to RF
ds us to think
more practica
ments made in
ication.
C
n
n
al
c
d
ts.
y
s
er
er
e
e
of
y
s
y
s
n
f-
y
of
of
n
s
er
of
o
F
k
al
n
II A. So
available for c

W
REG

ultra

Visib

Infra

IR.

The
conversion is
since the inci
light wave for
Irrad
visible region
400 to 1100 n
generating ap
The
provides perf
cope with R
is a critical pr

IIB. Powe
area of the sem

For a pho
proportional
diodes may b
and used with
deliver a mea
circuit. CMO
of light shi
structures. A
responsive fro
wave length
Thus a light
technology. I
large area pho
amplifier so
converted into
A va
altering the a
feedback resi
microwatt/sq.

S.No Dio
output

1 I
2 II
3 III

ources of Str
conversion to
Table: 1
ELECTRO-MA
WAVELENG
GION
0.2micromete
a-violet
0.5 micromet
ble
1.0 micromet
a-red
10 micromete
quantum of
s more in th
ident energy
r a give Activ
diance or flux
n when the w
nm is more tha
pplication for A
choice of Si
formance crit
Radiation Dam
roblem in sem
er from ambien
miconductor-
oto-diode curr
to the light i
be modified-
h OP- amps an
asurement of
OS process can
ields to mak
A photo diod
om 400 nm t
when encaps
voltage con
In these CM
oto-diode is co
that the ph
o an output vo
ariance of thi
active area of
stor values fo
.cm .The outp
Table: 2
ode type

25
45
285
ray light and
Electrical ene
AGOVETIC SPEC
GTH EN
er
ter
ter
er
energy that
he shorter w
is dependent
ve Area
in terms of w
wave length is
an the RF ran
Autonomous V
i for semi co
teria and des
mage since R
miconductor d
nt irradiance o
CMOS- photo
ent mode sen
intensity. Con
into photo-tr
nd data conve
light level to
n be easily ada
ke integrated
de made by
to 1100 nm (v
sulated in tra
nverter are re
OS semicond
ombined with
hoto-diode cu
oltage.
is design can
f the photo-di
r a given valu
put voltage is l
Irradiance
Microwatts/sq

d energy spr
ergy. [4]
CTRUM
NERGY
6ev
2.4ev
1.24ev
0.12ev
is available
avelength reg
on frequency
watts/sq. cm in
s in the range
nge for self-po
VLSI circuits
onductor dete
ign flexibility
Radiation dam
detectors.[5]
over the Activ
o- detector.
nsor-the curren
nventional ph
ransistor elem
ersion element
a digital- con
apted by addi
d photo- sen
this process
visible to shor
ansparent plas
alised in CM
ductor sensor
h trans-impeda
urrent output
be arrived at
iode and inte
ue of irradianc
listed below[4

q.cm volts
2
2
2
read
for
for
gion
y of
n the
e of
ower
s. .
ector
y to
mage
ve
nt is
hoto-
ment,
ts to
ntrol
ition
nsor
s is
rt IR)
stic.
MOS
rs, a
ance
t is
t by
ernal
ce in
4]
rad
cur
as
bel
fun
eac
bot
(Isc
the
forw
bel
The
cur
from
par
vol
elem
ma
suit
Note: A ph
diation of 90lu
When l
rrent is genera
irradiance ov
low:[6]

Table: 3
For silicon D

Direct sunlig
=1000 foot c
=10.764x100
=10764lux

Overcast DA
=100 foot can
=10.764x100
=10764lux

Room light o
=1.167 foot c
=1.167x10.76
=12.56lux

Full moon lig
=0.1 foot can
=0.1 x10.764
=1.076~1.1lu

A phot
ndamental no
ch of which pr
th of these no
c) due to light
e opposite d
ward biased d

A wo
low (Fig 2)

e non-ideal p
rrent source th
m light, an id
rasitic series a
A photo
ltaic mode ha
ment or is Z
aximized for
ted for prec
hoto- metric
ux= 14 micro w
light impinge
ated. The mag
ver the activ
Detector
ght @ noon
andle
00lux

RF
AY
ndle
00lux

RF
on table
candle
64lux

RF
ght night
ndle
4lux
ux
RF
o diode can
odes, photovo
rovides advan
odes, the direc
t impinging o
irection from
diode or from
orking model
photo-diode c
hat is excited
deal diode, a
nd shunt resis
o diode that i
as no voltage
ero- biased. I
light sensitiv
cision applica
equivalence
watts/sq.cm
es on the pho
gnitude of this
ve area varie
Isc=30
CpD=5
RpD=1
F=167KW
Isc=3m
CpD=5
RpD=1
F=1.67MW
Isc=35n
CpD=5
RpD=1
F=142.9MW
Isc=3nA
CpD=5
RpD=1
F=1.667GW
operate in on
oltaic or pho
ntages and dis
ction of the f
on the diode w
m normal op
cathode to an
for a photod
circuit model
d by the radian
junction capa
stance.
is configured
potential plac
In this mode
vity and linea
ations. The
for a visible
oto- detector a
current varie
es as shown
microA
0 pF
000MW
microA
0 pF
000MW
nA
0 pF
000MW
A
0 pF
000MW
ne of the two
otoconductive
advantages. In
flow of charge
will conduct in
peration of a
ode.
iode is shown

l consist of a
nt flux energy
acitance and a
in the photo
ced across the
e, the diode i
arity and bes
key parasitic
e
a
s
n
o
e,
n
e
n
a

n

a
y
a
o-
e
s
st
c
elements that influxes critical performance are Cp
D
and
RpD , which affects the frequency stability and noise-
performance of a photo- detector circuit.
The junction capacitance CpD is a by product
of the width of the depletion region between the p-type
and n-type material of the photo-diode. A wider
depletion region will increase the magnitude of the
junction capacitance. Conversely wider depletion regions
(found in PIM photodiode) exhibit broader spectral
responses. Values of the junction capacitance of silicon
photo-diodes range from approximately 20 or 25 pF up to
and above several thousand pico-Farads. This junction
capacitance produces profound performance affects in
terms of stability, band width and noise.
The parasitic (RpD) Resistance is also called
shunt Resistance or dark resistance in photodiode
data sheets. This resistance is taken with the photo diode
is its zero (photovoltaic) or forward biased state. At room
temperature the magnitudes this resistance typically
exceeds one hundred mega ohms. For most application
this resistance is generally ignored.
Shunt resistance (RpD) generates the dominant
noise from the photo-diode. The noise is modelled in the
above (fig-2) figure as CpD. The noise generator by RpD
is known as Johnson noise and is due to the thermal
generation of carriers. The magnitude of this noise in
terms of volts is:
EpD=0^(4*K*T*RF*BW)where
K is the Boltzmanns constant =1.38 e
-23
JK
-1

T is the temperature in Degree Kelvin
(25 Degree celeries=298.16 Deg Kelvin)
BW is the band width in Hertz.
The second parasitic diode resistance Rs is
known as the series resistance of the diode. The parasitic
resistance typically ranges from 10 to 1000 W (ohms).
Due to the small size of this resistor it only has an effect
on the frequency response of the circuit well past the
bandwidth of operation. A fourth source of photo-diode
error comes from the leakage of current across the photo-
diode IL. If the offset voltage of the amplifier is zero
volts, this error is sufficiently small.
In contrast a photo-diode that is configured in
the photo conductive mode has a reverse bias voltage,
which is applied across the photo sensing element; the
width of the depletion region is reduced when this
voltage is applied across the photo-detector, which
reduces the photovoltaic capacitance (CD) significantly.
This reduced parasitic capacitance facilitates high speed
operation, however, the linearity and offset errors are not
optimised. The design trade-off for this action is
increased diode leakage current (IL) and linearity errors.

III A. Design concept in CMOS photo-sensor
VLSI circuits:

CMOS photonic Integrated with VLSI circuits
Technology represents the intimate integration of
photonic devices with silicon. The results so for
reported in scientific and Technological journals point to
suitable increase in processing power and speed
improvements even when relatively small numbers of
photonic devices are driven with CMOS logic
Technologies .
The objectives of evolving a design variant of
a CMOS Photonic Integrated VLSI circuit is to supply
multiple high performance optical inputs and output
signals with aggregate data rates , up to and even
exceeding a tera-bit per second to the state of the art
VLSI circuits. CMOS photonic integrated circuits are
used most effectively in systems where a high band
width data flow must be received, switched, or quickly
processed by the electronic circuits and communicated
out of the systems.
Such a Technology allows a significant increase
in integration density over all electrical systems because
the functionality present in many separate electronic
chips can be condensed to fewer chips and in some case
one single chip (SOC) ,with large numbers of optical
inputs and or outputs (I/Os) The use of CMOS
Photonic integrated VLSI packaging simultaneously
affords a reduction in the energy required to transmit
digital signals with in the systems (and hence the power
delay product of the system ) by reducing (and in
certain cases eliminating ) the parasitics associated
With conventional packaging technology that uses
wire bond between chips, this permits an increase in
interconnect speed for a given power dissipation (or
likewise a reduction in power for a given system clock
rate).

III B. Semiconductor CMOS Detector
/sensor Technology for current and future needs of SOC
VLSI design

The CMOS photonic sensors systems needs are
depended on the following application and Technology
barriers.

1. Sensitivity
2. Wavelength selectivity
3. Speed
4. Dynamic Range
5. Form Factor /Cost
6. Self powered.
IIIC. Semiconductor photodiode design variants:
A basic design of photo sensing circuit for VLSI
application is to place a photo-diode across the inputs of
a CMOS, input amplifier and a resistor in the feedback
loop. The single supply circuit implementation of these
circuits is shown below in figure 3.


Figure 3. This
circuit with th
mode.
In this cir
causes curren
anode. Since
of the CMOS
generated by
resistor, R
F
.
amplifier trac
the amplifier
voltage in acc
R
F
. The transf
this circuit is
I
SC
= Radi
I
SC
is th
photodiode w
Radiant F
watts / cm
2
, a
Flux Resp
sensitivity wi
When ligh
(I
SC
) conducts
as shown in F
this figure c
voltage, whic
V
OUT
= I
SC
V
OUT
is th
amplifier in v
I
SC
is the
units in ampe
s is a typical ,
he photodiode
rcuit, the inc
nt to flow thro
the input imp
S amplifier i
the photodiod
The voltage
cks the voltag
r; consequentl
cordance with
fer function o
equal to:
iant Flux Ener
he current pr
with units in am
Flux Energy is
and
ponsivity is a
th units in wa
ht impinges o
s from the cat
Figure 3. The
converts the c
ch is equal to:
C
* R
F
, where
he voltage at
volts
current prod
eres
, single supply
e in the photov
ident light on
ough the diode
pedance of th
s extremely h
de flows throu
at the invert
ge at the non-i
ly, the outpu
h the IR drop a
f light to phot
rgy / Flux Res
roduced by
mperes/cm
2

s the light ene
a measure of
atts / amperes
on the photod
thode of the d
amplification
current of th
:
the output o
duced by the
y photodiode
voltaic (zero b
n the photodi
e from cathod
he inverting in
high, the cur
ugh the feedb
ting input of
inverting inpu
ut will change
across the resi
todiode curren
sponsivity, wh
the zero bia
ergy with unit
the photodio
diode, the cur
diode to the an
system show
he photodiode
of the operatio
photodiode w
bias)
iode
de to
nput
rrent
back
f the
ut of
e in
istor
nt in
here:
ased
ts in
ode's
rrent
node
wn in
e to
onal
with
wit
res
pol
for
tak
cou
of r
inst
resp
reli
star
circ
the
firs
the
in s
of
app
con
and
pho
resp
cap
stab
res
tem
noi
am
CM
low
inp
cap
acc
net
net
we
CM
EN
MA
a C
pho
pho
foll
mo
wid
R
F
is the fe
th units in ohm
C
RF
is the c
istor, R
F
, and
le at 1 / (2
Unfortunately
failure if sub
ken into accou
uld produce an
ringing. Or w
tability probl
ponse could
iable results.
The impleme
rts with und
cuit, analyzing
ese insights to
st design prior
e photodiode r
stability. Foll
the system
propriate level
There are th
nsider in this
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REFER
Zane Dept E
OS Emerging Te
mirtharajah and A
MA 02139 Se
on Based Powe
TATE CIRCUITS
Bhalerao , A
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ONDITIONING
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LABORATOR
TOR CENTER , S
on Circuit APP
chip Technology
Power Man
CLUSIONS:
source for w
ce or ultra-low
rter operation
fficient emb
in autono
nergy harvest
ange of light i
e of semicon
autonomous
arvesting req
diode with
nverter provi
ce storage.
n be filtered d
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ECE , University
echnologies Sep
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STRUMENTS
AR SECTION 1
ectures by Pro
NCE BERKELY
FORD LINEAR
999 .
TES by Bonnie C

b
w
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it
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Y
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C.
ISBN: 9788192057569 :: doi: 10. 73676/ISBN_0768
AUTONOMOUS NETWORK RECONFIGURATION OF WMN
USING ARS
Mohanram.S M.E, Dr . Rangarajan Dr. Sakunthala
Vel Tech Multi Tech Engg College,Avadi,Chennai.

Abstract--Wireless Mesh Networks (WMNs) are being
developed actively and deployed widely for a variety of
applications, such as public safety, environment monitoring,
and citywide wireless Internet services. However, due to
heterogeneous and fluctuating wireless link conditions,
preserving the required performance of such WMNs is still a
challenging problem. Even though many solutions for WMNs
to recover from wireless link failures have been proposed they
are no efficient to meet the demands of the increasing WMN
networks. During their lifetime, multi hop Wireless Mesh
Networks (WMNs) experience frequent link failures caused
by channel interference, dynamic obstacles, and/or
applications bandwidth demands. These failures cause severe
performance degradation in WMNs or require expensive
manual network management for their real-time recovery.
This paper presents an AUTONOMOUS NETWORK
RECONFIGURATION SYSTEM (ARS) that enables a multi
radio WMN to autonomously recover from local link failures
to preserve network performance. ARS is a distributed
system that is easily deployable in every mesh node, ARS
supports self reconfigurability. By using channel and radio
diversities in WMNs, ARS generates necessary changes in
local radio and channel assignments in order to recover from
failures. Next, based on the thus-generated configuration
changes, the system cooperatively reconfigures network
settings among local mesh routers. ARS has been
implemented and evaluated extensively on our IEEE 802.11-
based WMN test-bed as well as through ns2-based simulation.
Our evaluation will be able to prove that ARS outperforms
existing failure-recovery schemes in improving channel-
efficiency by more than 90% and in the ability of meeting the
applications bandwidth demands by an average of 200%.

Keywords: wireless mesh network, autonomous network
reconfiguration.

I. INTRODUCTION
Routing is the act of moving information from a source
to a destination in an internetwork. At least one
intermediate node within the internetwork is encountered
during the transfer of information. Basically two activities
are involved in this concept: determining optimal routing
paths and transferring the packets through an internetwork.
The transferring of packets through an internetwork is
called as packet switching which is straight forward, and
the path determination could be very complex. Routing
protocols useseveral metrics as a standard measurement to
calculate the best path for routing the packets to its
destination that could be number of hops, which are used
by the routing algorithm to determine the optimal path for
the packet to its destination. The process of path
determination is that, routing algorithms find out and
maintain routing tables, whichcontain the total route
information for the packet. The information of route varies
from one routing algorithm to another.

The routing tables are filled with entries in the routing
table are ip-address prefix and the next hop.
Destination/next hop associations of routing table tell the
router that a particular destination can be reached optimally
by sending the packet to a router representing thenext
hop on its way to the final destination and ip-address
prefix specifies a set of destinations for which the routing
entry is valid .Routing is mainly classified into static
routing and dynamic routing. Static routing refers to the
routing strategy being stated manually or statically, in the
router. Static routing maintains a routing table usually
written by a networks administrator.
The routing table doesnt depend on the state of the
network status, i.e., whether the destination is active or
.Dynamic routing refers to the routing strategy that is being
learnt by an interior or exterior routing protocol. This
routing primarily depends on the state of the network i.e
,the routing table is affected by the activeness of the
destination. WIRELESS mesh networks (WMNs) are
being developed actively and deployed widely for a variety
of applications, such as public safety, environment
monitoring, and citywide wireless Internet services. They
have also been evolving in various forms (e.g., using multi
radio/channel systems) to meet the increasing capacity
demands by the above-mentioned and other emerging
applications. However, due to heterogeneous and
fluctuating wireless link conditions , preserving the
required performance of such WMNs is still a challenging
problem. For example, some links of a WMN may
experience significant channel interference from other
coexisting wireless networks. Some parts of networks
might not be able to meet increasing bandwidth Demands
from new mobile users and applications. Links in a certain
area (e.g., a hospital or police station) might not be able to
use some frequency channels because of spectrum etiquette
or regulation. Even though many solutions for WMNs to
recover from wireless link failures have been proposed,
they still have several limitations as follows. First,
resource-allocation algorithms can provide (theoretical)
guidelines for initial network resource planning. However,
even though their approach provides a comprehensive and
optimal network configuration plan, they often require
global configuration changes, which are undesirable in
case of frequent local link failures. Next, a greedy channel-
assignment algorithm can reduce the requirement of
network changes by changing settings of only the faulty
link(s). However, this greedy change might not be able to
realize full improvements, which can only be achieved by
considering configurations of neighboring mesh routers in
addition to the faulty link(s). Third, fault-tolerant routing
protocols, such as local re routing or multipath routing ,
can be adopted to use network-level path diversity for
avoiding the faulty links. However, they rely on detour
paths or redundant transmissions, which may require more
network resources than link-level network reconfiguration.
With the advances in wireless technologies and the
explosive growth of the Internet, wireless networks,
especially Wireless Mesh Networks (WMNs), are going
through an important evolution. Designing efficient
WMNs has become a major task for networks operators.
Over the last few years, a plethora of studies has been
carried out to improve the efficiency of wireless networks.
However, only a few studies are related to WMNs design
and are mainly concerned with protocol design and routing
metrics optimization. In this paper, we survey different
aspects of WMNs design and examine various methods
that have been proposed either to improve the performance
of an already deployed network or to improve its
performance by a careful planning of its deployment.
WITH THE PROLIFERATION of Internet, Wireless Mesh
Networks (WMNs) have become a practical wireless
solution for providing community broadband Internet
access services. These networks exhibit characteristics that
are novel in the wireless context, and in many ways more
similar to traditional wired networks In Infrastructure
WMNs, Access Points (APs) provide internet access to
Mesh Clients (MCs) by forwarding aggregated traffic to
Mesh Routers (MRs), known as relays, in a multi-hop
fashion until a Mesh Gateway (MG) is reached. MGs act as
bridges between the wireless infrastructure and the
Internet.
WMNs can provide large coverage area, lower costs of
backhaul connections, prolong end-user battery life, and
more importantly provide no LOS (Line Of Sight)
connectivity among users without direct LOS links. Recent
commercial and academic deployments of WMNs in real
world are beginning to demonstrate some of these
advantages. However, several challenges remain so that
a WMN performance in terms of throughput and delays
match the performance of a wired network. Furthermore,
earlier deployments of WMNs have been linked to a
number of problems mainly related to connectivity
problems (such as lack of coverage, dead spots or
obstructions) and performance problems (low throughput
and/or high latency). WIRELESS Mesh Networks
(WMNs) are being developed actively and deployed
widely for a variety of applications, such as public safety,
environment monitoring, and citywide wireless Internet
services
They have also been evolving in various forms (e.g.,
using multi radio/channel systems )to meet the increasing
capacity demands by the above mentioned and other
emerging applications. However, due to heterogeneous and
fluctuating wireless link conditions, preserving the
required performance of such WMNs is still a challenging
problem. For example, some links of a WMN may
experience significant channel interference from other
coexisting wireless networks. Some parts of networks
might not be able to meet increasing bandwidth demands
from new mobile users and applications. Links in a certain
area (e.g., a hospital or police station) might not be able to
use some frequency channels because of spectrum etiquette
or regulation. Even though many solutions for WMNs to
recover from wireless link failures have been proposed,
they still have several limitations as follows. First,
resource-allocation algorithms can provide (theoretical)
guidelines for initial network resource planning. However,
even though their approach provides a comprehensive and
optimal network configuration plan, they often require
global configuration changes, which are undesirable in
case of frequent local link failures.
Next, a greedy channel assignment algorithm can
reduce the requirement of network changes by changing
settings of only the faulty link(s). However, this greedy
change might not be able to realize full improvements,
which can only be achieved by considering configurations
of neighboring mesh routers in addition to the faulty
link(s). Third, fault-tolerant routing protocols, such as local
or multipath routing can be adopted to use network-level
path diversity for avoiding the faulty links. However, they
rely on de-tour paths or redundant transmissions, which
may require more network resources than link-level
network reconfiguration.
LIMITATIONS OF EXISTING APPROACHES
Given the above system models, we now discuss the
pros and cons of using existing approaches for self
reconfigurable WMNs.
LOCALIZED RECONFIGURATION: Network
reconfiguration needs a planning algorithm that keeps
necessary network changes (to recover from link failures)
as local as possible, as opposed to changing the entire
network settings. Existing channel assignment and
scheduling algorithms provide holistic guidelines such as
throughput bounds and
schedule ability for channel assignment during a
network deployment stage. However, the algorithms do not
consider the degree of configuration changes from
previous network settings, and hence they often require
global network changes to meet all the constraints, akin to
edge coloring problems .Even though these algorithms are
suitable for static or
15 periodic network planning, they may cause network
service disruption, and thus are unsuitable for dynamic
network reconfiguration that has to deal with frequent local
link failures.

Next, the greedy channel-assignment algorithm, which
considers only local areas in channel assignments, might
do better in reducing the scope of network changes than the
above-mentioned assignment algorithms. However, this
approach still suffers from the ripple effect, in which one
local change triggers the change of additional network
settings at neighboring nodes due to association
dependency among neighboring radios. This undesired
effect might be avoided by transforming a mesh topology
into a tree topology, but this transformation reduces
network connectivity as well as path diversity among mesh
nodes. Finally, interference-aware channel-assignment
algorithms can minimize interference by assigning
orthogonal channels as closely as possible geographically.
While
this approach can improve overall network capacity by
using additional channels, the algorithm could further
improve its flexibility by considering both radio diversity
(i.e., link association) and local traffic information. For
example, in Fig. 2, if channel 5 is lightly loaded in a faulty
area, the second radio of node can reassociate itself with
the first radio of
node , avoiding configuration changes of other links.
QOS-AWARENESS: Reconfiguration has to satisfy
QoS constraints on each link as much as possible. First,
given each links bandwidth constraints, existing channel
assignment and scheduling algorithms can provide
approximately optimal network configurations. However,
as pointed out earlier, these algorithms may require global
network con-figuration changes from changing local
QoS demands, thus causing network disruptions. We need
instead a reconfiguration algorithm that incurs only local
changes while maximizing the chance of meeting the QoS
demands. For example, if link EH in Fig. 2 experiences a
QoS failure on channel 1, then one simple reconfiguration
plan would be to reassociate R1 of node H to R2 of node E
in channel 5, which has enough bandwidth. Next, the
greedy algorithm might be able to satisfy particular
linksQoS demands by replacing a faulty channel with a
new channel. However, neighboring links, whose channel
has been changed due to ripple effects (e.g., links GH and
HI in Fig. 2), may fail to meet QoS demands if the links in
the new channel experience interference from other
coexisting networks that operate in the same channel.
CROSS-LAYER INTERACTION: Network
reconfiguration has to jointly consider network settings
across multiple layers. In the network layer, fault-tolerant
routing protocols, such as local rerouting [16] or multipath
routing [17], allow for flow reconfiguration to meet the
QoS constraints by exploiting path diversity. However,
they consume more network resources than link
reconfiguration because of their reliance on detour paths or
redundant transmissions. On the other hand, channel and
link assignments across the network and link layers can
avoid the overhead of detouring, but they have to
Take interference into account to avoid additional QoS
failures of neighboring nodes.

II. PROPOSED SYSTEM

Maintaining the performance of WMNs in the face of
dynamic link failures remains achallenging However, such
failures can be withstood (hence maintaining the required
performance) by enabling mr-WMNs to autonomously
reconfigure channels and radio1 assignments.
a. Recovering from link-quality degradation: The
quality of wireless links in WMNs can degrade (i.e., link-
quality failure) due to severe interference from other
collocated wireless networks .For example, Bluetooth,
cordless phones, and other coexisting wireless networks
operating on the same or adjacent channels cause
significant and varying degrees of losses or collisions in
packet transmissions, as shown in By switching the tuned
channel of a link to other interference-free channels, local
links can recover from such a link failure.
b. Satisfying dynamic QoS demands: Links in some
areas may not be able to accommodate increasing QoS
demands from end-users (QoS failures), depending on
spatial or temporal locality . For example, links around a
conference room may have to relay too much data/video
traffic during the session. Likewise, relay links outside the
room may fail to support all attendees voice-over-IP calls
during a session break. By reassociating their
radios/channels with underutilized radios/channels
available nearby, links can avoid communication failures.
b. Coping with heterogeneous channel availability:
Links in some areas may not be able to access wireless
channels during a certain time period (spectrum failures)
due to spectrum etiquette or regulation. For example, some
links in a WMN need to vacate current channels if
channels are being used for emergency response near the
wireless links (e.g., hospital, public safety). Such links can
seek and identify alternative channels available in the same
area. Motivated by these three and other possible benefits
of using reconfigurable mr- WMNs, in the remainder of
this paper, we would like to develop a system that allows
mr- WMNs to autonomously change channel and radio
assignments (i.e., self-reconfigurable)to recover from the
channel-related link failures mentioned.
To overcome the above limitations, we propose an
autonomous network reconfiguration system (ARS) that
allows a multi radio WMN (mr-WMN) to autonomously
reconfigure its local network settingschannel, radio, and
route assignmentfor real-time recovery from link
failures. In its core, ARS is equipped with a
reconfiguration planning algorithm that identifies local
configuration changes for the recovery while minimizing
changes of healthy network settings. Briefly, ARS first
searches for feasible local configuration changes available
around a faulty area, based on current channel and radio
associations. Then, by imposing current network
settings as constraints, ARS identifies reconfiguration
plans that require the minimum number of changes for the
healthy network settings.
Next, ARS also includes a monitoring protocol that
enables a WMN to perform real-time failure recovery in
conjunction with the planning algorithm. The accurate link
quality information from the monitoring protocol is used to
identify network changes that satisfy applicationsnew QoS
demands or that avoid propagation of QoS failures to
neighboring links (orripple effects). Running in every
mesh node, the monitoring protocol periodically measures
wireless link conditions via a hybrid link-quality
measurement technique. Based on the measurement
information,
ARS detects link failures and/or generates QoS-aware
network reconfiguration plans upon detection of a link
failure.ARS has been implemented and evaluated
extensively via experimentation on our multi radio WMN
test bed as well as vians2-based simulation. Our evaluation
results show that ARS outperforms existing failure-
recovery methods, such as static or greedy channel
assignments, and local rerouting.
ARS is a distributed system that is easily deployable in
IEEE 802.11-based mr-WMNs. Running in every mesh
node, ARS supports self-reconfigurability via the
following distinct features.
c. LOCALIZED RECONFIGURATION: Based on
multiple channels and radio associations available, ARS
generates reconfiguration plans that allow for changes of
network configuration only in the vicinity where link
failures occurred while retaining configurations in areas
remote from failure locations.
d. QOS-AWARE PLANNING: ARS effectively
identifies QoS - satisfiable reconfiguration plans by: 1)
estimating the QoS satisfiability of generated
reconfiguration plans; and 2) deriving their expected
benefits in channel utilization.
e. AUTONOMOUS RECONFIGURATION VIA LINK-
QUALITY MONITORING: ARS accurately monitors the
quality4 of links of each node in a distributed manner.
Furthermore, based on the measurement sand given
linksQoS constraints, ARS detects local link failures and
autonomously initiates network reconfiguration.
f. CROSS-LAYER INTERACTION: ARS actively
interacts across the network and link layers for planning.
This interaction enables ARS to include a rerouting for
reconfiguration planning in addition to link-layer
reconfiguration. ARS can also maintain connectivity
during recovery period with the help of a routing protocol.

First, ARS in every mesh node monitors the quality of
its outgoing wireless links at every (e.g., 10 s) and reports
the results to a gateway via a management message.
Second, once it detects a link failure(s), ARS in the
detector node(s) triggers the formation of a group among
local mesh routers that use a faulty channel, and one of the
group members is elected as a leader using the well-known
bully algorithm for coordinating their configuration. Third,
the leader node sends a planning-request message to a
gateway. Then, the gateway synchronizes the planning
requestsif there are multiple requestsand generates a
reconfiguration plan for the request. Fourth, the gateway
sends a reconfiguration plan to the leader node and the
group members. Finally, all nodes in the group execute the
corresponding configuration changes, if any, and resolve
the group. We assume that during the formation and
reconfiguration, all messages are reliably delivered via a
routing protocol and per-hop retransmission timer.
LOCALIZED NETWORK RECONFIGURATION
The core function of ARS is to systematically generate
localized reconfiguration plans. A reconfiguration plan is
defined as a set of links configuration changes (e.g.,
channel switch,link association) necessary for a network to
recover from a link(s) failure on a channel, and there are
usually multiple reconfiguration plans for each link failure.
Existing channelassignment and scheduling algorithms
seek optimal solutions by considering tight QoS
constraints on all links, thus requiring a large configuration
space to be searched and hence
making the planning often an NP-complete problem.In
addition, change in a links requirement may lead to
completely different network configurations. By contrast,
ARS systematically generates re-configuration plans that
localize network changes by dividing the reconfiguration
planning into three processesfeasibility, QoS
satisfiability, and
optimalityand applying different levels of
constraints. As depicted in Fig. 3, ARS first applies
connectivity constraints to generate a set of feasible
reconfiguration plans that enumerate feasible channel, link,
and route changes around the faulty areas, given
connectivity and link-failure constraints. Then, within the
set, ARS applies strict constraints
(i.e., QoS and network utilization) to identify a
reconfiguration plan that satisfies the QoS demands and
that improves network utilization most.
Feasible Plan Generation: Generating feasible plans
is essentially to search all legitimate changes in links
configurations and their combinations around the faulty
area. Given multiple radios, channels, and routes, ARS
identifies feasible changes that help avoid a local link
failure but maintain existing network connectivity as much
as possible. However, in generating such plans, ARS has to
address the following challenges.
Avoiding a faulty channel: ARS first has to ensure
that the faulty link needs to be fixed via reconfiguration.
To this end, ARS considers three primitive link changes, as
explained in Table I. Specifically, to fix a faulty link(s),
ARS can use: 1) a channel-switch where both end-radios of
link AB can simultaneously change their tuned channel; 2)
a radio-switch where one radio in node A can switch its
channel and associate with another radio in node B; and a
route-switch where all traffic over the faulty link can use a
detour path instead of the faulty link.

Maintaining network connectivity and utilization:
While avoiding the use of the faulty channel, ARS needs to
maintain connectivity with the full utilization of radio
resources. Because each radio can associate itself with
multiple neighboring nodes, a change in one link triggers
other neighboring links to change their settings. To
coordinate such
propagation, ARS takes a two-step approach. ARS first
generates feasible changes of each link using the
primitives, and then combines a set of feasible changes that
enable a network to maintain its own connectivity.
Furthermore, for the combination, ARS maximizes the
usage of network resources by making each radio of a
mesh node associate itself with at least one link and by
avoiding the use of same (redundant) channel among
radios in one node.

h. Controlling the scope of reconfiguration changes:
ARS has to limit network changes as local as possible, but
at the same time it needs to find a locally optimal solution
by considering more network changes or scope. To make
this tradeoff, ARS uses a hop reconfiguration parameter.
Starting from a faulty link(s), ARS considers link changes
within the first hops and generates feasible plans. If ARS
cannot find a local solution, it increases the number of
hops so that ARS may explore a broad range of link
changes. Thus, the total number of reconfiguration changes
is deter-mined on the basis of existing configurations
around the faulty area as well as the value of .Let us
consider an illustrative example in
. Given the failure in link CI, ARS firstgenerates
feasible and desirable changes per link (gray columns)
using the primitives. Here, the changes must not include
the use of a faulty or redundant channel. Next, ARS
combines the generated per-link primitives of neighboring
links to generate a set of feasible plans. During the
combination, ARS has to
preserve link and/or radio connectivitys. For example,
plans and in Fig. 4 cannot be connected because each
change requires the same radio of node to set up different
channels. After the two steps, ARS has 11 feasible
reconfiguration plans by traversing connected changes of
all links considered in the
planning. Note that we set to 2 in this example, but we
will show the impact of on the planning.
QOS- SATISFIABILITY EVALUATION: Among a set
of feasible plans , ARS now needs to identify QoS-
satisfying reconfiguration plans by checking if the QoS
constraints are met under each plan. Although each
feasible plan ensures that a faulty link(s) will use non
faulty channels and maintain its connec-tivity, some plans
might not satisfy the QoS constraints or may even cause
cascaded QoS failures on neighboring links.

III. CONCLUSION

The above works shows that the routing protocols have
more disadvantages like global reconfiguration, lack of
quality of service , lack of monitoring of the network etc
.so a new schematic is needed so as to ensure that the
network performance does not degrades and constant
network failure is stopped. In the future work we present
an autonomous network reconfiguration system (ARS) that
enables a multi radio WMN to autonomously recover from
wireless link failures. ARS generates an effective
reconfiguration plan that requires only local network
configuration changes by exploiting channel, radio, and
path divers i t Furthermore, ARS effectively helps in
identifies reconfiguration plans that satisfy applications
QoS constraints, admitting upto two times more flows than
static assignment, through QoS aware planning. Next,
ARSs online reconfigurability allows for real-time failure
detection and network reconfiguration, thus improving
channel
Efficiency by 92%.

REFERENCES
[1] P. Kyasanur and N. Vaidya, Capacity of multi-channel wireless
networks: Impact of number of channels and interfaces, in Proc.
ACMMobiCom, Cologne, Germany, Aug. 2005, pp. 4357.

[2] K. Ramanchandran, E. Belding-Royer, and M. Buddhikot,
Interference-aware channel assignment in multi-radio wireless
meshnetworks, in Proc. IEEE INFOCOM, Barcelona, Spain, Apr.
2006,pp. 112.
[3] R. Draves, J. Padhye, and B. Zill, Routing in multi-radio, multi-hop
wireless mesh networks, in Proc. ACM MobiCom, Philadelphia, PA,Sep.
2004, pp. 114128.

[4] J. Zhao, H. Zheng, and G.-H. Yang, Distributed coordination in
dynamic spectrum allocation networks, in Proc. IEEE DySPAN,
Baltimore, MD, Nov. 2005, pp. 259268.

[5] M. J. Marcus, Real time spectrum markets and interruptible
spectrum: New concepts of spectrum use enabled by cognitive radio, in
Proc. IEEE DySPAN, Baltimore, MD, Nov. 2005,
pp. 512517.

[6] M. Alicherry, R. Bhatia, and L. Li, Joint channel assignment and
routing for throughput
optimization in multi-radio wireless mesh networks, in Proc. ACM
MobiCom, Cologne, Germany, Aug. 2005, pp. 5872.

[7] M. Kodialam and T. Nandagopal, Characterizing the capacity
region in multi-radio multichannelwireless mesh networks, in Proc.
ACMMobiCom, Cologne, Germany, Aug. 2005, pp.
7387.

[8] D. Aguayo, J. Bicket, S. Biswas, G. Judd, and R. Morris, Link-
levelmeasurements from an
802.11b mesh network, in Proc. ACM SIGCOMM, Portland, OR, Aug.
2004, pp. 121132. 51

[9] A. Akella, G. Judd, S. Seshan, and P. Steenkiste, Self-management
in chaotic wireless deployments, in Proc. ACM MobiCom, Cologne,
Germany, Sep. 2005, pp. 185199.

10] J. Zhao, H. Zheng, and G.-H. Yang, Distributed coordination in
dynamic spectrum
allocation networks, in Proc. IEEE DySPAN, Baltimore, MD, Nov.
2005, pp. 259268.

[11] M. J. Marcus, Real time spectrum markets and interruptible
spectrum: New concepts of spectrum use enabled by cognitive radio, in
Proc. IEEE DySPAN, Baltimore, MD, Nov. 2005, pp. 512517.

[12] M. Alicherry, R. Bhatia, and L. Li, Joint channel assignment and
routing for throughput
optimization in multi-radio wireless mesh networks, in Proc. ACM
MobiCom, Cologne, Germany, Aug. 2005, pp. 5872.

[13] M. Kodialam and T. Nandagopal, Characterizing the capacity
region in multi-radio multichannelwireless mesh networks, in Proc.
ACMMobiCom, Cologne, Germany, Aug. 2005, pp.
7387 .

ISBN: 9788192057569 :: doi: 10. 73669/ISBN_0768
Solar Tracking Fuzzy Control System Using AVR Microcontroller

B. B.Sonawane R. D. Kokate,
S.S.V.P.Ss C.O.E. Dhule MGMs Jawaharlal Nehru Engineering College,
Maharashtra Aurangabad, Maharashtra (India).

.
Abstract solar tracking system based on fuzzy logic System
implemented on AVR microcontroller. Four LDR light
sensitive devices are mounted on the solar panel and placed in
an enclosure. Each pair of the light sensors is used to sense
the controller on the orientation of the solar panel vertically
and horizontally respectively. Solar tracking allows for
getting more solar intensity. The solar panel to remain
aligned to the sun at a right angle to the rays of light. The
control circuit for the solar tracker is based on an AVR
microcontroller. This is programmed to detect the Sunlight
through the photocells and then drive the motor to position
the solar panel where it can receive maximum sunlight.

Keywordssolar tracking, two-axis tracking, AVR
Microcontroller, fuzzy control.
I. INTRODUCTION
The green energy also called the regeneration energy,
has gained much attention nowadays. The green energy
can be recycled, such as solar energy, water power, wind
power, biomass energy, terrestrial heat, sea waves,
morning and evening tides, etc. Among them, solar energy
is the most powerful resource that can be used to generate
power. So far the efficiency of generating power of solar
energy is relatively low. Thus, how to increase the
efficiency of generating power of solar energy is very
important.
A solar panel receives the most sunlight when it is
perpendicular to the suns rays, but the sunlight direction
changes regularly with changing seasons and weather.
Currently, most solar panels are fixed, i.e., the solar array
has a fixed orientation to the sky and does not turn to
follow the sun. To increase the unit area illumination of
sunlight on solar panels, we designed a solar tracking
system. The design mechanism holds the solar panel and
allows the panel to move clockwise or anticlockwise
direction to track the suns movement during the day and
improve the overall system to getting maximum intensity
from Sun. This system can achieve the maximum
illumination and energy concentration and cut the cost of
electricity by requiring fewer solar panels, therefore, it has
great significance for research and development referred
from [1-4].
In this paper, the main goal is to design and implement
a solar tracking control system using AVR
Microcontroller. The light sensitive resistors are used.
Feedback signals are delivered to the assigned chip through
an A/D converter. Then we developed a fuzzy controller
and implement it on the controller. Finally, a comparison
between the tracking system and the fixed system is made.
From the experimental results, the proposed tracking
system is verified more efficiently getting maximum
intensity than the fixed system.
II. SOLAR TRACKING SYSTEM
Solar tracking system has multiple functions and uses
two motors as the drive source, conducting an approximate
vertical and horizontal rotation of the solar panel (see
Figure 1). The two drive motors are decoupled, i.e., the
rotation angle of one motor does not influence that of the
other motor, reducing control problems. Additionally, the
tracker does not have the problems common to two axis
mechanical mechanisms (that one motor has to bear the
weight of the other motor). This implementation minimizes
the systems power consumption during operation and
increases efficiency and the total amount of intensity
accumulated.

Figure 1. Solar Tracking Array Architecture Scheme

The solar tracking system we designed based on the
considerations described previously.
The mechanism must support the solar panel and allow
the panel to conduct vertical or horizontal rotation within a
certain amount of space. The system mechanism has two
advantages:
a. High photoelectric conversion efficiency

Because the flexible panel of the solar tracker array
can conduct clockwise or anticlockwise rotation, tracking
the sun in real time, the system efficiently tracking
maximum intensity from sun.
b. Simple, energy-saving controls
The two rotational dimensions of the solar tracker are
controlled by two independent drive sources. The rotation
angles are decoupled and neither one has to bear the weight
of the other one. Additionally, the overall movement
inertia is dramatically reduced.

III. SOLAR TRACKER CONTROL BLOCK
DIAGRAM

Figure 2. Solar Tracker Control Block Diagram
We used the AVR Microcontroller to perform solar
tracking. The design combines AVR processor with a two-
axis motor tracking controller to integrate peripherals such
as microprocessor, memory, and I/O. This integration
accelerates development while maintaining design
flexibility, reduces the circuit board costs with a single-
chip solution, and simplifies product testing referred
from[1-4].
We have implemented the systems logic AVR control
circuit. Figure 3 shows the tracking control flow chart. The
system starts when we turn on the tracking control circuits
power supply switch. The tracking control circuit performs
system tracking, energy saving, and system protection, as
well as a designed control mode and external anti-
interference measures. External interference includes
weather influences, such as wind, sand, rain, snow, hail,
salt damage (i.e., salt erosion on the mechanism).

Figure 3.Flow Diagram of the Tracking Control
The tracking sensor is composed of four similar CdS
sensors, which are located at the east, west, south, and
north to detect the light source intensity in the four
orientations. The CdS sensor forms a 45 angle with the
light source. At the CdS sensor positions, brackets isolate
the light from other orientations to achieve a wide-angle
search and quickly determine the suns position (see Figure
4). The four sensors are divided into two groups, east/west
and north/south. In the east/west group, the east and west
CdS sensors compare the intensity of received light in the
east and west. If the light source intensity received by the
sensors is different, the system obtains signals from the
sensors output voltage in the two orientations. The system
then determines which sensor received more intensive light
based on the sensor output voltage value interpreted by
voltage type A/D converter (ADC).
The system drives the step motor towards the
orientation of this sensor. If the output values of the two
sensors are equal, the output difference is zero and the
motors drive voltage is zero, which means the system has
tracked the current position of the sun. The north/south
sensors track the position of the sun similarly.

Figure 4. Tracking Sensor Design
IV. DESIGN ARCHITECTURE OF AVR
MIRCROCONTROLLER

Fig 5.System Architecture
As shown in Fig. 5 processor is the control center and
integrates our two-axis control chip. The ATmega16 single
chip Risc microcontroller is the brain of the tracking
system. This micro-controller contains 16k bytes of
program memory, a 1KByte Internal of temporary data
SRAM and 512 Bytes of EEPROM. It also contains 8
multiplexed analog channels, a 10 bits analog converter
and a 4 PWM generator module. These features make the
AVR useful and powerful single chip micro-controller in
designing embedded systems referred from[7].
We designed a tracking sensor to determine the
orientation of the solar light source. The signals fed back
by the sensor form the basis of the controller input. The

control design outputs the signals to control the two axis
step motor and the solar tracking control system.

V. FUZZY CONTROLLER DESIGN
The fuzzy sets concept was proposed by Zadeh in
1965[4]. The fuzzy algorithm can make human knowledge
into the rule base to control a plant with linguistic
descriptions. It relies on expert experience instead of
mathematical models. The advantages of fuzzy control
include good popularization, high faults tolerance, and
suitable for nonlinear control systems.
A fuzzy controller design has four parts, fuzzification,
control rule base, fuzzy inference, and defuzzification. The
block diagram of the fuzzy control system is shown in Fig.
6.

Figure 6.Solar Energy Fuzzy Control System Structure
At first, the sun light illuminates on a light sensitive
resistor of the solar tracking device. Then a feedback
analog signal will be produced and transformed into a
digital signal through an analog/digital converter. When
the voltage on the eastward-westward direction or the
southward-northward direction is different, the differences
will be delivered into the fuzzy controller. Then, the fuzzy
controller produces pulses to motor drivers and the motor
drivers produce signals to control step motors for tuning
desired angles. Note that if the differences of sensors are
zero, i.e., the sun is vertical to the solar panel, so the fuzzy
controller does not work. Since the sun moves very slow,
the fast rotating speed of the solar tacking device is with
high speed rotation not necessary. By fuzzy control, some
advantages such as necessary. By fuzzy control, some
advantages such as reducing consumption power of step
motors and fast and reducing consumption power of step
motors and fast and smooth fixed position can be achieved.
Therefore, the fuzzy control algorithm has enough ability
to complete this goal.
Since the corresponding light sensitive resistors can
operate independently, it can be seen as independent
control. For one motor control, the error of output voltages
of corresponding sensors can be set as input variables. The
rotation time of the stepping motors for clockwise and
counterclockwise are output variables. The membership
functions are shown in Fig. Five fuzzy control rules are
used, as shown in the following.
Rule 1If e is PB, then Uf is PB.
Rule 2If e is PS, then Uf is PS.
Rule 3If e is ZE, then Uf is ZE.
Rule 4If e is NB, then Uf is NB.
Rule 5If e is NS, then Uf is NS.
In this paper, product inference is applied for fuzzy
inference. The center of gravity method is adopted for

Figure.7 Defuzzification

Defuzzification to achieve a practical operation value.
The defuzzification is shown in 7.referred from [5-6].

This defuzzification method is implemented by digital
circuits.
VI. Result
The following readings were obtained for designed
solar tracking system shown in table 1.
Table 1
Nos Time in Hrs Measured voltage
value of Solar panel
1 10am 0.6v
2 11am 1.2v
3 12pm 1.8v
4 1pm 2.4v
5 3pm 1.8v


VII. CONCLUSION
In this paper a solar tracking control system is
implemented with hardware. The fuzzy controller is
designed and implemented on AVR controller embedded
system. The light sensitivity resistors are used to determine
the solar light intensity. The proposed solar tracking
system can track the sun light automatically. Thus,
maximum intensity of Sun tracked by solar panel.
REFERENCES
[1] D. A. Pritchard, Sun tracking by peak power positioning for
photovoltaic concentrator arrays, IEEE Contr. Syst. Mag., vol. 3, no. 3,
pp. 2-8, 1983.
[2] Konar and A. K. Mandal, Microprocessor based automatic sun
tracker, IEE Proc. Sci., Meas. Technol., vol. 138, no. 4, pp. 237-
241,1991.
[3] B. Koyuncu and K. Balasubramanian, A microprocessor controlled
automatic sun tracker, IEEE Trans. Consumer Electron., vol. 37, no. 4,
pp. 913-917, 1991.
[4] L. A. Zadeh, Fuzzy sets, Inform. and contr., vol. 8, pp. 338-353,
1965.
[5] L. A. Zadeh, Fuzzy Algorithms, Inform. and contr., vol. 12, pp.
94-102, 1968.
[6] E. H. Mamdani, Application of fuzzy algorithms for control of a
simple dynamic plant, in Proc. Inst. Elect. Eng., vol. 121, pp. 1585-1588,
1974.
[7] DhananjayV.GadreProgramming and customizing AVR
Microcontroller.


Part IV
ICCA 12
Volume 3

ISBN: 978-81-920575-6-9 :: doi: 10. 74334/ISBN_0768
Quantum- dot Cellular Automata to Significantly Reduce the Size of
Super Computers
Karthikeyan Damodaran, Jaideep. H. Lakhani , A. Arun Kumar , S. Deepak
Department of Computer Science and Engineering
Rajiv Gandhi College of Engineering and Technology
Affiliated to Pondicherry University
Pondicherry-607402, India

Abstract- Quantum Computing describes computing
that uses extremely small or Nanoscale, devices.
The Integrated Circuits (IC) industry, however, looks to the
future to determine the smallest electronic devices possible
within the limits of computing technology. Quantum dots
behave like artificial atoms and molecules in that the
electrons inside of them can have only certain values of
energy, which can be used to represent logic information
robustly. The Quantum-dot Cellular Automata
(QCA) architecture uses arrangements of single electron
that communicate with each other by Coulomb repulsion
over large arrays. The arrangement of electrons at the edges
provides the computational output. The electron
arrangements of QCA are controlled by an external clock
and operate according to the rules of Boolean logic.

The QCA devices rely on the quantum mechanical
effects such as Electron Tunneling that are starting to
hinder transistor operation. The fundamental unit of QCA
is the QCA cell created with four Quantum-dots positioned
at the vertices of a square. The electrons in cells are placed
adjacent to each other will interact. As a result, the
polarization of one cell will be directly affected by the
polarization of its neighboring cells. This interaction forces
neighboring cells to synchronize their polarization.
Therefore, an array of QCA cells acts as a wire and is able
to transmit information from one end to another.

Complementary metal-oxide semiconductor (CMOS)
technology has been the industry standard for
implementing Very Large Scale Integrated (VLSI) devices
for the last two decades. Quantum dot Cellular Automata
(QCA) is only one of the many alternative technologies
proposed as a replacement solution to the fundamental
limits.

Key words
Electron tunneling, Quantum Mechanics, Quantum dots,
Boolean logic, CMOS.

I. INTRODUCTION
The Quantum-dot Cellular Automata
(QCA) which is an extension of Cellular Neural
Networks (CNN) uses arrangements of single
electrons that communicate with each other by
Coulomb repulsion over large arrays. The
arrangement of electrons at the edges provides the
computational output. The electron arrangements of
QCA are controlled by an external clock and operate
according to the rules of Boolean logic. The
quantum-dot cellular automata or QCA, consists of
planar arrays called QCA cells. These cells have
features on the very low nanometer scale, much
smaller than the smallest transistor. The QCA devices
rely on the quantum mechanical effects such as
electron tunneling that are starting to hinder transistor
operation.

II. QUANTUM DOT AND ITS
STRUCTURE

Quantum dots are Nanostructures created from
standard semiconductive materials such as
InAs/GaAs[2]. These structures can be modeled as a
3-dimensional quantum wells, exhibiting energy
quantization effects. A quantum dot can indeed be
visualized as a well. Electrons, once trapped inside
the dot, do not possess the energy required to escape.
We can use quantum physics to our advantage
because the smaller a quantum dot is physically, the
higher the potential energy necessary for an electron
to escape.


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ISBN: 978-81-920575-6-9 :: doi: 10. 74341/ISBN_0768
Resource Aware Scheduling of Slow Running Task in Data Parallel Computing

Bhushan Kandalkar
ME Student, Computer Department
Pune Institute of computer
Technology, India

Shyam Deshmukh
Assistant Professor,
I.T. Department,
Pune Institute of Computer
Technology, India
Kalyani Mehunkar
Assistant Professor,
Computer Department
Pune Institute of computer
Technology, India

Abstract MapReduce is a popular data parallel computing
model in shared nothing system that has been deployed on large
cluster of computers to process data generally in Petabyte. A
crucial factor that affects the response time of job is
rescheduling of slow tasks at nodes in cluster. Current
implementations of scheduler only considers the past progress
information of node while choosing a node for launching slow
task on it which causes over utilization of resources currently
present at that node and hence increases the response time of
job as it does not consider the current resource availability at
node and resource requirement of task for getting executed on
it. Here we propose a task scheduler which schedules task at
nodes considering the resource availability at node and resource
requirement of task for efficiently executing slow task on it
which helps in reducing response time of job.

Keywords MapReduce; Scheduler; Data Parallel
Computing; Distributed system; Distributed programming
I. INTRODUCTION
Data parallel computing in shared nothing system means
executing same task on different chunks of data which is
distributed on different nodes in cluster that does not share
anything . In the world of internet lots of data generally in
Petabyte gets produced everyday in the industrial
organization like Facebook, Yahoo, Google etc. This data
gets produced when user clicks on the links , write comment
etc. This invaluable data can be used to improve online
advertising strategies, user satisfaction etc. depends on
organizational needs. The problem is how to store and
process this big amount of data.As we know there is
restriction on processing power of single machine. So how
to process that data is currently a big question for
organizations. Thus the concept of data parallel computing
in shared nothing system arise which leads to formation of
many parallel programming model for processing large
amount of data. One of the most promising and efficient
programming model is MapReduce[1] which is developed
by Google in 2004.
The MapReduce programming [2] allows programmers to
specify a map function that processes a key/value pair to
generate an intermediate key/value pairs, and a reduce
function that merges all the intermediate key/value pairs to
produce the required output. Hadoop is the most popular
open source implementation of MapReduce. Programs
written in MapReduce functional style are automatically
parallelized and executed on a large cluster of commodity
machines. The run-time system takes care of the details of
partitioning the input data, scheduling the program's
execution across a set of machines, handling machine
failures, and managing the required inter-machine
communication. This allows programmers without any
experience with parallel and distributed systems to easily
utilize the resources of a large distributed system. The
performance of a parallel system like MapReduce system
closely ties to its task scheduler. Although Hadoop
scheduler [3] , LATE scheduler [4], Capacity scheduler [5] ,
Fair scheduler [6] and dynamic priority scheduler [7] also
launch backup tasks for slow tasks, they cannot find the
appropriate tasks which are really prolong the execution
time of the whole job because the two scheduler always use
a static way to find slow tasks. They does not consider the
current system level information such as CPU frequency
and memory usage which are main parameters for reducing
the response time of job. On the other hand,Scheduler
incorporates current system level information reducing the
job response time.
The rest of this paper is organized as follows: Section II
describes the Related work. In Section III we presented the
Proposed task scheduling algorithm. We conclude our work
in section IV.
II. RELATED WORK
The scheduling of a set of tasks in a parallel system has
been investigated by many researchers. Many schedule
algorithms has been proposed [8, 9, 10, 11, 12]. [11,12]
focus on scheduling tasks on heterogeneous hardware, and
[8,9,10] focus on the system performance under diverse
workload.
In order to understand the task scheduler, this section
provides a brief view of MapReduce. It first introduces the
preliminary knowledge about MapReduce and then
overviews the related work.
A. The MapReduce Programming Paradigm

MapReduce is a programming model for processing
large data set. The computation takes a set of input
key/value pairs and produces a set of output key/value pairs.
The user of the MapReduce library expresses the
computation as two functions Map and Reduce.Figure.1
depicts a Execution Overview of MapReduce Framework
Input data is split into independent blocks, which are
processed by the map tasks in parallel. Each map task
processes a single block consisting of some number of
records.

Fig.1 Execution Overview of MapReduce
Framework

Each record in turn consists of a key/value pair. A map
task applies the user defined map function to each input
key/value pair and produces intermediate key/value pairs.
The framework then sorts the intermediate data, and
forwards them to the reduce tasks via interconnected
networks. After receiving all intermediate key/value pairs
with the same key, a reduce task executes the user defined
reduce function and produces the output data. Finally, these
output data are written back to the distributed file system.

Moving computation close to the data is a design goal in
the MapReduce framework. In the MapReduce framework,
any application is specified by jobs.There is a single server,
called the Master, that keeps track of all jobs in the whole
distributed system. The Master runs a special process, called
the JobTracker, that is responsible for task assignment and
scheduling for the whole system. For the rest of servers that
are called the slaves, each of them runs a process called the
TaskTracker. The TaskTracker schedules the several tasks
assigned to the single server in a way similar to a normal
operating system.

B. Default Scheduler in Hadoop

Hadoop is the most popular open source
implementation of MapReduce. A Hadoop system runs on
top of a distributed file system, called the Hadoop
Distributed File System. HDFS usually runs on networked
commodity PCs, where data are replicated and locally stored
on hard disks of each machine. To store and process huge
volume of data sets, HDFS typically uses a block size of
64MB.This is used in default with Hadoop without any
extra configuration. It operates using a FIFO queue.
Scheduling in Hadoop is centralized and worker initiated.
Scheduling decisions are taken by a Master node, called the
JobTracker, whereas the worker nodes, called TaskTrackers
are responsible for task execution. The JobTracker
maintains a queue of currently running jobs, states of
TaskTrackers in a cluster, and list of tasks allocated to each
TaskTracker. Every TaskTracker periodically after every 3
seconds reports its state to the JobTracker via a heartbeat
mechanism.Heartbeat message is a mechanism by which the
Master node knows that the slave is alive.Task or worker
failures are dealt by relaunching tasks. The JobTracker
keeps track of the heartbeats received from the workers and
uses it in task assignment. If a heartbeat is not received from
a TaskTracker for a specified time interval, then that
TaskTracker is assumed to be dead. The JobTracker then
relaunches all the tasks previously assigned to the dead
TaskTracker, that could not be completed. Hadoop looks at
the average progress score of each category of tasks (maps
and reduces) to define a threshold for speculative execution.
When a tasks progress score is less than the average for its
category minus 0.2, and the task has run for at least one
minute, it is marked as a straggler. All tasks beyond the
threshold are considered equally slow, and ties between
them are broken by data locality also it does not consider
the time left for the task to complete execution. Thus the
probability of executing the slowest task gets decreases and
thus speculative execution does not effect much on reducing
the response time of job.

C. LATE Scheduler

LATE schedulers consider the phenomenon of
calculating the remaining time of task for execution. It
speculatively execute the task that it think will finish
farthest into the future. Because this task provides the
greatest opportunity for a speculative copy to overtake the
original and reduce the jobs response time. LATE
Scheduler estimate the Progress rate(PR) of each task as
PR = PS/T
where T is the amount of time the task has been running
for, and then estimate the time to completion (TTC) of task
as
TTC = (1 PS)/PR
But it has drawback. LATE scheduler uses the past
Hadoop-level information to estimate the response time of
tasks and it is not suitable for environments with dynamic
loading. Based on current load the capability of TaskTracker
varies thus if we assign a task based on past Hadoop-level
information and if current resources at TaskTracker are not
sufficient to execute that task efficiently then the probability
of the task which we assign to TaskTracker to improve the
job response time decreases and the probability that
assigned task becomes straggler increases.

III. PROPOSED TASK SCHEDULING ALGORITHM

The Proposed Task Scheduling algorithm gets current
resource information of CPU and MEMORY usage of
TaskTracker also resource requirement of tasks for getting
executed on it such as required CPU and MEMORY
availability. By using this resource information scheduler
schedules tasks that utilize availability of resources
currently present at TaskTracker and decreases execution
time of job compared with Hadoop and LATE scheduler.
The Algorithm illustrates the process of scheduling.

Subsection III-A describes how to find slow task.
Subsection III-B describes how to get current system level
resource information of TaskTracker and resource
requirement of task for getting executed on it. Subsection
III-C describes how to classify tasks as Good and Bad and
assign probability to them. Subsection III-D describes when
Scheduler launches backup tasks.
Finding Slow Tasks
TaskTrackers periodically sends heartbeat message to
scheduler.Out of that all or some of the TaskTracker
demands for execution of task on it based on slot
availability of task on it. In order to find slow task our
scheduler uses the progress score (P) of task. The P has
range from 0 to 1.i.e 0<P<1.
The P of ith task = P[i]
P for Map Task (M) is the fraction of input data read
and P for Reduce Task (R) is divided into three phases
such as copy , sort and reduce phase each of which has
score of 1/3 Suppose the number of tasks which are being
executed is N, the number of key/value pairs need to be
processed in a task is C, the number of key/value pairs that
have been processed in the task is D. Let the task has
finished H phases only for reduce task.
The following equation (1) & (2) gives the P of M and
R
PS = D/C for M
(1)
PS = 1/3 ( H+ M/N) for R
(2)
Pavg is the average progress score of N tasks which is
calculated as given by equation (3)
Pavg =
1
/ [ ]
T
i
N P i

(3)
Now , for M and R we look at Pavg to define Threshold
for speculative execution
Threshold Tp is set as given by equation (4)
Tp = Pavg 20%
(4)
If Tasks are below Tp means speculative execution is
needed
Let Ti be the ith task having P[i] as progress score then
Ti needs speculative execution if condition in equation (5)
holds
For task Ti : P[i] < Pavg 20%
i.e. P[i] < Tp
(5)
B. Reading Resource Information of Task and
TaskTracker

From subsection III-A we have tasks which are
progressing slowly. Now for that tasks we calculate their
resource requirement of CPU and MEMORY as Tcf and
Tmu respectively.This can be calculated as how much

Task Scheduling Algorithm :

1: Procedure Scheduler
2: Calculating progress score P of tasks running on
TaskTracker periodically.
3: Calculating Average Progress Score Pavg of
tasks
4: Setting threshold on Pavg as Tp.
5: Calculating slow running tasks S as task which
have P < Tp
6: If scheduler gets tasks Ti below Tp then
i. Read Current resource availability
of CPU and MEMORY as Cu and Mu
respectively of TaskTracker which demand
for
execution of task on it.
ii. For each task Ti S
a. Calculate resource requirement of task as
Tcu
and Tmu
b. Compare Tcu with Cu and Tmu with Mu
c. Using Nave Bayes classifier classify task
as
good G and bad B based on comparison.
d. Assign probability Pr to each task Ti G
Larger the difference greater the probability.
iii. Select a task t G which has the highest
probability.
iv. Schedule the selected slow task for execution
on TaskTracker
.
Else
Schedule a new task K of job J on node
which
demand for task to be executed on it..

7: End procedure

resource i.e. CPU and MEMORY gets consumed by task in
the interval of a minute while it is in execution on
TaskTracker. We modify the heartbeat message to include
current system level information such as CPU usage Cu and
memory usage Mu of TaskTracker which demand for task
for getting executed on it. Periodically TaskTracker send
this information to the scheduler which is hosted on
JobTracker.

C. Classifying Task as Good and Bad
From subsection III-B we have resource availability of
CPU and MEMORY of TaskTrackers and resource
requirement of task for getting executed on TaskTracker.
From this resource information Nave Bayes Classifier [13]
classify task as Good G and Bad B. For good tasks G
scheduler assigns the probability pr to each task where
0<pr<1.The probability 0 means worst task and probability
1 means best task.i.e.the task which does not overload the
resources available at TaskTracker after executing them are
classified as good and task which overload the resources at
TaskTracker are classified as bad tasks. If none of the task
have p<Tp our scheduler schedule a new task k of job J .
D. Launching Backup Task
Using subsection III-C we have tasks which are good for
speculative execution.From that task we have to select only
one task which is best for speculative execution.The
scheduler selects the best task as task which requires least
resource available at TaskTracker i.e. task having highest
probability and thus prevents TaskTracker from over
utilization of resources.

IV. CONCLUSION

The proposed Task Scheduler schedule backup tasks
considering current system level resource information of
TaskTracker and resource requirement of task for getting
executed on TaskTracker. The slow task gets scheduled at
node which is efficient to schedule that task in least amount
of time which helps in reducing the response time of job and
hence the system throughput increases.
.
V. REFERENCES

[1] Jeffrey Dean and Sanjay Ghemawat, MapReduce: Simplified Data
Processing on Large Clusters,In Communications of the ACM, Volume
51, Issue 1, pp. 107-113, 2008.
[2] J. Dean and S. Ghemawat, MapReduce: a flexible data processing
tool, Communications of the ACM, vol. 53, no. 1,pp. 7277, 2010.
[3] Hadoop http://hadoop.apache.org/
[4] Matei Zaharia, Andy Konwinski, Anthony D. Joseph, and Randy
KatzIon Stoica, Improving MapReduce Performance in Heterogeneous
Environments, Proceedings of the 8th conference on Symposium on
Opearting Systems Design & Implementation
[5]Hadoops Capacity Scheduler
http://hadoop.apache.org/core/docs/current/capacity_scheduler.html.
[6] Matei Zaharia, The Hadoop Fair Scheduler
http://developer.yahoo.net/blogs/hadoop/FairSharePres.ppt
[7]Dynamic Priority Scheduler for Hadoop.
http://issues.apache.org/jira/browse/HADOOP-4768.
[8] M.J. Atallah, C.L. Black, D.C. Marinescu, H.J. Siegel and
T.L.Casavant, Models and algorithms for co-scheduling compute-
intensive tasks on a network of workstations, Journal of Parallel and
Distributed Computing 16, 1992, pp.319327
[9] D.G. Feitelson and L. Rudolph, Gang scheduling performance
benefitsfor fine-grained synchronization, Journal of Parallel and
Distributed Computing 16(4),December 1992, pp.306318
[10] J.K. Ousterhout, Scheduling techniques for concurrent systems, in
Proc. of 3rd Int. Conf. on Distributed Computing Systems,
May1982,pp.2230.
[11] H. Lee, D. Lee and R.S. Ramakrishna, An Enhanced Grid Scheduling
with Job Priority and Equitable Interval Job Distribution, The first
International Conference on Grid and Pervasive Computing, Lecture Notes
in Computer Science, vol. 3947, May 2006, pp. 53-62
[12] A.J. Page and T.J. Naughton, Dynamic task scheduling using genetic
algorithms for heterogeneous distributed computing, in 19th IEEE
International Parallel and Distributed Processing Symposium, 2005.
[13] Visalakshi P and Karthik TU , MapReduce Scheduler Using
Classifiers for Heterogeneous Workloads IJCSNS International Journal of
Computer Science and Network Security.
ISBN: 978-81-920575-6-9 :: doi: 10. 74348/ISBN_0768
Performance Enhancement of DWT Processing using GPGPU
K Phani Tejaswi, Thara Nair, A V V Prasad
National Remote Sensing Centre
Indian Space Research Organisation
Hyderabad, India

Abstract Image compression refers to curtailing the size of an
image without degrading its quality to an unacceptable level.
Compression techniques like Discrete Wavelet Transform,
which has been adopted by Consultative Committee for Space
Data Systems (CCSDS), has been shown to be effective in
ensuring the quality of imagery. Being computationally
expensive, the computational requirements cannot be satisfied
by traditional computational environments in real time.
Graphical Processing Units (GPU) which have recently come
out in high performance computing applications, as a superior
alternative to parallel computing using clusters of traditional
CPUs, can be efficiently employed to speed up Discrete
Wavelet Transform (DWT) processing. This paper investigates
the existing state of art affairs in image data compression,
necessity of deployment of GPUs for the same, system-level
challenges and quantifies the benefits of integrating GPUs in
such environment. The results demonstrate that substantial
enhancement in performance margin can be achieved with the
optimum utilization of GPU resources and an efficient
parallelization strategy. Nevertheless, the data transfer time
continues to occupy a major chunk of resource timings, which
is yet to be addressed in case of huge data transfers.
Performance results in comparison with the traditional
processing environment have provided a speedup of 6x, with
respect to conventional computing scenario, on realization of
this parallelizing strategy.
Keywords-CCSDS, CUDA, 2-D DWT, GPU
I. INTRODUCTION
The objective of image compression is to reduce
irrelevance and redundancy of the image data in order to
store or transmit data in an efficient form. Image
compression standards bring about many benefits viz. easier
exchange of image files between different devices and
applications, reuse of existing hardware and software for a
wider array of products and existence of benchmarks and
reference data sets for new and alternative developments.
An international standard for image data compression
algorithm was formulated by Consultative Committee on
Space Data Systems (CCSDS) to be applied to two-
dimensional digital spatial image data from a variety of
payload instruments and to specify how this compressed
data shall be formatted into segments to enable
decompression at the receiving end.
This paper focuses on the image decorrelation module of
CCSDS standard viz. employing Discrete Wavelet
Transform. The paper is organized into eight sections. The
second section presents a comparison of the various
compression algorithms followed by the details of float and
integer as well as forward and inverse Discrete Wavelet
transforms. The succeeding section provides the necessity of
employing GPUs in DWT compression. Subsequent section
provides a prelude to GPUs and its design challenges. This
is followed by the parallelization strategies and the GPU
design configuration we have adopted. Finally, in the last
section, the results and a comparative assessment of the
technique employed using GPUs with the traditional
processors (CPUs) are provided.
II. COMPARISON OF COMPRESSION ALGORITHMS
The key goal of an image compression algorithm is the
best image quality at a given bit-rate with high scalability. In
addition, the Region of Interest coding (ROI) feature is to be
considered, in which certain parts of the image are encoded
with higher quality than others. Yet another criterion is
processing power. The quality of a compression method
often is measured by the peak signal-to-noise ratio and the
RMS error of the reconstructed image. Considering all these
features, many candidate algorithms were proposed viz.
JPEG2000, DWT etc [1].
JPEG is primarily a lossy method of compression.
JPEG2000 provides Region-Of-Interest (ROI) coding. This
can also handle multi-component images e.g., RGB color
images. The main drawback of this algorithm is its high
implementation complexity. This limits the suitability of
JPEG2000 for space-borne missions with high data-
throughput rates and limited capacity of acquisition, storage
and transmission.
Discrete Cosine Transform (DCT) performs efficiently at
medium bit rates. Compared to other input dependent
transforms, DCT has many advantages viz. it can be
implemented in a single integrated circuit, has the ability to
pack most information in fewest coefficients and it
minimizes the block like appearance called blocking artifact
.A shortcoming with DCT is that only spatial correlation of
the pixels inside the single 2-D block is considered and the
correlation from the pixels of the neighboring blocks is
neglected. Blocks cannot be decorrelated at their boundaries
using DCT.
The inherent multi-resolution nature has made wavelet-
coding schemes especially suitable for applications where
scalability and tolerable degradation are important. The
wavelet transform (WT) has gained widespread acceptance
in signal processing and image compression.DWT is used as
basis for transformation in JPEG 2000 standard. DWT
provides high quality compression at low bit rates. DWT
allows good localization both in time and spatial frequency
domain. It also avoids blocking artifacts which degrade
reconstructed images. The transformation on its own accord
introduces inherent scaling. On the other hand, the cost of
computing in DWT is higher compared to DCT and DWT
has a lower quality than JPEG at low compression rates.
Furthermore DWT has a longer compression time.
To summarize, considering its advantages, CCSDS has
adopted DWT as its scheme for image decorrelation.
III. DISCRETE WAVELET TRANSFORM
The CCSDS compressor consists of two functional parts
as depicted in Fig. 1.A DWT module which performs the
DWT decomposition of image data and a Bit-Plane Encoder
(BPE) which encodes the transformed data.
Discrete
Wavelet
Transform
Bit
Plane
Encoder
Input
data
Coded
data

Figure 1. CCSDS Coder- A General Schematic
The image information encoded in a compressed segment
consists of bit planes of DWT coefficients. After decoding
this information, the decompressor selects a reconstructed
value for each DWT coefficient and then performs the two-
dimensional inverse wavelet transform to produce a
reconstructed image.
The CCSDS DWT algorithm which addresses only
grayscale images, having a maximum bit depth of 16 bits, is
intended to be suitable for use in the on-board spacecraft
with sufficiently low algorithm complexity to make high-
speed hardware implementation feasible. This permits a
memory-efficient realization which does not require large
intermediate frames for buffering.
The standard provides both lossy and lossless
compression. Lossless compression using integers
reproduces the original image data exactly, while lossy
compression, by means of floating point calculations, results
in some distortion of the original image due to quantization
and other approximations used in the compression process.
The lossy compression scheme has a higher complexity of
computations, while it provides better compression
effectiveness at low bit rates. The selection of lossy/lossless
compression schemes by the user depends on his
requirement.
Even though the 9/7 biorthogonal float DWT possessed
several advantages in terms of rate/distortion, visual
representation and best compression performance , due to its
computational complexity and lossy nature, integer DWT
was selected. The 9/7 integer DWT offered better rate-
distortion performance than the 5/3 integer DWT when
other parts of the compression algorithm are fixed.
Image decorrelation is accomplished using a two-
dimensional DWT, which is achieved by iterated application
of the one-dimensional DWT. Viewing the image as a data
matrix, consisting of rows and columns of signal vectors, a
single-level 2-d DWT shall be performed on the image in
two steps. In the first step, single l-D DWT is performed
along the rows producing a horizontally low-pass and a
high-pass filtered intermediate data array. This is followed
by the application along the columns to produce four sub
bands as in Fig. 2[1].

Figure 2. 2-D DWT (One Level)
The number of levels of wavelet decomposition is fixed
at three in the CCSDS recommendation to maintain low
complexity.
2D images are usually transformed in both dimensions.
1D DWT transform is first applied to all rows then to all
columns resulting in four sub bands LL, HL, LH, and HH.
The LL sub band is an approximation of the original signal
and can be further transformed recursively, as shown in Fig.
3.

Figure 3. 3-level 2-D DWT Decomposition of an Image
This suggested standard for the decorrelation module
adopts a three-level, two dimensional (2-D), separable
Discrete Wavelet Transform (DWT) with nine and seven
taps for low- and high-pass filters, respectively.
A. Details of 9/7 Integer Forward and Inverse DWT
The advantage of lifting scheme over convolution is in
reduced memory and computational complexity[2]. Lifting
scheme allows for in-place data manipulation and reduces
memory dependencies. An input signal is split into even and
odd subsequences denoted as { and { } respectively.
These values are further modified using alternating
prediction (denoted as p) and update (denoted as u) steps. In
the prediction step, the algorithm takes an odd sample in a
turn and subtracts a linear combination of its (even)
neighbors from it; a prediction error { } is formed:

In the update step, a linear combination of already
modified adjacent odd samples is added to each even sample
and updated even sequence { } is formed:

The 9/7 forward wavelet filter shown in the Fig. 4
requires one lifting step; i.e., there is only one prediction-
update pair

Figure 4. Forward Discrete Wavelet Transform
The formulae shown in the Fig. 5 are the consecutive
filter operations to perform the forward 9/7 wavelet
transform using the lifting scheme.

Figure 5. Forward 9/7 Wavelet Transform
The 9/7 backward wavelet filter shown in the Fig. 6
requires one lifting step; i.e., there is only one prediction-
update pair

Figure 6. Backward Discrete Wavelet Transform
The formulae shown in the Fig. 7 are the consecutive
filter operations to perform the backward 9/7 wavelet
transform using the lifting scheme.

Figure 7. Backward 9/7 Wavelet Transform
IV. DWT IMPLEMENTATION - THE NEED FOR GPU
In future satellite missions with sub-meter resolution,
where the data rates are bound to be high, compression
techniques should be highly efficient to accommodate the
large volume of data that need to be handled in a limited
bandwidth. Additionally, the data received from remote
sensing and other payloads need to be processed in real-time.
This needs enormous computational power, which cannot be
handled rapidly by the present generation processors.
As per CCSDS recommendation, DWT transformation of
the image is the preliminary step in image data compression.
Realization of DWT in traditional processors can be
materialized only through a sequential method of execution.
For small image sizes, the performance achieved may be
adequate. For large image sizes of the order of 4096x4096 or
6144x6144, where considerable performance improvement
may be called for, computation employing traditional
processors may not yield the desired performance. As a
consequence of this scenario, utilization of GPUs (Graphics
Processing Units) has gained momentum in applications
where large volume of data needs to be processed in real-
time.
In this context, the application of General Purpose
Computing using Graphical Processing Unit (GPGPU) for
Inverse DWT transformation of satellite data in real-time, in
synchronism with the acquisition of signal has been thought
of. With GPU computing gaining momentum as a result of
increased hardware capabilities and improved
programmability, this paper presents how a GPU, with
parallel design architecture can boost computational power
appreciably to equal the requirements of handling enormous
data volumes.
The implementation details of 3-level,2-D,9/7 integer
forward and inverse DWT on GPU, the performance
achieved using GPUs and comparative assessment with the
results attained employing traditional processors for
different image sizes are provided in this paper.
V. GPU- AN INTRODUCTION AND OPTIMIZATION
STRATEGIES
This section presents a brief overview of GPU
architecture, programming model and the graphics standard
employed for full resolution image display.

A Graphical Processing Unit or a Graphics Processor
Unit (GPU) is a specialized multiprocessor, traditionally
built for rendering 2D or 3D graphics. Over the years, with
advancements in Very Large Scale Integration (VLSI)
technologies, it has evolved to become a co-processor to the
CPU. Contemporary GPUs are being used for general
purpose computing (GPGPU), which harness the computing
power of the chip to perform certain functions traditionally
handled by the CPU viz. massive scientific and high
performance computing applications.
GPUs are composed of a number of SIMD (single
instruction, multiple data) multiprocessor cores, each with
much less complexity than a CPU core, but nevertheless
supports operations required for general purpose high-
performance computing. Each multiprocessor incorporates a
small but fast shared memory. All processors in the
multiprocessor have direct access to this memory.
Additionally, all multiprocessors have access to three other
device-level memory modules: the global, texture, and
constant memory modules, which are also accessible from
the host. Apart from size, the critical characteristic
differentiating the various memory modules is their access
latency. To achieve maximum performance, applications
should maximize the use of shared memory and
multiprocessor registers.
GPUs process information in parallel. GPUs are designed
for fast execution of many parallel instruction threads. GPUs
can maintain up to 1024 threads per multiprocessor .GPUs
also use SIMT (single instruction, multiple threads) for
scalar thread processing. GPU cores execute the same
instructions simultaneously.
The programming platform that we have chosen is
NVIDIA Corporations CUDA (The Compute Unified
Device Architecture) [3].This is a compiler/language pair
which presents a C-style interface to the GPU. This allows a
programmer to directly develop and express parallel
programming concepts on the GPU. Additionally the
development environment provides a runtime library to
manage task execution, multi-GPU devices, timers, memory,
and per-multiprocessor thread synchronization. The main
advantage of CUDA over most other GPU-APIs is its
flexible access to the GPUs memory, allowing direct access
of the global memory as well as the multiprocessors shared
memory for reading and writing instructions.
Efficient offloading of an algorithm to the GPU implies
extracting the target applications parallelism, and, equally
important, employing efficient memory, data transfer, and
thread management techniques. Improper task
decomposition, memory allocation and management, or data
transfer scheduling can lead to dramatic performance
degradation. The resourceful use of the GPU hardware is
challenging. The threads must be scheduled efficiently and
synchronization between the threads is also essential.
Similarly, efficient use of various memories available, viz.
texture memory, constant memory, shared memory, global
memory and local registers can improve the overall
performance manifold.
Equally challenging is the parallelization of the existing
algorithms. While it is relatively simpler to increase the
degree of parallelism of existing applications, a significant
investment is needed to refactor them to achieve the required
computational gain. Moreover, not all applications offer
sufficient scope for parallelism.
The effective bandwidth of the computations should be
employed as a metric when measuring performance and
optimization benefits. To achieve high computational gain,
data transfer between the host and the device is to be
minimized.
The GPU used for this design set up is nVIDIA Quadro
FX 4800 with 24 multiprocessors or 192 CUDA cores (8
CUDA cores per multiprocessor) and 1.6GB Video RAM[4].
VI. DESIGN APPROACH USING GPGPU
One of the conventional approaches in the computation
of 2-D Discrete Wavelet Transform is design by means of C
language. The entire input image (.pgm file) is passed on to a
two-dimensional array. Row-wise DWT operations were
performed on the image to obtain 1-D DWT which was
followed by column-wise DWT operations to obtain the 2-D
DWT. This was replicated for three levels. For lesser image
dimensions, the performance of the conventional approach
was agreeable to obtain the 3-level, 2-D DWT. But for larger
image sizes (2048x2048 to 6144x6144), the performance
came down drastically as the processing time increased by a
significant margin (Figure -6).
In this scenario, it was indispensable to implement the
same in GPU with an efficient parallelization strategy.
The input image that was available in the host memory
was copied to GPU.A kernel which does both the forward
and inverse Discrete Wavelet Transform operations was
invoked. After the completion of forward DWT, the
compressed image was provided as input to Inverse DWT
function in the kernel. The output of the Inverse DWT
function, which was the original image, was copied back to
the host.
Several optimization strategies [5] were attempted for
maximizing the performance margin of GPUs, as discussed
in Table - I.
TABLE I. OPTIMIZATION APPROACHES INVESTIGATED
Alternatives Studied Implementation Intricacies
Input image was copied to
texture reference bound to
1-D CUDA array as DWT
transforms were carried out
on one dimensional thread
blocks
Restriction on the maximum image
width(2
13
), limited the implementation
for larger image sizes, which was much
warranted
Copied the input image to
texture reference bound to
linear memory
No significant time margin for bigger
images, since it involved copying image
to a linear memory and further binding to
a texture
Image data was to be made
available to shared
memory in each block.
Since the kernel was operating on the
entire image, with each thread working
on a row, the limited shared memory
available per block, made this
impracticable
Copied the image into page
locked memory to ensure
faster execution as no data
copy to device is involved.
The entire image had to be copied to
page-locked memory. Hence, the
performance improvement was
insignificant
The following sub-section furnishes the details of the
parallelization algorithm and its implementation.
A. Realized Algorithm and its Implementation
The entire input image (.pgm file) that was available in
the host memory was copied to GPU global memory.
Subsequent to the availability of data in global memory, a
kernel which does the Discrete Wavelet Transform
operations was invoked. Initially the wavelet transform was
applied row-wise to obtain 1-D DWT for the first level.
Unlike the conventional strategy, the image was not
transposed after the row-wise operations. The design was
modified so as to access the image column-wise while
performing the column-wise operations. Similar operations
were done for 3- levels. After the completion of forward
DWT, the compressed image was provided as input to
Inverse DWT function in the kernel. The inverse wavelet
transform was applied column-wise, followed by row-wise
for each level. This proceeded from third level backwards to
reconstruct the original image.
The flow chart shown in the Fig. 8 summarizes the
algorithm that provided the maximum performance
improvement.

Inputimagewasreadintoa2Darrayinthe
hostandcopiedtoGPUglobalmemory.
Start
RowwiseandcolumnwiseDWToperations
donefor3levelsinthekernelforforwardDWT.
Compressedimagepassedasinputtothe
InverseDWTfunction.
ReconstructedimagewascopiedfromGPU
globalmemorybacktothehostmemory
End

Figure 8. Flow Chart depicting the Algorithm flow
B. Optimization Strategies Incorporated
The entire operations involving the three levels of 2-D
transformation were done with a single kernel call from the
host. The optimization strategies adopted are detailed in
Table - II.
TABLE II. OPTIMIZATION STRATEGIES IMPLEMENTED
Optimization
Strategies Adopted
Description
Parallelization
Strategy
Involves assigning one row per thread, so that
the number of threads is equivalent to the
number of rows in the input image
Threads per block
Number of threads per block was optimally
chosen to be 512
Multiple Kernels
For improved performance margins, multiple
kernels were invoked within the device, so that
the load on the kernel came down considerably
Multiple Kernels
For improved performance margins, multiple
kernels were invoked within the device, so that
the load on the kernel came down considerably
Variable threads per
block
Optimum execution time was obtained by
reducing the total number of threads for lower
levels in both forward and inverse DWT
operations
Block
Synchronization
Synchronization between different row-wise
and column-wise operations was carried out
using syncthreads ()
VII. PERFORMANCE EVALUATION
The developed DWT GPGPU application was
implemented on the following workstation:
CPU : 2xIntel Xeon (2.93 GHz) Quad Core Processor
RAM: 8 GB
GPU : nVidia Quadro FX 4800
Video RAM : 1.6 GB
Consequently, Table- III summarizes the values of our
evaluation parameters for various image dimensions, which
include input transfer time, kernel processing time (forward
and Inverse DWT together) and the output transfer time.
TABLE III. TIME CONSUMED FOR VARIOUS PROCESSING
STAGES
Image Size
Input
Transfer
Time (ms)
Kernel
Processing time
(ms)
Output
Transfer Time
(ms)
2048x2048 1.1 0.09 3.2
4096x4096 3.9 0.19 7.7
6144x6144 8.3 0.19 13.2
8192x8192 14.4 0.19 21.2

From the above table, it is evident that kernel processing
time remains almost same for larger image sizes because of
the parallelization strategy adopted. For a 2048x2048 image,
since multiple kernels were not invoked, the kernel
processing time was one order less. As far as larger images
are concerned, there was an increase in the kernel processing
time, due to splitting of the design into multiple kernels
being invoked from the device. The results can be seen in
Fig. 9.

0
5
10
15
20
25
2
0
4
8
x
2
0
4
8
4
0
9
6
x
4
0
9
6
6
1
4
4
x
6
1
4
4
8
1
9
2
x
8
1
9
2
T
i
m
e
ImageDimension
Input
TransferTime
(ms)
Kernel
Processing
time(ms)
Output
TransferTime
(ms)

Figure 9. Representation of Processing times for varying image
dimensions
The efficiency of the parallelization strategy adopted can
be measured by comparing the GPU execution time with the
CPU execution time. From Fig. 10, it is evident that a
noticeable time gain was obtained using GPU. The quoted
time includes the time for the entire program execution
involving input image file opening, data reading, executing
3-levels of forward and inverse DWT and logging back the
decompressed data in both scenarios. The time was measured
from command line using 'time' command. A maximum
percentage improvement of 600% as compared to traditional
approach was obtained with this parallelization
methodology.
0
5
10
15
20
2
0
4
8
x
2
0
4
8
4
0
9
6
x
4
0
9
6
6
1
4
4
x
6
1
4
4
8
1
9
2
x
8
1
9
2
T
i
m
e
ImageDimension
GPU
Execution
Time(s)
CPU
Execution
Time(s)

Figure 10. Representation of Execution times for varying image
dimensions
The following figures show an extracted view of a
2048x2048 satellite image that was worked upon. Fig. 11
shows a segment of the original image, while Fig. 12 shows
the 2-D DWT output for level 3. A section of the
reconstructed image after inverse DWT is shown in Fig. 13.

Figure 11. Original Image

Figure 12. Output Image for 2-D, 3- level Forward DWT

Figure 13. Reconstructed Image

VIII. CONCLUSION
The Graphical Processing Units act as highly resourceful
parallel processors which accept data from the CPU to
perform repetitive calculations on huge volumes at a very
fast rate. The processed data would then be copied back to
the CPU. The discussed GPU design configuration has
imparted a significant performance improvement compared
to a traditional architecture. GPU performance margin can be
increased by copying the input image to a 2-D texture
reference bound to CUDA array on a two-dimensional
kernel, to be executed on a higher end GPU with larger
number of cores. Additionally, the algorithm design in GPU,
for the subsequent stage of CCSDS image compression viz.
Bit Plane Encoding is being attempted for attaining
improved performance margins.
ACKNOWLEDGMENT
The authors wish to acknowledge the excellent guidance
and support provided by Dr. V K Dadhwal, Director, NRSC
in successfully implementing this work. The support
provided by Sri. Maruthi Chandrasekhar Bh is also duly
acknowledged.

REFERENCES
[1] CCSDS 122.0-B-1, Image Data Compression CCSDS, Blue Book,
November 2005)
[2] CCSDS 120.1-G-1, Image Data Compression CCSDS, Green Book,
June 2007.
[3] NVIDIA.(2010) CUDA ZONE.[Online].http:// www.nvidia.com/
object/ cuda_home_new.html
[4] NVIDIA GPU Programming Guide Version 2.5.0 2006 by NVDIA
Corporation.
[5] David B. Kirk, Wen-mei W.Hwu, Programming Massively Parallel
Processors. Elsevier: 2010

1

ISBN: 978-81-920575-6-9 :: doi: 10. 74355/ISBN_0768
Resource allocation in p2p system using bittorrent
Thamaraiselvi Krishnamoorthy(Student)
Dept of Computer Science&engg
Karpagam university
Coimbatore,India

AbstractIn this paper, we study about p2p systems and
bittorrent, where peers have to share their available resources
between their own and other peers needs. One such example is
a system of peers who use their capacity-limited access links
both for their upstream and downstream connections. In the
selfish approach, each peer would like to exploit his full
capacity on his downloads. However, if all peers acted selfishly,
the system would collapse. In order to motivate peers to
cooperate, we propose a bittorrent used to exploit his full
capacity for his both upstream and downstream. So all peers
act as rationally, trying to achieve their maximum utility
Keywords-component;bittorrent,upstream,downstream
I. INTRODUCTION
P2P model is a communication model in which each
party may act as a client and a server. Both parties have the
same capabilities and both can initiate connection. It is the
opposite of client/server model in the sense that there is no
central entity that the other parties contact but every single
entity is able to initiate connection directly with all other
entities.
Pure P2P[2] communication doesnt need any kind of
central server or database to make a connection. In addition
to pure P2P there are a lot of solutions that are neither pure
P2P nor client/server. They combine characteristics from
both models. What makes them more P2P than client/server
solutions are that the communication channel that is
established will be directly between communicating parties
rather than through some central server.[4]
Our choice is motivated by the observation that
BitTorrent is composed of several interesting mechanisms
that interact in many complex ways depending on the
workload offered. Using a simulator provides the flexibility
of carefully controlling the input parameters of these
mechanisms or even selectively turning off certain
mechanisms and replacing them with alternatives.
Consider ad-hoc construction of the BitTorrent network
and its decentralized operation,[3] it is unclear at the outset
how well the system can utilize the perpendicular
bandwidth between peers. It is a situation that involves
losing one quality or aspect of something in return for
gaining another quality or aspect. It implies a decision to be
made with full comprehension of both the upside and
downside of a particular choice.

II. RESOURCE ALLOCATION
Network of N peers, who provide and consume
bandwidth for content sharing. Peers act both as servers and
clients simultaneously. We consider that the access
technology does not provide strict separation between
upstream and downstream flows; therefore, peers have to
share their link capacity between their uplink and downlink
connections.[2] Examples of such access technologies
include WiFi,WiMAX,Ehternet LANs, etc. There are
implementation tools which can be used to appropriately
adjust the uplink and downlink bandwidth for each
connected user without modifications in the access protocol,
but these issues are out of the scope of this paper.
Peers collect statistics about other peers and form
opinions about them (reputation rating)
0 <= Reputation Rating <= 1
Peers can share reputation ratings
Selection procedure: selects from which peer to
download based on reputation ratings

Table: 1
Name Description
BS Basic request Strategy
RA Reputation-based
Allocation policy
SA Simple Allocation Policy
NS No Strategy
AS Adaptive Strategy
GS Greedy Strategy

A. Homogeneous System

In this section, we consider a homogeneous system of peers
who have the same capacity C and request generSation rate
g and they send their requests to each one of the other peers
of the system with equal probability. In Figure 1, we can see
the performance (average bandwidth per request) of
different combination of strategies and policies for different
peers capacities [1]. The BS/RA scenario stands for the
combination of the basic request strategy (BS) and the
reputation-based allocation policy (RA). In the same way, all
possible scenarios are named. As we can see from the results
1

of Figure 1, the higher the capacity of all peers in the system,
the higher the average bandwidth they receive per request.

Figure 1. Average received bandwidth per request for different capacity
peers
It is obvious that our proposed policies lead to the
cooperation among peers and significantly improve the
performance (average received bandwidth per request) of
the system compared to a system of peers who do not follow
any strategies and reputation based policies (e.g., NS/SA
scheme). AS/RA scheme provides the best results in terms
of average received bandwidth per request, followed by
GS/RA and BS/RA.[1] Next, we would like to delve into the
fairness issues of the different aforementioned schemes. We,
thus, examine the average received and offered resources
from peers and would like to see whether they are
correlated.

Greedy Strategy:
when more than one server offer bandwidth
equal to the requested one. We note here that as soon as
servers decide the portions of their upload capacity that
they will give to each one of their requesters at a given
period p, we consider that they reserve these portions for
their requesters needs for the specific period. If their
requesters cannot absorb these resources, they remain
unexploited.

B.Hetrogeneous System

We investigate a network of cooperative peers with
different capabilities/link capacities.[1] Some of the peers are
more powerful than others. In particular, we study a network
of 100 peers, where 20 percent of them have a total capacity
of 8 Mb/s, 20 percent have one of 7 Mb/s, 20 percent have
one of 6 Mb/s, 20 percent have one of 5 Mb/s, and 20
percent have one of 4 Mb/s.
All peers have a request generation profile of two
requests per period. In Figure 2&3, we can see the average
received bandwidth per request and global reputations of
each category peer for the various schemes, respectively.

Figure 2. Performance of different capacity peers in the network

Figure 3. Global reputation of different capacity peers in the network
C. BitTorrents Choking Algorithm

On a technical level, each BitTorrent peer always
unchokes a fixed number of other peers (default is four), so
the issue becomes which peers to unchoke. This approach
allows TCPs built-in congestion control to reliably saturate
upload capacity. Decisions as to which peers to unchoke are
based strictly on current download rate. Calculating current
download rate meaningfully is a surprisingly difficult
problem; The current implementation essentially uses a
rolling 20-second average[3].
Former choking algorithms used information about long-
term net transfer amounts, but that performed poorly because
the value of bandwidth shifts rapidly over time as resources
go away and become available.
To avoid situations in which resources are wasted by
rapidly choking and unchoking peers, BitTorrent peers
recalculate who they want to choke once every ten seconds,
and then leave the situation as is until the next ten second
period is up. Ten seconds is a long enough period of time for
TCP to ramp up new transfers to their full capacity.
Upload Only

1

Figure 4. No of Complete and incomplete downloaders

Once a peer is done downloading, it no longer has useful
download rates to decide which peers to upload to. The
current implementation then switches to preferring peers
which it has better upload rates to, which does a decent job
of utilizing all available upload capacity and preferring peers
which non else happens to be uploading to at the moment[3].

Newcomers
In this section, we exhibit the behavior of the system
under the case of new peers periodically entering and leaving
the network. As in the previous section, we consider a
network of 100 peers where peers are categorized according
to their total physical capacity; there are five equal-sized
categories of peers with 8, 7, 6, 5, and 4 Mb/s capacities.
However, we consider that 50 percent of each category peers
are permanent in the system (stable), while the remaining 50
percent of each category (capacity) peers stay in the network
only for 100 periods and are replaced by new identity peers
of the same capacity with those who left every 100 periods.
We use this case in order to keep the same analogy of
capacity peers in the system and better investigate the
performance of the system compared to the static one where
no arrivals or departures occur. In Figure 5, we can see the
performance of the stable and newcomers of 8 and 4 Mb/s
capacity peers, when the BS/RA-SS scenario is used. [3]

Figure 5. Performance of stable peers and newcomers

The scenario of this performance of the other capacity
peers and when the GS/RA-SS or AS/RA-SS strategies are
used. What we see from Figure 5 is that the performance of
the stable peers is not much influenced by the presence of the
newcomers, and on the other hand, newcomers behavior is
very close to the one of the stable peers of the same capacity,
despite their short life in the network. We present our
experiments on mitigating message traffic using the Friends-
First technique.
Friends-First takes advantage of the Friend-Cache to try
and locate a positive query response among the known
reputable nodes, before querying the entire system. As we
will see, in a flood-based querying system, this can result
in85% less message traffic. This scenario, which is also
supported by many different scenarios that we run, shows
that newcomers adapt quickly to the network and do not
really affect the performance of the long-lived peers in the
system.
Motivation of Seeds

A well-known deficiency of the memoryless reciprocation
mechanism of BitTorrent[1] is the fact that it does not
provide incentives for seeds (peers who have downloaded a
file) to remain in the system and contribute resources to
others.

Figure 6. Performance of seed

(1) Due to the exponentially decreasing peer arrival rate
in reality, service availability in such systems becomes poor
quickly, after which it is difficult for the file to be located
and downloaded.
(2) Client performance in the BitTorrent[3] like systems
is unstable, and fluctuates widely with the peer population.
(3) Existing systems could provide unfair services to
peers, where peers with high downloading speed tend to
download more and upload less
Table 2:

1

III. FILE SELECTION

File selection mainly focusing for two ways
Random Selection
Local Reputation System
A. File selection:
Select-Best high load on few nodes
Weighted tries to distribute load
Friend-Cache (FC) with max size |FC|
B.Efficiency
Total number of V(R) evaluations

Verification ratio

C.Load
Load on node i:

Average load:
D.Message Traffic

IV. CONCLUSION
In this paper, we presented a complete methodology for
motivating peers using bittorrent to contribute their
resources in a loaded network where the capacity-limited
access link of each peer is shared among his download and
upload streams and BitTorrent chocking algorithm[3] used to
improve their performance and avoid misbehavior between
seeds. motivate seeds to remain and contribute in the system.

REFERENCES

[1] Reputation-Based Resource Allocation in P2P Systems of Rational
Users ieee transcation on parallel&distributed system,vol21,no
4,april2010
[2] Robust Incentive Techniques for Peer-to-Peer Networks
[3] Incentives Build Robustness in BitTorrent
[4] Incentivizing Peers to Contribute Their Resources Workshop on
Economics of Peer-to-Peer Systems June 6, 2003.

ISBN: 978-81-920575-6-9 :: doi: 10. 74320/ISBN_0768
GRID COMPUTING - HIGH LEVEL COMPUTING TO ACCESS INTERNET
FACILITY
R Dinesh,C.Ajit Nataraj
SSN College of Engineering,
Kalavakkam,Chennai,India-603 110

Abstract Today we are in the Internet world and
everyone prefers to enjoy fast access to the Internet. But
due to multiple downloading, there is a chance that the
system hangs up or slows down the performance that leads
to the restarting of the entire process from the beginning.
This is one of the serious problems that need the attention of
the researchers. So we have taken this problem for our
research and in this paper we are providing a layout for
implementing our proposed Grid Model that can access the
Internet very fast. By using our Grid we can easily
download any number of files very fast depending on the
number of systems employed in the Grid. We have used the
concept of Grid Computing for this purpose. The Grid
formulated by us uses the standard Globus Architecture,
which is the only Grid Architecture currently used
worldwide for developing the Grid. And we have proposed
an algorithm for laying our Grid Model that we consider as
a blueprint for further implementation. When practically
implemented, our Grid provides the user to experience the
streak of lightening over the Internet while downloading
multiple files.

I. INTRODUCTION

Grid computing is all about to create the illusion of a
simple yet large and powerful self managing virtual
computer out of a large collection of connected
heterogeneous systems sharing various combinations of
resources. A 'resource' may be computing power, data
storage, analysis/visualization tools, scientific hardware
(a spectrometer, telescope and so on) or any other remote
resource. The Grid aims to bring all these together -- in a
virtual sense -- allowing large or small scale resource
sharing and collaboration.

The standardization of communications between
heterogeneous systems created the Internet explosion.
The uniformity for sharing resources, along with the
availability of higher bandwidth, are driving a possibly
equally large evolutionary step in grid computing.
In a nutshell the grid computing is all about using the
wasted CPU cycles in the network as one virtual
machine, which can compete with supercomputer speed.

II. GENESIS OF GRID COMPUTING

Grid computing can mean different things to different
individuals. The grand vision is often presented as an
analogy to power grids where users get access to
electricity through wall sockets with no care or
consideration for where or how the electricity is actually
generated. In this view of grid computing, computing
becomes pervasive and individual users gain access to
computing resources (processors, storage, data,
applications, and so on) as needed with little or no
knowledge of where those resources are located or what
the underlying technologies, hardware, operating system.
Grid computing can be seen as a path of integrating
various technologies and solutions. Its key values are on
the context of distributed computing infrastructure
technologies that are evolving in support of cross-
organizational application and resource sharing in a
word, virtualization virtualization across technologies,
platforms, and organizations. This kind of virtualization
is only achievable through the use of open standards. An
environment that provides the ability to share and
transparently access resources across a distributed and
heterogeneous environment not only requires the
technology to virtualize certain resources, but also
technologies and standards in the areas of scheduling,
security, accounting, systems management. Autonomic
computing can come into play here too. Various tools
may be able to identify important trends throughout the
grid, informing management of those that require
attention.

III. GRID ORANIZATION
The Grid architecture has a layered approach and
each layer is defined in their, own behavioral manner to
work independently. On integration it works as one
complete well-organized grid model.

3.1. Fabric:
Fabric is the lowest layer in grid architecture. Unlike
in normal computer architecture where the lowest layer
represents logic gates, the fabric is an abstract layer
which represents local computing resources such as
storage, networking and computational resources.

3.2. Connectivity:
Connectivity layer connects several fabrics into one
giant node of fabric. Connectivity layer provides
secure connections and is implemented using network
protocols such as Internet protocol (TCP/IP) and
application protocols (DNS), etc.

3.3. Resource:
Resource layer deals with management of many
connectivity layers. Resource layer can be information
protocols used to obtain information about configuration,
load and usage policies, and management protocol that
negotiate the policies for handling resource requirement
and operations.

3.4. Collective:
Collective layer consist of the protocols of
interactions among several different resources. This layer
includes directory services, accounting payment,
collaboration services, and scheduling services to name a
few.

3.5. Application:
Application layer is the highest layer in grid
computing architecture. This layer calls other layers to
perform desired actions. Application layer is simply the
program we are working with to solve our problems.

IV. GRIDS & TYPES
The three primary types of grids and are summarized
below:

Computational grid
A computational grid is focused on setting aside
resources specifically for computing power. In this type
of grid, most of the machines are high-performance
servers.
Scavenging grid
A scavenging grid is most commonly used with large
numbers of desktop machines. Machines are scavenged
for available CPU cycles and other resources. Owners of
the desktop machines are usually given control over
when their resources are available to participate in the
grid.
Data grid
A data grid is responsible for housing and providing
access to data across multiple organizations. Users are
not concerned with where this data is located as long as
they have access to the data.

V. GRID MODEL PROPOSED
We are using the Scavenging Grid for our
implementation as large numbers of desktop machines
are used in our Grid and later planning to extend it by
using both Scavenging and data Grid. Figure2 gives an
idea about the Grid that we have proposed.

VI. PROBLEMS DUE TO MULTIPLE
DOWNLOADING
While accessing Internet most of us might have faced
the burden of multiple downloading and in particular
with downloading huge files i.e., there can be a total
abrupt system failure while a heavy task is assigned to
the system. The system may hang up and may be
rebooted while some percentage of downloading might
have been completed. This rebooting of the system leads
to download of the file once again from the beginning,
which is one of the major problems everyone is facing
today.
Let us consider N numbers of files of different
sizes (in order of several MBs) are being downloaded on
a single system (a PC). This will take approximately
some minutes or even some hours to download it by
using an Internet connection of normal speed with a
single CPU. This is one of the tedious tasks for the user
to download multiple files at the same time. Our Grid
plays a major role here.

VII. EMPLOYING THE GLOBUS
ARCHITECTURE IN PROPOSED GRID:
While planning to implement a Grid project, we must
address issues like security, managing and brokering the
workload, and managing data and resources information.
Most Grid applications contain a tight integration of all
these components.
The Globus Project provides open source software
tools that make it easier to build computational Grids and
Grid-based applications. These tools are collectively
called the Globus Toolkit. Globus Toolkit is the open
source Grid technology for computing and data Grids.
On the server side, Globus Toolkit 2.2 provides
interfaces in C. On the client side, it provides interfaces
in C, Java language, and other languages. On the client
side, the Java interfaces are provided by the Java
Commodity Grid (CoG) Kit. Globus runs on Linux, AIX,
HP-UX, Solaris, and also on windows operating systems.
The Globus architecture represents a multiple-layer
model. The local services layer contains the operating
system services and network services like TCP/IP. In
addition, there are the services provided by cluster
scheduling software (like IBM Load Leveler) -- job-
submission, query of queues, and so forth. The cluster
scheduling software allows a better use of the existing
cluster resources. The higher layers of the Globus model
enable the integration of multiple or heterogeneous
clusters.
The Globus Toolkit (GT) was developed by Global
Alliance, a division of Global Grid Forum. Global
Alliance comprises of R&D research groups based at
several universities such as the University of Chicago,
the University of Edinburgh and the University of
Southern California. GT is the de facto standard for grid
computing [2] and it is comprised of 3 main services:

The core services:
Basic infrastructures to enable grid computing such
as: resource management for naming and locating
computational resources on remote systems, security and
system level services, and monitor status.

Security services:
Security is implemented using the standard GSI (Grid
Security Infrastructure) and CAS
(Community Authorization Service). GSI offers
services such as basic certification, PKI, and many other
security libraries.

Data/Resource Management
Protocols to ensure rapid and secure data transfer
among resource nodes. There are 4 protocols:
GridFTP, Reliable File Transfer (RFT), Replica
Location Service (RLS), and Extensible
Input/output (XIO). GRAM (Globus Resource
Allocation Managers) is the Data Management for GT.
TeraGrid [5], TIGER, and Taiwan UniGrid [6] is
examples of grid projects that use GT.

Grid Security Infrastructure (GSI):
GSI provides elements for secure authentication and
communication in a grid. The infrastructure is based on
the SSL protocol (Secure Socket Layer), public key
encryption, and x.509 certificates. For a single sign-on,
Globus add some extensions on GSI. It is based on the
Generic Security Service API, which a standard API is
promoted by the Internet Engineering Task Force (IETF).

These are the main functions implemented by GSI:
Single/mutual authentication
Confidential communication
Authorization
Delegation

Grid Resource Allocation Manager (GRAM):
GRAM is the module that provides the remote
execution and status management of the execution. When
a job is submitted by a client, the request is sent to the
remote host and handled by the gatekeeper daemon
located in the remote host. Then the gatekeeper creates a
job manager to start and monitor the job. When the job is
finished, the job manager sends the status information
back to the Client and terminates.
Global Access to Secondary Storage (GASS)
GRAM uses GASS for providing the mechanism to
transfer the output file from servers to clients. Some APIs
are provided under the GSI protocol to furnish 138
Introduction to Grid Computing with Globus

Secure transfers. This mechanism is used by the
globusrun command, gatekeeper, and job manager.

Monitoring and Discovery Service (MDS):
MDS provides access to static and dynamic
information of resources. Basically, it contains the
following components:
Grid Resource Information Service
(GRIS)
Grid Index Information Service (GIIS)
Information Provider
MDS client
Grid Resource Information Service (GRIS)
GRIS is the repository of local resource information
derived from information providers. GRIS is able to
register its information with a GIIS, but GRIS itself does
not receive registration requests. The local information
maintained by GRIS is updated when requested, and
cached for a period of time known as the time-to-live
(TTL). If no request for the information is received by
GRIS, the information will time out and be deleted. If a
later request for the information is received, GRIS will
call the relevant information provider(s) to retrieve the
latest information.

Grid Index Information Service (GIIS):
GIIS is the repository that contains indexes of
resource information registered by the GRIS and other
GIISs. It can be seen as a grid wide information server.
GIIS has a hierarchical mechanism, like DNS, and each
GIIS has its own name. This means client users can
specify the name of a GIIS node to search for
information.

Security
Security is a much more important factor in planning
and maintaining a grid than in conventional distributed
computing, where data sharing comprises the bulk of the
activity. In a grid, the member machines are configured
to execute programs rather than just move data. This
makes an unsecured grid potentially fertile ground for
viruses and Trojan horse programs. For this reason, it is
important to
understand exactly which components of the grid
must be rigorously secured to deter any kind of attack.
Furthermore, it is important to understand the issues
involved in authenticating users and properly executing
the responsibilities of a Certificate Authority.

Certificate authority
The primary responsibilities of a Certificate Authority
are:
Positively identify entities requesting
certificates
Issuing, removing, and archiving
certificates
Protecting the Certificate Authority
server
Maintaining a namespace of unique
names for certificate owners
Serve signed certificates to those
needing to authenticate entities
Logging activity

Briefly, a Certificate Authority is based on the public
key encryption system. In this system, keys are generated
in pairs, a public key and a private key. Either one can be
used to encrypt some data such that the other is needed to
decrypt it. The private key is guarded by the owner and
never revealed to anyone. The public one is given to
anyone needing it. A Certificate Authority is used to hold
These public keys and to guarantee who they belong to.
When a user uses his private key to encrypt something,
the receiver uses the corresponding public key to decrypt
it. The receiver knows that only that users public key
can decrypt the message correctly. However, anyone
could intercept this message and decrypt it because
anyone can get the originators public key. If the
originator instead doubly encrypts the message with his
private key and the intended recipients public key, a
secure communication link is formed. The receiver uses
his private key to decrypt the message and then uses the
senders public key for the second decryption. Now the
recipient knows that if the message decrypts properly,
then only the sender could have sent it and furthermore,
the sender knows that only the intended receiver can
decrypt it. The beauty of all of this is that nobody had to
securely carry an encryption key from the sender to the
receiver,

Schedulers
Most grid systems include some sort of job
scheduling software. This software locates a machine on
which to run a grid job that has been submitted by a user.
In the simplest cases, it may just blindly assign jobs in a
round-robin fashion to the next machine matching the
resource requirements. However, there are advantages to
using a more advanced scheduler. Some schedulers
implement a job priority system. This is sometimes done
by using several job queues, each with a different
priority. As grid machines become available to execute
jobs, the jobs are taken from the highest priority queues
first. Policies of various kinds are also implemented
using schedulers. Policies can include various kinds of
constraints on jobs, users, and resources. For example,
there may be a policy that restricts grid jobs from
executing at certain times of the day.
More advanced schedulers will monitor the progress
of scheduled jobs managing the overall work-flow. If the
jobs are lost due to system or network outages, a good
scheduler will automatically resubmit the job elsewhere.
However, if a job appears to be in an infinite loop and
reaches a maximum timeout, then such jobs should not
be rescheduled. Typically, jobs have different kinds of
completion codes, some of which are suitable for re-
submission and some of which are not.
Monitoring progress and recovery
A grid system, in conjunction with its job scheduler,
often provides some degree of recovery for sub jobs that
fail. A job may fail due to a:
Programming error: The job stops part
way with some program fault.
Hardware or power failure: The
machine or devices being used stop working in
some way.
Communications interruption: A
communication path to the machine has failed or
is overloaded with other data traffic.
Excessive slowness: The job might be
in an infinite loop or normal job progress may
be limited by another process running at a
higher priority or some other form of
contention.
It is not always possible to automatically determine if
the reason for a jobs failure
is due to a problem with the design of the application
or if it is due to failures of
various kinds in the grid system infrastructure.
Schedulers are often designed to
categorize job failures in some way and automatically
resubmit jobs so that they
are likely to succeed, running elsewhere on the grid.

Communications
A grid system may include software to help jobs
communicate with each other. The open standard
Message Passing Interface (MPI) and any of several
variations is often included as part of the grid system for
just this kind of communication

VIII. ACCESSING THE INTRANET GRID:
When any user wants to access our proposed Intranet
Grid in order to download multiple files over the Internet,
then he should follow certain procedures that we consider
necessary for the security of our Grid. The main
Requirements for Processing in Grid Environment are:
Security: Single sign-on,
authentication, authorization, and secure data
transfer.
Resource Management: Remote job
submission and management.
Data Management: Secure and robust
data movement.
Information Services: Directory
services of available resources and their
status.
Fault Detection: Checking
the intranet.
Portability: C bindings (header files)
needed to build and compile programs
.
Existing Algorithm for Globus Architecture
Create security proxy via
GSI services
Access a MDS-GIIS server
Search for required machine(s)
Rank the machine list based on a
scheduling policy
Prepare the data
Transfer the data to the target
machine by using GASS services
Prepare a RSL document
Submit the program using
GRAM services
React to status changes from
GRAM
Get results via GASS

Here, we have got the resources available in the
Network which is automatically done by have the Globus
Toolkit in the server. When we want to download a file
this information has to be matched with the client module
and then the downloading has to be carried out in the
clients. For this we have added some modules to the Grid
Architecture.
Added module:
Get the Information about files to
be downloaded.
Match the files with appropriate Machines.
Store files in common database.
Retrieval of data from database is done after
proper authentication.

20. PPROPOSED ALGORITHM FOR
INTRANET PROPOSED GRID:
Steps to perform multiple downloading in the Grid,
The host details are got from the server of the LAN in
order to identify the various hosts.

The host information is got whenever needed on the
priority queue basis.
//module for downloading files
Start lookup // look for file size and resource
information
Declare nres, nfile // no of resources
available and no of files
Input nres, nfiles
Input size // the file size
Initialize P1 res info // store the
resource information in priority queue P1 with highest
system configuration as priority
Initialize P2 file size // store the file
information in the priority queue P2 with maximum file
size as priority
If condition (nfiles == nres) // check
whether the no of resources is equal to no of files
Initialize counter
For (counter =1; counter <= nres;
counter++) // initialize the loop to assign the files.
Assign the 1
st
file of P2 to the 1
st
node in P1. //
first node will be node with highest configuration and
first file will be the file with maximum size.
Start processing // files directed to the
appropriate system for accessing their wasted CPU
cycles.
Loop
Else:
Start timer
Delay 1 min
Collect incoming files // the files that the
user clicked to download in this duration.
Assign the files P2
Goto step 8
Goto step 1
End // when the user exits from proposed
Grid.

BENEFITS OF GRID
COMPUTING:
Grid computing enables organizations to
aggregate resources within an entire IT infrastructure no
matter where in the world they are located. It eliminates
situations where one site is running on maximum
capacity, while others have cycles to spare.
Grid computing enables companies to access
and share remote databases. This is especially beneficial
to the life sciences and research communities, where
enormous volumes of data are generated and analyzed
during any given day.
Grid computing enables widely dispersed
organizations to easily collaborate on projects by
creating the ability to share everything from software
applications and data, to engineering blueprints.
Grid computing can create a more robust and
resilient IT infrastructure better able to respond to minor
or major disasters.
A grid can harness the idle processing cycles
that are available in desktop PCs located in various
locations across multiple time zones. For example, PCs
that would typically remain idle overnight at a company's
Tokyo manufacturing plant could be utilized during the
day by its North American operations.
IX. CONCLUSION
Grid computing was once said to be fading out but
due to the technological convergence it is blooming once
again and the Intranet Grid we have proposed adds a
milestone for the Globalization of Grid Architecture,
which, leads to the hasty computing that is going to
conquer the world in the nearest future. By implementing
our proposed Intranet Grid it is very easy to download
multiple files very fast and no need to worry about the
security as we are authenticating each and every step
taking place in our Grid and in particular user to access
the database. Further implementations could be carried
out in the nearest future.

REFERENCES
[1].P Plaszczak, R Wellner, Grid computing, 2005,
Elsevier/Morgan Kaufmann, San Francisco
[2]Francesco Lelli, Eric Frizziero, Michele Gulmini, Gaetano
Maron, Salvatore Orlando, Andrea Petrucci and Silvano Squizzato.
The many faces of the integration of instruments and the grid.
International Journal of Web and Grid Services 2007 Vol. 3, No.3
[3]Fran Berman, Geoffrey Fox, Anthony J. G. Hey Grid
computing, 2005, Elsevier/Morgan Kaufmann, San Francisco
[4]Pawel Plaszczak, Richard Wellner
Jos Cardoso Cunha, Omer Rana
Lizhe Wang, Wei Jie, Jinjun ChenFundamentals of Grid
Computing: Theory, Algorithms and Technologies BY Frdric
[5]Advances in grid computing -- EGC 2005: European Grid
Conference, ... Peter Sloot
[6]Grid computing: the new frontier of high performance
computing-Lucio Grandinetti
[7] Distributed data management for grid computing-Michael Di
Stefano
[8]Grid Technology and Applications: Recent Developments-G. A.
Gravvanis, H. R. Arabina,
[9]Advances in grid and pervasive computing: third international-
Song Wu, Laurence Tianruo Yang, Tony Li Xu
ISBN: 978-81-920575-6-9 :: doi: 10. 74327/ISBN_0768
NANOTECHNOLOGY THE NEW UPGRADE FOR COMPUTERS

A.RAMYASREE
Affiliated to Anna University, Chennai.
B.E Final Year CSE,
MAILAM ENGINEERING COLLEGE. Mailam.
Tamil Nadu, India.

Abstract The Next Big Thing Is Really Small - K. Eric
Drexler, Founder and Chairman, Foresight Institute, and
Predictions, observing the rise of the human dependence on the
sector of Nano Technology. Nano technology is not just
studying every field in a larger scope but deriving an enormous
development in improvable areas like usage of NVRAM &
larger memory storage in it, Use of the nanomagnetism
initiative which provides an interdisciplinary framework to
help stage the next advance in complex materials research that
can be used in Computer sciences Application of nanocrystals
& nanocomputer, Molecular and Quantum and Nano
Computing and Nanomechanical computing, Usage of
Graphene chips instead of silicon.

I. INTRODUCTION
A basic definition: Nanotechnology is the engineering of
functional systems at the molecular scale.
This covers both current work and concepts that are
more advanced. In its original sense, 'nanotechnology' refers
to the projected ability to construct items from the bottom
up, using techniques and tools being developed today to
make complete, high performance products.
Driven by rapid technological advances within the past
two decades, computing and high-speed networkings have
emerged as powerful tools for science and are even
changing the ways in which modern science is conducted.
DOE is a national leader in the scientific computing field
supporting fundamental research in advanced scientific
computing, applied mathematics, computer science, and
networking. The DOE computational infrastructure provides
world-class, high-performance computational and
networking tools that enable scientific, energy,
environmental, and national security research.
More than 2400 scientists in universities, federal
agencies, and U.S. companies use DOE-(DEPARTMENT
OF ENERGY-Washington D.C) funded high-performance
computers. Research communities that benefit from these
resources include structural biology; superconductor
technology; medical research and technology development;
materials, chemical and plasma sciences; high energy and
nuclear physics; and environmental and atmospheric
research.
II. NANO COMPUTING

Quantum Nano computing and quantum computers are
in advanced stages of development due to recent
nanotechnology advances in these areas. These computers
promise to be so fast and powerful that our modern
supercomputers will be little more than toys in years to
come. The problem is that their sheer capacity for
processing data means that they will likely be able to readily
crack even the most advanced encryption methods through
brute force.
Computers play a pivotal part in nanotechnology as they
allow us to develop atomic models and foresee the Nano
devices we desire. Furthermore, as nanotechnology evolves,
new, more powerful computers will emerge, which will lead
to breakthroughs in nanotechnology and yet to more
powerful computers. Hence we will have a cycle of
scientific discovery unprecedented in human history. It will
be the singularity.

A. CONSEQUENCES:

Because of the singularity, it is shortsighted to discuss
the applications of nanotech, but here's an attempt: In
computer science, we would have nanocomputer that would
open the door for androids and artificial intelligences.
Nanotech would develop an army of molecular robots and
nanodevices that would allow us to completely dominate
Nature. We now dominate it at a macroscopic level; we
would then dominate it at a microscopic level, too. With
molecular medicine we would eliminate many, if not all,
diseases with intelligent molecules capable of repairing and
changing our cells. Just for curiosity, my first idea towards
ending aging, inspired by the legendary TV series
Transformers which we used to watch growing up, was to
use microscopic devices capable of turning our neurons into
metal ones with a far greater strength and therefore
impossible to kill.
In synergy with other technologies such as genetic
engineering, the changes each of us could pursue would be
staggering; from having a skin invulnerable to bullets to
augmenting our physical and psychological capacities.
Industrial, agricultural, and environmental applications are
almost unimaginable at this stage: eradicating hunger,
creating molecular superconductors at room temperature,
developing nanomachines that eliminate pollution, etc.
Importantly, we would be capable of space conquest and
colonization. Each nanomachines would be capable of
amazing molecular engineering achievements and even
reproducing. Remember that every single adult human being
started as a tiny cell containing all the genetic instructions to
blossom into an adult being. In a sense, these molecular
assemblers are like a human egg. The goal behind nanotech
is to create such tiny nanodevices that, if properly coded,
can give rise to machines with a high level of complexity.
Thus nanodevices would make excellent scouts in space
exploration. To give an idea of the inherited power of
nanotechnology, just think that a bacterium with a
generation time of 20 minutes can in 48 hours, if allowed to
grow, reach a population 4000 times the weight of the earth.
This means that a nanodevice with enough mass/energy has
the potential to create planets, outposts and life throughout
the galaxy. Of course this is theory but it shows the
dimension of the powers we're dealing with.
There are some dangers inherited to nanotechnology, as
I also mention elsewhere. For example, the grey cloud,
theorized by Ralph Merkle as a doomsday offspring of
nanotechnology. Basically, the grey cloud is a self-
replicating airborne nanodevice that catalyzes carbon
dioxide into graphite. Should such nanodevice be unleashed
and, in as little as a few days, a solid wall would cover the
earth, block the sun, and eventually destroy life on earth.
Robert Freitas Jr., a world expert on nanotechnology, offers
an optimistic but well-documented review of the dangers of
nanotech. The dangers of nanotech are another reason for
space colonization. Nanotech will forever change humanity.

B. FASTER, LIGHTER COMPUTERS
POSSIBLE WITH NANOTECHNOLOGY.

Smaller, lighter computers and an end to worries about
electrical failures sending hours of on-screen work into an
inaccessible limbo mark the potential result of Argonne
research Lab at Chicago on tiny ferroelectric crystals.
"Tiny" means billionths of a meter, or about 1/500th the
width of a human hair. These nanomaterials behave
differently than their larger bulk counterparts. Argonne
researchers have learned that they are more chemically
reactive, exhibit new electronic properties and can be used
to create materials that are stronger, tougher and more
resistant to friction and wear than bulk materials.


Fig: Shows a picture of Nano fibrils that are 10 to 100
times smaller in diameter than conventional textile fibers. In
comparison to a human hair which is ca. 80,000 nm in
diameter, the Nano fibers are 1,000 times smaller in
diameter.

III. COMPUTING APPLICATIONS

A. RAM & NVRAM. (Nonvolatile RAM)

RAM Random Access Memory is used when
someone enters information or gives a command to the
computer. It can be written to as well as read but - with
standard commercial technology - holds its content only
while powered by electricity. Argonne materials scientists
have created and are studying nanoscale crystals of
ferroelectric materials that can be altered by an electrical
field and retain any changes.
Ferroelectric materials so called, because they behave
similarly to ferromagnetic materials even though they don't
generally contain iron consist of crystals whose low
symmetry causes spontaneous electrical polarization along
one or more of their axes. The application of voltage can
change this polarity. Ferroelectric crystals can also change
mechanical to electrical energy the piezoelectric effect or
electrical energy to optical effects.
A strong external electrical field can reverse the plus and
minus poles of ferroelectric polarization. The crystals hold
their orientation until forced to change by another applied
electric field. Thus, they can be coded as binary memory,
representing "zero" in one orientation and "one" in the other.
Because the crystals do not revert spontaneously, RAM
made with them would not be erased should there be a
power failure. Laptop computers would no longer need
back-up batteries, permitting them to be made still smaller
and lighter. There would be a similar impact on cell phones.
Achieving such permanence is a long-standing dream of
the computer industry.
Companies such as AT&T, Ford, IBM, RCA and
Westinghouse Electric made serious efforts to develop non-
volatile RAMs (NVRAM) in the 1950s, but couldn't achieve
commercial use.
Back then, NVRAMs were based on expensive
ferroelectric single crystals, which required substantial
voltage to switch their polarity. This, and cross talk inherent
in the then recently devised row matrix address concept,
made them impractical.
The usage of NVRAM is a good option in the field of
computers as it may lead further towards the development of
Data Storage and unearths new concepts in the arena of data
mining and Data storage.

Fig: AN NVRAM
Working on the nanoscale changes this. It means higher
density memories with faster speeds and megabyte (the
amount of memory needed to store one million characters of
information) - or even gigabyte (one billion bytes) -
capacity. It's not clear how soon such capacity will be
available, but competition is heavy, stakes are high, and
some companies claim they will have the first fruits of this
research within less time.
B. SMART CARDS
Scientists are using their expertise in ferroelectrics to
improve smart cards. These are the size and shape of credit

cards but contain ferroelectric memory that can carry
substantial information, such as its bearer's medical history
for use by doctors, pharmacists and even paramedics in an
emergency. Unlike magnetic strips on credit cards, these
memories do not come in contact with their readers and will
not wear out.

Fig: A SMART CARD
Current smart cards carry about 250 kilobytes of
memory. Argonne researchers are collaborating with the
Colorado Springs, Colo., Symetrix Corp. to develop a
higher capacity card with a more flexible and longer-lasting
memory. Nanomaterials have been studied at Argonne since
the 1980s. They are now one of the hottest research topics
worldwide. Several nanoscale materials research centers are
being planned by the U.S. Department of Energy (DOE),
with one likely to be built at Argonne.
Nanomaterials challenge researchers:
The effort to understand ultra-small materials is on the
frontier where physics, chemistry and biology meet.
Chemists work with atoms and molecules, moving from the
smallest particles to larger ones, while physical scientists
work from larger materials down. They come together as we
approach the nanoscale.
Materials behave differently in the range of size below
100 nanometers (billionths of a meter. Atomic and
molecular clusters at this size may be different colors from
the same elements or compounds in bulk. They become
more chemically reactive and display new electronic
properties. Objects assembled from them can be stronger
and tougher than their bulk counterparts. However, the
science that is the foundation for the technology is still not
understood.
Nanoscale ferroelectrics allow us to develop better
multilayer capacitors, which could be used in even smaller
cell phones, application in motors to power micro- and
Nano-electro-mechanical systems.
Nature likes to put things together in certain ways. As
we learn more about nanoscience - when we can control
construction at the nanoscale - we will be able to engineer
the nanoworld differently and create novel combinations.
We should find new materials, things we can't even imagine
yet.
It is synergistic with a broader strength in complex oxide
materials, including related high-temperature
superconductors and thermal barrier coatings and colossal
magneto resistive materials.
Ferroelectrics are just one of the hot new areas in
nanomaterials, Gibson said. Argonne's work with ultra-
Nano crystalline diamond films for micro machines for
medical, transportation, industrial and aerospace uses was
featured in logos Nano Science Summit. Although many
novel nanosize effects have been found in ferroelectrics,
there are as many or more in magnets, superconductors,
metals, etcIn addition, there are composite materials,
where two or more of the above are combined, introducing
proximity effects, which can be dominant on the nanoscale.
The possibilities for creating new useful materials through
nanotechnology are endless.
Closeness breeds material changes:
Such proximity effects changes in material behavior
because the materials are so close show up in giant
magneto-resistance, a phenomenon discovered in 1988 and
used in computer hard drives. Tiny magnetic bits are hard to
read individually, but interleaved nanolayers of cobalt,
copper, iron and chromium show substantial changes in
resistance in magnetic fields because the layers are so close
together. IBM and the magnetic recording industry have
used this to create ultra sensitive hard-drive read
mechanisms. The Nano-community looks at a wide range of
phenomena. The research initiative in nanomagnetism
research that DOE recently approved for funding at a rate of
$1.2 million a year. It includes atoms, molecules and small
clusters, and carries forward some existing technologies -
such as semiconductors - by understanding bulk materials
from a micro-structural view.
We want to know how properties change at the smaller
scales and are finding new effects, some of which are
commercially viable. Nanoscience draws some of its
importance from how quickly we've been able to turn these
into technological applications."
The nanomagnetism initiative provides an
interdisciplinary framework to help stage the next advance
in complex materials research. It takes a broad approach,
working with materials that fall from around one micron
(one millionth of a meter) in size to less than 10 nanometers.
As the scale decreases, the dominant physics changes, and
new materials, properties and applications emerge.
Computer world might one day be based in magnetic
properties instead of electrical. This might make it possible
to build computers with architectures that could be
restructured depending on the task of the moment. The same
machine could be configured like a Macintosh for tasks that
a Mac operating system performs best and like a PC when
Windows OS is preferable.
Also possible could be magnetic configurations that
would not be limited by binary logic, making them more
like the human brain. This is far away, but promising.
Studies on the nanoscale could lead to better bulk
magnets and more efficient motors with consequent savings
in the use of fossil fuels. It may also become possible to
incorporate magnetic molecules in polymers, creating
plastics that could be used where traditional magnets cannot,
for example in certain corrosive environments.

IV. MOLECULAR COMPUTING
Molecular computing uses switches made of a single
protein molecule. Proteins "can self-assemble complex
arrays of molecules on a surface [nanometer-scale
patterns]....Many proteins do have charge-transfer and
charge-switching properties, which could...be harnessed to
provide some aspects of the information processing
capability of a semiconductor device. Longmuir-Blodgett
films - thin films of lipids - are known to be an essential part
of the electrical properties of nerve cells, and can be made
quite readily in the laboratory. Nerve-cell proteins are
inserted into the lipid film which alters the film's ability to
let ions pass depending on what other ions are present or on
the electric field to which they are exposed. This has
progressed to the stage of building films, putting proteins
into them, and demonstrating the electrical characteristics of
the protein, which is similar to the position with transistors
in 1930

A. QUANTUM COPMPUTERS
Seth Lloyd of Los Alamos National Laboratory proposes
computers "made of weakly coupled quantum systems
arranged in one-, two-, or three-dimensional arrays.
Computations are performed in response to sequences of
light pulses imposed upon the entire array simultaneously.
Lloyd shows that by an appropriate choice of materials and
architecture, and appropriate choices of pulses, each subunit
in the array will change to a new quantum state in a manner
that depends both on its previous state and upon the pulse
sequence. He presents a simple proof that such an array
could carry out the full range of logic operations required of
any computer."
For any given pair of quantum states in the set of
allowed states of such a device, there are sequences of
pulses which, if applied at the proper times, will switch the
device from one state to the other. Since the physical
conformation of an object is determined by its quantum
state, the conclusion is inescapable that an appropriately
designed quantum "computer" can be used as a quantum-
mechanical micromanipulator.
The quantum states of an effective manipulator would
need to correspond to useful configurations of some kind of
molecular arm. Manipulators would be designed specifically
for that purpose rather than for carrying out general
computations. Both types of devices would, however, be
based on the same general principles and would be
controlled by sequences of light pulses.

V. NANOMECHANICAL COMPUTERS
Even with a billion bytes of storage, a Nanomechanical
computer could fit in a box a micron wide, about the size of
a bacterium. Although mechanical signals move about 10
5

times slower than the electrical signals in today's machines,
they will need to travel only 10
-6
as far, and thus will face
less delay."
VI. NEXT GENERATION NANOTECHNOLOGY
COMPUTER MEMORY MADE OF GRAPHENE:
Carbon comes in many different forms, from the
graphite found in pencils to the world's most expensive
diamonds. In 1980, we knew of only three basic forms of
carbon, namely diamond, graphite, and amorphous carbon.
In recent times Graphene was also discovered which caused
a lot of fuzz and interest.
Experiments with Graphene have revealed some
fascinating phenomena that excite nanotechnology
researchers who are working towards molecular electronics.
It was found that Graphene remains capable of conducting
electricity even at the limit of nominally zero carrier
concentration because the electrons don't seem to slow
down or localize. This has to do with the fact that the
electrons moving around carbon atoms interact with the
periodic potential of graphemes honeycomb lattice, which
gives rise to new quasi particles that have lost their mass, or
'rest mass' (so-called mass less Dirac fermions). This means
that Graphene never stops conducting.
For computer chips, 'smaller and faster' just isn't good
enough anymore. Power and heat have become the biggest
issues for chip manufacturers and companies integrating
these chips in everyday devices such as cell phones and
laptops. The computing power of today's computer chips is
provided mostly by operations switching at ever higher
frequency. This physically induced power dissipation
represents the limiting factor to a further increase of the
capability of integrated circuits. Heat dissipation of the
latest Intel processors has become a widely discussed issue.
By the end of the decade, you might as well be feeling a
rocket nozzle than touching a chip. And soon after 2010,
computer chips could feel like the bubbly hot surface of the
sun itself. As the electronics industry continues to churn out
smaller and slimmer portable devices, manufacturers have
been challenged to find new ways to combat the persistent
problem of thermal management. New research suggests
that the integration of carbon nanotubes (CNTs) as heat
sinks into electronic devices might provide a solution to this
problem.
HEAT is becoming one of the most critical issues in
computer and semiconductor design. There are six
fundamental ways the electronics industry faces growing
thermal distress:

Diamondoid
nanotube

Super nanotube

Nanotube pipe
a) Shortened product lifetimes - Every
increase of 10C in operating temperature cuts product
lifetimes in half. Increased operating costs Keeping
devices cool increasingly requires more and faster
spinning fans, which use more electricity.
b) Consumer acceptance More heat
requires more cooling fans which create more noise.
c) Reduced reliability There have been
several recalls and product failures due to heat.
d) Degraded performance With RF
amplifiers as much as 90% of power is lost through
heat, a serious problem affecting battery life on all
kinds of wireless devices.
e) Increased build costs Ever-larger and
more complex heat sinks and fans, and even more
exotic approaches are driving up costs.
To reduce high temperatures, today's heat sinks finned
devices made of conductive metal such as aluminum or
copper are attached to the back of the chips to pull thermal
energy away from the microprocessor and transfer it into the
surrounding air.
Using micro fin structures made of aligned multiwalled
carbon nanotube arrays mounted to the back of silicon chips
have proven that nanotubes can dissipate chip heat as
effectively as copper the best known, but most costly,
material for thermal management applications. And the
nanotubes are more flexible, resilient, and 10 times lighter
than any other cooling material available.
Discovered only in 2004, graphene is a flat one-atom
thick sheet of carbon. Existing forms of carbon basically
consist of sheets of graphene, either bonded on top of each
other to form a solid material like graphite, rolled up into
carbon nanotubes (think of a single-walled carbon nanotube
as a Graphene cylinder), or folded into soccer ball shaped
fullerenes., just like the Carbon C6 or Buck Minister
Fullerine
So Graphene can be used for not only the sole purpose
of replacing the silicon chip but also for better and fast
operations of the Computer.

VII. MERITS OF NANOTECHNOLOGY
Through NVRAM large amount of data
can be stored and can be used for large scale operations.
New concepts regarding the operational Speed of
Computers can be developed.
The use of Molecular nanotechnology
improves technically the areas of genetical engineering
indirectly and also serves the purpose of Large Data
base management.
The Use of Graphene can reduce the heat
of electronic devices. It also Graphene remains capable
of conducting electricity even at the limit of nominally
zero carrier concentration.
A nanocomputer system will be able to
direct the disassembly of an object, record its structure,
and then direct the assembly of perfect copies. An
advanced assembler could have as many as ten
thousand moving parts, each containing an average of
one hundred atoms.
Androids and Artificial intelligence can be
developed thereby developing Nano robotics.
Excellent and multifaceted servers can
built upon so that they handle more complexity within
less time.
Thus Nano technology serves well, the
purpose of future mechanisms and the develops every
field into a larger bioscope through which a man can
live more comfortable life.

VIII. STEPS FOR DEVOLOPEMENT OF NANO
TECHNOLOGY
The government should lay emphasis on
research and development of Nanotechnology
South Asian Countries which are booming
economies such as India China have a great chance
of being first to develop a field such as
nanotechnology.
Students should show more interest on
deep sectors such as nanotechnology and
Biotechnology.
Artificial Intelligence and Android
applications must be used instead of relying upon
overloaded Servers.
REFERENCES
[1] BC Crandall, Nanotechnology: Molecular Speculations on Global
Abundance, The MIT Press: Cambridge, Massachusetts; London, England.
1996.
[2] Douglas Mulhall, Our Molecular Future: How Nanotechnology,
Robotics, Genetics, and Artificial Intelligence Will Transform Our World.
Prometheus Books, Amherst, New York, Hard Cover, 392 pages, 2002.
[3] Cristina Buzea, Ivan Pacheco, and Kevin Robbie (2007),
"Nanomaterials and Nanoparticles: Sources and Toxicity". Biointerphases
2: MR17.
[4] N. Taniguchi (1974), On the Basic Concept of Nano-Technology.
Proc. Intl. Conf. Prod. London, Part II British Society of Precision
Engineering.
[5] Fritz Allhoff, Patrick Lin, Daniel Moore, What is nanotechnology and
why does it matter? from science to ethics, pp.3-5, John Wiley and Sons,
2010.
[6] Rodgers, P. (2006). "Nanoelectronics: Single file". Nature
Nanotechnology.
[7] Smith, Rebecca (August 19, 2009). "Nanoparticles used in paint could
kill, research suggests". London: Telegraph. Retrieved May 19, 2010.
ISBN: 978-81-920575-6-9 :: doi: 10. 74362/ISBN_0768
A NEW EARLEY PARSING ALGORITHM FOR LEXICALISED TREE
ADJOINING GRAMMAR
Sharafudheen K A
Department of Computer Science and Engineering
MES College of Engineering
Kuttippuram, Kerala, India

Abstract In computer science and linguistics, parsing or more
formally syntactic analysis, is the process of analysing a text,
made of a sequence of tokens to determine its grammatical
structure with respect to a given (more or less) formal grammar.
In traditional parsing methods Earley parsing is one of the best
parser implemented for both NLP and programming language
requirements. Tree Adjoining Grammar is powerful than
traditional CFG and suitable to represent complex structure of
natural languages. An improved version LTAG has appropriate
generative capacity and a strong linguistic foundation. Here we
introduce a new algorithm that simply adopts Earley method in
LTAG which results combined advantages of TAG and Earley
Parsing. Operations used are adjunction and Substitution.
In section 1 we just introduce what is a parser and its needs
in NLP and introduce TAG. In section 2 we describe the LTAG
and its properties. Third section explains how dotted rules of
Earley parsing can be extended to use with TAG. In section 4 we
describe the proposed algorithm and method used in it
Keywords-LTAG, Earley Parsing, Adjunction, Substitution
I. INTRODUCTION
In computing, a parser is one of the components in an
interpreter or compiler, which checks for correct syntax and
builds a data structure (often some kind of parse tree, abstract
syntax tree or other hierarchical structure) implicit in the input
tokens. The parser often uses a separate lexical analyser to
create tokens from the sequence of input characters.
Among Chomsky Hierarchy of languages, context
free grammars are important in linguistics for describing the
structure of sentences and words in natural language, and in
computer science for describing the structure of programming
languages and other artificial languages. Language generated
by context free grammars called context free languages.
Popular notation of CFG is Backus Normal Form(BNF).
Tree Adjoining Grammars are somewhat similar to
context-free grammars, but the elementary unit of rewriting is
the tree rather than the symbol. Whereas context-free
grammars have rules for rewriting symbols as strings of other
symbols, tree-adjoining grammars have rules for rewriting the
nodes of trees as other trees.
TAG has more generative capacity than CFG. For
example it can be shown that L
3
={a
n
b
n
c
n
} is a context free
language, but L
4
={a
n
b
n
c
n
d
n
} is not context free. TAG can
generate L
4
, so it is more powerful than CFG. So TAG is a
mildly context sensitive language. On the other hand
L
5
={a
n
b
n
c
n
d
n
e
n
} is not a Tree Adjoining language, but it is
context sensitive. So it follows that L(CFG) < L(TAG) <
L(CSG).
Definition 1(Tree Adjoining Grammar): A TAG is a
5-tuple G = (V
N
, V
T
,S,I,A) where V
N
is a finite set of non-
terminal symbols, V
T
is a finite set of terminals, S is a
distinguished nonterminal, I is a finite set of trees called
initial trees and A is a finite set of trees called auxiliary trees.
The trees in I U A are called elementary trees.
II. LTAG AND PROPERTIES
Tree Adjoining Grammar (TAG) was rst introduced by
Joshi in 1975. A recent review of TAG, which is called
lexicalized TAG (LTAG) given by Joshi and Schabes in1997
[12], provides a detailed description of TAG with respect to
linguistic, formal, and computational properties. In this section,
we will briey describe the TAG formalism and the relation to
linguistics for the sake of completeness.
A. Formalism
In LTAG, each word is associated with a set of elementary
trees. Each elementary tree represents a possible tree structure
for the word. An elementary tree may have more than one
lexical item. There are two kinds of elementary trees, initial
trees and auxiliary trees.
Initial trees (see left tree in Fig. 1) are characterized as
follows: internal nodes are labeled by non-terminals; leaf
nodes are labeled by either terminal symbols or the empty
string.
Auxiliary trees (see right tree in Fig. 1) are characterized as
follows: internal nodes are labeled by non-terminals; leaf nodes
are labeled by a terminal or by the empty string except
for exactly one node (called the foot node) labeled by a
non-terminal; furthermore the label of the foot node is the
same as the label of the root node.
Elementary trees can be combined through two operations,
substitution and adjunction.
Substitution is used to attach an initial tree, and adjunction
is used to attach an auxiliary tree. In addition to standard

adju
statis
[10]
and
adju
the h
subs
Th
is ca
histo
is ca
is an
pare
Gorn
Figu
Figure 3. E
unction, we a
stical LTAG
.Adjunction is
the foot nod
unction is used
head, e.g. in b
stitution.
he tree resulti
alled a derive
ory of how a d
alled a derivati
n elementary t
nt elementary
n tree address.
ure 1. Initial tre
Figure 2. D
lementary tree f
lso use sister
G parser des
s used in the
de appear in
d in generating
base NPs. Bu
ing from the c
d tree (See F
derived tree is
ion tree. Each
tree name a
y tree where
.
e and Auxiliary
Derived Tree
for LTAG examp
r adjunction
scribed by
case where b
the Treeban
g modier sub
ut we need on
combination o
Fig. 2).The tre
s built from th
h node (n) in
along with the
is inserted. Th
tree
ple sentence
as dened in
Chiang in
both the root
nk tree and s
b-trees as siste
nly adjunction
of elementary
ee that record
he elementary
the derivation
e location n in
he location n i

n the
2000
node
sister
ers to
n and
trees
ds the
trees
n tree
n the
is the
F
sent
dire
C
for
LTA
TAG
exis
T
F
the
is ex
A
gram
pars
leng
Hafi
algo
com
recu
poly
num
Fros
T
secti
algo
trees
U
Earl
idea
tree
its c
scan
diffe
A. O
B
Som
an a
root
tree
exci
T
but
and
node
mark

Fig. 3 shows t
tence Pierre V
ctor.
CYK model, H
LTAG were
AG currently
G. But our
sting one.
The key Prope
Extended
Factoring
(FRD), th
Schabes,
Frank in 2002
fundamental T
xpressed local
A recognition
mmars and cu
se by imposin
gth and curren
fiz in 2006. It
orithm to acco
mputed context
ursion in po
ynomial-size r
mber of parse
st, Hafiz and C
III. EXTEND
The full algo
ion introduces
orithm. We fi
s.
Use of dots in
ley (1970) for
a here. Dot on
has not been
children are a
nning, predict
erent data stru
Operations us
Basic operatio
me algorithm C
additional oper
Adjunction bu
t/foot node X)
at internal no
ised sub-tree i
The most com
substitution m
derived tree
es of the front
ked for substit
the initial and
Vinken will jo
Head-corner p
e suggested
using is the
algorithm ha
erties of LTAG
Domain Loca
g Recursion fro
hus making al
1997 [12]).
2 [7] claims t
TAG hypothe
ly within a sin
n algorithm w
urtails an eve
ng depth rest
nt input posit
t was again e
ommodate ind
t with current
lynomial tim
representation
e trees for h
Callaghan in 2
DING DOTTED S
rithm is expl
s preliminary c
rst show how
n LTAG is bas
r his algorithm
n left side of a
explored yet.
already explor
ting and com
uctures that is s
sed by propose
ons of TAG a
Chiang (2000)
ration for LTA
uilds a new tre
and a tree (
ode X in is
s then attached
mmon usage f
may also be do
s. Substitutio
tier of a tree (u
tution is replac
d auxiliary tre
oin the board
parsing and bi
already. Ear
same that pr
as significan
G are
ality
om the domai
ll dependencie
that these two
esis: Every syn
ngle elementar
which accomm
er-growing d
strictions with
tion, is descr
extended to a
direct (by com
t context) as w
me, and to
ns of the pote
highly-ambigu
2007 [9].
SYMBOLS AND
lained in the
concepts that
w dotted rules
sically same a
m for CFG. W
a non-termina
Right side do
red. We use t
mpleting in th
suitable for LT
ed Algorithm
are adjunction
) proposed a s
AG but we nee
ree from an au
(with internal
excised and
d to the foot n
for substitutio
one at frontier
on takes place
usually an init
aced by the tre
ees for an exa
as a non-exec
directional pa
rleyAlgorithm
oposed for si
nt advantage
in of Depende
es local (Josh
o properties r
ntactic depend
ry tree.
modates ambig
irect left-recu
h respect to
ibed by Frost
a complete pa
mparing previ
well as direct
generate com
entially-expone
uous grammar
D DOTTED TRE
next section.
will be used b
can be extend
as that propose
We mimic the
al indicates tha
ot indicates th
the same oper
he algorithm
TAG.
n and substitu
sister adjuncti
ednt use it.
uxiliary tree
node X). The
replaced by
node of .
ons on initial
r nodes of aux
e on non-term
tial tree). The
e to be substit
ample
cutive
arsing
m for
imple
over
encies
hi and
eect
dency
guous
ursive
input
t and
arsing
ously
t left-
mpact
ential
rs by
ES
This
by the
ded to
ed by
same
at the
hat all
ration
on a
ution.
on as
(with
e sub-
; the
trees,
xiliary
minal
node
tuted.
the d
suffi
A. D
T
state
A
will
prese
inpu
D
cur_
B. A
L
L
/
s
E
F
Fig
I
Before expla
data structure
icient data stru
Data structure
The algorithm
es set.
A state set S i
be indexed
ence of any
ut string a
1
...a
Definition 2:
_it, pos, paren
a: is the
cur_it: is
tree a.
pos: is th
parent: i
node it is
lchild: is
.
Algorithm for
Let G be a
Let a
1
a
n
be
/* Push i
stateset 0
ENQUEUE(
0
For(i=1 to
For eac
If (in
Operati
PRE
If (in
Operat
SCA
Else
gure 4. Adjunctio
IV. PROPOS
aining the alg
es used in the
ucture for our
e used in the a
m uses two b
is defined as
d by an in
state in sta
a
i
has been re
: A state s
nt, lchild wher
name of the
the address
he position of
s the parent e
.
the left child
stateset creat
an LTAG,
e the inpu
initial st
0
0
,s,L,,S
o LENGTH(s
ch state i
ncomplete
ion is pos
EDICTOR(st
ncomplete
tion is no
ANNER(stat
on and Substitut
SED ALGORITH
gorithm we h
e algorithm. W
algorithm.
algorithm
basic data stru
a set of states
nteger: Si w
ates set i wi
ecognized.
is defined
re:
dotted tree.
s or element o
f the dot;
element of th
d of the cur_it;
tion
ut string,
tate (
0
,s
S) {Dummy}
sentence)
in statese
(sentence
ssible
tate)
(sentenc
ot possibl
te)

tion
HM
have to unders
We have desi
uctures: state
s. The states
with i N.
ll mean that
as a 5-tuple

of the dot in
he cur_it; For
; For leaf node
,
s,L,,S)
stateset
do
et i do
e) ) and
ce)) and
e
stand
igned
e and
sets
The
t the
e, [a,
n the
start
e it is
to
0
any
any
End
C. A
F
sta
NT
{Pr
sta
chi
Ter
{Pr
E
D. A
/
F
E
E. A
F
all
N
End
End
d
Algorithm Pre
For each
ateset(i)
Case 1:
If N
ENQUEU
redictor}
/*Do A
/*Add
ateset(i)
M
ild
Else
ENQUEU
{Predi
End
Case 2:
rminal
ENQUEU
redictor}
/*Move
End
Algorithm Sca
/*Incremen
For word (
Find e
ENQUEU
End
Algorithm Com
For each
l child ex
Case 1:
NT
I
{Com
imme
E
{Com
COMPLETOR
edictor
state
and for a
: Dot is
NT is not
UE(tree,cu
Adjunction
all cur_
Move dot
e
UE(tree,cu
ictor} /*S
: Dot is
UE(tree,cu
e dot to r
anner
nt statese
(j) in inp
elementary
UE(tree,ro
mpleter
state tha
xplored
Dot is o
f a sibli
ENQUEUE(t
mpleter}
/*Move
ediate sib
lse
ENQUEUE(t
mpleter}
R(state)
cur_it a
all GRAMMA
on the le
a leaf
ur_it,L,P,
n Operatio
_it rooted
to imm
ur_it,L,P,
Substituti
on the le
ur_it,R,P,
right of t
et index
put senten
y tree for
oot,L,,lc
at all le
on the rig
ing exist
tree,sibl,
dot to
bling
tree,P,R,G
as root
AR_RULE
eft side o
lc)
on
d element
mediate l
lc)
ion Operat
eft side o
)
the termin
nce
r the word
c) {Scanne
eft tree
ght side o
L,P,nlc)
left
GP,cur_it)
in
of a
to
left
tion
of a
nal
d
er}
and
of a
of

/*Move dot to right of the
parent
End
Case 2: If Dot is on right of a
Terminal
ENQUEUE(tree,root,R,GP,cur_it)
{Completer)
End
F. Algorithm ENQUEUE
If state is not already in stateset
PUSH(state, action) to stateset
End
G. Complexity
The basic idea and method of the proposed algorithm is
from the Earley Parsing Technique for CFGs. We have made
changes in all the core parts without changing the basic method
to adapt the TAGs property and tree structure. So the average
complexity is of the proposed work is not changed than Earley
Parsing. On Analysing it shows O(Gn
3
) in average behavior in
time and O(G.n) in space where G is the length of input
grammar. Current using Earley algorithm has complexity
O(G
2
n
6
) in time and O(Gn
2
) in space.
H. Extracting the tree
Text Because of the pointers are used, it will be very easy
to extract the parse tree from stateset by using parent and child
state parameters.
V. CONCLUSION
We design a new Earley parser based algorithm for LTAG.
It works in lesser complexity than any of the existing TAG
parser. It is easy to implement and complex data structure of
existing Earley algorithm for TAG has modified to a simple
one. It combines the advantages of both TAG and Earley
parsing. Worst case behavior is also adaptable. So the proposed
one will be better in behavior for todays complex NLP
requirements.

REFERENCES

[1] Abeill, Anne, A Computational Grammar for French in TAG, In
Proceeding of the 12th International Conference on Computational
Linguistics, 1988.
[2] Aho, A. V. and Ullman, J. D, Theory of Parsing, Translation and
Compiling, Prentice-Hall, Englewood Cliffs, NJ.,VOL 1, 1973.
[3] LibinShen and A K Joshi, Statitical LTAG Parsing, Ph.D. thesis,
Universityof Pennsylvania. 2006
[4] Earley, J, An Efficient Context-Free ParsingAlgorithm,
Commun.ACM 13(2), 1970, pp. 94-102.
[5] Joshi, Aravind K, An Introduction to Tree Ad- joining Grammars, in
Magnetism, Mathematics of Language. John Benjamins, Amster- dam,
1987.
[6] Yaoyong Li, Hugo Zaragoza, Ralf Herbrich, John Shawe-Taylor, and
Jaz Kandola, The perceptron algorithm with uneven margins, In
Proceedings of the 19thInternational Conference on Machine Learning,
2002.
[7] R. Frank,Phrase Structure Composition and Syntactic Dependencies,,
The MIT Press,2002.
[8] R. McDonald, K. Crammer, and F. Pereira, Online large-margin
training ofdependency parsers, In Proceedings of the 43th Annual
Meeting of the Association forComputational Linguistics (ACL), 2005.
[9] L. Shen and A. K. Joshi, An SVM based voting algorithm with
applicationto parse reranking, In Proceedings of the 7th Conference on
Computational NaturalLanguage Learning, 2003.
[10] Frost, R., Hafiz, R. and Callaghan, "Modular and Efficient Top-Down
Parsingfor Ambiguous Left-Recursive Grammars",ACL-
SIGPARSE,10
th
InternationalWorkshop on Parsing Technologies
(IWPT), pp. 109-120,2007.
[10] D. Chiang, . Statistical Parsing with an Automatically-Extracted Tree
AdjoiningGrammar, In Proceedings of the 38th Annual Meeting of the
Association for Computational Linguistics (ACL)., 2000
[11] H. Daum e III and D. Marcu, Learning as search optimization:
Approximatelarge margin methods for structured prediction,, In ICML
2005.
[12] A. K. Joshi and Y. Schabes, Tree-adjoining grammars. In G.
Rozenberg and A. Salomaa, editors, Handbook of Formal Languages,
Springer-Verlag , volume 3, 1997, pp. 69 124.
[13] Aho, A.V., Sethi, R. and Ullman, Compilers: principles, techniques, and
tools,Addison-Wesley, 2002.


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