AML8726M3QuickReferenceManual

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COPYRIGHT 2010Amlogic,Inc. Allrightsreserved.Nopartofthisdocumentmaybereproduced.Transmitted,transcribed,ortranslatedintoanylanguage inanyformorbyanymeanswiththewrittenpermissionofAmlogic,Inc. TRADEMARKS AMLOGICisatrademarkofAmlogic,Inc.Allothertrademarksandregistered trademarksarepropertyoftheirrespective companies. DISCLAIMER AmlogicInc.maymakeimprovementsand/orchangesinthisdocumentorintheproductdescribedinthisdocumentatany time. Thisproductisnotintendedforuseinmedical,lifesaving,orlifesustainingapplications. Circuit diagrams and other information relating to products of Amlogic Inc. are included as a means or illustrating typical applications.Consequently,completeinformationsufficientforproductiondesignisnotnecessarilygiven.Amlogicmakes norepresentationsorwarrantieswithrespecttotheaccuracyorcompletenessofthecontentspresentedinthisdocument. REVISIONHISTORY Revision RevisionDate Changes Number 0.7 2011/06/17 Initialdraft 1.0 2011/06/30 RevisePinout CONTACTINFORMATION Amlogic,Inc. 3930FreedomCircle,Suite101 SantaClara,CA95054 U.S.A. www.amlogic.com

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Contents
1. 2. 3. GeneralDescription..............................................................................................................................4 FeaturesSummary................................................................................................................................5 PinOutSpecification............................................................................................................................9 PinOutDiagram(topview)......................................................................................................................9 3.1PinAssignments................................................................................................................................10

4. 5.

OperatingConditions .........................................................................................................................35 . MechanicalDimensions......................................................................................................................36

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3.2PinMultiplexingTables....................................................................................................................21 .

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1. GeneralDescription
AML8726M3isanadvancedconnectedmultimediaprocessordesignedforTablet/MID,SetTopBox(STB),TVandhighend media player applications. It integrates powerful CPU/GPU, and a stateoftheart video decoding engine with all major peripheralstoformtheultimatelowpowermultimediaSoC. TheintegratedprocessorisanARMCortexA9CPUwith32KBL1instructionand32Kdatacacheandalarge128KBL2unified cache to improve system performance. In addition, the CortexA9 CPU includes the NEON SIMD coprocessor to improve software media processing capability. The ARM CortexA9 CPU can run up to 1GHz and has a wide bus connecting to the memorysubsystem.

Thegraphicsubsystemconsistsoftwographicenginesandaflexiblevideo/graphicoutputpipeline.TheARMMali400GPU handles all the OpenGL ES 1.1/2.0 and OpenVG graphics programs, while the 2.5D graphics processor handles additional scaling, alpha, rotation and color space conversion operations. The video output pipeline can perform advanced image correction and enhancements. Together, the CPU and GPU handle all operating system, networking, userinterface and

ThreeadditionalprocessorsoffloadtheCortexA9CPUbyhandlingallaudioandvideodecodingprocessingtheMediaCPU and two MediaDSPs with a dedicated hardware video decoders. The MediaCPU is audio optimized and handles all audio decodingtasks.ThedualMediaDSPswithhardwaredecodercandecodeallHDvideoformatsincludingH.264,MVC,MPEG withnosizelimitation.

AML8726M3integratescompleteaudio/videoinput/outputinterfacesincludingLVDS/miniLVDSpanelinterfacewithTCON, RGB888TTLpanelinterfacewithTCON,anHDMI1.4atransmitterwith3Dsupport,CECandPHY,fourvideoDACsupporting composite,CVBS,YPbPrandVGAoutput,acompleteaudioCODECwithheadphonePAandmicrophonebias,I2SandSPDIF digitalaudioinput/outputinterface,aPCMaudiointerfaceandanITU601/656camerainputinterface. AML8726M3integratesasetoffunctionalblocksfordigitalTVbroadcastingstreams.Thebuildinthreedemuxcanprocess theTVstreamsfromthreetransportstreaminputinterfaces,whichcanconnecttotuner/demodulator.AnISO7816smart cardinterfaceandacryptoprocessorbuildintohelphandlingencryptedtrafficandmediastreams. The processor has rich advanced network and peripheral interfaces, including a 10/100 Fast Ethernet MAC with RMII interface,dualUSB2.0highspeedports(oneOTGandoneHOST),twoSDIOwithmultistandardmemorycardcontroller, fourUARTinterface,fourI2Cinterface,twohighspeedSPIinterfaceandtwoPWMs. StandarddevelopmentenvironmentutilizingGNU/GCCAndroidtoolchainissupported.PleasecontactyourAMLOGICsales

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1/2/4,VC1/WMV,AVS,RealVideoandMJPEGstreams.ThevideodecodingengineisalsocapableofdecodingJPEGpictures

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2. FeaturesSummary

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CPUSubsystem ARMCortexA9CPUupto1GHzfrequencyand2500DMIPS ARMv7instructionset,multiissuesuperscalar,outoforderarchitecture 32KBinstructioncacheand32KBdatacache 128KBUnifiedL2cache AdvancedNEONandVFPcoprocessor MemoryManagementUnit ApplicationbasedtrafficoptimizationusinginternalQoSbasedswitchingfabrics 3DGraphicsProcessingUnit ARMMali400GPU,250MHz Unified32KBcachetoreducegraphicdatabandwidth 250Mpix/secand25Mtri/sec Fullsceneoversampled4Xantialiasingenginewithnoadditionalbandwidthusage OpenGLES1.1/2.0andOpenVG1.1support 2.5DGraphicsProcessor

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Audio IF

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Enhancement De-interlacer Scalar

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Fastbitbltenginewithdualinputsandsingleoutput Programmablerasteroperations(ROP) Programmablepolyphasescalingfilter Supportsmultiplevideoformats4:2:0,4:2:2and4:4:4andmultiplepixelformats(8/16/24/32bitsgraphicslayer) Fastcolorspaceconversion Advancedantiflickeringfilter

CryptoEngine SupportsAESblockcipherwith128/192/256bitskeys,standard16bytesblocksizeandstreaming SupportsDES/3DESblockcipherwithElectronicCodeBook(ECB)andCipherBlockChaining(CBC)operationmode Supportsstandard64bitskeyforDESand192bitskeyfor3DES Supportstreamingdecoderwithstandard64bitsblocksize BuildinLSFRRandomnumbergenerator Video/PictureDecoder DualprogrammableDSPenginesat200MHzwithDSPinstructions Dedicatedhardwarevideodecoder H.264HP@L4.1upto1080P,MVCat30Hz MPEG4Part2ASPupto1080P(ISO144962) WMV/VC1SP/MP/APupto1080P AVSJiZhunProfileupto1080P MPEG2MP/HLupto1080P(ISO13818) MPEG1MP/HLupto1080P(ISO11172) RealVideo8/9/10upto720P WebMuptoVGA Multiplelanguageandmultipleformatsubtitlevideosupport Supports*.mkv,*.wmv,*.mpg,*.mpeg,*.dat,*.avi,*.mov,*.iso,*.mp4,*.rmand*.jpgfileformats MJPEGandJPEGunlimitedpixelresolutiondecoding(ISO/IEC10918) SupportsJPEGthumbnail,scaling,rotationandtransitioneffects VideoPostProcessingController Motiveadaptive3Dnoisereductionfilter Advancedmotionadaptiveedgeenhancingdeinterlacingengine 3:2pulldownsupport Programmablepolyphasescalarforbothhorizontalandverticaldimensionforzoomandwindowing Programmablecolormanagementfilter(toenhanceblue,green,red,faceandothercolors) Chromacoringandblackextensionprocessing DynamicNonLinearLumafilter Programmablecolormatrixpipeline Videomixer:2videoplanesand2graphicsplanes DigitalLCDPanelOutput TTLandLVDS/miniLVDSpanelsupporting SingleportLVDS/miniLVDSwithTCONsupportingbothsingleanddualgatepanelsupto1366x768resolution RGB888TTLinterfacewithTCONsupportingdigitalpanelupto1920x1200resolution LEDBLPWMandVGHLPWMbuildin ThreeindependentGammatableforLCDpaneltuning DitheringlogicformappingtodifferentLCDpanelcolordepth

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VideoOutput BuildinHDMI1.4atransmitterwithCEC,bothcontrollerandPHY Programmable4channelshighspeedvideoDACsforanalogvideooutputincludingCVBS,SVideo,YPbPrandVGA SupportsallstandardSD/HDvideooutputformats:480i/p,576i/p,720pand1080i/p SupportsdualvideooutputwithcombinationofLCD+HDMI,TTL+LVDSorCVBS+HDMI AudioDecoderandInput/Output MediaCPUwithDSPaudioprocessing SupportsMP3,AAC,WMA,RM,LFAC,Oggandprogrammablewith7.1downmixing Buildin2channelsaudioDACwithheadphonepoweramplifier Stereoheadphoneoutputandmonospeakeroutput I2S,SPDIF/IEC958andPCMserialdigitalaudiooutput SupportsconcurrentdualaudiostereochanneloutputwithcombinationofAnalog+PCMorI2S+PCM OtherDigitalAudio/VideoInput/OutputInterfaces ITU601/656parallelvideoinputwithdownscalar SupportscamerainputasYUV422,RGB565,10bitrawRGB,16bitRGBorJPEG MemoryandStorageInterface SupportsDDR31066SDRAMwith32bitdatabus Supportsupto2GBDDR3memory SupportsSLC/MLC/TLCNANDFlashwith4chipenablepinswithBCH60 SupportsserialNORFlashviaSPIinterface BuildinOneTimeProgrammingROMforkeystorage SDIOwithmemorycardcontrollerwith8bitdatabussupportingSD/SDHC/SDXC/MMC/MS/MSPromemorycards Network IntegratedIEEE802.310/100FastEthernetcontrollerwithRMIIinterface 50MHzclockoutputtoFastEthernetPHY WiFi/IEEE802.11supportingviaSDIO/USB DigitalTelevisionInterface Threetransportstream(TS)inputinterfaceswiththreebuildindemuxprocessorforconnectingtoexternaldigitalTV tuner/demodulatorandoneoutputTSinterface BuildinPWM,I2CandSPIinterfacestocontroltuneranddemodulator CI+PCMCIAcontrollerandinterface IntegratedISO7816smartcardcontroller IntegratedI/OControllersandInterfaces DualUSB2.0highspeedUSBI/O,oneUSBHostandoneUSBDevice FourUARTInterfacewithRTS/CTSoneinAOdomain 4xI2Cmaster/slaveinterface2xinAOdomain HighspeedbidirectionalSPIinterfacewith3slaveselectsignals 2xPWMchannelwithfeedbackcontrollogicand4xsimplePWMchannel ProgrammableIRremotecontroller Buildin10bitSARADCwith8inputchannelswithresistivetouchpanelcontroller AsetofGeneralPurposeIOinterfaces

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System,PeripheralsandMisc.Interfaces Multiplepowerdomain Dedicatedalwayson(AO)powerdomaintocommunicatewithexternalPMIC Integratedgeneralpurposetimers,counters,DMAcontrollers IntegratedRTCwithbatterybackupoption Single24MHzcrystaloscillatorinput EmbeddeddebuginterfaceusingICE/JTAG AMPOWERpowermanagementcircuitssupportingmultiplesleepandsuspendoperatingmodes Software SupportsAndroidandLinuxoperatingsystems SupportsAdobeFlashPlayer10.x GNU/GCCAndroidtoolschain Package 445ballLFBGA,RoHScompliant,17x17mm

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3. PinOutSpecification

PinOutDiagram(topview)

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3.1PinAssignments
TheAML8726M3A/Vprocessorpinassignmentisdescribedinthefollowingtable.

Table1.PinNameassignments
BGA Ball A5 B5 C4 B4 D4 A3 B3 A2 A1 B2 B1 C3 F12 E15 C1 C2 D3 D2 E3 E1 E2 F3 D5 E5 E4 F4 F5 G5 G6 G1 PinName GPIOA_0 GPIOA_1 GPIOA_2 GPIOA_3 GPIOA_4 GPIOA_5 GPIOA_6 GPIOA_7 GPIOA_8 GPIOA_9 GPIOA_10 GPIOA_11 VDD33_EE VDD12_CPU GPIOA_12 GPIOA_13 GPIOA_14 GPIOA_15 GPIOA_16 GPIOA_17 GPIOA_18 GPIOA_19 Group GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA Power Power GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA Pull up/down PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU Description General purpose input/output bank A signal 0. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank A signal 1. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank A signal 2. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank A signal 3. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank A signal 4. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank A signal 5. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank A signal 6. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank A signal 7. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank A signal 8. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank A signal 9. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank A signal 10. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank A signal 11. Please refer to following Table2forfunctionalmultiplexinformation. Type I/O I/O I/O

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3.3Vpower 1.2Vpower

GPIOA_20

GPIOA_21 GPIOA_22 GPIOA_23 GPIOA_24

GPIOA_25 GPIOA_26 GPIOA_27

General purpose input/output bank A signal 12. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank A signal 13. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank A signal 14. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank A signal 15. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank A signal 16. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank A signal 17. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank A signal 18. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank A signal 19. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank A signal 20. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank A signal 21. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank A signal 22. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank A signal 23. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank A signal 24. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank A signal 25. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank A signal 26. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank A signal 27. Please refer to following

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Table2 forfunctionalmultiplexinformation. F2 G3 H5 G2 H3 H2 J3 J1 F15 F17 F11 H4 J4 K6 K5 L6 L5 L4 M4 J2 K3 K2 L3 F18 L1 L2 M3 M2 F6 GPIOB_0 GPIOB_1 GPIOB_2 GPIOB_3 GPIOB_4 GPIOB_5 GPIOB_6 GPIOB_7 VDD12_EE VDD12_CPU VDD33_EE GPIOB_8 GPIOB_9 GPIOB_10 GPIOB_11 GPIOB_12 GPIOB_13 GPIOB_14 GPIOB_15 GPIOB_16 GPIOB_17 GPIOB_18 GPIOB_19 VDD12_CPU GPIOB_20 GPIOB_21 GPIOB_22 GPIOB_23 GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB Power Power Power GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB Power PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD General purpose input/output bank B signal 0. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank B signal 1. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank B signal 2. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank B signal 3. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank B signal 4. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank B signal 5. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank B signal 6. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank B signal 7. Please refer to following Table2forfunctionalmultiplexinformation. 1.2Vpower 1.2Vpower 3.3Vpower General purpose input/output bank B signal 8. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank B signal 9. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank B signal 10. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank B signal 11. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank B signal 12. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank B signal 13. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank B signal 14. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank B signal 15. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank B signal 16. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank B signal 17. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank B signal 18. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank B signal 19. Please refer to following Table2forfunctionalmultiplexinformation. 1.2Vpower General purpose input/output bank B signal 20. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank B signal 21. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank B signal 22. Please refer to following Table2forfunctionalmultiplexinformation. General purpose input/output bank B signal 23. Please refer to following Table2forfunctionalmultiplexinformation. 3.3Vpower General purpose input/output bank D signal 0. Please refer to following Table3forfunctionalmultiplexinformation. General purpose input/output bank D signal 1. Please refer to following Table3forfunctionalmultiplexinformation. General purpose input/output bank D signal 2. Please refer to following Table3forfunctionalmultiplexinformation. General purpose input/output bank D signal 3. Please refer to following Table3forfunctionalmultiplexinformation. General purpose input/output bank D signal 4. Please refer to following Table3forfunctionalmultiplexinformation. General purpose input/output bank D signal 5. Please refer to following Table3forfunctionalmultiplexinformation. I/O I/O I/O I/O I/O I/O I/O I/O

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GPIOB GPIOB GPIOB GPIOB Power

PD PD PD PD

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VDD33_EE GPIOD_0 GPIOD_1 GPIOD_2 GPIOD_3 GPIOD_4 GPIOD_5 GPIOD_6

PD PD PD PD PD PD PD

N3 N1 N2 P2 P3 R3 R4

GPIOD GPIOD GPIOD GPIOD GPIOD GPIOD GPIOD

General purpose input/output bank D signal 6. Please refer to following I/O

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Table3 forfunctionalmultiplexinformation. R2 T3 T2 M5 N5 N6 P5 P4 R1 R5 T6 T5 W1 F19 V2 U1 U2 U3 V6 U4 U6 Y2 W5 V3 V4 W3 U5 W2 Y5 Y4 Y3 GPIOD_7 GPIOD_8 GPIOD_9 GPIOC_0 GPIOC_1 GPIOC_2 GPIOC_3 GPIOC_4 GPIOC_5 GPIOC_6 GPIOC_7 GPIOC_8 GPIOC_9 VDD12_CPU RTC_VBAT RTC_XOUT RTC_XIN RTC_AVSS RTC_GPO GPIOAO_0 GPIOAO_1 GPIOAO_2 GPIOAO_3 VDD12_AO VDD12_AO GPIOAO_4 GPIOAO_5 GPIOAO_6 GPIOAO_7 GPIOD GPIOD GPIOD GPIOC GPIOC GPIOC GPIOC GPIOC GPIOC GPIOC GPIOC GPIOC GPIOC Power RTC RTC RTC RTC RTC GPIOAO GPIOAO GPIOAO PD PD PD PD PD PD PD PD PD PD PD PD PD PU PU Z General purpose input/output bank D signal 7. Please refer to following Table3forfunctionalmultiplexinformation. General purpose input/output bank D signal 8. Please refer to following Table3forfunctionalmultiplexinformation. General purpose input/output bank D signal 9. Please refer to following Table3forfunctionalmultiplexinformation. General purpose input/output bank C signal 0. Please refer to following Table3forfunctionalmultiplexinformation. General purpose input/output bank C signal 1. Please refer to following Table3forfunctionalmultiplexinformation. General purpose input/output bank C signal 2. Please refer to following Table3forfunctionalmultiplexinformation. General purpose input/output bank C signal 3. Please refer to following Table3forfunctionalmultiplexinformation. General purpose input/output bank C signal 4. Please refer to following Table3forfunctionalmultiplexinformation. General purpose input/output bank C signal 5. Please refer to following Table3forfunctionalmultiplexinformation. General purpose input/output bank C signal 6. Please refer to following Table3forfunctionalmultiplexinformation. General purpose input/output bank C signal 7. Please refer to following Table3forfunctionalmultiplexinformation. General purpose input/output bank C signal 8. Please refer to following Table3forfunctionalmultiplexinformation. General purpose input/output bank C signal 9. Please refer to following Table3forfunctionalmultiplexinformation. I/O I/O I/O I/O I/O I/O I/O I/O

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1.2Vpower

RTCbatterypowersupplyinput RTC32Kcrystaloutput RTC32Kcrystalinput

RTCanalogpowerground

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GPIOAO Power Power

General purpose input/output bank AO signal 0. Please refer to following Table4forfunctionalmultiplexinformation. General purpose input/output bank AO signal 1. Please refer to following Table4forfunctionalmultiplexinformation. General purpose input/output bank AO signal 2. Please refer to following Table4forfunctionalmultiplexinformation. General purpose input/output bank AO signal 3. Please refer to following Table4forfunctionalmultiplexinformation. 1.2Vpower 1.2Vpower General purpose input/output bank AO signal 4. Please refer to following Table4forfunctionalmultiplexinformation. General purpose input/output bank AO signal 5. Please refer to following Table4forfunctionalmultiplexinformation. General purpose input/output bank AO signal 6. Please refer to following Table4forfunctionalmultiplexinformation. General purpose input/output bank AO signal 7. Please refer to following Table4forfunctionalmultiplexinformation. 3.3Vpower

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GPIOAO

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GPIOAO

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GPIOAO

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GPIOAO

VDD33_AO GPIOAO_8 GPIOAO_9

Power GPIOAO GPIOAO GPIOAO GPIOAO System Power USB

V5

AA3 AA1 AA2 AB3 F16 AB2

GPIOAO_10 GPIOAO_11 TEST_N RESET_N VDD12_EE USBA_ID

General purpose input/output bank AO signal 8. Please refer to following Table4forfunctionalmultiplexinformation. General purpose input/output bank AO signal 9. Please refer to following Table4forfunctionalmultiplexinformation. General purpose input/output bank AO signal 10. Please refer to following Table4forfunctionalmultiplexinformation. General purpose input/output bank AO signal 11. Please refer to following Table4forfunctionalmultiplexinformation. Masterresetinput 1.2Vpower USBOTGminireceptacleidentifierbetweenminiA/miniBplug

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AB4 AC1 AA5 AC2 AD1 W6 AA4 AB5 AE1 AD2 AE2 AC3 AE3 AD3 AC4 AD4 AC5 AE5 AD5 AC6 AD6 AC7 AB6 AA6 AE7 AA7 AA8 W7 AD7 AC8 AB8 AB9 AD8 AC9 AE9 Y8 Y7 AA9 AA10 Y6 AD9 AC10 AC11 AC13 AC14 Y10 AD13 AE13 Y9 AC15 AD12 AD10

USBA_VBUS USBA_DP USBA_VSSA USBA_DM USBA_TXRTUNE USB_VDD25 USB_VDD33 USBB_VSSA USBB_TXRTUNE USBB_DM USBB_DP USBB_VBUS LED_CS0 VGHL_CS1 SARADC_CH7 SARADC_CH6 SARADC_CH5 SARADC_CH4 SARADC_CH3 SARADC_CH2 SARADC_CH1 SARADC_CH0 AVDD25_ADC AVSS25_ADC LVDS_AVSS25 LVDS_5N LVDS_5P LVDS_AVDD25 LVDS_4N LVDS_4P LVDS_3N LVDS_3P LVDS_CKN LVDS_CKP LVDS_AVSS25

USB USB USB USB USB USB USB USB USB USB USB USB LCDPanel LCDPanel ADC ADC ADC ADC ADC ADC ADC ADC Power Power Power LVDS LVDS Power LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS

USBOTGcablepowerdetection USBOTGpositivedatasignal USBground USBOTGnegativedatasignal USBPortBexternalcompensationresistorconnection USB2.5Vpower USB3.3Vpower USBground USBPortBexternalcompensationresistorconnection USBhostnegativedatasignal USBhostpositivedatasignal USBOTGcablepowerdetection LEDbacklightcurrentfeedback LCDVGHLcurrentfeedback ADCchannel7input ADCchannel6input ADCchannel5input ADCchannel4input ADCchannel3input ADCchannel2input ADCchannel1input ADCchannel0input 2.5Vpower

AI AIO AP AIO A AP AP AP A AIO AIO AO AO AI

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AnalogpowergroundforLVDS LVDSdata5negativeoutput LVDSdata5positiveoutput Analogpowersupply2.5VforLVDS LVDSdata4negativeoutput LVDSdata3negativeoutput LVDSdata3positiveoutput LVDSClocknegativeoutput LVDSClockpositiveoutput AnalogpowergroundforLVDS LVDSportcompensativeresisteroutputpin Analogpowersupply2.5VforLVDS LVDSdata5negativeoutput LVDSdata5positiveoutput AnalogpowergroundforLVDS LVDSdata1negativeoutput LVDSdata1positiveoutput LVDSdata0negativeoutput LVDSdata0positiveoutput AnalogpowergroundforHDMI HDMITMDSdata2+ HDMITMDSdata2 Analogpowersupply3.3VforHDMI HDMITMDSdata1+ HDMITMDSdata1 HDMIExternalresisterreference AnalogpowergroundforHDMI HDMITMDSdata0+

AnalogpowergroundforADC

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LVDSdata4Positiveoutput

LVDS_REXT_600 LVDS_AVDD25 LVDS_2N LVDS_2P

LVDS_AVSS25 LVDS_1N LVDS_1P LVDS_0P

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LVDS LVDS LVDS LVDS HDMI HDMI HDMI HDMI HDMI HDMI HDMI HDMI HDMI LVDS

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LVDS_0N

HDMI_AVSS33 HDMITX_2P HDMITX_2N

AD14

HDMI_AVDD33 HDMITX_1P HDMITX_1N HDMIREXT_5K HDMI_AVSS33 HDMITX_0P

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AO AO AO AO AP A AP AO AO
AP

AO AO AO AO
AP AO AO AP AO AO A AP AO

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AC12 Y11 AD11 AE11 AA11 AA12 Y12 R6 G7 AE15 AD15 AB11 AB12 AA13 AA14 AB14 AB15 AA15 AD16 AC16 J6 AE17 W19 AD17 AC18 R20 AD18 AC22 R21 AD21 AE21 U20 AC24 AC25 AB22 V20 AD25 AC19 W20 AD19 AC20 AC21 AD22 AC23 AE23 AD23 AE25 AD24

HDMITX_0N HDMI_AVDD33 HDMITX_CKP HDMITX_CKN PLLS_EXFIL PLLS_EXT_IREF HDMI_PLL_AVDD33 VDD12_EE VDD33_EE XTAL24_IN XTAL24_OUT BSD_EN GPIOC_10 GPIOC_11 GPIOC_12 GPIOC_13 GPIOC_14 GPIOC_15 AVSS25_DPLL AVDD25_DPLL VDD12_EE DDR3_DQ_4 SSTL_VDD DDR3_DQ_6 DDR3_DQ_2 SSTL_VDD DDR3_DQ_0 DDR3_DM_0 SSTL_VDD DDR3_DQS_N_0 DDR3_DQS_0 SSTL_VDD DDR3_DQ_5 DDR3_DQ_7 DDR3_DQ_3 SSTL_VDD

HDMI HDMI HDMI HDMI HDMI HDMI HDMI Power Power System System System GPIOC GPIOC GPIOC GPIOC GPIOC GPIOC Power Power Power DDR Power DDR DDR Power DDR DDR DDR DDR Power

Z Z Z Z Z Z

HDMITMDSdata0 Analogpowersupply3.3VforHDMI HDMITMDSclock+signal HDMITMDSclocksignal ExternalFilterforPLL ExternalresisterreferenceforPLL5K_1%toGND Analogpowersupply3.3VforHDMIPLL 1.2Vpower 3.3Vpower 24MHzcrystaloscillatorinput 24MHzcrystaloscillatoroutput TBD

AO AP AO AO A A AP P P

ro m

General purpose input/output bank C signal 10. Please refer to following Table3forfunctionalmultiplexinformation. General purpose input/output bank C signal 11. Please refer to following Table3forfunctionalmultiplexinformation. General purpose input/output bank C signal 12. Please refer to following Table3forfunctionalmultiplexinformation. General purpose input/output bank C signal 13. Please refer to following Table3forfunctionalmultiplexinformation. General purpose input/output bank C signal 14. Please refer to following Table3forfunctionalmultiplexinformation. General purpose input/output bank C signal 15. Please refer to following Table3forfunctionalmultiplexinformation. AnalogpowergroundforDigitalPLL 1.2Vpower Analogpowersupply2.5VforDigitalPLL DDR3SDRAMdataBusbit4 DDR3SDRAMpowersupply1.5V DDR3SDRAMdataBusbit6 DDR3SDRAMdataBusbit2 DDR3SDRAMdataBusbit0

to

DDR3SDRAMpowersupply1.5V DDR3SDRAMdatamask0 DDR3SDRAMpowersupply1.5V DDR3SDRAMDataStrobeComplementary0 DDR3SDRAMdataStrobe0 DDR3SDRAMdowersupply1.5V DDR3SDRAMdataBusbit5 DDR3SDRAMdataBusbit7 DDR3SDRAMdataBusbit3

te

ib u

Power DDR DDR DDR

tr

Power DDR DDR Power DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR

DDR3SDRAMpowersupply1.5V DDR3SDRAMdataBusbit1 DDR3SDRAMdataBusbit11 DDR3SDRAMdataBusbit9 DDR3SDRAMpowersupply1.5V DDR3SDRAMdataBusbit13 DDR3SDRAMdataMask1 DDR3SDRAMdataBusbit15 DDR3SDRAMdataStrobe1 DDR3SDRAMdataStrobeComplementary1 DDR3SDRAMdataBusbit12 DDR3SDRAMdataBusbit14 DDR3SDRAMdataBusbit10 DDR3SDRAMdataBusbit8

DDR3_DQ_1 DDR3_DQ_9

D is

DDR3_DQ_11

SSTL_VDD

DDR3_DQ_13 DDR3_DM_1 DDR3_DQ_15 DDR3_DQS_1

AD20

DDR3_DQS_N_1 DDR3_DQ_12 DDR3_DQ_14 DDR3_DQ_10 DDR3_DQ_8

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I I/O I/O I/O I/O I/O I/O AP AP P I/O P I/O I/O P I/O O P I/O I/O P I/O I/O I/O P I/O I/O I/O P I/O O I/O I/O I/O I/O I/O I/O I/O

AI AO

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AC17 Y16 AB23 AB24 AA16 Y17 AA17 M21 AB17 AB18 AA18 Y19 AA19 AA20 AB20 AB21 AA21 AA22 Y22 Y21 W21 V21 V22 U22 U21 T21 T20 R22 P22 P21 N21 P20 L22 N20 M22 M24 L23 Y14 AA23 AA24 Y23 Y24 T23

DDR3_VREF DDR3_PZQ DDR3_CK DDR3_CK_B DDR3_RAS_B DDR3_ODT1 DDR3_ODT0 VDD12_EE DDR3_CAS_B DDR3_CS1_B DDR3_WE_B DDR3_BA_2 DDR3_A_2 DDR3_A_9 DDR3_A_7 DDR3_A_13 DDR3_A_5 DDR3_A_0 DDR3_A_3 DDR3_BA_0 DDR3_CS0_B DDR3_A_8 DDR3_A_14 DDR3_A_6 DDR3_A_11 DDR3_A_1 DDR3_A_4 DDR3_A_12 DDR3_BA_1 DDR3_A_15 DDR3_A_10 DDR3_RST_B DDR3_RET_N DDR3_CKE_0 DDR3_CKE_1 DDR3_CK_1 VDD12_EE DDR3_DQ_22 DDR3_DQ_18 DDR3_DQ_16 DDR3_DM_2

DDR DDR DDR DDR DDR DDR DDR Power DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR Power DDR DDR DDR DDR DDR

DDR3SDRAMreferencevoltage ReferencepinforZQcalibration DDR3SDRAMPortAclockoutput DDR3SDRAMPortAclockoutputcomplementary RowAddressStrobe Ondietermination1 Ondietermination0 1.2Vpower ColumnAddressStrobe DDR3SDRAMportBchipselectoutput1 WriteEnable DDR3SDRAMbankaddress2 DDR3SDRAMaddressbusbit2 DDR3SDRAMaddressbusbit9 DDR3SDRAMaddressbusbit7 DDR3SDRAMaddressbusbit13 DDR3SDRAMaddressbusbit5 DDR3SDRAMaddressBusbit0 DDR3SDRAMaddressBusbit3 DDR3SDRAMbankaddress0

A A O O O O O P O O O O

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DDR3SDRAMportBchipselectoutput0 DDR3SDRAMaddressbusbit8 DDR3SDRAMaddressbusbit14 DDR3SDRAMaddressbusbit6 DDR3SDRAMaddressbusbit1 DDR3SDRAMaddressbusbit4

DDR3SDRAMaddressbusbit11

to

DDR3SDRAMaddressbusbit12 DDR3SDRAMaddressbusbit15 DDR3SDRAMaddressbusbit10

DDR3SDRAMbankaddress1

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DDR3SDRAMReset.ActiveLOW. DDR3standbycontrolinput.LOWisStandby.HIGHisnormal DDR3SDRAMclockenableoutput0 DDR3SDRAMclockenableoutput1 DDR3SDRAMPortBclockoutput DDR3SDRAMPortBclockoutput1complementary Digitalpowersupply1.2V DDR3SDRAMdatabusbit20 DDR3SDRAMdatabusbit22 DDR3SDRAMdatabusbit18 DDR3SDRAMdatabusbit16 DDR3SDRAMdatamask2 DDR3SDRAMdatastrobe2complementary DDR3SDRAMdatastrobe2 DDR3SDRAMdatabusbit21 DDR3SDRAMdatabusbit23 Digitalpowersupply1.2V DDR3SDRAMdatabusbit19 DDR3SDRAMdatabusbit17 DDR3SDRAMdatabusbit27 DDR3SDRAMdatabusbit25

ib u

DDR3_CK_1_N DDR3_DQ_20

Power

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D is

U24 U25 N24 Y15 N25 N23

DDR3_DQS_N_2 DDR3_DQS_2 DDR3_DQ_23

M23

DDR3_DQ_21 VDD12_EE DDR3_DQ_19 DDR3_DQ_17 DDR3_DQ_27 DDR3_DQ_25

W23 W25

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W24 V23 V24 T24 R23 R25 R24 P23 P24 L20 L21 K21 M20 J21 J20 K20 H20 G21 J22 G19 L24 K23 J24 K24 J23 J25 H23 H22 H24 G23 G25 G24 H21 F23 F24 E23 E25 E24 D23 F20 Y18

DDR3_DQ_29 DDR3_DM_3 DDR3_DQ_31 DDR3_DQS_3 DDR3_DQS_N_3 DDR3_DQ_28 DDR3_DQ_30 DDR3_DQ_26 DDR3_DQ_24 EFUSE_VDAC_AVDD25 VDAC_G VDAC_B EFUSE_VDAC_AVDD25 VDAC_R VDAC_AVSS25 VDAC_AVSS25 VDAC_COMP VDAC_REXT VDAC_CVBS VDD33_SD AUD_LINE_OUT_L AUD_LINE_OUT_R AUD_AVSS_HS AUD_AVDD25_HS AUD_AVSS AUD_AVDD25 AUD_HS_RIGHT AUD_MIC_BIAS AUD_HS_LEFT AUD_VCM AUD_VREF_DAC AUD_VREF_ADC AUD_SPK AUD_LINEIN_R_3 AUD_LINEIN_R_2 AUD_LINEIN_R_1 AUD_LINEIN_L_1 AUD_LINEIN_L_2 AUD_SPK+ VDD12_EE CARD_0 CARD_1 CARD_2 CARD_3 CARD_4 VDD12_CPU

DDR DDR DDR DDR DDR DDR DDR DDR DDR Power VideoDAC VideoDAC Power VideoDAC VideoDAC VideoDAC VideoDAC VideoDAC VideoDAC Power Audio Audio Power Power Power Power Audio Audio Audio Audio Audio Audio Audio Audio Audio Audio

DDR3SDRAMdatabusbit29 DDR3SDRAMdatamask3 DDR3SDRAMdatabusbit31 DDR3SDRAMdatastrobe3 DDR3SDRAMdatastrobe3complementary DDR3SDRAMdatabusbit28 DDR3SDRAMdatabusbit30 DDR3SDRAMdatabusbit26 DDR3SDRAMdatabusbit24 Analogpowersupply2.5VforeFuse VideoDACgreenoutputsignal VideoDACblueoutputsignal Analogpowersupply2.5VforeFuse VideoDACredoutputsignal VideoDACground VideoDACground VideoDACcompensationsignal VideoDACvoltagereference 3.3Vpower

I/O O I/O I/O I/O I/O I/O I/O I/O

VideoDACcompositevideooutputsignal

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AudioDAClineoutleftchannelanalogoutput AudioDAClineoutrightchannelanalogoutput Analogpowergroundforheadphonepoweramplifier Analogpowersupply2.5Vforheadphonepoweramplifier AnalogpowergroundforaudioADCandDAC Analogpowersupply2.5VforaudioADCandDAC AudioDACheadphonepoweramplifierrightchannelanalogoutput Biasingvoltageoutputformicrophone

to

AudioDACheadphonepoweramplifierleftchannelanalogoutput AudioDACandADCcompensationcapacitorconnection AudioDACreferencevoltage AudioADCreferencevoltage AudioDACmonospeakerdifferentialoutputminus Audiostereolinein3rightchannel Audiostereolinein2rightchannel Audiostereolinein1rightchannel Audiostereolinein1leftchannel Audiostereolinein2leftchannel Audiostereolinein3leftchannel AudioDACmonospeakerdifferentialoutputplus 1.2Vpower

te

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Audio Audio

D is

AUD_LINEIN_L_3

Audio Audio Power SDIO SDIO SDIO SDIO SDIO

PU PU PU PU PU PU

G20 C24 F22 B24 E21 F7

Cardreadermultiplexingpin0.PleaserefertofollowingTable7forfunctional I/O multiplexinformation. Cardreadermultiplexingpin1.PleaserefertofollowingTable7forfunctional I/O multiplexinformation. Cardreadermultiplexingpin2.PleaserefertofollowingTable7forfunctional I/O multiplexinformation. Cardreadermultiplexingpin3.PleaserefertofollowingTable7forfunctional I/O multiplexinformation. Cardreadermultiplexingpin4.PleaserefertofollowingTable7forfunctional I/O multiplexinformation. 1.2Vpower P

Power

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AP AO AO AP AO AP A AP A P AO AO AP AP AP AP AO AO AO A A A AO AI AI AI AI AI AI AI P AO

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 AML8726M3QuickReferenceManual

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D21 D20 E20 E19 F8 D24 D22 C25 F21 B25 F14 H6 D14 A24 C23 A23 B23 F9 C22 B22 B15 A21 E13 C20 E12 C19

CARD_5 CARD_6 CARD_7 CARD_8 VDD12_CPU BOOT_0 BOOT_1 BOOT_2 BOOT_3 BOOT_4 BOOT_5 VDD33_EE BOOT_6 BOOT_7 BOOT_8 BOOT_9 BOOT_10 VDD12_CPU BOOT_11 BOOT_12 BOOT_13 BOOT_14 BOOT_15 BOOT_16 BOOT_17 GPIOX_0

SDIO SDIO SDIO SDIO Power NAND NAND NAND NAND NAND NAND Power NAND NAND NAND NAND NAND Power NAND NAND NAND NAND NAND NAND NAND

PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PD

Cardreadermultiplexingpin5.PleaserefertofollowingTable7forfunctional I/O multiplexinformation. Cardreadermultiplexingpin6.PleaserefertofollowingTable7forfunctional I/O multiplexinformation. Cardreadermultiplexingpin7.PleaserefertofollowingTable7forfunctional I/O multiplexinformation. Cardreadermultiplexingpin8.PleaserefertofollowingTable7forfunctional I/O multiplexinformation. 1.2Vpower Bootdevicemultiplexingpin0.PleaserefertofollowingTable8forfunctional multiplexinformation. Bootdevicemultiplexingpin1. PleaserefertofollowingTable8forfunctional multiplexinformation. Bootdevicemultiplexingpin2. PleaserefertofollowingTable8forfunctional multiplexinformation. Bootdevicemultiplexingpin3. PleaserefertofollowingTable8forfunctional multiplexinformation. Bootdevicemultiplexingpin4. PleaserefertofollowingTable8forfunctional multiplexinformation. Bootdevicemultiplexingpin5.PleaserefertofollowingTable8forfunctional multiplexinformation. P I/O I/O I/O I/O I/O I/O

Bootdevicemultiplexingpin6.PleaserefertofollowingTable8forfunctional I/O multiplexinformation. Bootdevicemultiplexingpin7.PleaserefertofollowingTable8forfunctional I/O multiplexinformation. Bootdevicemultiplexingpin8.PleaserefertofollowingTable8forfunctional I/O multiplexinformation. Bootdevicemultiplexingpin9.PleaserefertofollowingTable8forfunctional I/O multiplexinformation.

to

Boot device multiplexing pin 10. Please refer to following Table8 for I/O functionalmultiplexinformation. P Boot device multiplexing pin 11. Please refer to following Table8 for I/O functionalmultiplexinformation. Boot device multiplexing pin 12. Please refer to following Table8 for I/O functionalmultiplexinformation. Boot device multiplexing pin 13. Please refer to following Table8 for I/O functionalmultiplexinformation. Boot device multiplexing pin 14. Please refer to following Table8 for functionalmultiplexinformation. Boot device multiplexing pin 15. Please refer to following Table8 for functionalmultiplexinformation. Boot device multiplexing pin 16. Please refer to following Table8 for functionalmultiplexinformation. Boot device multiplexing pin 17. Please refer to following Table8 for functionalmultiplexinformation. General purpose input/output bank X signal 0. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 1. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 2. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 3. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 4. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 5. Please refer to following Table5forfunctionalmultiplexinformation. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O P

1.2Vpower

tr

D is

D17 B19 C21 B18 C17 Y20 D18

GPIOX_1

GPIOX_2 GPIOX_3 GPIOX_4 GPIOX_5

VDD12_EE GPIOX_6

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GPIOX GPIOX GPIOX GPIOX GPIOX GPIOX Power GPIOX

te

PU PU PU PU PU PU PU PU PU PU PU

PU

1.2Vpower

General purpose input/output bank X signal 6. Please refer to following I/O Table5forfunctionalmultiplexinformation.

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P

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 AML8726M3QuickReferenceManual

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B17 C16 B16 C15 A15 C18 M6 E18 A17 E22 A19 E16 A25 D15 A11 Y13 E14 B21 F13 B20 D12 D11 E11 F10 P6 C14 E17 C13

GPIOX_7 GPIOX_8 GPIOX_9 GPIOX_10 GPIOX_11 GPIOX_12 VDD12_CPU GPIOX_13 GPIOX_14 GPIOX_15 GPIOX_16 GPIOX_17 GPIOX_18 GPIOX_19 GPIOX_20 VDD33_EE GPIOX_21 GPIOX_22 GPIOX_23 GPIOX_24 GPIOX_25 GPIOX_26 GPIOX_27 GPIOX_28 VDD12_CPU GPIOX_29 GPIOX_30 GPIOX_31 GPIOX_32 GPIOX_33 GPIOX_34 GPIOX_35 GPIOY_0 GPIOY_1 GPIOY_2

GPIOX GPIOX GPIOX GPIOX GPIOX GPIOX Power1.2V GPIOX GPIOX GPIOX GPIOX GPIOX GPIOX GPIOX GPIOX

PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU

General purpose input/output bank X signal 7. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 8. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 9. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 10. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 11. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 12. Please refer to following Table5forfunctionalmultiplexinformation. 1.2Vpower General purpose input/output bank X signal 13. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 14. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 15. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 16. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 17. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 18. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 19. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 20. Please refer to following Table5forfunctionalmultiplexinformation.

I/O I/O I/O I/O I/O I/O P

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Power
GPIOX GPIOX GPIOX GPIOX GPIOX GPIOX GPIOX GPIOX

3.3Vpower

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General purpose input/output bank X signal 21. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 22. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 23. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 24. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 25. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 26. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 27. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 28. Please refer to following Table5forfunctionalmultiplexinformation.

to

te

Power

1.2Vpower General purpose input/output bank X signal 29. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 30. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 31. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 32. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 33. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 34. Please refer to following Table5forfunctionalmultiplexinformation. General purpose input/output bank X signal 35. Please refer to following Table5forfunctionalmultiplexinformation. Generalpurposeinput/outputbankY signal0.PleaserefertofollowingTable6 forfunctionalmultiplexinformation. Generalpurposeinput/outputbankY signal1.PleaserefertofollowingTable6 forfunctionalmultiplexinformation. Generalpurposeinput/outputbankY signal2.PleaserefertofollowingTable6 forfunctionalmultiplexinformation.

GPIOX GPIOX GPIOX GPIOX GPIOX GPIOX GPIOX GPIOY GPIOY GPIOY

PU PU PU PU PU PU PU

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D is

B12 B13 C12

A13 C11 B14 B11

PU PU PU

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I/O I/O I/O I/O I/O I/O I/O I/O

P
I/O I/O I/O I/O I/O I/O I/O I/O P I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

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C10 B10 C9 A9 B9 C8 B8 J5 C7 E9 B7 E10 A7 D9 D8 E8 E7 E6 C6 B6 C5 U23 AA25 AE19 AE24 D6 K11 K12 K13 K14 K15 L10 L11 L12 L13 L14 L15 L16 L25 M10 M11

GPIOY_3 GPIOY_4 GPIOY_5 GPIOY_6 GPIOY_7 GPIOY_8 GPIOY_9 VDD12_CPU GPIOY_10 GPIOY_11 GPIOY_12 GPIOY_13 GPIOY_14 GPIOY_15 GPIOY_16 GPIOY_17 GPIOY_18 GPIOY_19 GPIOY_20 GPIOY_21 GPIOY_22 SSTL_VDD_RET GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

GPIOY GPIOY GPIOY GPIOY GPIOY GPIOY GPIOY Power GPIOY GPIOY GPIOY GPIOY GPIOY GPIOY GPIOY GPIOY GPIOY GPIOY GPIOY GPIOY GPIOY

PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU

1.2Vpower

te

Power

General purpose input/output bank Y signal 10. Please refer to following Table6forfunctionalmultiplexinformation. General purpose input/output bank Y signal 11. Please refer to following Table6forfunctionalmultiplexinformation. General purpose input/output bank Y signal 12. Please refer to following Table6forfunctionalmultiplexinformation. General purpose input/output bank Y signal 13. Please refer to following Table6forfunctionalmultiplexinformation. General purpose input/output bank Y signal 14. Please refer to following Table6forfunctionalmultiplexinformation. General purpose input/output bank Y signal 15. Please refer to following Table6forfunctionalmultiplexinformation. General purpose input/output bank Y signal 16. Please refer to following Table6forfunctionalmultiplexinformation. General purpose input/output bank Y signal 17. Please refer to following Table6forfunctionalmultiplexinformation. General purpose input/output bank Y signal 18. Please refer to following Table6forfunctionalmultiplexinformation. General purpose input/output bank Y signal 19. Please refer to following Table6forfunctionalmultiplexinformation. General purpose input/output bank Y signal 20. Please refer to following Table6forfunctionalmultiplexinformation. General purpose input/output bank Y signal 21. Please refer to following Table6forfunctionalmultiplexinformation. General purpose input/output bank Y signal 22. Please refer to following Table6forfunctionalmultiplexinformation. DDR3SDRAMretentiondomainpowersupply

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Generalpurposeinput/outputbankY signal3.PleaserefertofollowingTable6 forfunctionalmultiplexinformation. Generalpurposeinput/outputbankY signal4.PleaserefertofollowingTable6 forfunctionalmultiplexinformation. Generalpurposeinput/outputbankY signal5.PleaserefertofollowingTable6 forfunctionalmultiplexinformation. Generalpurposeinput/outputbankY signal6.PleaserefertofollowingTable6 forfunctionalmultiplexinformation. Generalpurposeinput/outputbankY signal7.PleaserefertofollowingTable6 forfunctionalmultiplexinformation. Generalpurposeinput/outputbankY signal8.PleaserefertofollowingTable6 forfunctionalmultiplexinformation. Generalpurposeinput/outputbankY signal9.PleaserefertofollowingTable6 forfunctionalmultiplexinformation.

I/O I/O I/O I/O I/O I/O I/O

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 AML8726M3QuickReferenceManual

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M12 M13 M14 M15 M16 N10 N11 N12 N13 N14 N15 N16 P10 P11 P12 P13 P14 P15 P16 R10 R11 R12 R13 R14 R15 R16 T11 T12 T13 T14 T15

GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND

Abbreviations: I=Digitalinputpin O=Digitaloutputpin I/O=Digitalinput/outputpin AI=Analoginputpin AO=Analogoutputpin AIO=Analoginput/outputpin P=Powerpin AP=Analogpowerpin NC=Noconnection PU=PullUp PD=Pulldown Z=TriState

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3.2PinMultiplexingTables
Multipleusagepinsareusedtoconversepinconsumptionfordifferentfeatures.TheAML8726M3devicescanbeusedin many different applicationsbut each application will not utilize all the on chip features. As a result, some of the features sharethesamepin.MostofthemultipleusagepinscanbeusedasaGPIOpinalso.

Table2.GPIOA_xandGPIOB_xMultiFunctionPin
Pin# A5 B5 C4 B4 D4 A3 B3 A2 A1 B2 B1 C3 C1 C2 D3 D2 E3 E1 E2 F3 D5 E5 E4 F4 F5 G5 G6 G1 F2 G3 H5 G2 H3 H2 J3 J1 H4 J4 K6 K5 L6 L5 L4 M4 J2 K3 K2 L3 PinName GPIOA_0 GPIOA_1 GPIOA_2 GPIOA_3 GPIOA_4 GPIOA_5 GPIOA_6 GPIOA_7 GPIOA_8 GPIOA_9 GPIOA_10 GPIOA_11 GPIOA_12 GPIOA_13 GPIOA_14 GPIOA_15 GPIOA_16 GPIOA_17 GPIOA_18 GPIOA_19 GPIOA_20 GPIOA_21 GPIOA_22 GPIOA_23 GPIOA_24 GPIOA_25 GPIOA_26 GPIOA_27 GPIOB_0 GPIOB_1 GPIOB_2 GPIOB_3 GPIOB_4 GPIOB_5 GPIOB_6 GPIOB_7 GPIOB_8 GPIOB_9 GPIOB_10 GPIOB_11 GPIOB_12 GPIOB_13 GPIOB_14 GPIOB_15 GPIOB_16 GPIOB_17 GPIOB_18 GPIOB_19 LCDInput LCDin_R0 LCDin_R1 LCDin_R2 LCDin_R3 LCDin_R4 LCDin_R5 LCDin_R6 LCDin_R7 LCDin_G0 LCDin_G1 LCDin_G2 LCDin_G3 LCDin_G4 LCDin_G5 LCDin_G6 LCDin_G7 LCDin_B0 LCDin_B1 LCDin_B2 LCDin_B3 LCDin_B4 LCDin_B5 LCDin_B6 LCDin_B7 LCDin_CLK LCDin_HS LCDin_VS LCDin_DE LCD_R0 LCD_R1 LCD_R2 LCD_R3 LCD_R4 LCD_R5 LCD_R6 LCD_R7 LCD_G0 LCD_G1 LCD_G2 LCD_G3 LCD_G4 LCD_G5 LCD_G6 LCD_G7 LCD_B0 LCD_B1 LCD_B2 LCD_B3 FEC/ENC FEC_D0_A FEC_D1_A FEC_D2_A FEC_D3_A/ FEC_D0_C FEC_D4_A/ FEC_CLK_C FEC_D5_A/ FEC_SOP_C FEC_D6_A/ FEC_D_VALID_C FEC_D7_A/ FEC_FAIL_C FEC_CLK_A FEC_SOP_A FEC_D_VALID_A FEC_FAIL_A ENC_0 ENC_1 ENC_2 ENC_3 ENC_4 ENC_5 ENC_6 ENC_7 ENC_8 ENC_9 ENC_10 ENC_11 ENC_12 ENC_13 ENC_14 ENC_15 FEC_D0_B FEC_D1_B FEC_D2_B FEC_D3_B FEC_D4_B FEC_D5_B FEC_D6_B FEC_D7_B FEC_CLK_B FEC_SOP_B FEC_D_VALID_B FEC_FAIL_B FEC_FAIL_OUT FEC_D_VALID_OUT FEC_SOP_OUT FEC_CLK_OUT FEC_D0_OUT FEC_D1_OUT FEC_D2_OUT FEC_D3_OUT

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L1 L2 M3 M2

GPIOB_20 GPIOB_21 GPIOB_22 GPIOB_23

LCD_B4 LCD_B5 LCD_B6 LCD_B7

FEC_D4_OUT FEC_D5_OUT FEC_D6_OUT FEC_D7_OUT

Table3.GPIOC_xandGPIOD_xMultiFunctionpins
Pin# N3 N1 N2 P2 P3 R3 R4 R2 T3 T2 M5 N5 N6 P5 P4 R1 R5 T6 T5 W1 AB12 AA13 AA14 AB14 AA15 PinName GPIOD_0 GPIOD_1 GPIOD_2 GPIOD_3 GPIOD_4 GPIOD_5 GPIOD_6 GPIOD_7 GPIOD_8 GPIOD_9 GPIOC_0 GPIOC_1 GPIOC_2 GPIOC_3 GPIOC_4 GPIOC_5 GPIOC_6 GPIOC_7 GPIOC_8 GPIOC_9 GPIOC_10 GPIOC_11 GPIOC_12 GPIOC_13 GPIOC_15 LCD/LED LCD_VGHL_PWM LED_BL_PWM LCD_VGHL_PWM LED_BL_PWM FEC/ENC ENC_16 ENC_17 TCON TCON_0_B(LCD)/TCON_STH1_B TCON_1_B/TCON_STV1_B TCON_2_B/TCON_OEH_B TCON_3_B/TCON_CPV1_B TCON_4_B/TCON_OEV1_B TCON_5_B/TCON_CPH50_B/TCON_CPH1_B/ TCON_CPH2_B/TCON_CPH3_B TCON_6_B/TCON_VCOM_B TCON_7_B TCON_0_A(mLVDS)/TCON_STH1 TCON_1_A/TCON_STV1 TCON_2_A/TCON_OEH SPI/SPDIF HDMI CLK PCM/PWM PWM_C PWM_D VGA VGA_HS VGA_VS

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SPDIF_IN SPDIF_OUT HDMI_HPD(5V) HDMI_SDA(5V) HDMI_SCL(5V) HDMI_CEC

TCON_3_A/TCON_CPV1

TCON_4_A/TCON_OEV1

to

TCON_5_A/TCON_CPH50/TCON_CPH1/TCON_CPH/ TCON_CPH3 TCON_6_A/TCON_VCOM

te

TCON_7_A

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CLK_OUT1(XTAL,RTC, PLL) PWM_A PWM_A PWM_B PWM_C

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Table4.GPIOAO_xMultiFunctionpins
Pin# U4 U6 Y2 W5 W3 U5 W2 Y5 Y3 V5 AA3 AA1 PinName GPIOAO_0 GPIOAO_1 GPIOAO_2 GPIOAO_3 GPIOAO_4 GPIOAO_5 GPIOAO_6 GPIOAO_7 GPIOAO_8 GPIOAO_9 GPIOAO_10 GPIOAO_11 UART UART_TX_AO UART_RX_AO UART_CTS_AO UART_RTS_AO I2C/I2S I2C_SCK_AO/I2C_CLK_SLAVE_AO I2C_SDA_AO//I2C_SDA_SLAVE_AO I2C_SCK_AO/I2C_SCK_SLAVE_AO I2C_SDA_AO/I2C_SDA_SLAVE_AO JTAG JTAG_TDO JTAG_TDI JTAG_TMS JTAG_TCK JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO CLK Remote

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CLK_OUT2(XTAL,RTC,PLL) CLK_OUT2(XTAL,RTC,PLL)

REMOTE_INPUT

 AML8726M3QuickReferenceManual

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Table5.GPIOX_xMultiFunctionpins
Pin# C19 D17 B19 C21 B18 PinName GPIOX_0 GPIOX_1 GPIOX_2 GPIOX_3 GPIOX_4 SPI/SPDIF UART I2C/I2S I2S_OUT_CH67 I2S_OUT_CH45 I2S_OUT_CH23 I2S_OUT_CH01 SD SDXC_D0_A/SD_D0_A SDXC_D1_A/SD_D1_A SDXC_D2_A/SD_D2_A SDXC_D3_A/SD_D3_A SDXC_D4_A ISO7816 PCM/PWM PCM_OUT

C17

GPIOX_5

I2S_IN_CH01

D18

GPIOX_6

I2S_LR_CLK

SDXC_D6_A

C16 B16 C15 A15 C18 E18 A17 E22 A19 E16 A25 D15 A11 E14 B21 F13 B20 D12 D11 E11 F10

GPIOX_8 GPIOX_9 GPIOX_10 GPIOX_11 GPIOX_12 GPIOX_13 GPIOX_14 GPIOX_15 GPIOX_16 GPIOX_17 GPIOX_18 GPIOX_19 GPIOX_20 GPIOX_21 GPIOX_22 GPIOX_23 GPIOX_24

UART_TX_A UART_RX_A UART_CTS_A UART_RTS_A UART_TX_B UART_RX_B

ro m

B17

GPIOX_7

I2S_AM_CLK

SDXC_D7_A

SDXC_CLK_A/SD_CLK_A

as te r!
SDXC_D5_A ISO7816_DET ISO7816_RESET ISO7816_CLK ISO7816_DATA ISO7816_DET ISO7816_RESET ISO7816_CLK ISO7816_DATA

PCM_IN

PCM_FS

PCM_CLK

SDXC_CMD_A/SD_CMD_A SDXC_GPIO0_A SDXC_GPIO1_A SDXC_GPIO2_A

to
I2S_AM_CLK I2S_AO_CLK I2S_LR_CLK

I2S_AO_CLK

PCM_CLK PCM_FS PCM_IN

UART_CTS_B

ib u
UART_TX_C UART_RX_C

UART_RTS_B

te

I2S_IN_CH01/I2S_OUT_CH01 I2C_SDA_A I2C_SCK_A I2C_SDA_B I2C_SCK_B I2C_SCK_C I2C_SDA_C

UART_CTS_C/UART_TX_B

GPIOX_25 GPIOX_26

C14 E17 C13

B12 B13 C12 A13

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GPIOX_27 GPIOX_28 GPIOX_29 GPIOX_30 GPIOX_31 GPIOX_32 GPIOX_33 GPIOX_34 GPIOX_35

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SPI_SS2 SPI_RDYn SPI_SS0 SPI_SS1 SPI_SCLK SPI_MOSI SPI_MISO

UART_RTS_C/UART_RX_B

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Table6.GPIOY_xMultiFunctionpins
Pin# C11 B14 B11 C10 B10 C9 A9 B9 C8 B8 C7 E9 B7 E10 A7 D9 D8 E8 E7 E6 C6 B6 C5 PinName GPIOY_0 GPIOY_1 GPIOY_2 GPIOY_3 GPIOY_4 GPIOY_5 GPIOY_6 GPIOY_7 GPIOY_8 GPIOY_9 GPIOY_10 GPIOY_11 GPIOY_12 GPIOY_13 GPIOY_14 GPIOY_15 GPIOY_16 GPIOY_17 GPIOY_18 GPIOY_19 GPIOY_20 GPIOY_21 GPIOY_22 RMII RMII_CLK50_IN_OUT RMII_RX_ERR RMII_CRS_DV RMII_RX_DATA1 RMII_RX_DATA0 RMII_TX_EN RMII_TX_DATA1 RMII_TX_DATA0 RMII_MDC RMII_MDIO ITU601 ITU601_FIR/ITU601_IDQ ITU601_HS ITU601_VS ITU601_D0 CLK

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ITU601_D1 ITU601_D2 ITU601_D3 ITU601_D4 ITU601_D5 ITU601_D6

P to

ITU601_D7 ITU601_CLK

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CLK_OUT0(XTAL,RTC,PLL)

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Table7.CARD_xMultiFunctionPin
Pin# G20 C24 F22 B24 E21 D21 D20 E20 E19 PinName CARD_0 CARD_1 CARD_2 CARD_3 CARD_4 CARD_5 CARD_6 CARD_7 CARD_8 SDXC SDXC_D0_B SDXC_D1_B SDXC_D2_B SDXC_D3_B SDXC_CLK_B SDXC_CMD_B SDXC_GPIO0_B SDXC_GPIO1 SDXC_GPIO2 SDIO SD_D0_B SD_D1_B SD_D2_B SD_D3_B SD_CLK_B SD_CMD_B

Table8.BOOT_xMultiFunctionPin
Pin# D24 D22 C25 F21 B25 F14 D14 A24 C23 A23 B23 C22 B22 B15 E12 E13 C20 E12 PinName BOOT_0 BOOT_1 BOOT_2 BOOT_3 BOOT_4 BOOT_5 BOOT_6 BOOT_7 BOOT_8 BOOT_9 BOOT_10 BOOT_11 BOOT_12 BOOT_13 BOOT_14 BOOT_15 BOOT_16 BOOT_17 NAND NAND_IO_0 NAND_IO_1 NAND_IO_2 NAND_IO_3 NAND_IO_4 NAND_IO_5 NAND_IO_6 NAND_IO_7 NAND_CE0boot NAND_CE1 NAND_CE2/NAND_RB0 NAND_CE3/NAND_BR1 NAND_ALE NAND_CLE NAND_WEn_CLK NAND_REn_WR NAND_DQS SDXC SDXC_D0_C SDXC_D1_C SDXC_D2_C SDXC_D3_C SDXC_D4_C SDXC_D5_C SDXC_D6_C SDXC_D7_C SDXC_CMD_C SDXC_CLK_C(bootable)

SDIO SD_D0_C SD_D1_C SD_D2_C SD_D3_C SD_CMD_C SD_CLK_C

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NOR_SPI SPI_NOR_D_A SPI_NOR_Q_A SPI_NOR_C_A SPI_NRO_CS_n_A

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4.SignalDescription
Table9.LCD/LEDSignalDescription
SignalName LCDin_R0 LCDin_R1 LCDin_R2 LCDin_R3 LCDin_R4 LCDin_R5 LCDin_R6 LCDin_R7 LCDin_G0 LCDin_G1 LCDin_G2 LCDin_G3 LCDin_G4 LCDin_G5 LCDin_G6 LCDin_G7 LCDin_B0 LCDin_B1 LCDin_B2 LCDin_B3 LCDin_B4 LCDin_B5 LCDin_B6 LCDin_B7 LCDin_CLK LCDin_HS LCDin_VS LCDin_DE LCD_R0 LCD_R1 LCD_R2 LCD_R3 LCD_R4 LCD_R5 LCD_R6 LCD_R7 Type I I I I I I I I I I I I I I I I I I I I I I I I Description Digitalvideoinputredbit0(LSB) Digitalvideoinputredbit1 Digitalvideoinputredbit2 Digitalvideoinputredbit3 Digitalvideoinputredbit4 Digitalvideoinputredbit6 Digitalvideoinputredbit5

Digitalvideoinputredbit7(MSB) Digitalvideoinputgreenbit1 Digitalvideoinputgreenbit2 Digitalvideoinputgreenbit3 Digitalvideoinputgreenbit4 Digitalvideoinputgreenbit5

Digitalvideoinputgreenbit0(LSB)

to
I I

te

I I O O O O O O O O O O O O O O O O O O O

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LCD_G0 LCD_G1 LCD_G2 LCD_G3 LCD_G4 LCD_G5 LCD_G6 LCD_G7 LCD_B0 LCD_B1 LCD_B2

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Digitalvideoinputbluebit1 Digitalvideoinputbluebit2 Digitalvideoinputbluebit3 Digitalvideoinputbluebit4 Digitalvideoinputbluebit5 Digitalvideoinputbluebit6 Digitalvideoinputclock

Digitalvideoinputgreenbit6 Digitalvideoinputgreenbit7(MSB) Digitalvideoinputbluebit0(LSB)

Digitalvideoinputbluebit7(MSB) Digitalvideoinputhorizontalsync Digitalvideoinputverticalsync Digitalvideoinputdataenable TTLLCDdataoutputredbit0(LSB) TTLLCDdataoutputredbit1 TTLLCDdataoutputredbit2 TTLLCDdataoutputredbit3 TTLLCDdataoutputredbit4 TTLLCDdataoutputredbit5 TTLLCDdataoutputredbit6 TTLLCDdataoutputredbit7(MSB) TTLLCDdataoutputgreenbit0(LSB) TTLLCDdataoutputgreenbit1 TTLLCDdataoutputgreenbit2 TTLLCDdataoutputgreenbit3 TTLLCDdataoutputgreenbit4 TTLLCDdataoutputgreenbit5 TTLLCDdataoutputgreenbit6 TTLLCDdataoutputgreenbit7(MSB) TTLLCDdataoutputbluebit0(LSB) TTLLCDdataoutputbluebit1 TTLLCDdataoutputbluebit2

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SignalName LCD_B3 LCD_B4 LCD_B5 LCD_B6 LCD_B7 LCD_VGHL_PWM LED_BL_PWM

Type O O O O O O O TTLLCDdataoutputbluebit3 TTLLCDdataoutputbluebit4 TTLLCDdataoutputbluebit5 TTLLCDdataoutputbluebit6

Description

TTLLCDdataoutputbluebit7(MSB) LCDpanelVGHLtuningpulsewidthmodulationsignaloutput LEDbacklighttuningpulsewidthmodulationsignaloutput

Table10.FEC/ENCInterfaceSignalDescription
SignalName FEC_D0_A FEC_D1_A FEC_D2_A FEC_D3_A/ FEC_D0_C FEC_D4_A/ FEC_CLK_C FEC_D5_A/ FEC_SOP_C FEC_D6_A/ FEC_D_VALID_C FEC_D7_A/ FEC_FAIL_C FEC_CLK_A FEC_SOP_A FEC_D_VALID_A FEC_FAIL_A FEC_D0_B FEC_D1_B FEC_D2_B FEC_D3_B FEC_D4_B FEC_D5_B FEC_D6_B FEC_D7_B Type I I I I I I I I I I I I I I I I I I I I I I I I O O O O O O O O O O O O I/O Description TSinputportAdatabusbit0(LSB) TSinputportAdatabusbit1 TSinputportAdatabusbit2

to te

ib u

FEC_CLK_B

FEC_SOP_B

FEC_D_VALID_B FEC_FAIL_B FEC_D0_OUT FEC_D1_OUT FEC_D2_OUT FEC_D3_OUT FEC_D4_OUT FEC_D5_OUT FEC_D6_OUT FEC_D7_OUT FEC_FAIL_OUT

tr

D is

FEC_D_VALID_OUT FEC_SOP_OUT FEC_CLK_OUT ENC_0

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TBD

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TSinputportAclock TSinputportBclock TSoutputdatabusbit1 TSoutputdatabusbit2 TSoutputdatabusbit3 TSoutputdatabusbit4 TSoutputdatabusbit5 TSoutputdatabusbit6 TSoutputdatafailuresignal TSoutputdatavalidsignal TSoutputclock

TSinputportAdatabusbit3 SerialTSinputdata TSinputportAdatabusbit4 SerialTSinputclock TSinputportAdatabusbit5 SerialTSstartofstreamsignal TSinputportAdatabusbit6 SerialTSdatavalidsignal

TSinputportAdatabusbit7(MSB) SerialTSdatafailuresignal TSinputportAstartofstreamsignal

TSinputportAdatevalidsignal TSinputportBdatabusbit0(LSB) TSinputportBdatabusbit1 TSinputportBdatabusbit2 TSinputportBdatabusbit3 TSinputportBdatabusbit4 TSinputportBdatabusbit5 TSinputportBdatabusbit6 TSinputportBdatabusbit7(MSB) TSinputportBstartofstreamsignal TSinputportBdatevalidsignal

TSinputportAdatafailuresignal

TSinputportBdatafailuresignal TSoutputdatabusbit0(LSB)

TSoutputdatabusbit7(MSB)

TSoutputstartofstreamsignal

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SignalName ENC_1 ENC_2 ENC_3 ENC_4 ENC_5 ENC_6 ENC_7 ENC_8 ENC_9 ENC_10 ENC_11 ENC_12 ENC_13 ENC_14 ENC_15 ENC_16 ENC_17

Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

Description TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD

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Table11.TCONInterfaceSignalDescription
SignalName TCON_0_B/TCON_STH1_B TCON_1_B/TCON_STV1_B TCON_2_B/TCON_OEH_B TCON_3_B/TCON_CPV1_B TCON_4_B/TCON_OEV1_B TCON_5_B/TCON_CPH50_B/TCON_CPH1_B/TCON_CPH2_B/TCON_CPH3_B TCON_6_B/TCON_VCOM_B TCON_7_B TCON_0_A/TCON_STH1 TCON_1_A/TCON_STV1 TCON_2_A/TCON_OEH TCON_3_A/TCON_CPV1 TCON_4_A/TCON_OEV1 TCON_5_A/TCON_CPH50/TCON_CPH1/TCON_CPH/TCON_CPH3 TCON_6_A/TCON_VCOM TCON_7_A SignalName SPDIF_IN SPDIF_OUT Type O O O O O O O O O O O Description ProgrammableTCONportBsignal0forTTLLCD st TCON1 sourcedriverstartpulseforTTLLCD ProgrammableTCONportBsignal1forTTLLCD st TCON1 gatedriverstartpulseforTTLLCD ProgrammableTCONportBsignal2forTTLLCD TCONoutputenablesignalforsourcedriverforTTLLCD ProgrammableTCONportBsignal3forTTLLCD st TCON1 gatedrivershiftclockoutputforTTLLCD

ProgrammableTCONportBsignal5forTTLLCD TCONsourcedrivershiftclockoutputforTTLLCD ProgrammableTCONportBsignal6forTTLLCD TCONPOLdrivingsignalforTTLLCD ProgrammableTCONportBsignal7forTTLLCD

ProgrammableTCONportAsignal0forLVDSandminiLVDS ProgrammableTCONportAsignal1forMINILVDS

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O O O

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Type I O Type O I O O O O I

te

Table12.SPDIFInterfaceSignalDescription
Description SPDIFinputsignal SPDIFoutputsignal

ib u

Table13.SPIIOInterfaceSignalDescription
Description SPIslaveselect2 SPIReadysignal,lowactive SPIslaveselect0 SPIslaveselect1 SPISerialClock SPIMasterOutput,SlaveInput SPIMasterInput,SlaveOutput

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SignalName SPI_SS2 SPI_RDYn SPI_SS0 SPI_SS1 SPI_SCLK SPI_MOSI SPI_MISO

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O O

ProgrammableTCONportAsignal2forMINILVDS ProgrammableTCONportAsignal3forMINILVDS ProgrammableTCONportAsignal4forMINILVDS

ProgrammableTCONportAsignal5forMINILVDS ProgrammableTCONportAsignal6forMINILVDS ProgrammableTCONportAsignal7forMINILVDS

as te r!

ProgrammableTCONportBsignal4forTTLLCD st TCONoutputenablesignalfor1 gatedriverforTTLLCD

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Table14.UARTInterfaceSignalDescription
SignalName UART_TX_AO UART_RX_AO UART_CTS_AO UART_RTS_AO UART_TX_A UART_RX_A UART_CTS_A UART_RTS_A UART_TX_B UART_RX_B UART_CTS_B UART_RTS_B UART_TX_C UART_RX_C UART_CTS_C/UART_TX_B UART_RTS_C/ UART_RX_B Type O I I O O I I O O I I O O I I O UARTPortAOdataoutput UARTPortAOdatainput UARTPortAOClearToSendSignal UARTPortAOReadyToSendSignal UARTPortAdataoutput UARTPortAdatainput UARTPortAClearToSendSignal UARTPortBdataoutput UARTPortBdatainput UARTPortAReadyToSendSignal Description

UARTPortBClearToSendSignal UARTPortCdataoutput UARTPortCdatainput

UARTPortBReadyToSendSignal

SignalName I2S_OUT_CH67 I2S_OUT_CH45 I2S_OUT_CH23 I2S_OUT_CH01 I2S_IN_CH01 I2S_LR_CLK I2S_AM_CLK I2S_AO_CLK Type O O O O I

Table15.I2SInterfaceSignalDescription

to
O O

SignalName I2C_SCK_AO/I2C_SCK_SLAVE_AO I2C_SDA_A I2C_SCK_A I2C_SCK_B I2C_SCK_C I2C_SDA_C I2C_SDA_B

ib u

te

O/I

Table16.I2CInterfaceSignalDescription
Type I/O I/O I/O I/O I/O I/O I/O I/O Description AlwaysonI2Cserialclockline,MasterorSlave,needpullhigh AlwaysonI2Cserialdataline,MasterorSlave,needpullhigh I2CbusportAdatainput/output,MasterorSlave,needpullhigh I2CbusportAclockinput/output,MasterorSlave,needpullhigh I2CbusportBdatainput/output,MasterorSlave,needpullhigh I2CbusportBclockinput/output,MasterorSlave,needpullhigh I2CbusportCclockinput/output,MasterorSlave,needpullhigh I2CbusportCclockinput/output,MasterorSlave,needpullhigh

I2C_SDA_AO/I2C_SDA_SLAVE_AO

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I2SLeft/RightClockOut I2Smasterclockoutput I2Sdataclockinput/output

UARTPortCClearToSendSignal UARTPortBdataoutput UARTPortCClearToSendSignal UARTPortBdatainput

Description I2SAudioDataOutputchannel6and7 I2SAudioDataOutputchannel4and5 I2SAudioDataOutputchannel2and3 I2SAudioDataOutputchannel0and1

I2SAudioDataInputchannel0and1

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Table17.HDMIInterfaceSignalDescription
SignalName HDMI_HPD(5V) HDMI_SDA(5V) HDMI_SCL(5V) HDMI_CEC Type I/O I/O I/O I/O Description HDMIhotplugindetectionsignalinput HDMII2Ccontrolinterfacedatasignal,needpullhigh HDMII2Ccontrolinterfaceclocksignal,needpullhigh HDMICEC(Consumerelectronicscontrol)

Table18.SDInterfaceSignalDescription
SDXC_D1_A/SD_D1_A SDXC_D2_A/SD_D2_A SDXC_D3_A/SD_D3_A SDXC_D4_A SDXC_D5_A SDXC_D6_A SDXC_D7_A SDXC_CLK_A/SD_CLK_A SDXC_CMD_A/SD_CMD_A SDXC_GPIO0_A SDXC_GPIO1_A SDXC_GPIO2_A I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I/O SDXC/SDIOPortAdatabusbit1signal SDXC/SDIOPortAdatabusbit2signal SDXCPortAdatabusbit4signal SDXCPortAdatabusbit5signal SDXCPortAdatabusbit6signal SDXCPortAdatabusbit7signal SDXC/SDIOPortAclocksignal SDXCPortAGPIObit0signal SDXCPortAGPIObit1signal SDXCPortAGPIObit2signal

SDXC/SDIOPortAdatabusbit3signal

SignalName ISO7816_DET ISO7816_RESET ISO7816_CLK ISO7816_DATA Type I O O

to
I/O

ib u

SignalName RMII_CLK50_IN_OUT RMII_RX_ERR RMII_CRS_DV

te

Table20.RMIIInterfaceSignalDescription
Type I/O I I I I O O O O I/O Description EthernetRMIIinterfaceMasterClockinput/output(50MHz) EthernetRMIIinterfaceReceiveError EthernetRMIIinterfaceCarrierSense/ReceiveDataValidSignal EthernetRMIIinterfaceReceiveData1 EthernetRMIIinterfaceReceiveData0 EthernetRMIIInterfaceTransmitEnable EthernetRMIIinterfaceTransmitData1 EthernetRMIIinterfaceTransmitData0 EthernetRMIIinterfaceManagementDataClock EthernetRMIIinterfaceManagementDatainput/output

RMII_RX_DATA1 RMII_RX_DATA0 RMII_TX_EN RMII_TX_DATA1 RMII_TX_DATA0 RMII_MDC RMII_MDIO

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Table19.ISO7816InterfaceSignalDescription
Description ISO7816detectsignal ISO7816resetsignal ISO7816clocksignal ISO7816serialdatasignal

ro m

SDXC/SDIOPortAcommandsignal

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SignalName SDXC_D0_A/SD_D0_A

Type I/O

Description SDXC/SDIOPortAdatabusbit0signal

 AML8726M3QuickReferenceManual

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Table21.ITU601InterfaceSignalDescription
SignalName ITU601_FIR/ ITU601_IDQ ITU601_HS ITU601_VS ITU601_D0 ITU601_D1 ITU601_D2 ITU601_D3 ITU601_D4 ITU601_D5 ITU601_D6 ITU601_D7 ITU601_CLK Type I I I I I I I I I I I I/O Description ITU601VideoInputFieldSignal ITU601VideoInputHorizontalSyncSignal ITU601VideoInputVerticalSyncSignal ITU601VideoInputDataBusbit0(LSB) ITU601VideoInputDataBusbit1 ITU601VideoInputDataBusbit2 ITU601VideoInputDataBusbit3 ITU601VideoInputDataBusbit5 ITU601VideoInputDataBusbit6 ITU601VideoInputMasterClock ITU601VideoInputDataBusbit4

ITU601VideoInputDataBusbit7(MSB)

SignalName JTAG_TDO JTAG_TDI JTAG_TMS JTAG_TCK Type O I I I JTAGScandatainput

Table22.JTAGInterfaceSignalDescription
JTAGScandataoutput

SignalName CLK_OUT2(XTAL,RTC,PLL) CLK_OUT1(XTAL,RTC,PLL) CLK_OUT0(XTAL,RTC,PLL) Type O O O

Table23.CLKInterfaceSignalDescription

to
Type I Type O O O O

SignalName REMOTE_INPUT

Table24.RemoteInterfaceSignalDescription

SignalName PWM_A PWM_B PWM_C

ib u

te

Table25.PWMInterfaceSignalDescription
Description PWMchannelAoutputsignal PWMchannelBoutputsignal PWMchannelCoutputsignal PWMchannelDoutputsignal

D is

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PWM_D

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JTAGTestmodeselectinput JTAGTestclockinput Description XTAL,RTCCLK,PLLclockoutput2 XTAL,RTCCLK,PLLclockoutput1 XTAL,RTCCLK,PLLclockoutput0 Description IRRemotecontrollerinputsignal

as te r!
Description

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Table26.PCMInterfaceSignalDescription
SignalName PCM_OUT PCM_IN PCM_FS PCM_CLK Type O I O O PCMoutputdatastream PCMinputdatastream PCMframesynchronization PCMmasterclockinput Description

Table27.VGAInterfaceSignalDescription
O O VGA_VS VGAoutputverticalsyncsignal

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SignalName VGA_HS

Type

Description VGAoutputhorizontalsyncsignal

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4. OperatingConditions
AbsoluteMaximumRatings
Thetablebelowgivestheabsolutemaximumratings.Exposuretostressesbeyondthoselistedinthistablemayresultin permanentdevicedamage,unreliabilityorboth. Characteristic Value Unit 1.2VCoreSupplyVoltage 1.4 V 1.5VSupplyVoltage 1.65 V 2.5VSupplyVoltage 2.75 V 3.3VSupplyVoltage 3.63 V Inputvoltage,VI 0.5~VDD+0.3 V JunctionTemperature TBD C

RecommendedOperatingConditions
Symbol VDD(CORE) 1.2VCoreSupplyVoltage VDD(SSTL) 1.5VSSTLSupplyVoltage VDD(AVDD) 2.5VAVDDSupplyVoltage VDD(IO) 3.3VIOSupplyVoltage TJ JunctionTemperature Parameter

DCCharacteristics
VDD=3.3+/0.3V,TA=0to75C Symbol Parameters VIH HighLevelInput VIL LowLevelInput VT+ Schmitttrigger,positivegoingThreshold VT Schmitttrigger,negativegoingthreshold Vol Lowleveloutputvoltage

to

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Condition Ioh=2.0mA Iol=2.0mA 35/37

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Voh

Highleveloutputvoltage

te

D is

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Min. 1.14 1.35 2.38 3.14 0 Typ. 1.2 1.5 2.5 3.3 Max 1.32 1.65 2.75 3.63 125 Unit V V V V C Min Typ 2.0 0.3 1.5 0.93 2.4 Max 3.3 0.8 0.4 Unit V V V V V AMLOGIC,Inc.Proprietary

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5. MechanicalDimensions
TheAML8726M3processorcomesina445ballsLFBGARoHSpackage.Themechanicaldimensionsaregiveninmillimeters asbelow:

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