Introducci al llenguatge AHDL

En aquest apartat es pretn fer una petita introducci al l l e n g u a t g e q u e s u t i l i t z a r p e r i mp l e m e n t a r l a u n i t a t d e u n i t a t de c o n t r o l . E s v e u r a n a l g u n s e x e m p l e s p er c o n e i x e r l a s e v a e s t r u c t u r a , aix com unes taules per conixer els operadors que es poden utilitzar i la forma dimplementar una mquina destats, registres, comptadors, etc..

1- Operado rs lgics

Operador ! NOT & AND !& NAND # OR !# NOR $ XOR !$ XNOR 2- Comparadors

Exemple !a NOT a a&b a AND b a[3..1] !& b[5..3] a[3..1] NAND b[5..3] a#b a OR b c[8..5] !# d[7..4] c[8..5] NOR d[7..4] a$b a XOR b x2 !$ x4 x2 XNOR x4

Descripci negada AND AND negada OR OR negada OR exclusiva NOR exclusiva

Comparador == != < <= > >=

Tipus lgic lgic aritmtic aritmtic aritmtic aritmtic

exemple addr[19..4] = = BB800 b1 != b3 a[] < b [] a[] <= b[] a[] > b[] a[] >= 0

Descripci Igual a No igual a Menor que Menor o igual que Mayor que Mayor o igual que

3- Operado rs aritmtic s

Operador + (unario)

Exemple +1

Descripci Positivo 2

- (unario) + 4- TDF

-a[4..1] count[7..0] + delta[7..0] a[] b[]

Negativo Suma resta

SUBDESIGN boole2 ( a0, a1, b :INPUT; out :OUTPUT; ) VARIABLE a_equals_2 : NODE; BEGIN a_equals_2 = a1 & !a0; out = a_equals_2 # b; END; 5- GDF

Definici E/S

Definici de variables Descripci del circuit

6- Registr es

SUBDESIGN bur_reg ( clk, load, d[7..0] q[7..0] ) VARIABLE ff[7..0] : DFFE; BEGIN ff[].clk = clk; ff[].ena = load; ff[].d = d[]; q[] = ff[].q; END;

:INPUT; :OUTPUT;

7- Comptadors

SUBDESIGN ahdlcnt ( clk, load, ena, clr, d[15..0] :INPUT; q[15..0] :OUTPUT; ) VARIABLE count[15..0] : DFF; BEGIN count[].clk = clk; count[].clrn = !clr; IF load THEN count[].d = d[]; ELSIF ena THEN count[].d = count[].q + 1; ELSE count[].d = count[].q; END IF; q[] = count[]; END; 8- Mquines destats

SUBDESIGN stepper ( clk, reset : INPUT; ccw, cw : INPUT; phase[3..0] : OUTPUT; ) VARIABLE ss: MACHINE OF BITS (phase[3..0]) WITH STATES ( s0 = B"0001", s1 = B"0010", s2 = B"0100", s3 = B"1000"); BEGIN ss.clk = clk; ss.reset = reset; TABLE ss, s0, s0, s1, s1, s2, s2, s3, s3, END TABLE; END; 9- Func ions IF SUBDESIGN priority ( low, middle, high : INPUT; highest_level[1..0] : OUTPUT; ) BEGIN IF high THEN highest_level[] = 3; ELSIF middle THEN highest_level[] = 2; ELSIF low THEN highest_level[] = 1; ELSE highest_level[] = 0; END IF; END; 5

ccw, 1, x, 1, x, 1, x, 1, x,

cw x 1 x 1 x 1 x 1

=> => => => => => => => =>

ss; s3; s1; s0; s2; s1; s3; s2; s0;

10- Funciones C ASE SUBDESIGN decoder ( code[1..0] :INPUT; out[3..0] :OUTPUT; ) BEGIN CASE code[] IS WHEN 0 => out[] = B"0001"; WHEN 1 => out[] = B"0010"; WHEN 2 => out[] = B"0100"; WHEN 3 => out[] = B"1000"; END CASE; END; 11- Tablas SUBDESIGN 7segment ( i[3..0] a, b, c, d, e, f, g ) BEGIN TABLE i[3..0] => H"0" => H"1" => H"2" => H"3" => H"4" => H"5" => H"6" => H"7" => H"8" => H"9" => H"A" => H"B" => H"C" => H"D" => H"E" => H"F" => END TABLE; END;

:INPUT; :OUTPUT;

a, b, c, d, e, f, g; 1, 1, 1, 1, 1, 1, 0; 0, 1, 1, 0, 0, 0, 0; 1, 1, 0, 1, 1, 0, 1: 1, 1, 1, 1, 0, 0, 1; 0, 1, 1, 0, 0, 1, 1; 1, 0, 1, 1, 0, 1, 1; 1, 0, 1, 1, 1, 1, 1; 1, 1, 1, 0, 0, 0, 0; 1, 1, 1, 1, 1, 1, 1; 1, 1, 1, 1, 0, 1, 1; 1, 1, 1, 0, 1, 1, 1; 0, 0, 1, 1, 1, 1, 1; 1, 0, 0, 1, 1, 1, 0; 0, 1, 1, 1, 1, 0, 1; 1, 0, 0, 1, 1, 1, 1; 1, 0, 0, 0, 1, 1, 1;