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A

Compal Confidential
2

NAL90/NALG0 M/B Schematics Document


Intel Auburndale/Clarksfield Processor with DDRIII + Ibex Peak-M

2009-10-20

REV:1.0

2009/5/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/04/15

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Cover Page

NALG0 M/B LA-5681P Schematic

Date:

Friday, October 23, 2009

Sheet
E

of

60

Rev
1.0

Clock Generator

Compal Confidential

IDT: 9LRS3199AKLFT
SILEGO: SLG8SP587

Model Name NALG0


File Name : LA5681P

133/120/100/96/14.318MHZ to PCH

Fan Control

48MHZ to CardReader

page 41

page 12

PEG(DIS)

100MHz

PCI-E 2.0x16 5GT/s PER LANE

Nvidia N11MGE1

HDMI(DIS)

Memory BUS(DDRIII)
Intel
204pin DDRIII-SO-DIMM X2
Dual Channel
page 10,11
Auburndale / Clarksfield
BANK 0, 1, 2, 3
1.5V DDRIII 800/1066/1333
(UMA/DIS)
(DIS)
6.4G/8.5G/10.6G

133MHz

LVDS(DIS)
CRT(DIS)

page
22,23,24,25,26,27

100M/133M/166M(CFD)

Processor
rPGA988A

page 4,5,6,7,8,9

CRT Conn.

HDMI Conn.
page 30

page 29

CRT
SW
page 29

LVDS Conn.

FDI x8
(UMA)

LVDS
SW
page 28

page 28

DMI x4

100MHz

100MHz

2.7GT/s

1GB/s x4

LVDS(UMA)

Intel
Ibex Peak-M

CRT(UMA)

Level Shift

HDMI(UMA)

page 30

port 2,4

page 13,14,15,16,17
18,19,20,21

port 1

MINI Card x2

LAN(GbE)

WLAN, TV

BCM57780

page 32

Bluetooth
Conn

CMOS
Camera

USB port 10

USB port 3

page 35

USBx14

3.3V 48MHz

HD Audio

3.3V 24MHz

page 35

USB port 11

page 28

page 8

USB/B

page 35

page 35

port 1

port 4

SATA HDD
Conn.

SATA ODD
Conn.

eSATA
Conn.

page 31

page 31

page 35

Audio AMP
APA2051
page 41

33MHz

Int. Speaker
page 41

page 37

Touch Pad

Int.KBD

page 38

Power On/Off CKT.


page 8

MDC
page 39

page 40

LPC BUS

NALG0 Sub-board
LS-5682P

USB/B

page 36

ALC888

ENE KB926
RTC CKT.

USB port 6

HDA Codec

page 13

page 34

NAL90 Sub-board
LS-5682P

Card
Reader

page 35

SPI

SPI ROM x2

RJ45

Finger
Printer

port 0

page 33

USB port 8 HS
USB Port 2 (eSATA)
USB port 0 (sub board)

SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S) 100MHz

PCH

PCI-Express x 8 (ABD PCIE1 2.5GT/S CKD PCIE1/2 2.5/5GT/S) 100MHz

USB conn x2

page 38

LS-4493P
Media/B

BIOS ROM

page 38

page 38

DC/DC Interface CKT.


4

LS-5683P

LS-5683P

Function/B

Function/B

page 38

page 38
4

page 42

LS-5681P
Power Circuit DC/DC

LS-5681P

Finger Printer/B

Finger Printer/B

page 35

page 35
2009/5/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

page

2010/04/15

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Block Diagrams
Document Number

NALG0 M/B LA-5681P Schematic


Friday, October 23, 2009

Sheet
E

of

60

Rev
1.0

SIGNAL

STATE

Voltage Rails

Full ON

HIGH

HIGH

HIGH

ON

ON

ON

ON

HIGH

HIGH

HIGH

ON

ON

ON

LOW

N/A

N/A

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

N/A

N/A

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

S3

Adapter power supply (19V)

N/A

B+

AC or battery power rail for power circuit.

N/A

+CPU_CORE

Core voltage for CPU

ON

ON

OFF

+GFX_core

Core voltage for CPU

ON

OFF

OFF

+1.1VS_VTT

1.1V switched power rail (1.05 for AUB CPU)

ON

OFF

OFF

+VGA_CORE

Core voltage for N11M VGA

ON

OFF

OFF

+1.05VS

1.05V switched power rail for PCH

ON

OFF

OFF

+1.5VS

1.5V power rail for DDRIII

ON

ON

OFF

+0.75VS

0.75V switched power rail for DDR terminator

ON

OFF

OFF

Vcc
Ra/Rc/Re

+1.5VS

1.5V switched power rail

ON

OFF

OFF

Board ID

+1.8VS

1.8V switched power rail

ON

OFF

OFF

+3VALW

3.3V always on power rail

ON

ON

ON*

+3V_LAN

3.3V power rail for LAN

ON

ON

ON*

+3VS

3.3V switched power rail

ON

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON*

+5VS

5V switched power rail

ON

OFF

OFF

0
1
2
3
4
5
6
7

+VSB

VSB always on power rail

ON

ON

ON*

+RTCVCC

RTC power

ON

ON

ON

3.3V +/- 5%
100K +/- 5%
Rb / Rd / Rf
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC

Smart Battery

0001 011X b

Interrupts

Device

Address

USB 2.0 USB 1.1 Port


UHCI0

VGA

UHCI1
EHCI1
UHCI2

Ibex SM Bus address


Address

Clock Generator
(9LRS3199AKLFT, SLG8SP587)

1101 0010b

DDR DIMM0

1001 000Xb

DDR DIMM2

1001 010Xb

UHCI3
UHCI4
EHCI2

Mini card

BTO Item
UMA
UMA only
DIS
DIS Only
Switchable

UHCI5
UHCI6

0
1

4 External
USB Port

Ext4 HS USB
sub Board

2
3
4
5
6

S3 power

Camera
1st Min-Card
2st Min-Card

Caps@
X76@
HDCP@
AMIC@
S3@
non S3@

BOM Config
UMA only
UMA@/UMA only@/FP@/Dmic@/XDP@/S3@

7
8
9
10
11
12
13

BOM Structure
UMA@
UMA only@
DIS@
DIS only@
SG@
XDP@
NonSG@
MINI2@
FP@
eDriver@
Dmic@

USB Port Table

PCH

Device

V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V

BTO Option Table


PCB Revision
0.1
0.2
0.3
1.0

1
2
3
4
5
6
7

External PCI Devices

Address

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

BOARD ID Table
0

Device

V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

Board ID

EC SM Bus2 address

Board ID / SKU ID Table for AD channel

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

Clock

LOW

VIN

EC SM Bus1 address

+VS

HIGH

S1

REQ#/GNT#

+V

S1(Power On Suspend)

Description

IDSEL#

+VALW

S5

Power Plane

Device

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

Ext4 HS USB
Card Reader
Blue Tooth
Finger Print

DIS ONLY
DIS@/DIS only@/FP@/Dmic@/XDP@/S3@
Switchable Graphics
SG@/UMA@/DIS@/FP@/Dmic@/XDP@/S3@

Note:do cost BOM add X76@


2009/5/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2010/04/15

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Notes List
Document Number

Rev
1.0

NALG0 M/B LA-5681P Schematic


Friday, October 23, 2009

Sheet
E

of

60

JCPU1E

DMI_PTX_HRX_P0
DMI_PTX_HRX_P1
DMI_PTX_HRX_P2
DMI_PTX_HRX_P3

B24
D23
B23
A22

DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]

DMI_HTX_PRX_N0
DMI_HTX_PRX_N1
DMI_HTX_PRX_N2
DMI_HTX_PRX_N3

D24
G24
F23
H23

DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]

DMI_HTX_PRX_P0
DMI_HTX_PRX_P1
DMI_HTX_PRX_P2
DMI_HTX_PRX_P3

D25
F24
E23
G23

DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]

E22
D21
D19
D18
G21
E19
F21
G18

FDI_TX#[0]
FDI_TX#[1]
FDI_TX#[2]
FDI_TX#[3]
FDI_TX#[4]
FDI_TX#[5]
FDI_TX#[6]
FDI_TX#[7]

H_FDI_TXP0
H_FDI_TXP1
H_FDI_TXP2
H_FDI_TXP3
H_FDI_TXP4
H_FDI_TXP5
H_FDI_TXP6
H_FDI_TXP7

D22
C21
D20
C18
G22
E20
F20
G19

FDI_TX[0]
FDI_TX[1]
FDI_TX[2]
FDI_TX[3]
FDI_TX[4]
FDI_TX[5]
FDI_TX[6]
FDI_TX[7]

F17
E17

FDI_FSYNC[0]
FDI_FSYNC[1]

H_FDI_INT

C17

FDI_INT

15 H_FDI_LSYNC0
15 H_FDI_LSYNC1

F18
D17

FDI_LSYNC[0]
FDI_LSYNC[1]

15 H_FDI_FSYNC0
15 H_FDI_FSYNC1
15

Intel(R) FDI

H_FDI_TXN0
H_FDI_TXN1
H_FDI_TXN2
H_FDI_TXN3
H_FDI_TXN4
H_FDI_TXN5
H_FDI_TXN6
H_FDI_TXN7

PCI EXPRESS -- GRAPHICS

DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]

DMI

A24
C23
B22
A21

PEG_IRCOMP

R520
1

2 49.9_0402_1%

EXP_RBIAS

R535
1

2 750_0402_1%

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS

B26
A26
B27
A25

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

K35
J34
J33
G35
G32
F34
F31
D35
E33
C33
D32
B32
C31
B28
B30
A31

PEG_GTX_C_HRX_N15
PEG_GTX_C_HRX_N14
PEG_GTX_C_HRX_N13
PEG_GTX_C_HRX_N12
PEG_GTX_C_HRX_N11
PEG_GTX_C_HRX_N10
PEG_GTX_C_HRX_N9
PEG_GTX_C_HRX_N8
PEG_GTX_C_HRX_N7
PEG_GTX_C_HRX_N6
PEG_GTX_C_HRX_N5
PEG_GTX_C_HRX_N4
PEG_GTX_C_HRX_N3
PEG_GTX_C_HRX_N2
PEG_GTX_C_HRX_N1
PEG_GTX_C_HRX_N0

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

J35
H34
H33
F35
G33
E34
F32
D34
F33
B33
D31
A32
C30
A28
B29
A30

PEG_GTX_C_HRX_P15
PEG_GTX_C_HRX_P14
PEG_GTX_C_HRX_P13
PEG_GTX_C_HRX_P12
PEG_GTX_C_HRX_P11
PEG_GTX_C_HRX_P10
PEG_GTX_C_HRX_P9
PEG_GTX_C_HRX_P8
PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_P0

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

L33
M35
M33
M30
L31
K32
M29
J31
K29
H30
H29
F29
E28
D29
D27
C26

PEG_HTX_GRX_N15
PEG_HTX_GRX_N14
PEG_HTX_GRX_N13
PEG_HTX_GRX_N12
PEG_HTX_GRX_N11
PEG_HTX_GRX_N10
PEG_HTX_GRX_N9
PEG_HTX_GRX_N8
PEG_HTX_GRX_N7
PEG_HTX_GRX_N6
PEG_HTX_GRX_N5
PEG_HTX_GRX_N4
PEG_HTX_GRX_N3
PEG_HTX_GRX_N2
PEG_HTX_GRX_N1
PEG_HTX_GRX_N0

C473
C475
C470
C458
C454
C447
C460
C455
C448
C464
C477
C463
C450
C482
C480
C468

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

PEG_HTX_C_GRX_N15
PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_N12
PEG_HTX_C_GRX_N11
PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_N8
PEG_HTX_C_GRX_N7
PEG_HTX_C_GRX_N6
PEG_HTX_C_GRX_N5
PEG_HTX_C_GRX_N4
PEG_HTX_C_GRX_N3
PEG_HTX_C_GRX_N2
PEG_HTX_C_GRX_N1
PEG_HTX_C_GRX_N0

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

L34
M34
M32
L30
M31
K31
M28
H31
K28
G30
G29
F28
E27
D28
C27
C25

PEG_HTX_GRX_P15
PEG_HTX_GRX_P14
PEG_HTX_GRX_P13
PEG_HTX_GRX_P12
PEG_HTX_GRX_P11
PEG_HTX_GRX_P10
PEG_HTX_GRX_P9
PEG_HTX_GRX_P8
PEG_HTX_GRX_P7
PEG_HTX_GRX_P6
PEG_HTX_GRX_P5
PEG_HTX_GRX_P4
PEG_HTX_GRX_P3
PEG_HTX_GRX_P2
PEG_HTX_GRX_P1
PEG_HTX_GRX_P0

C472
C474
C471
C465
C456
C451
C466
C457
C452
C469
C476
C462
C449
C481
C479
C467

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

PEG_HTX_C_GRX_P15
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_P9
PEG_HTX_C_GRX_P8
PEG_HTX_C_GRX_P7
PEG_HTX_C_GRX_P6
PEG_HTX_C_GRX_P5
PEG_HTX_C_GRX_P4
PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_P0

AP25
AL25
AL24
AL22
AJ33
AG9
M27
L28
J17
H17
G25
G17
E31
E30

10 H_DIMMA_REF
11 H_DIMMB_REF

R74
3.01K_0402_1%

1 @

CFG0

R72
3.01K_0402_1%
R75
3.01K_0402_1%

1 DIS@
1 @

2
2

CFG3
CFG4

R71
3.01K_0402_1%

1 @

CFG7

WW41 Recommend not pull down


PCIE2.0 Jitter is over on ES1

R557
0_0402_5%
@
1
2
@
1
2

H_RSVD17_R
H_RSVD18_R

R548
0_0402_5%

DMI_PTX_HRX_N[0..3] 15
DMI_PTX_HRX_P[0..3] 15

15
15

PEG_GTX_C_HRX_N[0..15] 22
PEG_GTX_C_HRX_P[0..15] 22
PEG_HTX_C_GRX_N[0..15] 22
PEG_HTX_C_GRX_P[0..15] 22

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
RSVD_TP_86

B19
A19

RSVD15
RSVD16

A20
B20

RSVD17
RSVD18

U9
T9

RSVD19
RSVD20

AC9
AB9

RSVD21
RSVD22

C1
A3

DMI_HTX_PRX_N[0..3] 15
DMI_HTX_PRX_P[0..3] 15
H_FDI_TXN[0..7]
H_FDI_TXP[0..7]

AM30
AM28
AP31
AL32
AL30
AM31
AN29
AM32
AK32
AK31
AK28
AJ28
AN30
AN32
AJ32
AJ29
AJ30
AK30
H16

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
SA_DIMM_VREF
SB_DIMM_VREF
RSVD11
RSVD12
RSVD13
RSVD14

RSVD32
RSVD33

AJ13
AJ12

RSVD34
RSVD35

AH25
AK26

RSVD36
RSVD_NCTF_37

AL26
AR2

RSVD38
RSVD39

AJ26
AJ27

(CFD Only)
(CFD Only)

RESERVED

JCPU1A
DMI_PTX_HRX_N0
DMI_PTX_HRX_N1
DMI_PTX_HRX_N2
DMI_PTX_HRX_N3

RSVD_NCTF_40
RSVD_NCTF_41

AP1
AT2

RSVD_NCTF_42
RSVD_NCTF_43

AT3
AR1

RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53
RSVD_NCTF_54
RSVD_NCTF_55
RSVD_NCTF_56
RSVD_NCTF_57
RSVD58

AL28
AL29
AP30
AP32
AL27
AT31
AT32
AP33
AR33
AT33
AT34
AP35
AR35
AR32

RSVD_TP_59
RSVD_TP_60
KEY
RSVD62
RSVD63
RSVD64
RSVD65

E15
F15
A2
D15
C15
AJ15
AH15

RSVD_TP_66
RSVD_TP_67
RSVD_TP_68
RSVD_TP_69
RSVD_TP_70
RSVD_TP_71
RSVD_TP_72
RSVD_TP_73
RSVD_TP_74
RSVD_TP_75

AA5
AA4
R8
AD3
AD2
AA2
AA1
R9
AG7
AE3

RSVD_TP_76
RSVD_TP_77
RSVD_TP_78
RSVD_TP_79
RSVD_TP_80
RSVD_TP_81
RSVD_TP_82
RSVD_TP_83
RSVD_TP_84
RSVD_TP_85

V4
V5
N2
AD5
AD7
W3
W2
N3
AE5
AD9

RSVD_NCTF_23
RSVD_NCTF_24

J29
J28

RSVD26
RSVD27

A34
A33

RSVD_NCTF_28
RSVD_NCTF_29

C35
B35

RSVD_NCTF_30
RSVD_NCTF_31

IC,AUB_CFD_rPGA,R1P0
CONN@

VSS

R214
0_0402_5%
RSVD64_R 2
@
RSVD65_R 2
@
R213
0_0402_5%

1
1

AP34

IC,AUB_CFD_rPGA,R1P0
CONN@

eDP Signals
eDP Singal
eDP_TX0
eDP_TX#0
eDP_TX1
eDP_TX#1
eDP_TX2
eDP_TX#2
eDP_TX3
eDP_TX#3
eDP_AUX
eDP_AUX#
eDP_HPD#

MAPPING
PEG Singals
PEG_HTX_C_GRX_P15
PEG_HTX_C_GRX_N15
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_N12
PEG_GTX_C_HRX_P13
PEG_GTX_C_HRX_N13
PEG_GTX_C_HRX_P12
5

Lane Reversal
PEG_HTX_C_GRX_P0
PEG_HTX_C_GRX_N0
PEG_HTX_C_GRX_P1
PEG_HTX_C_GRX_N1
PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_N2
PEG_HTX_C_GRX_P3
PEG_HTX_C_GRX_N3
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_N2
PEG_GTX_C_HRX_P3

H_FDI_FSYNC0
H_FDI_FSYNC1

R163 1 DIS only@


2 1K_0402_5%
R166 1 DIS only@
2 1K_0402_5%

H_FDI_INT

R171 1 DIS only@


2 1K_0402_5%

H_FDI_LSYNC0
H_FDI_LSYNC1

R167 1 DIS only@


2 1K_0402_5%
R172 1 DIS only@
2 1K_0402_5%

CFG0 - PCI-Express Configuration Select

CFG4 - Display Port Presence

*1:Single PEG
0:Bifurcation enabled

*1:Disabled; No Physical Display Port


attached to Embedded Display Port
0:Enabled; An external Display Port
device is connected to the Embedded
Display Port

CFG3 - PCI-Express Static Lane Reversal


*:Default
*1 :Normal Operation
0 :Lane Numbers Reversed
15 -> 0, 14 -> 1, ...

CheckList0.8 1.22
Auburndale Graphics Disable

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/5/12

Issued Date

Deciphered Date

2010/04/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Title

PROCESSOR (1/6) DMI,FDI,PEG


Size
B
Date:

Document Number

Rev
1.0

NALG0 M/B LA-5681P Schematic


Friday, October 23, 2009

Sheet
1

of

60

JCPU1B

COMP1

AT26

COMP0

AH24

SKTOCC#

AK14

CATERR#

H_PECI_R

AT15

PECI

H_PROCHOT#

R211 1
0_0402_5%

18 H_THERMTRIP#

H_CPURST#

AP26

RESET_OBS#

H_PM_SYNC_R

AL15

PM_SYNC

R215 1
0_0402_5%

H_CPUPW RGD_1

AN14

VCCPWRGOOD_1

2
2

PM_DRAM_PW RGD_R 1
R742

H_PW RGD_XDP R452 1


0_0402_5%

H_CPUPW RGD_0

AN27

VCCPWRGOOD_0

PM_DRAM_PW RGD_R

AK13

SM_DRAMPWROK

2 CPU_VTTPW RGD
0_0402_5%
2

AM15

VTTPWRGOOD

H_PW RGD_XDP_R

AM26

TAPPWRGOOD

PLT_RST#_R

AL14

RSTIN#

AR30
AT30

CLK_CPU_ITP_R
CLK_CPU_ITP#_R

R506 1 XDP@
R515 1 XDP@

2 0_0402_5%
2 0_0402_5%

PEG_CLK
PEG_CLK#

E16
D16

CLK_CPU_DMI_R
CLK_CPU_DMI#_R

R577 1
R571 1

2 0_0402_5%
2 0_0402_5%

DPLL_REF_SSCLK
DPLL_REF_SSCLK#

A18
A17

CLK_CPU_DP_R
CLK_CPU_DP#_R

R563 1 UMA@ 2 0_0402_5%


R568 1 UMA@ 2 0_0402_5%

BCLK_ITP
BCLK_ITP#

SM_DRAMRST#

F6

2009/2/4
#414044 DG
Update Rev1.11

SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2

PM_EXT_TS#[0]
PM_EXT_TS#[1]

AN15
AP15

PM_EXTTS#0
PM_EXTTS#1_R

PRDY#
PREQ#

AT28
AP27

XDP_PRDY#
XDP_PREQ#

TCK
TMS
TRST#

AN28
AP28
AT27

XDP_TCLK
XDP_TMS
XDP_TRST#

TDI
TDO
TDI_M
TDO_M

AT29
AR27
AR29
AP29

XDP_TDI_R
XDP_TDO_R
XDP_TDI_M
XDP_TDO_M

DBR#

AN25

XDP_DBR#_R

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

AJ22
AK22
AK24
AJ24
AJ25
AH22
AK23
AH23

CLK_CPU_XDP
CLK_CPU_XDP#
CLK_CPU_DMI 14
CLK_CPU_DMI# 14

CLK_CPU_DP_R
CLK_CPU_DP#_R

CLK_CPU_DP 14
CLK_CPU_DP# 14

R561 1 DIS only@


2 0_0402_5%
R569 1 DIS only@
2 0_0402_5%
D

+1.1VS_VTT
R591 1
R586 1
R594 1

2 10K_0402_5%
2 10K_0402_5%
2 0_0402_5%

XDP_PRDY#
XDP_TMS
XDP_TDI_R
XDP_PREQ#
XDP_TCLK

R147
R38
R537
R152
R446

XDP_TRST#

R145 1

2 51_0402_5%

XDP_TDI_R
XDP_TDO_M

R525 1
R514 1 @

2 0_0402_5%
2 0_0402_5%

1
1
1
1
1

@
@
@
@
@

2
2
2
2
2

51_0402_5%
51_0402_5%
51_0402_5%
51_0402_5%
51_0402_5%

PM_EXTTS#0_1 10,11

R151 1

2 0_0402_5% XDP_DBRESET#

XDP_TDI
XDP_TDO

R522
0_0402_5%
XDP_DBRESET# 15
XDP_TDI_M
XDP_TDO_R

XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7

1 @
R524 1
R150

2
2 0_0402_5%
0_0402_5%

JTAG MAPPING

2009/2/4
Delete dampling resistor for
power noise and Layout space
issue

IC,AUB_CFD_rPGA,R1P0
CONN@

Scan Chain
(Default)

STUFF -> R653, R657, R662


NO STUFF -> R655, R660

CPU Only

STUFF -> R653, R655


NO STUFF -> R657, R660, R662

GMCH Only

STUFF -> R660, R662


NO STUFF -> R653, R655, R657

R182
750_0402_1%

CLK_CPU_BCLK 18
CLK_CPU_BCLK# 18

SM_DRAMRST# 11

AL1
AM1
AN1

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

R181
1
1.5K_0402_1%

17,33,37 PLT_RST#

THERMTRIP#

R216 1
0_0402_5%

15 PM_DRAM_PW RGD

AK15

R212 1
0_0402_5%

R210 1
0_0402_5%

18 H_CPUPW RGD

H_THERMTRIP#_R

PROCHOT#

2 0_0402_5%
2 0_0402_5%

+1.1VS_VTT

PWR MANAGEMENT

15 H_PM_SYNC

AN26

CLOCKS

H_CATERR#

R578 1
R581 1

G16

H_COMP0

CLK_CPU_BCLK_R
CLK_CPU_BCLK#_R

H_COMP1

A16
B16

BCLK
BCLK#

DDR3
MISC

55 H_PROCHOT#

COMP2

THERMAL

R595 1
0_0402_5%

H_PECI

AT24

SKTOCC#_R

18

COMP3

H_COMP2

JTAG & BPM

AT23

MISC

PAD

T5

H_COMP3

+3VS

2009/4/13
Intel Suggestion by Desige guide V1.52
1

2 4

B
A

2K_0402_5%

R747
1K_0402_1%

H_VTTPW RGD

XDP_PREQ#
XDP_PRDY#
XDP_OBS0
XDP_OBS1

NC7SZ08P5X_NL_SC70-5
U48

CPU_VTTPW RGD

Test:
1. change R203 to 750 ohm
2. del R217
3. pop R736
+1.5V
+1.5V_CPU

JP5

XDP_OBS2
XDP_OBS3

R217
1.1K_0402_1%
non S3@

R746

R735
1.1K_0402_1%

S3@ 2
4
1.5K_0402_1%

R203
3K_0402_1%
non S3@

H_CATERR#
H_PROCHOT#
H_CPURST#
A

H_COMP0
H_COMP1
H_COMP2
H_COMP3

R203

H_VTTPW RGD

R204 1
R155 1
R156 1 @
R526
R179
R541
R544

1
1
1
1

2 49.9_0402_1%
2 68_0402_5%
2 68_0402_5%
2
2
2
2

C435
1
0.1U_0402_16V4Z
@

XDP_OBS6
XDP_OBS7

2
2

12 XDP_SDATA
12 XDP_SCLK

49.9_0402_1%
49.9_0402_1%
20_0402_1%
20_0402_1%

XDP Connector

GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16
CONN@

2009/5/12

Issued Date

2 100_0402_1%
2 24.9_0402_1%
2 130_0402_1%

GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TDI
TMS
GND17

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

H_RESET#_R

Deciphered Date

R49
1K_0402_5%
1 XDP@ 2
1 @
2

H_CPURST#
PLT_RST#

R50
0_0402_5%
CLK_CPU_XDP
CLK_CPU_XDP#
H_RESET#_R
XDP_DBRESET#
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS

+1.1VS_VTT

1 XDP@
1 XDP@

R46
1K_0402_5%
2 R43
51_0402_5%

+3VS

Leakage Issue

+1.1VS_VTT

SAMTE_BSH-030-01-L-D-A

Compal Electronics, Inc.


2010/04/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Compal Secret Data

Security Classification
SM_RCOMP_0 R636 1
SM_RCOMP_1 R632 1
SM_RCOMP_2 R629 1

H_PW RGOOD_R
PBTN_OUT#_XDP
0_0402_5%
H_PW RGD_XDP

XDP_TCLK

SD034750080

15,37 PBTN_OUT#
+1.1VS_VTT

R457
1K_0402_5%
H_CPUPW RGD 1 XDP@
1 XDP@
R455

S3@

750_0402_1%

H_VTTPW RGD 53

1
NC7SZ08P5X_NL_SC70-5
U46
+1.1VS_VTT

S3@

C713
1
0.1U_0402_16V4Z

1
R736

PM_DRAM_PW RGD_R

XDP_OBS4
XDP_OBS5

+3VS

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

Title

PROCESSOR (2/6) CLK,JTAG


Size
B
Date:

Document Number

Rev
1.0

NALG0 M/B LA-5681P Schematic


Friday, October 23, 2009

Sheet
1

of

60

10
10
10

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

10 DDR_A_CAS#
10 DDR_A_RAS#
10 DDR_A_W E#

A10
C10
C7
A7
B10
D10
E10
A8
D8
F10
E6
F7
E9
B7
E7
C6
H10
G8
K7
J8
G7
G10
J7
J10
L7
M6
M8
L9
L6
K8
N8
P9
AH5
AF5
AK6
AK7
AF6
AG5
AJ7
AJ6
AJ10
AJ9
AL10
AK12
AK8
AL7
AK11
AL8
AN8
AM10
AR11
AL11
AM9
AN9
AT11
AP12
AM12
AN12
AM13
AT14
AT12
AL13
AR14
AP14

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

AC3
AB2
U7

DDR_A_CAS#
DDR_A_RAS#
DDR_A_W E#

AE1
AB3
AE9

SA_CK[0]
SA_CK#[0]
SA_CKE[0]
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

AA6
AA7
P7

Y6
Y5
P6

DDR_A_CLK1 10
DDR_A_CLK1# 10
DDR_A_CKE1 10

SA_CS#[0]
SA_CS#[1]

AE2
AE8

DDR_A_CS0# 10
DDR_A_CS1# 10

SA_ODT[0]
SA_ODT[1]

AD8
AF9

DDR_A_ODT0 10
DDR_A_ODT1 10

B9
D7
H7
M7
AG6
AM7
AN10
AN13

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_A_CLK0 10
DDR_A_CLK0# 10
DDR_A_CKE0 10

SA_CK[1]
SA_CK#[1]
SA_CKE[1]

SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]

DDR SYSTEM MEMORY A

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

C9
F8
J9
N9
AH7
AK9
AP11
AT13

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

C8
F9
H9
M9
AH8
AK10
AN11
AR13

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

Y3
W1
AA8
AA3
V1
AA9
V8
T1
Y9
U6
AD4
T2
U3
AG8
T3
V9

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

11
11
11

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

11 DDR_B_CAS#
11 DDR_B_RAS#
11 DDR_B_W E#

JCPU1D

11 DDR_B_D[0..63]
11 DDR_B_DM[0..7]
11 DDR_B_DQS#[0..7]
11 DDR_B_DQS[0..7]
11 DDR_B_MA[0..15]

JCPU1C

10 DDR_A_D[0..63]
10 DDR_A_DM[0..7]
10 DDR_A_DQS#[0..7]
10 DDR_A_DQS[0..7]
10 DDR_A_MA[0..15]

B5
A5
C3
B3
E4
A6
A4
C4
D1
D2
F2
F1
C2
F5
F3
G4
H6
G2
J6
J3
G1
G5
J2
J1
J5
K2
L3
M1
K5
K4
M4
N5
AF3
AG1
AJ3
AK1
AG4
AG3
AJ4
AH4
AK3
AK4
AM6
AN2
AK5
AK2
AM4
AM3
AP3
AN5
AT4
AN6
AN4
AN3
AT5
AT6
AN7
AP6
AP8
AT9
AT7
AP9
AR10
AT10

SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

AB1
W5
R7

SB_BS[0]
SB_BS[1]
SB_BS[2]

DDR_B_CAS#
DDR_B_RAS#
DDR_B_W E#

AC5
Y7
AC6

SB_CAS#
SB_RAS#
SB_WE#

DDR SYSTEM MEMORY - B

SB_CK[0]
SB_CK#[0]
SB_CKE[0]

W8
W9
M3

DDR_B_CLK0 11
DDR_B_CLK0# 11
DDR_B_CKE0 11

SB_CK[1]
SB_CK#[1]
SB_CKE[1]

V7
V6
M2

DDR_B_CLK1 11
DDR_B_CLK1# 11
DDR_B_CKE1 11

SB_CS#[0]
SB_CS#[1]

AB8
AD6

DDR_B_CS0# 11
DDR_B_CS1# 11

SB_ODT[0]
SB_ODT[1]

AC7
AD1

DDR_B_ODT0 11
DDR_B_ODT1 11

SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]

D4
E1
H3
K1
AH1
AL2
AR4
AT8

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

D5
F4
J4
L4
AH2
AL4
AR5
AR8

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

C5
E3
H4
M5
AG2
AL5
AP5
AR7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

U5
V2
T5
V3
R1
T8
R2
R6
R4
R5
AB5
P3
R3
AF7
P5
N1

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

IC,AUB_CFD_rPGA,R1P0
CONN@
IC,AUB_CFD_rPGA,R1P0
CONN@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/5/12

Issued Date

Deciphered Date

2010/04/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

PROCESSOR (3/6) DDRIII


Size
B
Date:

Document Number

Rev
1.0

NALG0 M/B LA-5681P Schematic


Friday, October 23, 2009

Sheet
1

of

60

JCPU1F

WW15 MOW
+CPU_CORE

Peak 21A

VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8
VTT0_9
VTT0_10
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32

VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_43
VTT0_44

PSI#

POWER

+1.1VS_VTT
10U_0805_6.3V6M
10U_0805_6.3V6M

AH14
AH12
AH11
AH10
J14
J13
H14
H12
G14
G13
G12
G11
F14
F13
F12
F11
E14
E12
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

10U_0805_6.3V6M
+CPU_CORE

C228

C209

C222

C226

10U_0805_6.3V6M

C224

C212

10U_0805_6.3V6M

10U_0805_6.3V6M

C204

2
10U_0805_6.3V6M

10U_0805_6.3V6M
1

C185

10U_0805_6.3V6M

C195

10U_0805_6.3V6M
1

C203

C207

10U_0805_6.3V6M

10U_0805_6.3V6M
1

C217

10U_0805_6.3V6M

C196

10U_0805_6.3V6M
1

C187

C202

10U_0805_6.3V6M

C218

10U_0805_6.3V6M

(Place these capacitors between inductor and socket on Bottom)


+1.1VS_VTT
+CPU_CORE
1

330U_X_2VM_R6M
1

C250

C248

C249
@

10U_0805_6.3V6M

1
+

C220

C192

10U_0805_6.3V6M
1

C221

C208

C191

C219

2
2

330U_X_2VM_R6M

10U_0805_6.3V6M
1

C216

330U_X_2VM_R6M
10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

(Place these capacitors under CPU socket, top layer)

CSC (Current Sense Configuration)


8/25
+1.1VS_VTT

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
PROC_DPRSLPVR

VTT_SELECT

C231

C232

R412 1
R413 1 @

2 1K_0402_1%
2 1K_0402_1%

CPU_VID1

R415 1
R416 1 @

2 1K_0402_1%
2 1K_0402_1%

2
2
22U_0805_6.3V6M

CPU_VID2

R419 1
R420 1 @

2 1K_0402_1%
2 1K_0402_1%

CPU_VID3

R422 1 @
R423 1

2 1K_0402_1%
2 1K_0402_1%

CPU_VID4

R425 1 @
R426 1

2 1K_0402_1%
2 1K_0402_1%

CPU_VID5

R428 1
R429 1 @

2 1K_0402_1%
2 1K_0402_1%

CPU_VID6

C502

H_PSI#

AK35
AK33
AK34
AL35
AL33
AM33
AM35
AM34

CPU_VID0 55
CPU_VID1 55
CPU_VID2 55
CPU_VID3 55
CPU_VID4 55
CPU_VID5 55
CPU_VID6 55
H_DPRSLPVR 55

H_VTTVID1

R432 1 @
R433 1

2 1K_0402_1%
2 1K_0402_1%

H_DPRSLPVR R435 1
R436 1 @

2 1K_0402_1%
2 1K_0402_1%

H_PSI#

2 1K_0402_1%
2 1K_0402_1%

R437 1 @
R438 1

VTT_SENSE
VSS_SENSE_VTT

AJ34
AJ35
B15
A15

C501

C499

22U_0805_6.3V6M
1

C498

22U_0805_6.3V6M

C497

22U_0805_6.3V6M

(Place these capacitors on CPU cavity, Bottom Layer)

+CPU_CORE
22U_0805_6.3V6M
C524

C529

22U_0805_6.3V6M
C528

C527

22U_0805_6.3V6M
1

C526

22U_0805_6.3V6M

C525

22U_0805_6.3V6M

(Place these capacitors on CPU cavity, Bottom Layer)


B

VTT Rail

pop 330u 6mohm p/n: SGA00001Q80


+CPU_CORE

IMVP_IMON 55

VCCSENSE_R R466 1
VSSSENSE_R R465 1

C165
2 0_0402_5%
2 0_0402_5%

VTT_SENSE 53

VSS_SENSE_VTT
R585 1

4 x 470uF(4.5mohm@100kHz; 4.0mohm@SRF)
1

1
R464
VCCSENSE
VSSSENSE

2
100_0402_1%

1
R463

2
100_0402_1%

+CPU_CORE

VCCSENSE 55
VSSSENSE 55

C171

330U_X_2VM_R6M
2

1
C172

2 3
470U_D2T_2VM~D

C173

2 3
470U_D2T_2VM~D

1
C170
@

2 3
470U_D2T_2VM~D

C174
@

2 3

470U_D2T_2VM~D

470U_D2T_2VM~D

2 0_0402_5%

2009/5/12

Issued Date

C,uF

ESR, mohm

4X330uF

6m ohm/4

16X22uF

3m ohm/12

16X10uF

3m ohm/16

Stuffing Option
4X330uF

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/04/15

Deciphered Date

Title

PROCESSOR (4/6) PWR,Bypass

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NALG0 M/B LA-5681P Schematic

Date:

+
2 3

TOP side (under inductor)

+CPU-CORE
Decoupling
SPCAP,Polymer

IC,AUB_CFD_rPGA,R1P0
CONN@

22U_0805_6.3V6M

Auburndale +1.1VS_VTT=1.05V
Clarksfield +1.1VS_VTT=1.1V

VCC_SENSE
VSS_SENSE

C500

22U_0805_6.3V6M

55

H_VTTVID1 = high, 1.05V

AN35

22U_0805_6.3V6M

H_VTTVID1 53

H_VTTVID1 = low, 1.1V

ISENSE

+CPU_CORE
22U_0805_6.3V6M

AN33

G15

CPU_VID0
22U_0805_6.3V6M

AF10
AE10
AC10
AB10
Y10
W10
U10
T10
J12
J11
J16
J15

MLCC 0805 X5R

+1.1VS_VTT

CPU VIDS

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
VCC86
VCC87
VCC88
VCC89
VCC90
VCC91
VCC92
VCC93
VCC94
VCC95
VCC96
VCC97
VCC98
VCC99
VCC100

SENSE LINES

CPU CORE SUPPLY

AG35
AG34
AG33
AG32
AG31
AG30
AG29
AG28
AG27
AG26
AF35
AF34
AF33
AF32
AF31
AF30
AF29
AF28
AF27
AF26
AD35
AD34
AD33
AD32
AD31
AD30
AD29
AD28
AD27
AD26
AC35
AC34
AC33
AC32
AC31
AC30
AC29
AC28
AC27
AC26
AA35
AA34
AA33
AA32
AA31
AA30
AA29
AA28
AA27
AA26
Y35
Y34
Y33
Y32
Y31
Y30
Y29
Y28
Y27
Y26
V35
V34
V33
V32
V31
V30
V29
V28
V27
V26
U35
U34
U33
U32
U31
U30
U29
U28
U27
U26
R35
R34
R33
R32
R31
R30
R29
R28
R27
R26
P35
P34
P33
P32
P31
P30
P29
P28
P27
P26

Continuous 18A

1.1V RAIL POWER

48A

Friday, October 23, 2009

Sheet
1

of

60

Rev
1.0

+1.5V_CPU

JCPU1G

UMA@

C198
UMA@

C507

UMA@
2

C523

UMA@
2

R549
0_0402_5%
DIS only@

C206
@

2
330U_X_2VM_R6M

C205
330U_X_2VM_R6M
UMA@

J24
J23
H25

VTT1_45
VTT1_46
VTT1_47

15A

3A

+1.1VS_VTT

22U_0805_6.3V6M

C234

FDI

C233

+1.5VS

JUMP_43X118

GRAPHICS

22U_0805_6.3V6M
22U_0805_6.3V6M
22U_0805_6.3V6M
10U_0805_6.3V6M

VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36

VAXG_SENSE
VSSAXG_SENSE

AR22
AT22

VCC_AXG_SENSE 54
VSS_AXG_SENSE 54

2
GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]

AM22
AP22
AN22
AP23
AM23
AP24
AN24

GFX_VR_EN
GFX_DPRSLPVR
GFX_IMON

AR25
AT25
AM24

- 1.5V RAILS

C213

DDR3

C214
@

SENSE
LINES

C215
@

AT21
AT19
AT18
AT16
AR21
AR19
AR18
AR16
AP21
AP19
AP18
AP16
AN21
AN19
AN18
AN16
AM21
AM19
AM18
AM16
AL21
AL19
AL18
AL16
AK21
AK19
AK18
AK16
AJ21
AJ19
AJ18
AJ16
AH21
AH19
AH18
AH16

GRAPHICS VIDs

C199
@

10U_0805_6.3V6M

POWER

C200
@

22U_0805_6.3V6M
22U_0805_6.3V6M

JUMP_43X118
PJ28 @
2 2
1 1

+VGFX_CORE

22U_0805_6.3V6M

PJ27

22U_0805_6.3V6M

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18

AJ1
AF1
AE7
AE4
AC1
AB7
AB4
Y1
W7
W4
U1
T7
T4
P1
N7
N4
L1
H1

VTT0_59
VTT0_60
VTT0_61
VTT0_62

P10
N10
L10
K10

GFXVR_VID_0
GFXVR_VID_1
GFXVR_VID_2
GFXVR_VID_3
GFXVR_VID_4
GFXVR_VID_5
GFXVR_VID_6

GFXVR_DPRSLPVR_R

R536 1

PJ29

+1.5V

JUMP_43X118

54
54
54
54
54
54
54

PJ30

JUMP_43X118
@
1
2
R739
4.7K_0402_5%
GFXVR_EN 54
GFXVR_DPRSLPVR 54
GFXVR_IMON 54

2 0_0402_5%

1 DIS only@2
R146

1K_0402_5%

1U_0402_6.3V4Z

1U_0402_6.3V4Z

+1.5V_CPU

22U_0805_6.3V6M

1
C252

C259

C253

1U_0402_6.3V4Z

C251

1U_0402_6.3V4Z

C262

C271

C258

C269
330U_X_2VM_R6M

1U_0402_6.3V4Z
22U_0805_6.3V6M

+1.1VS_VTT

1
+1.1VS_VTT

C235
10U_0805_6.3V6M

C238
22U_0805_6.3V6M

VTT1_63
VTT1_64
VTT1_65
VTT1_66
VTT1_67
VTT1_68

J22
J20
J18
H21
H20
H19

VCCPLL1
VCCPLL2
VCCPLL3

L26
L27
M26

C236
22U_0805_6.3V6M
B

+1.8VS

0.6A

1.8V

22U_0805_6.3V6M

VTT1_48
VTT1_49
VTT1_50
VTT1_51
VTT1_52
VTT1_53
VTT1_54
VTT1_55
VTT1_56
VTT1_57
VTT1_58

PEG & DMI

C237

K26
J27
J26
J25
H27
G28
G27
G26
F26
E26
E25

1.1V

+1.1VS_VTT

2.2U_0603_6.3V6K

+1.8VS_VCCSFR
C189
1U_0402_6.3V4Z

IC,AUB_CFD_rPGA,R1P0
CONN@

C186

C197

1U_0402_6.3V4Z

C193

1
R157

2 22U_0805_6.3V6M

2
0_0805_5%

C194

4.7U_0805_10V4Z

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/5/12

Issued Date

Deciphered Date

2010/04/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

PROCESSOR (5/6) PWR


Size
Document Number
Custom

Rev
1.0

NALG0 M/B LA-5681P Schematic

Date:

Friday, October 23, 2009

Sheet
1

of

60

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

JCPU1I

VSS

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE6
AD10
AC8
AC4
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
AB6
AA10
Y8
Y4
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
W6
V10
U8
U4
U2
T35
T34
T33
T32
T31
T30
T29
T28
T27
T26
T6
R10
P8
P4
P2
N35
N34
N33
N32
N31
N30
N29
N28
N27
N26
N6
M10
L35
L32
L29
L8
L5
L2
K34
K33
K30

K27
K9
K6
K3
J32
J30
J21
J19
H35
H32
H28
H26
H24
H22
H18
H15
H13
H11
H8
H5
H2
G34
G31
G20
G9
G6
G3
F30
F27
F25
F22
F19
F16
E35
E32
E29
E24
E21
E18
E13
E11
E8
E5
E2
D33
D30
D26
D9
D6
D3
C34
C32
C29
C28
C24
C22
C20
C19
C16
B31
B25
B21
B18
B17
B13
B11
B8
B6
B4
A29
A27
A23
A9

IC,AUB_CFD_rPGA,R1P0
CONN@

VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233

VSS

NCTF

JCPU1H

AT20
AT17
AR31
AR28
AR26
AR24
AR23
AR20
AR17
AR15
AR12
AR9
AR6
AR3
AP20
AP17
AP13
AP10
AP7
AP4
AP2
AN34
AN31
AN23
AN20
AN17
AM29
AM27
AM25
AM20
AM17
AM14
AM11
AM8
AM5
AM2
AL34
AL31
AL23
AL20
AL17
AL12
AL9
AL6
AL3
AK29
AK27
AK25
AK20
AK17
AJ31
AJ23
AJ20
AJ17
AJ14
AJ11
AJ8
AJ5
AJ2
AH35
AH34
AH33
AH32
AH31
AH30
AH29
AH28
AH27
AH26
AH20
AH17
AH13
AH9
AH6
AH3
AG10
AF8
AF4
AF2
AE35

VSS_NCTF1
VSS_NCTF2
VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
VSS_NCTF6
VSS_NCTF7

AT35
AT1
AR34
B34
B2
B1
A35

H_NCTF1
H_NCTF2

@
@

PAD T14
PAD T19

H_NCTF6
H_NCTF7

@
@

PAD T18
PAD T13

IC,AUB_CFD_rPGA,R1P0
CONN@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/5/12

Issued Date

Deciphered Date

2010/04/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

PROCESSOR (6/6) VSS


Size
Document Number
Custom

Rev
1.0

NALG0 M/B LA-5681P Schematic

Date:

Friday, October 23, 2009

Sheet
1

of

60

+1.5V
JDIMM1

6 DDR_A_DQS#[0..7]

+1.5V

H_DIMMA_REF

H_DIMMA_REF

R324 1 @

VREF_DQA

2 0_0402_5%

6 DDR_A_D[0..63]
1

DDR_A_D0
DDR_A_D1

6 DDR_A_DM[0..7]

R312

R325 1

+V_DDR3_DIMM_REF
2

2 0_0402_5%

DDR_A_DM0

6 DDR_A_DQS[0..7]

+V_DDR3_DIMM_REF

1K_0402_1%

DDR_A_D2
DDR_A_D3

6 DDR_A_MA[0..15]

+V_DDR3_DIMM_REF

+1.5V

DDR_A_D8
DDR_A_D9

R319
D

C322

1K_0402_1%

0.1U_0402_16V4Z

DDR_A_DQS#1
DDR_A_DQS1

C321
2.2U_0805_16V4Z

DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
DDR_A_DQS#2
DDR_A_DQS2
DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

VREF_DQA

DDR_A_DM3
2

DDR_A_D26
DDR_A_D27

+V_DDR3_DIMM_REF

R738
100K_0402_5%

H_DIMMA_REF

@ Q64
BSS138_NL_SOT23-3

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT

VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

DDR_A_D4
DDR_A_D5
DDR_A_DQS#0
DDR_A_DQS0
DDR_A_D6
DDR_A_D7
DDR_A_D12
DDR_A_D13
D

DDR_A_DM1
DIMM_RST#

DIMM_RST# 11

DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D30
DDR_A_D31

@
C

R725

DDR_A_CKE0

DDR_A_BS2

DDR_A_CKE0

R323
DDR_A_BS2
DDR_A_MA12
DDR_A_MA9

+DDR_VREF_CA

DDR_A_MA8
DDR_A_MA5

1K_0402_1%
DDR_VREF_CA_DIMMA 2
R726

DDR_A_MA3
DDR_A_MA1

0_0402_5%
R496
6
6

DDR_A_CLK0
DDR_A_CLK0#

1K_0402_1%

DDR_A_CLK0
DDR_A_CLK0#

6
6
6
6

DDR_A_MA10
DDR_A_BS0

DDR_A_BS0

DDR_A_WE#
DDR_A_CAS#

DDR_A_WE#
DDR_A_CAS#

DDR_A_MA13
DDR_A_CS1#

DDR_A_CS1#

DDR_A_D32
DDR_A_D33

Layout Note:
Place near JDIMM1

DDR_A_DQS#4
DDR_A_DQS4
DDR_A_D34
DDR_A_D35

Layout Note: Place these 4 Caps near Command


and Control signals of DIMMA

DDR_A_D40
DDR_A_D41

+1.5V

DDR_A_DM5
10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_A_D42
DDR_A_D43

1
C309

C310

C285

10U_0805_6.3V6M

C290

C295

10U_0805_6.3V6M

C311

10U_0805_6.3V6M

C326

0.1U_0402_16V4Z

C325

C323

C324

DDR_A_D48
DDR_A_D49

C300
330U_X_2VM_R6M

DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D50
DDR_A_D51

0.1U_0402_16V4Z

DDR_A_D56
DDR_A_D57
DDR_A_DM7
DDR_A_D58
DDR_A_D59

Layout Note:
Place near JDIMM1.203 & JDIMM1.204
R335 1

2 10K_0402_5%

+0.75VS

C344
2.2U_0603_6.3V4Z

1U_0603_10V4Z

1U_0603_10V4Z

C345

+3VS

R332
0.1U_0402_16V4Z

205
207

C624

C629

C625

C680

BOSS1
BOSS2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_A_CKE1

DDR_A_CKE1 6

DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7

DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_CLK1
DDR_A_CLK1#

DDR_A_CLK1 6
DDR_A_CLK1# 6

DDR_A_BS1
DDR_A_RAS#

DDR_A_BS1 6
DDR_A_RAS# 6

DDR_A_CS0#
DDR_A_ODT0

DDR_A_CS0# 6
DDR_A_ODT0 6

DDR_A_ODT1

DDR_A_ODT1 6

+DDR_VREF_CA

DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39

C318

DDR_A_D44
DDR_A_D45

C317
0.1U_0402_16V4Z
B

DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63
PM_EXTTS#0_1
D_CK_SDATA
D_CK_SCLK

PM_EXTTS#0_1 5,11
D_CK_SDATA 11,12
D_CK_SCLK 11,12

+0.75VS

206
208

DDR3 SO-DIMM A
Standard Type

FOX_AS0A626-U2SN-7F_204P

C291

CONN@

10U_0805_6.3V6M

Compal Secret Data

Security Classification
1U_0603_10V4Z

GND1
GND2

10K_0402_5%
2

CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT

2.2U_0603_6.3V4Z

1
2
0_0402_5%

11,18 RST_GATE

+1.5V

2009/5/12

Issued Date

1U_0603_10V4Z

2010/04/15

Deciphered Date

Title

Compal Electronics, Inc.


DDRIII-SODIMM SLOT1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

NALG0 M/B LA-5681P Schematic

Date:

Friday, October 23, 2009

Sheet
1

10

of

60

H_DIMMB_REF

4 H_DIMMB_REF

2008/9/8 #400755
Calpella Clarksfield
+V_DDR3_DIMM_REF
DDR3 SO-DIMM
VREFDQ Platform
Design Guide Change Details

6 DDR_B_DQS#[0..7]
6 DDR_B_D[0..63]

R327 1

+1.5V

2 0_0402_5%
VREF_DQB

2 0_0402_5%

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

DDR_B_D0
DDR_B_D1
DDR_B_DM0
DDR_B_D2
DDR_B_D3

6 DDR_B_DQS[0..7]

2009/04/13
For Arrandale ,it should be use M1 Circuit (pop R328)
For Clarksfield ,it should be use M3 Circuit (pop R327)
DG V1.52

PCH_SMBCLK

12,14,32 PCH_SMBCLK

PCH_SMBDATA

12,14,32 PCH_SMBDATA

DDR_B_D8
DDR_B_D9

C335

C336

2.2U_0805_16V4Z

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17
0.1U_0402_16V4Z
DDR_B_DQS#2
DDR_B_DQS2

@ Q63
BSS138_NL_SOT23-3
D

H_DIMMB_REF

VREF_DQB

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

R737
100K_0402_5%

C714

10,18 RST_GATE

DDR_B_DM3

0.047U_0402_16V7K
@

DDR_B_D26
DDR_B_D27

+1.5V

R734

2 0_0402_5%

DDR_B_CKE0

6 DDR_B_CKE0

R732
1K_0402_1%

DDR_B_BS2

6 DDR_B_BS2

DDR_B_MA12
DDR_B_MA9

BSS138_NL_SOT23-3
D

3
1

5 SM_DRAMRST#

DDR_B_MA8
DDR_B_MA5

DIMM_RST# 10

Q62
2

R294
100K_0402_5%

@
1 S3@
C712
0.047U_0402_16V7K

S3@

DIMM_RST#

DDR_B_MA3
DDR_B_MA1

C711
0.1U_0402_16V4Z

6
6

10,18 RST_GATE

DDR_B_CLK0
DDR_B_CLK0#

DDR_B_CLK0
DDR_B_CLK0#

DDR_B_MA10
DDR_B_BS0

6 DDR_B_BS0

DDR_B_WE#
DDR_B_CAS#

6 DDR_B_WE#
6 DDR_B_CAS#

Layout Note:
Place near JDIMM2

DDR_B_MA13
DDR_B_CS1#

6 DDR_B_CS1#

Layout Note: Place these 4 Caps near Command


and Control signals of DIMMA

DDR_B_D32
DDR_B_D33

+1.5V

DDR_B_DQS#4
DDR_B_DQS4
10U_0805_6.3V6M

10U_0805_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_B_D34
DDR_B_D35

1
C660

C657

10U_0805_6.3V6M 2

C659

C655

C656

C658

C331

C330

C329

C333

DDR_B_D40
DDR_B_D41

C307
330U_X_2VM_R6M

DDR_B_DM5
DDR_B_D42
DDR_B_D43

10U_0805_6.3V6M

10U_0805_6.3V6M

10U_0805_6.3V6M

0.1U_0402_16V4Z

0.1U_0402_16V4Z
DDR_B_D48
DDR_B_D49
DDR_B_DQS#6
DDR_B_DQS6

Layout Note:
Place near JDIMM2.203 & JDIMM2.204

DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57

+0.75VS

DDR_B_DM7
DDR_B_D58
DDR_B_D59

1U_0603_10V4Z
R685 1
C667 2 C666 2 C671 2 C665 2

1 C690

+3VS

2 10K_0402_5%
1

R686
1U_0603_10V4Z

10U_0805_6.3V6M
C661

2.2U_0603_6.3V4Z
1U_0603_10V4Z

+1.5V
JDIMM2

R328

6 DDR_B_DM[0..7]

6 DDR_B_MA[0..15]

C663
0.1U_0402_16V4Z

2
10K_0402_5%

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207

VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT

VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT

GND1
GND2

BOSS1
BOSS2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D6
DDR_B_D7
DDR_B_D12
DDR_B_D13

DDR_B_DM1
DIMM_RST#
DDR_B_D14
DDR_B_D15
DDR_B_D20
DDR_B_D21
DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D28
DDR_B_D29
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D30
DDR_B_D31

DDR_B_CKE1

DDR_B_CKE1 6

DDR_B_MA15
DDR_B_MA14

DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_CLK1
DDR_B_CLK1#

+DDR_VREF_CA
DDR_B_D36
DDR_B_D37
DDR_B_DM4
DDR_B_D38
DDR_B_D39

C334
2.2U_0603_6.3V4Z

DDR_B_D44
DDR_B_D45

C332
0.1U_0402_16V4Z
B

DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D61
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63
PM_EXTTS#0_1
D_CK_SDATA
D_CK_SCLK

PM_EXTTS#0_1 5,10
D_CK_SDATA 10,12
D_CK_SCLK 10,12

+0.75VS

DDR3 SO-DIMM B
Standard Type
Title

Date:

DDR_B_DQS#5
DDR_B_DQS5

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

DDR_B_ODT1 6

206
208

2010/04/15

Deciphered Date

DDR_B_CS0# 6
DDR_B_ODT0 6

DDR_B_ODT1

Compal Secret Data


2009/5/12

DDR_B_BS1 6
DDR_B_RAS# 6

DDR_B_CS0#
DDR_B_ODT0

TYCO_2-2013310-1_204P
CONN@

Issued Date

DDR_B_CLK1 6
DDR_B_CLK1# 6

DDR_B_BS1
DDR_B_RAS#

1U_0603_10V4Z

Security Classification

DDR_B_MA11
DDR_B_MA7

Compal Electronics, Inc.


DDRIII-SODIMM SLOT2
Document Number

Rev
1.0

NALG0 M/B LA-5681P Schematic


Friday, October 23, 2009

Sheet
1

11

of

60

power save CLK gen use +1.5VS at +CLK_VDD


+1.5VS
+CLK_VDDSRC

+CLK_VDD
@
L12
2
1
FBMA-L11-201209-221LMA30T_0805
0.1U_0402_16V4Z

L13 2
1
FBMA-L11-201209-221LMA30T_0805

+1.05VS

C297
C286
10U_0805_10V4Z

L14
2
1
FBMA-L11-201209-221LMA30T_0805
1
C298

+3VS

10U_0805_10V4Z

C628

C632
0.1U_0402_16V4Z

0.1U_0402_16V4Z

10U_0805_10V4Z

Clock Generator

C630

C631

0.1U_0402_16V4Z

+CLK_SE
0.1U_0402_16V4Z

C308

+CLK_VDD

L17
2
1
FBMA-L11-201209-221LMA30T_0805

+3VS

+CLK_VDDSRC

C634

0.1U_0402_16V4Z

C636

C633
0.1U_0402_16V4Z

10U_0805_10V4Z

+CLK_VDDSRC
+CLK_VDD

U27

Integrated 33ohm Resistor


14 CLK_BUF_DREF_96M
14 CLK_BUF_DREF_96M#
22
22
36

27M_CLK
27M_SSC
CLK_SD_48M

0_0404_4P2R_5%
1
4 CLK_BUF_DREF_96M_R
2
3 CLK_BUF_DREF_96M#_R
RP12
+CLK_SE
R316 1 DIS@
27M_CLK_R
2 0_0402_5%
R317 1 DIS@
27M_SSC_R
2 0_0402_5%
CLK_SD_48M_R
1
2
R318
33_0402_5%

CLK_BUF_DREF_96M
CLK_BUF_DREF_96M#

CLK_SD_48M

14 CLK_BUF_PCIE_SATA
14 CLK_BUF_PCIE_SATA#
14 CLK_BUF_CPU_DMI
14 CLK_BUF_CPU_DMI#

CLK_BUF_PCIE_SATA
CLK_BUF_PCIE_SATA#
CLK_BUF_CPU_DMI
CLK_BUF_CPU_DMI#

1
2
RP11
1
2
RP10

4
3
4
3

CLK_BUF_PCIE_SATA_R
CLK_BUF_PCIE_SATA#_R
0_0404_4P2R_5%
CLK_BUF_CPU_DMI_R
CLK_BUF_CPU_DMI#_R
0_0404_4P2R_5%
H_STP_CPU#

Integrated 33ohm Resistor

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
33

VDD_USB_48
VSS_48M
DOT_96
DOT_96#
VDD_27
27MHZ
27MHZ_SS
USB_48

SCL
SDA
REF_0/CPU_SEL
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
CKPWRGD/PD#

32
31
30
29
28
27
26
25

VDD_CPU
CPU_0
CPU_0#
VSS_CPU
CPU_1
CPU_1#
VDD_CPU_IO
VDD_SRC

24
23
22
21
20
19
18
17

VSS_27M
SATA
SATA#
VSS_SRC
SRC_1
SRC_1#
VDD_SRC_IO
CPU_STOP#

D_CK_SCLK
D_CK_SDATA
REF_0/CPU_SEL

R305 1

CLK_XTAL_IN
CLK_XTAL_OUT

D_CK_SCLK 10,11
D_CK_SDATA 10,11
CLK_BUF_ICH_14M 14

2 33_0402_5%
+CLK_SE

CK505_PW RGD
2

CLK_BUF_CPU_BCLK_R
CLK_BUF_CPU_BCLK#_R

CLK_BUF_CPU_BCLK
4
CLK_BUF_CPU_BCLK#
3
0_0404_4P2R_5%

1
2

CLK_BUF_CPU_BCLK 14
CLK_BUF_CPU_BCLK# 14

RP9

Integrated 33ohm Resistor

IDT SA000030P00

TGND

SLG8SP587VTR_QFN32_5X5
<BOM Structure>

IDT: 9LRS3199AKLFT, SA000030P00


SILEGO: SLG8SP587V(WF), SA00002XY10

+3VS

R301
10K_0402_5%

+3VS

R320
4.7K_0402_5%
1
2
+3VS

IDT Have Internal Pull-Down

3
S

1 XDP@ 2
R310
0_0402_5%

CPU_1
133MHz

100MHz

100MHz

14,32 PCH_SMBCLK

3
S

CPU_0
133MHz

Q34
2N7002_SOT23

15,55

2
G
Q29
2N7002_SOT23

CLK_ENABLE# 55

XDP_SDATA 5
CLK_XTAL_IN

2
2

R321
4.7K_0402_5%
1
2

PIN 30

VGATE

+3VS

2 10K_0402_5% REF_0/CPU_SEL

0 (Default)

C715

D_CK_SDATA

Q33
2N7002_SOT23

2
G

R315 1

1
D

14,32 PCH_SMBDATA

0.1U_0402_16V4Z

+3VS

H_STP_CPU#

R297
0_0402_5%
@
1
2

CK505_PW RGD

+3VS

D_CK_SCLK

1 XDP@ 2
R311
0_0402_5%

CLK_XTAL_OUT

2 10K_0402_5%

2
G

R302 1

Silego Have Internal Pull-Up

C303
1

27P_0402_50V8J
Y4
C301
14.318MHZ_16PF_7A14300083
27P_0402_50V8J
2
1

XDP_SCLK 5

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/5/12

Deciphered Date

2010/04/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Clock Generator (CK505)


Size
Document Number
Custom

Rev
1.0

NALG0 M/B LA-5681P Schematic

Date:

Friday, October 23, 2009


G

Sheet

12

of
H

60

+3VS

C210
18P_0402_50V8J
2
1

NC

OSC

100K_0402_5%
U18A

10M_0402_5%

32.768KHZ_12.5PF_Q13MC14610002
C211
2
1

R729

R176

B13
D13

PCH_RTCX2

REV1.0
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3

D33
B33
C32
A32

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

FWH4 / LFRAME#

C34

LPC_FRAME#

LDRQ0#
LDRQ1# / GPIO23

A34
F34

SERIRQ

AB9

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

AK7
AK6
AK11
AK9

SATA_DTX_C_PRX_N0
SATA_DTX_C_PRX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0

SATA_DTX_C_PRX_N0 31
SATA_DTX_C_PRX_P0 31
SATA_PTX_DRX_N0 31
SATA_PTX_DRX_P0 31

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

AH6
AH5
AH9
AH8

SATA_DTX_C_PRX_N1
SATA_DTX_C_PRX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1

SATA_DTX_C_PRX_N1 31
SATA_DTX_C_PRX_P1 31
SATA_PTX_DRX_N1 31
SATA_PTX_DRX_P1 31

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

AF11
AF9
AF7
AF6

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

AH3
AH1
AF3
AF1

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

AD9
AD8
AD6
AD5

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

AD3
AD1
AB3
AB1

RTCX1
RTCX2

2 1M_0402_5%

SM_INTRUDER#

A16

INTRUDER#

R564 1

2 332K_0402_1% PCH_INTVRMEN

A14

INTVRMEN

HDA_BITCLK_PCH

A30

HDA_BCLK

HDA_SYNC_PCH

D29

HDA_SYNC

R183

40 HDA_RST_AUDIO#

R186

40 HDA_SDOUT_AUDIO

R180

1
1
1
1

PCH_SPKR

37,40 PCH_SPKR

HDA_BITCLK_PCH
2
33_0402_5%
HDA_SYNC_PCH
2
33_0402_5%
HDA_RST#_PCH
2
33_0402_5%
HDA_SDOUT_PCH
2
33_0402_5%

P1

HDA_RST#_PCH

40 HDA_SDIN0

C30

HDA_RST#

G30

HDA_SDIN0

F30

HDA_SDIN1

E32

HDA_SDIN2

F32

HDA_SDIN3

HDA_SDOUT_PCH

B29

HDA_SDO

ME_EN#

H32

HDA_DOCK_EN# / GPIO33

GPIO33 can not pull down


(manufacturing environments)

J30

HDA_DOCK_RST# / GPIO13

PCH_JTAG_TCK

M3

JTAG_TCK

PCH_JTAG_TMS

K3

JTAG_TMS

PCH_JTAG_TDI

K1

JTAG_TDI

PCH_JTAG_TDO

J2

JTAG_TDO

PCH_JTAG_RST#

J4

TRST#

39 HDA_SDIN1

HDA for MDC


39 HDA_BITCLK_MDC

R593

39 HDA_SYNC_MDC

R590

39 HDA_RST_MDC#

R596

39 HDA_SDOUT_MDC

R583

1
1
1
1

HDA_BITCLK_PCH
2
33_0402_5%
HDA_SYNC_PCH
2
33_0402_5%
HDA_RST#_PCH
2
33_0402_5%
HDA_SDOUT_PCH
2
33_0402_5%

If GPIO33 pull down, ME will not working.


For factory update ME, pull down resistor pull
under door.

1
2
R512
10K_0402_5%

PCH_SPI_CLK

2 15_0402_5%

PCH_SPI_CS0#_R AV3

SPI_CS0#

AY3

SPI_CS1#

R124 1

BA2

37
37
37
37

37

2
G

R730

LPC_FRAME# 37

Q61
2N7002_SOT23

100K_0402_5%

SERIRQ

37

SATA for HDD1

SATA for ODD

2/10 SATA2, SATA3 not support on HM55


C

SATA_DTX_C_PRX_N4
SATA_DTX_C_PRX_P4
SATA_PTX_DRX_N4
SATA_PTX_DRX_P4

SATA_DTX_C_PRX_N4 35
SATA_DTX_C_PRX_P4 35
SATA_PTX_DRX_N4 35
SATA_PTX_DRX_P4 35

SATA for eSATA

+1.05VS

SATAICOMPO

AF16

SATAICOMPI

AF15

SATA_COMP

R576 1

2 37.4_0402_1%

R136 1

2 10K_0402_5%

+3VS

SPI_CLK

SATALED#

T3

SATA0GP / GPIO21

Y9

R517 1

2 10K_0402_5%

SATA1GP / GPIO19

V1

R135 1

2 10K_0402_5%

SATA_LED# 44

+3VS
B

PCH_SPKR

Have internal PD
SERIRQ

PCH_SPI_MOSI_1 R123 1

2 15_0402_5%

PCH_SPI_MOSI AY1

PCH_SPI_MISO_1 R125 1

2 33_0402_5%

PCH_SPI_MISO

AV1

SPI_MOSI
SPI_MISO

IBEXPEAK-M_FCBGA107
R111
+1.05VS

R518

R115 1
R114 1
R138 1

PCH_JTAG_TMS

R141 1
R118 1
R140 1

PCH_JTAG_TDO

2 51_0402_5%
2 200_0402_5%
2 100_0402_5%

R116 1
R117 1
R139 1

PCH_JTAG_TDI

2 51_0402_5%
2 200_0402_5%
2 100_0402_5%

R142 1
R119 1
R143 1

2 51_0402_5%
2 200_0402_5%
2 100_0402_5%

10K_0402_5%

10K_0402_5%

+3VALW

PCH_JTAG_RST#

ME_EN

ME_EN#
D

R130
1K_0402_5%
@
1
2

2 0_0402_5%

PCH_SPI_CS0#

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

+3VS
B

PCH_SPI_CLK_1 R122 1

SPI

SPKR

SATA

INTVRMEN - Integrated SUS 1.1V VRM Enable


High - Enable Internal VRs

R185

40 HDA_SYNC_AUDIO

SRTCRST#

R567 1

HDA for AUDIO


40 HDA_BITCLK_AUDIO

D17

IHDA

1
2
J5
@
10K_0603_5%
C518
1U_0603_10V6K
1
2

RTCRST#

PCH_SRTCRST#

JTAG

close to RAM door

C14

RTC

+RTCVCC

RC Delay 18~25mS

PCH_RTCRST#

LPC

18P_0402_50V8J
PCH_SRTCRST#

1
2
R566
20K_0402_1%

OSC

NC

X1

1
2
J4
@
10K_0603_5%
C505
1U_0603_10V6K
1
2

PCH_RTCX1

RC Delay 18~25mS

close to RAM door

+RTCVCC

PCH_RTCRST#

1
2
R565
20K_0402_1%

+RTCVCC

2008 Intel MOW36/MOW50

TDO:
Reserved on ES1 Sample
Mount R516, R517 on ES2 Sample

MP mount R689, R690,


R691, R692 and remove
others

+3VS
U14

2 51_0402_5%
2 20K_0402_5%
2 10K_0402_5%

+3VS

R97
R96

1
1

2 3.3K_0402_5%
2 3.3K_0402_5%

PCH_SPI_CS0#
SPI_W P1#
SPI_HOLD1#

1
3
7
4

CS#
WP#
HOLD#
GND

VCC
SCLK
SI
SO

8
6
5
2

PCH_SPI_CLK_1
PCH_SPI_MOSI_1
PCH_SPI_MISO_1

MX25L1605DM2I-12G SOP 8P

SA000021A00

SPI ROM (4M)

+3VS

PCH_SPI_MOSI

R134

2 1K_0402_5%

enable iTPM: SPI_MOSI High


PCH_JTAG_TCK

R137

2 4.7K_0402_5%

CRB 1.0 Change to 4.7K


5

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/5/12

Issued Date

Deciphered Date

2010/04/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

PCH (1/9) SATA,HDA,SPI, LPC


Size
Document Number
Custom

Rev
1.0

NALG0 M/B LA-5681P Schematic

Date:

Friday, October 23, 2009

Sheet
1

13

of

60

U18B

BG34
BJ34
BG36
BJ36

R244 1
R245 1

33 CLK_PCIE_LAN#
33 CLK_PCIE_LAN

For PCIE LAN

For Wireless LAN

2 0_0402_5%
2 0_0402_5%

CLK_PCIE_LAN#_R
CLK_PCIE_LAN_R

33 LAN_CLKREQ#

R528 1

2 0_0402_5%

32 CLK_PCIE_MINI1#
32 CLK_PCIE_MINI1

R242 1
R243 1

2 0_0402_5%
2 0_0402_5%

CLK_PCIE_MINI1#_R
CLK_PCIE_MINI1_R

AM43
AM45

R129 1

2 0_0402_5%

PCH_GPIO18

U4

32 MINI1_CLKREQ#

PCH_GPIO73

PCIECLKRQ0# / GPIO73
CLKOUT_PCIE1N
CLKOUT_PCIE1P
PCIECLKRQ1# / GPIO18

AM47
AM48
PCH_GPIO20

CLKOUT_PCIE2N
CLKOUT_PCIE2P

N4

CL_CLK1

T13
T11

CL_RST1#

T9

PEG_A_CLKRQ# / GPIO47

H1

R98
10K_0402_5%

+3VALW

+3VS_DELAY

DIS@
R109
10K_0402_5%

R121
Q16
2N7002_SOT23

10K_0402_5%

3
DIS@

PEG_CLKREQ#_R

AD43
AD45

CLK_PEG_VGA# 22
CLK_PEG_VGA 22

CLKOUT_DMI_N
CLKOUT_DMI_P

AN4
AN2

CLK_CPU_DMI# 5
CLK_CPU_DMI 5

CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P

AT1
AT3

CLK_CPU_DP# 5
CLK_CPU_DP 5

1 @
R120
1 @
R144

2
0_0402_5%
2
0_0402_5%

PEG_CLKREQ# 22
VGA_PW ROK 39,52
+3VS

CLKOUT_PCIE0N
CLKOUT_PCIE0P

P9

PCH_SML1DAT

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

PERN8
PERP8
PETN8
PETP8

AK48
AK47

G12

PERN7
PERP7
PETN7
PETP7

SML1DATA / GPIO75

AT34
AU34
AU36
AV36

2/10 PCIE7, PCIE8 not support on HM55

SML1CLK / GPIO58

PCH_SML1CLK

2
G

PERN6
PERP6
PETN6
PETP6

PCH_GPIO74

E10

CLK_BUF_CPU_DMI# 12
CLK_BUF_CPU_DMI 12

CLKIN_BCLK_N
CLKIN_BCLK_P

AP3
AP1

CLK_BUF_CPU_BCLK# 12
CLK_BUF_CPU_BCLK 12

CLKIN_DOT_96N
CLKIN_DOT_96P

F18
E18

CLK_BUF_DREF_96M# 12
CLK_BUF_DREF_96M 12

AH13
AH12

CLK_BUF_PCIE_SATA# 12
CLK_BUF_PCIE_SATA 12

REFCLK14IN

P41

CLK_BUF_ICH_14M

CLKIN_PCILOOPBACK

J42

CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P

EC_SMB_CK2

EC_SMB_CK2 22,37

Q17
2N7002_SOT23

AW24
BA24

CLKIN_DMI_N
CLKIN_DMI_P

PCIECLKRQ2# / GPIO20

PCH_SML1CLK

BA34
AW34
BC34
BD34

M14

CL_DATA1

+3VS_DELAY

SML1ALERT# / GPIO74

+3VS

PCH_SML1DAT

3
S

PERN5
PERP5
PETN5
PETP5

G8

BF33
BH33
BG32
BJ32

1
1
mini2@
mini2@

C6

2
G

C246 2
C244 2

SML0CLK
SML0DATA

PERN4
PERP4
PETN4
PETP4

PCH_GPIO60

BA32
BB32
BD32
BE32

PCIE_DTX_C_PRX_N4
PCIE_DTX_C_PRX_P4
0.1U_0402_16V7K
PCIE_PTX_DRX_N4
0.1U_0402_16V7K
PCIE_PTX_DRX_P4

PCH_SMBDATA 12,32

J14

For Mini2

PCIE_DTX_C_PRX_N4
PCIE_DTX_C_PRX_P4
PCIE_PTX_C_DRX_N4
PCIE_PTX_C_DRX_P4

PCH_SMBCLK 12,32

PCH_SMBDATA

32
32
32
32

SML0ALERT# / GPIO60

PCH_SMBCLK

C8

2
G

PERN3
PERP3
PETN3
PETP3

H14

1. Connect Directly
EXPRESS CARD, MINI1, MINI2
2. Level Shift1, Pull-Up to +3VS
CLOCK GEN, DIMM1, DIMM2
3. Level Shift2, Pull-Up to +3VS
LAN
4. Level Shift3, Pull-Up to +3VS
CPU & PCH XDP

EC_LID_OUT# 37

AU30
AT30
AU32
AV32

EC_LID_OUT#

PERN2
PERP2
PETN2
PETP2

B9

1
1

SMBCLK
SMBDATA

SMBus

C242 2
C243 2

PCIE_DTX_C_PRX_N2 AW30
PCIE_DTX_C_PRX_P2 BA30
0.1U_0402_16V7K
PCIE_PTX_DRX_N2 BC30
0.1U_0402_16V7K
PCIE_PTX_DRX_P2 BD30

SMBALERT# / GPIO11

Link

PCIE_DTX_C_PRX_N2
PCIE_DTX_C_PRX_P2
PCIE_PTX_C_DRX_N2
PCIE_PTX_C_DRX_P2

1
1

PERN1
PERP1
PETN1
PETP1

Controller

32
32
32
32

2
2

BG30
BJ30
BF29
BH29

PEG

For Wireless LAN

C240
C241

REV1.0

PCIE_DTX_C_PRX_N1
PCIE_DTX_C_PRX_P1
0.1U_0402_16V7K
PCIE_PTX_DRX_N1
0.1U_0402_16V7K
PCIE_PTX_DRX_P1

PCI-E*

For PCIE LAN

PCIE_DTX_C_PRX_N1
PCIE_DTX_C_PRX_P1
PCIE_PTX_C_DRX_N1
PCIE_PTX_C_DRX_P1

From CLK BUFFER

33
33
33
33

EC_SMB_DA2

EC_SMB_DA2 22,37

Q21
2N7002_SOT23

Layout guide 1.52 update

2 0_0402_5%
2 0_0402_5%

A8

CLK_PCIE_MINI2#_R
CLK_PCIE_MINI2_R

AM51
AM53

MINI2_CLKREQ#_1

PCH_GPIO44

1
R551

2
0_0402_5%

PCH_GPIO56

XCLK_RCOMP

AF38

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

P13

PEG_B_CLKRQ# / GPIO56

CLK_PCI_FB 17
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP

R604 1

2 90.9_0402_1%

R209
1M_0402_5%
UMA@

+1.05VS
+3VS

CLKOUTFLEX0 / GPIO64

T45

CLKOUTFLEX1 / GPIO65

P43 PROJECT_ID1

R617 1
R622 1

CLKOUTFLEX2 / GPIO66

T42

PROJECT_ID0

R616 1
R609 1

CLKOUTFLEX3 / GPIO67

N50

C255
27P_0402_50V8J
1
2
UMA@

Y6
25MHZ_20PF_7A25000012
UMA@

Project Port ID

1
@
@

2
UMA@
C254
27P_0402_50V8J

2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%

IBEXPEAK-M_FCBGA107

2 10K_0402_5%
2 10K_0402_5%

Project ID

+3VALW

EC_LID_OUT#
PCH_SMBCLK
PCH_SMBDATA

R170 1
R178 1
R547 1

2 10K_0402_5%
2 2.2K_0402_5%
2 2.2K_0402_5%

PCH_GPIO60

R572 1

2 10K_0402_5%

PCH_SML1CLK
PCH_SML1DAT

R546 1
R148 1

2 2.2K_0402_5%
2 2.2K_0402_5%

PCH_GPIO74

R573 1

2 10K_0402_5%

R727 1

2 10K_0402_5%

R534 1
R574 1
R538 1

2 10K_0402_5%
2 10K_0402_5%
2 10K_0402_5%

PCH_GPIO18
PCH_GPIO44
PCH_GPIO56
PCH_GPIO73

PCIECLKRQ5# / GPIO44

AK53
AK51

MINI2_CLKREQ#_1

+3VS

MINI1_CLKREQ# R112 1
PCH_GPIO20
R107 1

CLKOUT_PCIE5N
CLKOUT_PCIE5P

H6

10K_0402_5%

32 MINI2_CLKREQ#

PCIECLKRQ4# / GPIO26

AJ50
AJ52

R545

XTAL25_IN
XTAL25_OUT

AH51
AH53

CLKOUT_PCIE4N
CLKOUT_PCIE4P

M9

+3VS

For CardReader

PCIECLKRQ3# / GPIO25

R230 1
R229 1

PCH_GPIO25

32 CLK_PCIE_MINI2#
32 CLK_PCIE_MINI2

2 10K_0402_5%

DIS only@
R228 1
2
0_0402_5%

12

For Mini2

R554 1

Clock Flex

+3VS

CLKOUT_PCIE3N
CLKOUT_PCIE3P

AH42
AH41

ID1

ID0

Project

1
1

0
1

JV 40
JM 40

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/5/12

Issued Date

Deciphered Date

2010/04/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

PCH (2/9) PCIE, SMBUS, CLK


Size
Document Number
Custom

Rev
1.0

NALG0 M/B LA-5681P Schematic

Date:

Friday, October 23, 2009

Sheet
1

14

of

60

DMI_PTX_HRX_N[0..3]

4 DMI_PTX_HRX_N[0..3]

DMI_PTX_HRX_P[0..3]

4 DMI_PTX_HRX_P[0..3]

H_FDI_TXN[0..7]

4 H_FDI_TXN[0..7]

U18C

DMI_PTX_HRX_N0
DMI_PTX_HRX_N1
DMI_PTX_HRX_N2
DMI_PTX_HRX_N3

BE22
BF21
BD20
BE18

DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN

DMI_PTX_HRX_P0
DMI_PTX_HRX_P1
DMI_PTX_HRX_P2
DMI_PTX_HRX_P3

BD22
BH21
BC20
BD18

DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP

BH25
DMI_COMP

SYS_PW ROK
VGATE

R100 2
R95 2

1 0_0402_5%
1 0_0402_5%

PWROK

K5

MEPWROK

A10

LAN_RST#
DRAMPWROK

C16

RSMRST#

SUS_PW R_ACK

M1

PBTN_OUT#

P5

PCH_ACIN

P7

ACPRESENT / GPIO31

PCH_GPIO72

A6

BATLOW# / GPIO72

EC_SW I#

FDI_FSYNC1

BH13

H_FDI_FSYNC1

FDI_LSYNC0

BJ12

H_FDI_LSYNC0

FDI_LSYNC1

BG14

H_FDI_LSYNC1

J12

PCH_PCIE_W AKE#

CLKRUN# / GPIO32

Y1

PM_CLKRUN#

SUS_STAT# / GPIO61

P8

PCH_GPIO61

PAD

T17

PCH_GPIO62

PAD

T15

PWRBTN#

PCH_PCIE_W AKE#

4
4

32,33

PM_CLKRUN# 37

SUSCLK / GPIO62

F3

SLP_S5# / GPIO63

E4

PM_SLP_S5# 37

SLP_S4#

H7

PM_SLP_S4# 37

SLP_S3#

P12

SLP_M#

K8

PM_SLP_M#

PAD

T16

TP23

N2

PM_SLP_DSW # @

PAD

T4

SUS_PWR_DN_ACK / GPIO30

PM_SLP_S3# 37

@
1 0_0402_5%

R198 2
Q25
MMBT3906_SOT23-3
PCH_RSMRST#
1
3

EC_RSMRST# 37

1
R530

37

H_FDI_FSYNC0

SYS_PWROK

10/2 Intel suggestion change to 10K

37,43,44,45 ACIN

H_FDI_INT

BF13

M6

PCH_RSMRST#

5,37 PBTN_OUT#
2
100K_0402_5%
2
D10
CH751H-40PT_SOD323-2

BJ14

SYS_PW ROK_R

D9

FDI_INT

WAKE#

1 ME_PW ROK
0_0402_5%

FDI_FSYNC0

SYS_RESET#

5 PM_DRAM_PW RGD

+3VALW

H_FDI_TXP0
H_FDI_TXP1
H_FDI_TXP2
H_FDI_TXP3
H_FDI_TXP4
H_FDI_TXP5
H_FDI_TXP6
H_FDI_TXP7

DMI_IRCOMP

B17

37 SUS_PW R_ACK

BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12

T6

LAN_RST#

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

XDP_DBRESET#

SYS_PW ROK

2
R101

H_FDI_TXN0
H_FDI_TXN1
H_FDI_TXN2
H_FDI_TXN3
H_FDI_TXN4
H_FDI_TXN5
H_FDI_TXN6
H_FDI_TXN7

EC_SW I#

F14

PMSYNCH

RI#

SLP_LAN# / GPIO29

BJ10
F6

H_PM_SYNC

2
B

5 XDP_DBRESET#

DMI_ZCOMP

BF25

BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12

R184
49.9_0402_1%
1
2

DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

R197
10K_0402_5%

PM_SLP_LAN#

1
R207

IBEXPEAK-M_FCBGA107
@

2
4.7K_0402_5%

+3VALW

D14A

+1.05VS
SUS_PW R_ACK
2
10K_0402_5%
PCH_GPIO72
2
8.2K_0402_5%
EC_SW I#
2
10K_0402_5%
PCH_PCIE_W AKE#
2
1K_0402_5%
PM_SLP_LAN#
2
10K_0402_5%

BD24
BG22
BA20
BG20

FDI

+3VALW

DMI_HTX_PRX_P0
DMI_HTX_PRX_P1
DMI_HTX_PRX_P2
DMI_HTX_PRX_P3

DMI

PM_CLKRUN#
2
8.2K_0402_5%
XDP_DBRESET#
2
10K_0402_5%

DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN

System Power Management

+3VS

REV1.0

DMI_HTX_PRX_N0 BC24
DMI_HTX_PRX_N1 BJ22
DMI_HTX_PRX_N2 AW20
DMI_HTX_PRX_N3 BJ20

H_FDI_TXP[0..7]

4 H_FDI_TXP[0..7]

1
R108
1
R165
1
R580
1
R552
1 @
R540

DMI_HTX_PRX_P[0..3]

4 DMI_HTX_PRX_P[0..3]

1
R127
1 @
R509

DMI_HTX_PRX_N[0..3]

4 DMI_HTX_PRX_N[0..3]

1
6
2

EC_PW ROK
VGATE

4
3

EC_PW ROK 37
VGATE

12,55

P
4

D14B
U13
2

BAV99DW -7_SOT363

R206
2.2K_0402_5%

NC7SZ08P5X_NL_SC70-5

SYS_PW ROK

BAV99DW -7_SOT363

+3VS

SYS_PW ROK

1
R103

2
10K_0402_5%

2
10K_0402_5%

1
R174

2
10K_0402_5%

EC_PW ROK
R94
LAN_RST#

2009/5/12

Issued Date

Deciphered Date

2010/04/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

No used Integrated LAN,


connecting LAN_RST# to GND
5

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Title

PCH (3/9) DMI, FDI, PM


Size
Document Number
Custom

Rev
1.0

NALG0 M/B LA-5681P Schematic

Date:

Friday, October 23, 2009

Sheet
1

15

of

60

U18D

L_BKLTEN
L_VDD_EN

28 DPST_PW M

Y48

L_BKLTCTL

28 PCH_LCD_CLK
28 PCH_LCD_DATA

AB48
Y45

L_DDC_CLK
L_DDC_DATA

AB46
V48

L_CTRL_CLK
L_CTRL_DATA

PCH_ENVDD

LCTLA_CLK
LCTLB_DATA
LVDS_IBG

AP39
AP41

LVD_IBG
LVD_VBG

R618 1 UMA@ 2
0_0402_5%

LVD_VREF

AT43
AT42

LVD_VREFH
LVD_VREFL

28 PCH_TXCLK28 PCH_TXCLK+

+3VS

R608 1 UMA@ 2
2.37K_0402_1%

11/21 intel JIM suggest Pull high at LVDS Conn


for LVDS DDC

28 PCH_TXOUT028 PCH_TXOUT128 PCH_TXOUT2-

R639 1

28 PCH_TXOUT0+
28 PCH_TXOUT1+
28 PCH_TXOUT2+

2 10K_0402_5%

LCTLA_CLK

R641 1

2 10K_0402_5%

LCTLB_DATA

R219 1

2 2.2K_0402_5%

PCH_CRT_CLK

R220 1

2 2.2K_0402_5%

PCH_CRT_DATA

R227
R226
R225

PCH_CRT_B
150_0402_1%
PCH_CRT_G
150_0402_1%
PCH_CRT_R
150_0402_1%

AV53
AV51

LVDSA_CLK#
LVDSA_CLK

PCH_TXOUT0PCH_TXOUT1PCH_TXOUT2-

BB47
BA52
AY48
AV47

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

PCH_TXOUT0+
PCH_TXOUT1+
PCH_TXOUT2+

BB48
BA50
AY49
AV48

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

AP48
AP47

LVDSB_CLK#
LVDSB_CLK

AY53
AT49
AU52
AT53

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

AY51
AT48
AU50
AT51

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

AA52
AB53
AD53

CRT_BLUE
CRT_GREEN
CRT_RED

PCH_CRT_CLK
PCH_CRT_DATA

29 PCH_CRT_CLK
29 PCH_CRT_DATA
29 PCH_CRT_HSYNC
29 PCH_CRT_VSYNC

CRT_DDC_CLK
CRT_DDC_DATA

Y53
Y51

CRT_HSYNC
CRT_VSYNC
DAC_IREF
CRT_IRTN

SDVO_STALLN
SDVO_STALLP

BJ48
BG48

SDVO_INTN
SDVO_INTP

BF45
BH45

T51
T53

SDVO_SCLK 30
SDVO_SDATA 30
R606 1

DDPB_AUXN
DDPB_AUXP
DDPB_HPD

BG44
BJ44
AU38

PCH_DPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38

PCH_DPB_N0
PCH_DPB_P0
PCH_DPB_N1
PCH_DPB_P1
PCH_DPB_N2
PCH_DPB_P2
PCH_DPB_N3
PCH_DPB_P3

DDPC_CTRLCLK
DDPC_CTRLDATA

Y49
AB49

DDPC_AUXN
DDPC_AUXP
DDPC_HPD

BE44
BD44
AV40

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36

2 100K_0402_5%
PCH_DPB_HPD

C613
C611
C615
C614
C620
C618
C617
C616

2
2
2
2
2
2
2
2

1
1
1
1
1
1
1
1

UMA only@
0.1U_0402_16V7K
UMA only@
0.1U_0402_16V7K
UMA only@
0.1U_0402_16V7K
UMA only@
0.1U_0402_16V7K
UMA only@
0.1U_0402_16V7K
UMA only@
0.1U_0402_16V7K
UMA only@
0.1U_0402_16V7K
UMA only@
0.1U_0402_16V7K

30

PCH_TMDS_D2# 30
PCH_TMDS_D2 30
PCH_TMDS_D1# 30
PCH_TMDS_D1 30
PCH_TMDS_D0# 30
PCH_TMDS_D0 30
PCH_TMDS_CK# 30
PCH_TMDS_CK 30

HDMI D2
HDMI D1
HDMI D0
HDMI CLK

DDPD_CTRLCLK
DDPD_CTRLDATA

V51
V53

CRT_IREF AD48
AB51

REV1.0

U50
U52

DDPD_AUXN
DDPD_AUXP
DDPD_HPD

BC46
BD46
AT38

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36

IBEXPEAK-M_FCBGA107
@

BJ46
BG46

SDVO_CTRLCLK
SDVO_CTRLDATA

PCH_TXCLKPCH_TXCLK+

PCH_CRT_B
PCH_CRT_G
PCH_CRT_R

29 PCH_CRT_B
29 PCH_CRT_G
29 PCH_CRT_R

SDVO_TVCLKINN
SDVO_TVCLKINP

CRT

28

Digital Display Interface

T48
T47

LVDS

IGPU_BKLT_EN

2/3 Change to 1K_0402_0.5% from Intel


Suggestion. (EDS 1.0 is incorrect)

R623
1K_0402_0.5%

+5VS

22 VGA_BKL_EN

IGPU_BKLT_EN

28 PW MSEL_1#
28 IGPU_PW M_SELECT#

2
5
1
7

1A
2A
1OE#
2OE#

VCC
1B
2B
GND

8
3
6
4

C178
SG@
0.1U_0402_16V4Z
2

ENBKL

ENBKL

37

U11

R83
100K_0402_5%

SN74CBTD3306CPW R_TSSOP8
SG@
A

IGPU_BKLT_EN

R76

1 UMA only@
2

0_0402_5% ENBKL

Reserved for UMA Only


R77

1 DIS only@2

0_0402_5%

ENBKL

2009/5/12

Issued Date

Reserved for DIS Only

Compal Electronics, Inc.

Compal Secret Data

Security Classification
VGA_BKL_EN

Deciphered Date

2010/04/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Title

PCH (4/9) LVDS, CRT, DPI


Size
Document Number
Custom

Rev
1.0

NALG0 M/B LA-5681P Schematic

Date:

Friday, October 23, 2009

Sheet
1

16

of

60

2
2
2
2

1
1
1
1

2
2
2
2

8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%

8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%

28,29 DGPU_SELECT#

PCI_GNT0#
PCI_GNT1#
PCI_GNT3#

F48
K45
F36
H53

GNT0#
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

B41
K53
A36
A48

PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5

PCI_SERR#
PCI_PERR#

E44
E50

SERR#
PERR#

PCI_IRDY#
PCI_DEVSEL#
PCI_FRAME#

A42
H44
F46
C46

IRDY#
PAR
DEVSEL#
FRAME#

PCI_PLOCK#

D49

PLOCK#

PCI_STOP#
PCI_TRDY#

D41
C48

STOP#
TRDY#

M7

PME#

D5

PLTRST#

28 DGPU_PW MSEL#

K6

5,33,37 PLT_RST#

37 CLK_PCI_LPC
14
CLK_PCI_FB

R221
R627

1
1

2 22_0402_5%
2 22_0402_5%

PLT_RST#

CLK_PCI_LPC_R
CLK_PCI_FB_R

N52
P53
P46
P51
P48

2008/1/6 2009MOW01 change to 22 ohm

NV_RCOMP

NV_RB#

AV7

NV_WR#0_RE#
NV_WR#1_RE#

AY8
AY5

NV_WE#_CK0
NV_WE#_CK1

PCIRST#

NC7SZ08P5X_NL_SC70-5

R149
100K_0402_5%

+VCCQ_NAND
+3VS
R153 1
R555 1

@
@

2 1K_0402_5%
2 1K_0402_5%

R133 1

U19
2 B

2 32.4_0402_1%
18 DGPU_HOLD_RST#

Y
A

NC7SZ08P5X_NL_SC70-5
DIS@

H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24

USBRBIAS#

B25

USBRBIAS

D25

OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14

N16
J16
F16
L16
E14
G16
F12
T15

R162 1 DIS@
100_0402_5%

PLTRST_VGA# 22

R161
100K_0402_5%
DIS@

AV11
BF5

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

PLT_RST_BUF# 32

REQ0#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54

AU2

Y
A

F51
A46
B45
M53

NV_RCOMP

PCI_REQ0#
PCI_REQ1#
DGPU_SELECT#
PCI_REQ3#

NV_ALE
NV_CLE

U17
2 B

PIRQA#
PIRQB#
PIRQC#
PIRQD#

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

BD3
AY6

PLT_RST#

G38
H51
B37
A44

PCI_FRAME#
PCI_REQ1#
PCI_PIRQH#
PCI_TRDY#

NV_ALE
NV_CLE

+3VS

C/BE0#
C/BE1#
C/BE2#
C/BE3#

PCI_IRDY#
PCI_PIRQD#
DGPU_SELECT#
PCI_DEVSEL#

NVRAM

J50
G42
H47
G34

PCI_REQ0#
PCI_PIRQB#
PCI_PIRQF#
PCI_REQ3#

AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6

1
1
1
1

8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%

NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15

2
2
2
2

PCI_PLOCK#
PCI_PERR#
PCI_PIRQE#
PCI_STOP#

AV9
BG8

1
1
1
1

8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%

NV_DQS0
NV_DQS1

R200
R199
R202
R201

2
2
2
2

AY9
BD1
AP15
BD8

R194
R195
R196
R625

1
1
1
1

NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3

R224
R223
R222
R235

2
2
2
2

REV1.0

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

PCI_PIRQA#
PCI_PIRQG#
PCI_PIRQC#
PCI_SERR#

USB

R218
R624
R192
R193

1
1
1
1

8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%
8.2K_0402_5%

H40
N34
C44
A38
C36
J34
A40
D45
E36
H48
E40
C40
M48
M45
F53
M40
M43
J36
K48
F40
C42
K46
M51
J52
K51
L34
F42
J40
G46
F44
M47
H36

PCI

R621
R187
R188
R205

U18E

+3VS

USB20_N0
USB20_P0
USB20_N1
USB20_P1

35
35
35
35

USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5

28
28
32
32
32
32

eSATA USB Conn.(LEFT REAR)


USB/B(RIGHT)
EHCI 1

CMOS Camera (LVDS)

Danbury Technology Enabled

Mini Card(WLAN)
Mini Card(Mini2)

High = Enabled

NV_ALE
USB20_N8 35
USB20_P8 35
USB20_N9 36
USB20_P9 36
USB20_N10 35
USB20_P10 35
USB20_N11 35
USB20_P11 35

Low = Disabled

USB Conn. (HS)(LEFT FRONT)


DMI Termination Voltage

Card Reader
Bluetooth
EHCI 2

Fingerprint

Set to Vss when LOW

NV_CLE

Set to Vcc when HIGH

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

USB_BIAS

1
2
R584
22.6_0402_1%

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3_R
USB_OC#4
USB_OC#5_R
USB_OC#6_R
USB_OC#7_R

IBEXPEAK-M_FCBGA107
@

USB_OC#0 35
USB_OC#2 35

(For USB Port0)

USB_OC#0

(For eSATA USB Port)

USB_OC#1

1
R281
1
R750

2
10K_0402_5%
2
10K_0402_5%

(For USB Port8)

USB_OC#4 35

RP17
USB_OC#3_R
USB_OC#5_R
USB_OC#7_R
USB_OC#6_R

OC[0..3] use for EHCI 1


OC[4..7] use for EHCI 2

1
2
3
4

8
7
6
5

+3VALW

10K_1206_8P4R_5%
<BOM Structure>

Boot BIOS Strap


PCI_GNT0#

PCI_GNT#0

PCI_GNT#1

Boot BIOS Location

PCI_GNT1#

LPC

Reserved (NAND)

PCI

SPI

2 1K_0402_5%

R238 1

2 1K_0402_5%

2009/5/12

Issued Date

Low = A16 swap


High = Default

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Swap Override jumper

2 1K_0402_5%

Have internal PU

A16 swap override Strap/Top-Block

PCI_GNT#3

R620 1

Have internal PU
PCI_GNT3#

R638 1

Have internal PU

Deciphered Date

2010/04/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Title

PCH (5/9) PCI, USB, VRAM


Size
Document Number
Custom

Rev
1.0

NALG0 M/B LA-5681P Schematic

Date:

Friday, October 23, 2009

Sheet
1

17

of

60

+3VS
U18F

37
37

R531 1
R110 1

2 10K_0402_5% PCH_GPIO48
2 10K_0402_5% PCH_TEMP_ALERT#

R529 1
R602 1

2 10K_0402_5% PCH_GPIO34
2 10K_0402_5% EC_SCI#

+3VALW

30

EC_SCI#
EC_SMI#

HDMI_HPD#
17 DGPU_HOLD_RST#
R619 1
0_0402_5%

39 DGPU_PW ROK_BUF

C38

TACH1 / GPIO1

PCH_GPIO6

D37

TACH2 / GPIO6

EC_SCI#

J32

TACH3 / GPIO7

EC_SMI#

F10

CP_PE#

K9

1 SG@
2PCH_GPIO15 T7
R519
0_0402_5%
DGPU_HOLD_RST# AA2
DGPU_PW ROK_BUF_R
GPIO22

R550 1

2 10K_0402_5% PCH_GPIO57

R553 1

2 10K_0402_5% EC_SMI#

R508 1

2 1K_0402_5% PCH_GPIO15

F38
Y7

AM3

CLK_CPU_BCLK# 5

CLKOUT_BCLK0_P / CLKOUT_PCIE8P

AM1

CLK_CPU_BCLK 5

SCLOCK / GPIO22

H10

GPIO24

PCH_GPIO34

M11

STP_PCI# / GPIO34

PCH_GPIO35

V6

R615 1 @

2 10K_0402_5% DGPU_PW ROK_BUF_R

R539 1

2 10K_0402_5% PCH_GPIO35

R511 1 @

2 10K_0402_5% PCH_GPIO27

DIS@

2 10K_0402_5%

TP1

BA22

AB13

AW22
BB22

GPIO39

P3

SDATAOUT0 / GPIO39

TP4

AY45

PCH_GPIO45

H3

PCIECLKRQ6# / GPIO45

TP5

AY46

PCH_GPIO46

F1

PCIECLKRQ7# / GPIO46

TP6

AV43

SDATAOUT1 / GPIO48

TP7

AV45

SATA5GP / GPIO49

TP8

AF13

GPIO57

TP9

M18

TP10

N18

TP11

AJ24

TP12

AK41

TP13

AK42

TP14

M32

TP15

N32

TP16

M30

TP17

N30

TP18

H12

TP19

AA23

NC_1

AB45

NC_2

AB38

NC_3

AB42

NC_4

AB41

NC_5

T39

F8

A4
A49
A5
A50
A52
A53
B2
B4
B52
B53
BE1
BE53
BF1
BF53
BH1
BH2
BH52
BH53
BJ1
BJ2
BJ4
BJ49
BJ5
BJ50
BJ52
BJ53
D1
D2
D53
E1
E53

2
1
1
3

SATA2GP / GPIO36

AB6

2 10K_0402_5%

EC_KBRST# 37
H_CPUPW RGD

THRMTRIP_PCH#

SATACLKREQ# / GPIO35

AB7

PCH_TEMP_ALERT# AA4

2 10K_0402_5%

H_PECI 5
EC_KBRST#

2
R558

5
H_THERMTRIP#

1
56_0402_5%

2
R559

TP3

High: CRT Plugged

2
Q15G
2N7002_SOT23

BD10

TP2

R104
10K_0402_5%

CRT_DET#

BE10

THRMTRIP#

SLOAD / GPIO38

+3VS

29

PROCPWRGD

SATA3GP / GPIO37

GPIO27 (Have internal Pull-High)


High: VCCVRM VR Enable
Low: VCCVRM VR Disable

CRT_DET

T1

V3

PCH_GPIO57

RCIN#

BG10

GPIO38

PCH_GPIO48
37 PCH_TEMP_ALERT#

R105 1

EC_KBRST# R106 1

H_THERMTRIP# 5

1
56_0402_5%

+1.1VS_VTT

WW46 Platform/Design Updates


2008/11/17 54.9 1% ->56 5%
C

MAINPW ON 46,47,49

+1.1VS_VTT

R556
@ 330_0402_5%
1
2

Q43

2
B
E

R731 1

PECI

CPU

R507 1
R560 1
R131 1

+3VS

EC_GA20 37

CLKOUT_BCLK0_N / CLKOUT_PCIE8N

GPIO28

EC_GA20

TACH0 / GPIO17

GPIO27

DGPU_PW R_EN

U2

SATA4GP / GPIO16

V13

PCH_GPIO37

EC_GA20

A20GATE

+3VS

GPIO15

AB12

39 DGPU_PW R_EN

AF48
AF47

LAN_PHY_PWR_CTRL / GPIO12

PCH_GPIO28

R562 1
2 10K_0402_5%
UMA only@

CLKOUT_PCIE7N
CLKOUT_PCIE7P

GPIO8

PCH_GPIO27

(Rev:1.0 GPIO24 Only)

AH45
AH46

(GPIO8 Should not be Pull-Low)

10/7 Not Use PCH_GPIO15 PU 1K to +3V


2 10K_0402_5% PCH_GPIO28
2 10K_0402_5% CP_PE#
2 10K_0402_5% PCH_GPIO45

CLKOUT_PCIE6N
CLKOUT_PCIE6P

2 10K_0402_5% GPIO38
2 10K_0402_5% GPIO39
2 10K_0402_5% DGPU_PW R_EN

BMBUSY# / GPIO0

DGPU_EDIDSEL#

MISC

R128 1
R113 1
R532 1

28 DGPU_EDIDSEL#

Y3

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31

RSVD

2
2
2
2

DGPU_EDIDSEL#
PCH_GPIO6
DGPU_HOLD_RST#
GPIO22

NCTF

1
1
1
1

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

GPIO

CRT_DET
R191
R190
R126
R510

INIT3_3V#

REV1.0

TP24

2SC2411K_SOT23
@

H_THERMTRIP#

P6

(Have internal PD,


Do not pull high)

C10

TP24_SST

PAD T6

IBEXPEAK-M_FCBGA107
@

+3VALW

10K_0402_5%
R132

10,11 RST_GATE

1
R733

S3@
PCH_GPIO46
2
0_0402_5%

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/5/12

Issued Date

Deciphered Date

2010/04/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

PCH (6/9) GPIO, CPU, MISC


Size
Document Number
Custom

Rev
1.0

NALG0 M/B LA-5681P Schematic

Date:

Friday, October 23, 2009

Sheet
1

18

of

60

+1.05VS

+3VS

Near AB24
Top Side

Near AB24

All Ibex Peak-M Power rails with netnames +1.1VS and


+1.1V rails are actually +1.05VS and +1.05V rails

10U_0805_10V4Z
1
C549

Near AN20
1
C535

1U_0402_6.3V4Z
1
C547

Top Side

1U_0402_6.3V4Z
1

1
C542

1U_0402_6.3V4Z

C537

1U_0402_6.3V4Z

Near AN35
+3VS

Follow Intel suggestion 8/21


0.1U_0402_16V4Z
C556 2
1

LVDS

42mA

1uH inductor, 405mA


Change to 0 ohm
for discrete

+VCCAPLL_FDI

VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]
VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]
VCCIO[50]
VCCIO[51]
VCCIO[52]
VCCIO[53]

AN30
AN31

VCCIO[54]
VCCIO[55]

AN35

VCC3_3[1]

AT22

VCCVRM[1]

BJ18

VCCFDIPLL

1
+1.05VS

C223
10U_0805_10V4Z
2
@

VCCALVDS

AH38

VSSA_LVDS

AH39

AM23

VCCTX_LVDS[1]
VCCTX_LVDS[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]

AP43
AP45
AT46
AT45

VCC3_3[2]

AB34

VCC3_3[3]

AB35

VCC3_3[4]

AD35

HVCMOS

AN20
AN22
AN23
AN24
AN26
AN28
BJ26
BJ28
AT26
AT28
AU26
AU28
AV26
AV28
AW26
AW28
BA26
BA28
BB26
BB28
BC26
BC28
BD26
BD28
BE26
BE28
BG26
BG28
BH27

VCCIO[1]

0.01U_0402_16V7K
1
C597

+VCCADAC

R635
0_0402_5%
@

C554

VCCVRM[2]

3208mA

6mA

C256
0.1U_0402_16V4Z
2

61mA
VCCDMI[1]
VCCDMI[2]

AU16

156mA
VCCPNAND[1]
VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]
VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]

22U_0805_6.3V6M
1

2
+3VS

CRB 0.9 is 180 ohm @ 100MHz


DG0.8 is 600 ohm FB (Page 290)

+1.8VS

Near AP43

L41 UMA@
2
1
0.1UH_MLF1608DR10KT_10%_1608

+VCCTX_LVDS
C596
C590 1
UMA@ 1
1
0.01U_0402_16V7K
22U_0805_6.3V6M
C591
UMA@
0.01U_0402_16V7K
2
2
UMA@ 2

0.1uH inductor, 200mA


1 DIS only@2
R628
0_0402_5%

+3VS

Near AB34
R587 1 @

2 0_0805_5%

+1.05VS

R588 1 @

2 0_0805_5%

+1.5VS

2
0_0805_5%

+1.8VS

1
R582

+1.1VS_VTT
+VCC_DMI
1

1
R575

C516
1U_0402_6.3V4Z
2

AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15

600 ohm bead,350mA

C257

1 UMA@ 2
R634
0_0805_5%

AT24
AT16

L9
1
2
BLM18AG601SN1D_2P

R605
0_0402_5%
DIS only@

0.1U_0402_16V4Z
2

35mA

22U_0805_6.3V6M
1

C598

Near AE50

+VCCVRM

FDI

+VCCVRM

AF51

VCCAPLLEXP

+1.05VS

L7 1
@
2
1UH_CBC2012T1R0M_20%

VSSA_DAC[2]

DMI

+1.05VS

BJ24

VCCIO[24]

NAND / SPI

AF53

300mA

PCI E*

DG 0.8 is 1uH Inductor (Page 291)


Have Internal VRM (DG0.8 Page 293)

+VCCAPLL_EXP
1
C225
@
10U_0805_10V4Z
2

VSSA_DAC[1]

59mA
AK24

L8 1
@
2
1UH_CBC2012T1R0M_20%

AE52

+VCCA_LVDS

+1.05VS
+1.05VS

1uH inductor, 405mA

AE50

VCCADAC[2]

VCCADAC[1]

69mA

C544

VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4]1524mA
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]

C550

AB24
AB26
AB28
AD26
AD28
AF26
AF28
AF30
AF31
AH26
AH28
AH30
AH31
AJ30
AJ31

CRT

1U_0402_6.3V4Z
1

Intel suggest follow CRB 8/21

VCC CORE

10U_0805_10V4Z
1

60mA

POWER

U18G

1
R570

2
0_0805_5%
@

+1.05VS

2
0_0805_5%

Near AT16

+VCCQ_NAND

C514

+1.8VS

1
R527

2
0_0805_5%

0.1U_0402_16V4Z
2

85mA
VCCME3_3[1]
VCCME3_3[2]
VCCME3_3[3]
VCCME3_3[4]

AM8
AM9
AP11
AP9

Near AK13
+3VS

C506

REV1.0
IBEXPEAK-M_FCBGA107

0.1U_0402_16V4Z
2

Near AM8
DG 0.8 is 1uH Inductor (Page 291)
Have Internal VRM (DG0.8 Page 293)

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/5/12

Issued Date

Deciphered Date

2010/04/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

PCH (7/9) PWR


Size
Document Number
Custom

Rev
1.0

NALG0 M/B LA-5681P Schematic

Date:

Friday, October 23, 2009

Sheet
1

19

of

60

22U_0805_6.3V6M
1

22U_0805_6.3V6M

C587

Near AD38

VCCME[2]

AD41

VCCME[3]

AF43

VCCME[4]

AF41

VCCME[5]

AF42

VCCME[6]

V39

VCCME[7]

V41

VCCME[8]

V42

VCCME[9]

Y39

VCCME[10]

Y41

VCCME[11]

All Ibex Peak-M Power rails with netnames +1.1VS and


+1.1V rails are actually +1.05VS and +1.05V rails

Y42

Near V9

C503
0.1U_0402_16V4Z
+VCCRTCEXT
1
2

V9

AU24

+VCCVRM

BB51
BB53

+VCCADPLLA

+VCCADPLLB

+1.05VS

Near AF32
1
C555
1U_0402_6.3V4Z

C546

Near AH23

Near AH35

C533

+3VALW

72mA
VCCADPLLA[1]
VCCADPLLA[2]

73mA

AH23
AJ35
AH35

VCCIO[21]
VCCIO[22]
VCCIO[23]

AF34

VCCIO[2]

1U_0402_6.3V4Z

AH34

V12

+VCCSUS
1
2
C531
Near
0.1U_0402_16V4Z

Y22

0.1U_0402_16V4Z

VCCVRM[3]

VCCADPLLB[1]
VCCADPLLB[2]

+VCCSST
1
2
C509
Near
0.1U_0402_16V4Z

C515

DCPRTC

BD51
BD53

1U_0402_6.3V4Z

VCCME[12]

C530

AF32

VCCIO[4]

V12

DCPSST

Y22

4.7U_0805_10V4Z

C522

V5REF

357mA

K49

VCC3_3[8]

J38

VCC3_3[9]

L38

VCCSUS3_3[30]

U20

VCCSUS3_3[31]

U22

VCCSUS3_3[32]

V15

VCC3_3[5]

V16

VCC3_3[6]

Y16

VCC3_3[7]

AT18

> 1mA

AT18

V_CPU_IO[1]

AU18

V_CPU_IO[2]

A12

2mA
VCCRTC

IBEXPEAK-M_FCBGA107

+VCCADPLLB

C595
C260
1U_0402_6.3V4Z
2
220U_B2_2.5VM_R35
2

+3VALW

+1.05VS

Near BD51

D11
CH751H-40PT_SOD323-2

2/12 Follow
EDS1.11 Change
to 100 ohm

+VCC5REFSUS

+3VS
+5VALW

R589
2 100_0402_5%

C536
1U_0402_6.3V6K

Near F24

+VCC5REF

D15
CH751H-40PT_SOD323-2
R630
100_0402_5%
1
2

Change to 1U for power


sequence issue on ICH9

2/12 Follow EDS1.11


Change to 100 ohm

+5VS

C593
1U_0402_6.3V6K

Near K49
+3VS

N36

VCC3_3[12]

P36

C558

VCC3_3[13]

U35

0.1U_0402_16V4Z
2

VCC3_3[14]

AD13

+3VS

Near J38

Near AD13

+1.05VS

2 C508
0.1U_0402_16V4Z

+VCCSATAPLL

L6 1 @
2
1 10UH_LB2012T100MR_20%

10uH inductor, 120mA

C181
10U_0805_10V4Z
2
@

DG 0.8 is 10uH Inductor (Page 291)


Have Internal VRM (DG0.8 Page 293)

C183
1U_0402_6.3V4Z
2
@

Near AK1

VCCIO[9]

AH22

VCCVRM[4]

AT20

VCCIO[10]

AH19

VCCIO[11]

AD20

VCCIO[12]

AF22

VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]

AD19
AF20
AF19
AH20

C517
1U_0402_6.3V4Z
2

VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]

AB19
AB20
AB22
AD22

VCCME[13]
VCCME[14]
VCCME[15]
VCCME[16]

AA34
Y34
Y35
AA35

+VCCVRM
+1.05VS

Near AB19
+1.05VS

PCH_VCCME13
PCH_VCCME14
PCH_VCCME15
PCH_VCCME16

R599
R232
R234
R233

1
1
1
1

2
2
2
2

L30

0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%

+3VALW
C541 1

2 1U_0402_6.3V4Z

Near L30
1

C512

C510

C504
1U_0402_6.3V4Z

0.1U_0402_16V4Z
2

0.1U_0402_16V4Z

Near A12

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/5/12

Issued Date

Deciphered Date

2010/04/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

+RTCVCC

Near U23

R208
0_0402_5%
@

L10
1
2
10UH_LB2012T100MR_20%

M36

6mA

C594
1U_0402_6.3V4Z
C261
2
220U_B2_2.5VM_R35
2

10uH inductor, 120mA 1

VCC3_3[11]

VCCSUSHDA

0.1U_0402_16V4Z
2

Near A26

VCC3_3[10]

AK3
AK1

C534

0.1U_0402_16V4Z
2

>1mA

DCPSUS

VCCSUS3_3[29]

0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z
Near

F24

VCCSATAPLL[1]
VCCSATAPLL[2]

P18

C521

V5REF_SUS

>1mA

32mA

U19

Near V15

VCCIO[56]

V23

RTC

+1.1VS_VTT

U23

Near BB51

L11
1
2
10UH_LB2012T100MR_20%

10uH inductor, 120mA


1
C227

VCCIO[3]

+3VS

0.1U_0402_16V4Z

VCCSUS3_3[28]

+3VALW

Near V24

+1.05VS

Near P18

C513

163mA

+VCCADPLLA

VCCME[1]

Near V39

1U_0402_6.3V4Z

1998mA

AD39

C229
C588
22U_0805_6.3V6M
2
2
1U_0402_6.3V4Z

DCPSUSBYP

AD38

V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26

+1.05VS

C540
1U_0402_6.3V4Z
2

0.1U_0402_16V4Z
2

VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCSUS3_3[21]
VCCSUS3_3[22]
VCCSUS3_3[23]
VCCSUS3_3[24]
VCCSUS3_3[25]
VCCSUS3_3[26]
VCCSUS3_3[27]

+1.05VS

C520

Follow Intel suggestion

C559

VCCLAN[2]

Near Y20
+1.05VS

C230

VCCLAN[1]

AF24
Y20

+PCH_VCCD6W

V24
V26
Y24
Y26

C532
1U_0402_6.3V4Z
2
@

Near AF23

AF23

R579
0_0402_5%

VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]

344mA

USB

Near AP51

VCCACLK[2]

HDA

R592 1
0_0603_5%

AP53

SATA

+1.05VS

C599
1U_0402_6.3V4Z
2
@

VCCACLK[1]

PCI/GPIO/LPC

C608
10U_0805_10V4Z
2
@

REV1.0

52mA

AP51

Clock and Miscellaneous

10uH inductor, 120mA

POWER

U18J

L43
+1.1VS_VCCACLK
1 @
2
10UH_LB2012T100MR_20% 1
1

PCI/GPIO/LPC

+1.05VS

DG 0.8 is 10uH Inductor (Page 290)


Have Internal VRM (DG0.8 Page 293)

CPU

Title

PCH (8/9) PWR


Size
Document Number
Custom

Rev
1.0

NALG0 M/B LA-5681P Schematic

Date:

Friday, October 23, 2009

Sheet
1

20

of

60

U18I

AY7
B11
B15
B19
B23
B31
B35
B39
B43
B47
B7
BG12
BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49
BB5
BC10
BC14
BC18
BC2
BC22
BC32
BC36
BC40
BC44
BC52
BH9
BD48
BD49
BD5
BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50
BE6
BE8
BF3
BF49
BF51
BG18
BG24
BG4
BG50
BH11
BH15
BH19
BH23
BH31
BH35
BH39
BH43
BH47
BH7
C12
C50
D51
E12
E16
E20
E24
E30
E34
E38
E42
E46
E48
E6
E8
F49
F5
G10
G14
G18
G2
G22
G32
G36
G40
G44
G52
AF39
H16
H20
H30
H34
H38
H42

U18H

VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[326]
VSS[327]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[332]
VSS[333]
VSS[334]
VSS[335]
VSS[336]
VSS[337]
VSS[338]
VSS[339]
VSS[340]
VSS[341]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[366]

H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14

AB16

VSS[0]

AA19
AA20
AA22
AM19
AA24
AA26
AA28
AA30
AA31
AA32
AB11
AB15
AB23
AB30
AB31
AB32
AB39
AB43
AB47
AB5
AB8
AC2
AC52
AD11
AD12
AD16
AD23
AD30
AD31
AD32
AD34
AU22
AD42
AD46
AD49
AD7
AE2
AE4
AF12
Y13
AH49
AU4
AF35
AP13
AN34
AF45
AF46
AF49
AF5
AF8
AG2
AG52
AH11
AH15
AH16
AH24
AH32
AV18
AH43
AH47
AH7
AJ19
AJ2
AJ20
AJ22
AJ23
AJ26
AJ28
AJ32
AJ34
AT5
AJ4
AK12
AM41
AN19
AK26
AK22
AK23
AK28

VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

REV1.0

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47

IBEXPEAK-M_FCBGA107
@

REV1.0

Compal Electronics, Inc.

Compal Secret Data

Security Classification

IBEXPEAK-M_FCBGA107
@

2009/5/12

Issued Date

Deciphered Date

2010/04/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

PCH (9/9) VSS & PCH XDP Port


Size
Document Number
Custom

Rev
1.0

NALG0 M/B LA-5681P Schematic

Date:

Friday, October 23, 2009

Sheet
1

21

of

60

U35A

DIS@ 1 2K_0402_5%
DIS@ 1 2K_0402_5%

VGA_LCD_CLK
VGA_LCD_DAT

R478 1
R477 1

DIS@ 22.2K_0402_5%
DIS@ 22.2K_0402_5%

I2CS_SCL
I2CS_SDA

R748 1
R749 1

DIS@ 22.2K_0402_5%
DIS@ 22.2K_0402_5%

I2CB_SCL
I2CB_SDA

LVDS
28 VGA_LCD_CLK
28 VGA_LCD_DAT

B1
B2

XTAL_OUTBUFF
XTAL_SSIN

D1
D2

I2CS_SCL
I2CS_SDA

E2
E1

VGA_LCD_CLK
VGA_LCD_DAT
I2CB_SCL
I2CB_SDA

CRT

29 VGA_DDC_CLK
29 VGA_DDC_DATA

VGA_DDC_CLK
G1
VGA_DDC_DATA G4

+1.05VSDGPU

Q60B
2N7002DW-T/R7_SOT363-6 DIS@
I2CS_SDA 4
3

@
R44
10K_0402_5%

GPIO1

IN

HDMI Hot-plug

GPIO2

OUT

VGA_PNL_PWM

GPIO3

OUT

ENVDD

GPIO4

OUT

VGA_BKL_EN

GPIO5

OUT

N/A

NVVDD VID0

GPIO6

OUT

N/A

NVVDD VID1

GPIO7

OUT

N/A

N/A

GPIO8

IN

N/A

GPIO9

OUT

N/A

GPIO10

OUT

N/A

N/A

GPIO11

OUT

N/A

N/A

GPIO12

IN

N/A

N/A

GPIO13

OUT

N/A

N/A

GPIO14

OUT

N/A

N/A

VID_PLLVDD
XTAL_IN
XTAL_OUT
XTAL_OUTBUFF
XTAL_SSIN

MIOBCAL_PD_VDDQ
MIOBCAL_PU_GND
DACA_RED
DACA_GREEN
DACA_BLUE
DACA_HSYNC
DACA_VSYNC

I2CS_SCL
I2CS_SDA

DACA_VDD
DACA_VREF
DACA_RSET

I2CC_SCL
I2CC_SDA
I2CB_SCL
I2CB_SDA
I2CA_SCL
I2CA_SDA
I2CH_SCL
I2CH_SDA

BLM18PG181SN1D_0603
2
1
DIS@ L54

EC_SMB_DA2 14,37

+3VS_DELAY

1
2
3
4

A0
A1
A2
GND

AT24C16AN-10SU-2.7_SO8
@
R39
2.2K_0402_5%

HDCP@ R48
100K_0402_1%

12

27M_CLK

R70

1 @

XTALIN

2
0_0402_5%
Y2

XTALOUT
VGA_CRT_R

3
2

VGA_CRT_G

C160
18P_0402_50V8J
DIS@

OUT

GND

GND

IN

4
1
1

27MHZ_16PF_X7T027000BG1H-V
DIS@

VGA_CRT_B

C161
18P_0402_50V8J
DIS@

External Spread Spectrum

OSC_OUT

R51

2 @ 22_0402_5%

XTAL_OUTBUFF

U8
REFOUT

XOUT

1 DIS@ 2
R487
10K_0402_5%

VSS

MODOUT

XIN/CLKIN

VDD

R54
10K_0402_5%
DIS@
OSC_SPREAD

+3VS_DELAY
1

@ ASM3P2872AF-06OR_TSOT-23-6

@
C86
0.1U_0402_16V4Z

OSC_SPREAD R52

2 @ 22_0402_5%

XTAL_SSIN
1

R62
R61
R58
DIS@ DIS@ DIS@

12

XTAL_SSIN

27M_SSC

W4

DACB_RED
DACB_GREEN
DACB_BLUE
DACB_HSYNC
DACB_VSYNC
DACB_VDD
DACB_VREF
DACB_RSET

AA7
AA6
VGA_CRT_R 29
VGA_CRT_G 29
VGA_CRT_B 29

AM13
AL13

VGA_CRT_HSYNC
VGA_CRT_VSYNC

AJ12
AK12
AK13

R55
10K_0402_5%
DIS@

If External Spread Spectrum not stuff then stuff resistor

AM15
AM14
AL14

1
1
124_0402_1% R59

2
DIS@

29
29

AK4
AL4
AJ4

1
C478
DIS@

AM1
AM2

BLM18PG181SN1D_0603
1
2
+3VS_DELAY
DIS@L38

150 mA

DACA_VDD
2 0.1U_0402_16V4Z
C133 DIS@

1
C487
DIS@

1
C490
DIS@

1
C704
DIS@
2

0.1U_0402_16V4Z
AG7
2 R494
1
AK6 10K_0402_5% DIS@
1
2
R474 2
DIS@ C152
AH7
1
124_0402_1%
DIS@

SP_PLLVDD

1
C702
DIS@
2

1
C703
DIS@

Compal Secret Data

Security Classification
Issued Date

2009/5/12

Deciphered Date

2009/12/31

Title

Compal Electronics, Inc.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

N11M PEG 1/6


Rev
1.0

NALG0 M/B LA-5681P Schematic

Date:

HDCP_SCL
HDCP_SDA

VCC
WP
SCL
SDA

2
MIOB_CLKOUT_N

USAGE

U9 HDCP@
8
7
6
5

R37
2.2K_0402_5%

HDCP@
C81
0.1U_0402_16V4Z

PLLVDD
SP_PLLVDD

N/A

DIS@ N11M-GE1-B-A2_BGA969

EC_SMB_CK2 14,37

+3VS_DELAY

F6
G6

4.7U_0603_6.3V6M

Q60A
2N7002DW-T/R7_SOT363-6 DIS@
I2CS_SCL
1
6

E3
E4
G3
G2

HDCP_SCL
HDCP_SDA
4

AE1
V4

N/A

2
AD9
XTALIN
XTALOUT

DIS@ 1 2K_0402_5% VGA_DDC_CLK


DIS@ 1 2K_0402_5% VGA_DDC_DATA

R470 2
R469 2

R36
2.2K_0402_5%

DIS@

4.7U_0603_6.3V6M

C149
DIS@

+3VS_DELAY

R471 2
R472 2

DIS@

1U_0402_6.3V6K

+3VS_DELAY

4700P_0402_25V7K

C154
DIS@

AF9

2
+3VS_DELAY
10K_0402_5%

470P_0402_50V7K

AE9
SP_PLLVDD

37

OSC_OUT
MIOB_CLKIN
MIOB_CLKOUT

CLK

1
R740 DIS@

ACTIVE

IN

+3VS_DELAY

PEX_RST_N
PEX_TERMP

I2C
DACs

C159
DIS@
2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C164
DIS@

GPU_PLLVDD

0.1U_0402_16V4Z

1U_0402_6.3V6K

4.7U_0603_6.3V6M

22U_0805_6.3V6M

36 mA

AM16
AG21

@
2
1
R53
2.49K_0402_1%

Y5
W3
AF1

1
+3VS_DELAY
2.2K_0402_5%

VGA_idle

I/O

GPIO0

1
17 PLTRST_VGA#

MIOB_DE
MIOB_CTL3
MIOB_VREF

W1
W2

DIS@

PEX_TSTCLK_OUT
PEX_TSTCLK_OUT_N

MIOB_HSYNC
MIOB_VSYNC

+3VS_DELAY

2N7002_SOT23
1

AJ17
AJ18

R57 @
2
1
200_0402_1%

BLM18PG181SN1D_0603
2
1
+1.05VSDGPU
DIS@ L5
1
1
C492
C169
DIS@
DIS@
2
2

GPIO

PEX_REFCLK
PEX_REFCLK_N
PEX_CLKREQ_N

14 CLK_PEG_VGA
14 CLK_PEG_VGA#

Q65

150_0402_1%

14 PEG_CLKREQ#

R93

GPIO
+3VS_DELAY

2
10K_0402_5%

150_0402_1%

R497
10K_0402_5%
DIS@

Y1
Y2
Y3
AB3
AB2
AB1
AC4
AC1
AC2
AC3
AE3
AE2
U6
W6
Y6

1 DIS@

150_0402_1%

AR16
AR17
AR13

MIOB_D0
MIOB_D1
MIOB_D2
MIOB_D3
MIOB_D4
MIOB_D5
MIOB_D6
MIOB_D7
MIOB_D8
MIOB_D9
MIOBD_10
MIOB_D11
MIOB_D12
MIOB_D13
MIOB_D14

R63

PEX_TXP15
PEX_TXN15

PEX_TX0
PEX_TX0_N
PEX_TX1
PEX_TX1_N
PEX_TX2
PEX_TX2_N
PEX_TX3
PEX_TX3_N
PEX_TX4
PEX_TX4_N
PEX_TX5
PEX_TX5_N
PEX_TX6
PEX_TX6_N
PEX_TX7
PEX_TX7_N
PEX_TX8
PEX_TX8_N
PEX_TX9
PEX_TX9_N
PEX_TX10
PEX_TX10_N
PEX_TX11
PEX_TX11_N
PEX_TX12
PEX_TX12_N
PEX_TX13
PEX_TX13_N
PEX_TX14
PEX_TX14_N
PEX_TX15
PEX_TX15_N

GPU_VID0 52
GPU_VID1 52
1 DIS@ 2
R7141 DIS@ 10K_0402_5%
2
R715
10K_0402_5%
1 DIS@ 2
R67
10K_0402_5%

PEX_TXP9
PEX_TXN9
PEX_TXP10
PEX_TXN10
PEX_TXP11
PEX_TXN11
PEX_TXP12
PEX_TXN12
PEX_TXP13
PEX_TXN13
PEX_TXP14
PEX_TXN14

AL17
AM17
AM18
AM19
AL19
AK19
AL20
AM20
AM21
AM22
AL22
AK22
AL23
AM23
AM24
AM25
AL25
AK25
AL26
AM26
AM27
AM28
AL28
AK28
AK29
AL29
AM29
AM30
AM31
AM32
AN32
AP32

1
2.2K_0402_5%

ENVDD
28
VGA_BKL_EN 16

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

PEX_TXP0
PEX_TXN0
PEX_TXP1
PEX_TXN1
PEX_TXP2
PEX_TXN2
PEX_TXP3
PEX_TXN3
PEX_TXP4
PEX_TXN4
PEX_TXP5
PEX_TXN5
PEX_TXP6
PEX_TXN6
PEX_TXP7
PEX_TXN7
PEX_TXP8
PEX_TXN8

PCI EXPRESS
DVO

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

PEG_GTX_C_HRX_P0
PEG_GTX_C_HRX_N0
PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_N1
PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_N2
PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_N3
PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_N4
PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_N5
PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_N6
PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_N7
PEG_GTX_C_HRX_P8
PEG_GTX_C_HRX_N8
PEG_GTX_C_HRX_P9
PEG_GTX_C_HRX_N9
PEG_GTX_C_HRX_P10
PEG_GTX_C_HRX_N10
PEG_GTX_C_HRX_P11
PEG_GTX_C_HRX_N11
PEG_GTX_C_HRX_P12
PEG_GTX_C_HRX_N12
PEG_GTX_C_HRX_P13
PEG_GTX_C_HRX_N13
PEG_GTX_C_HRX_P14
PEG_GTX_C_HRX_N14
PEG_GTX_C_HRX_P15
PEG_GTX_C_HRX_N15
+3VS_DELAY

C151
C146
C129
C124
C139
C135
C121
C118
C130
C126
C116
C112
C104
C101
C110
C106
C96
C92
C102
C97
C94
C91
C67
C63
C62
C60
C57
C56
C54
C53
C51
C50

N1
P4
P1
P2
P3
T3
T2
T1
U4
U1
U2
U3
R6
T6
N6
N2
N3
L3
P5
N5
N4
R4
U5
T5
T4

2
R716

VGA_HDMI_DET 30
VGA_PNL_PWM 28

4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4

DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

K1
K2
K3
H3
H2
H1
H4
H5
H6
J7
K4
K5
H7
J4
J6
L1
L2
L4
M4
L7
L5
K6
L6
M6

4
4
4
4

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23

4
4
4
4
4
4

Part 1 of 7

PEX_RX0
PEX_RX0_N
PEX_RX1
PEX_RX1_N
PEX_RX2
PEX_RX2_N
PEX_RX3
PEX_RX3_N
PEX_RX4
PEX_RX4_N
PEX_RX5
PEX_RX5_N
PEX_RX6
PEX_RX6_N
PEX_RX7
PEX_RX7_N
PEX_RX8
PEX_RX8_N
PEX_RX9
PEX_RX9_N
PEX_RX10
PEX_RX10_N
PEX_RX11
PEX_RX11_N
PEX_RX12
PEX_RX12_N
PEX_RX13
PEX_RX13_N
PEX_RX14
PEX_RX14_N
PEX_RX15
PEX_RX15_N

1U_0402_6.3V6K

AP17
AN17
AN19
AP19
AR19
AR20
AP20
AN20
AN22
AP22
AR22
AR23
AP23
AN23
AN25
AP25
AR25
AR26
AP26
AN26
AN28
AP28
AR28
AR29
AP29
AN29
AN31
AP31
AR31
AR32
AR34
AP34

4 PEG_HTX_C_GRX_P0
4 PEG_HTX_C_GRX_N0
4 PEG_HTX_C_GRX_P1
4 PEG_HTX_C_GRX_N1
4 PEG_HTX_C_GRX_P2
4 PEG_HTX_C_GRX_N2
4 PEG_HTX_C_GRX_P3
4 PEG_HTX_C_GRX_N3
4 PEG_HTX_C_GRX_P4
4 PEG_HTX_C_GRX_N4
4 PEG_HTX_C_GRX_P5
4 PEG_HTX_C_GRX_N5
4 PEG_HTX_C_GRX_P6
4 PEG_HTX_C_GRX_N6
4 PEG_HTX_C_GRX_P7
4 PEG_HTX_C_GRX_N7
4 PEG_HTX_C_GRX_P8
4 PEG_HTX_C_GRX_N8
4 PEG_HTX_C_GRX_P9
4 PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_N11
PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_N12
4 PEG_HTX_C_GRX_P13
4 PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_P15
PEG_HTX_C_GRX_N15

Friday, October 23, 2009

Sheet
E

22

of

60

U35D
Part 4 of 7

+3VS_DELAY

AP13
AN13
AN8
AP8
AP10
AN10
AR11
AR10
AN11
AP11

IFPB_TXC
IFPB_TXC_N
IFPB_TXD4
IFPB_TXD4_N
IFPB_TXD5
IFPB_TXD5_N
IFPB_TXD6
IFPB_TXD6_N
IFPB_TXD7
IFPB_TXD7_N

AM7
AM6
AL5
AM5
AM3
AM4
AP1
AR2

30 VGA_HDMI_TXD2+
30 VGA_HDMI_TXD230 VGA_HDMI_TXD1+
30 VGA_HDMI_TXD130 VGA_HDMI_TXD0+
30 VGA_HDMI_TXD030 VGA_HDMI_TXC+
30 VGA_HDMI_TXC-

R475
4.7K_0402_5%
DIS@

IFPA_TXC
IFPA_TXC_N
IFPA_TXD0
IFPA_TXD0_N
IFPA_TXD1
IFPA_TXD1_N
IFPA_TXD2
IFPA_TXD2_N
IFPA_TXD3
IFPA_TXD3_N

AR8
AR7
AP7
AN7
AN5
AP5
AR5
AR4

IFPD_L0
IFPD_L0_N
IFPD_L1
IFPD_L1_N
IFPD_L2
IFPD_L2_N
IFPD_L3
IFPD_L3_N

AH6
AH5
AH4
AG4
AF4
AF5
AE6
AE5

IFPE_L0
IFPE_L0_N
IFPE_L1
IFPE_L1_N
IFPE_L2
IFPE_L2_N
IFPE_L3
IFPE_L3_N

AL2
AL3
R476
AJ3
4.7K_0402_5% AJ2
DIS@
AJ1
AH1
AH2
AH3

30 VGA_HDMI_SCLK
30 VGA_HDMI_SDATA
B

IFPC_L0
IFPC_L0_N
IFPC_L1
IFPC_L1_N
IFPC_L2
IFPC_L2_N
IFPC_L3
IFPC_L3_N

NC
NC
NC
NC
NC
NC
NC
NC

AP2
AN3

IFPC_AUX_I2CW_SCL
IFPC_AUX_I2CW_SDA_N

AP4
AN4

IFPD_AUX_I2CX_SCL
IFPD_AUX_I2CX_SDA_N

AE4
AD4

IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N

AF3
AF2

NC
NC

A7
B7
C7
D6
D7

DBG_DATA0
DBG_DATA1
DBG_DATA2
DBG_DATA3
DBG_DATA4

A4

BUFRST_N

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

NC

AM11
AM12
AM8
AL8
AM10
AM9
AK10
AL10
AK11
AL11

LVDS/TMDS

28 VGA_TXCLK+
28 VGA_TXCLK28 VGA_TXOUT0+
28 VGA_TXOUT028 VGA_TXOUT1+
28 VGA_TXOUT128 VGA_TXOUT2+
28 VGA_TXOUT2-

STRAP0
STRAP1
STRAP2

W5
W7
V7

Straps

MULTI LEVEL STRAPS

STRAP0
STRAP1
STRAP2
ROM_SI
ROM_SO
ROM_SCLK

+3VS_DELAY

@
1
2
R493 5.1K_0402_5%

1 DIS@
2
R481 45.3K_0402_1%

@
1
2
R492 10K_0402_1%

R480

1
R491

DIS@

2
30K_0402_5%

1 X76@ 2
R79
20K_0402_5%

VDD_SENSE_0
VDD_SENSE_1
VDD_SENSE_2

D35
P7
AD20

GND_SENSE_0
GND_SENSE_1
GND_SENSE_2

AD19
E35
R7

R461 1 DIS@
R68 1 DIS@
R462 1 DIS@

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

R80

1 DIS@
2
10K_0402_1%

R81

@
1
2
5.1K_0402_5%

1
R479

strap0

strap1
34.8K_0402_1%

2
30K_0402_5%

strap2

@
1
2
5.1K_0402_5%

ROM_SI

R88

@
1
2
5.1K_0402_5%

ROM_SO

R89

R90

DIS@
15K_0402_5%

ROM_SCLK

R56 1 DIS@
R443 1 DIS@
R69 1 DIS@

+NVVDD_SENSE 52

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

strap0

TEST
TESTMODE
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N

DBG

DIS@ 1 R431
2
10K_0402_5%

AP35
AP14
AN14
AN16
AR14
AP16

SERIAL
ROM_CS_N
ROM_SI
ROM_SO
ROM_SCLK

C3
D3
C4
D4

NC

A5

MULTI_STRAP_REF0_GND

N9

MULTI_STRAP_REF1_GND

M9

THERMDP
THERMDN

B5
B4

NC
STRAP0
STRAP1
STRAP2

ES: pop R479 30K ohm


GS: pop R491 30K ohm
MP ID check R491 and R479

GENERAL
AB5

A2
C5
D5
E5
E7
F4
G5
G11
G12
G14
G15
G27
G28
G24
G25
H32
J18
J19
J25
J26
L29
M7
M29
P6
P29
R29
U7
V6
Y4
AA4
AB4
AB7
AC5
AD6
AD29
AE29
AF6
AG6
AG20
AG29
AH29
AJ5
AK15
AL7

ROM_CS#
ROM_SI
ROM_SO
ROM_SCLK

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST

PAD
PAD
PAD
PAD
PAD

T11
T12
T9
T10
T8

strap1

strap2

ROM_SI

64MX16
Samsung
SA000035700

H
45K

H
35K

L
30K

L
20K

ROM_SO
L
10K

ROM_SCLK
H
15K

64MX16
Hynix
SA000032400

H
45K

H
35K

L
30K

L
15K

L
10K

H
15K

@
@
@
@
@

2 R460
1
10K_0402_5%
DIS@
R468
10K_0402_5%1
2 @
+3VS_DELAY

DIS@ R65
2
1
40.2K_0402_1%
2
1
40.2K_0402_1%
DIS@ R66

N11M-GE1-B-A2_BGA969

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/5/12

Issued Date

Deciphered Date

2010/04/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

N11M LVDS 2/6


Size
Document Number
Custom

Rev

NALG0 M/B LA-5681P Schematic

Date:

Friday, October 23, 2009

Sheet
1

23

of

60

U35E
Part 5 of 7

IFPC_PLLVDD
1 R473 IFPD_RSET

DIS@

AC6
AB6

IFPD_PLLVDD
IFPD_RSET

AK8

IFPD_IOVDD

IFPB_IOVDD
IFPC_IOVDD
1K_0402_5% 1 DIS@
1K_0402_1% 2 DIS@

2 R495
IFPE_RSET
1 R78
1 R482
2 DIS@
1K_0402_5%

IFPEF_PLLVDD
IFPEF_RSET

AE7

IFPE_IOVDD

C156
DIS@

470P_0402_50V7K

DIS@

0.1U_0402_16V4Z

1 C155

P9
R9
T9
U9

MIOB_VDDQ_0
MIOB_VDDQ_1
MIOB_VDDQ_2
MIOB_VDDQ_3

NC

1
C95
DIS@

C140
DIS@

1U_0402_6.3V6K

0.01U_0402_25V7K

C120
DIS@

C125
DIS@

1
C90
DIS@

1
C80
DIS@

1
C107
DIS@

1
C113
DIS@

1
C122
DIS@

1
C82
DIS@

1
C98
DIS@

1
C84
DIS@

1
C109
DIS@

1
C136
DIS@

1
C65
DIS@

1
C85
DIS@

1
C128
DIS@

1
C117
DIS@

2
39,43,52 VGA_ON

C720
0.1U_0603_25V7K

2
DIS@

2N7002DW-T/R7_SOT363-6
Q66B

Q66A

R743
470_0603_5%
DIS@

3 1

1
2
R745 DIS@ 1K_0402_5%
R678
DIS@
1K_0402_5%
2
1

C717
DIS@
10U_0805_10V4Z
2

DIS@
2N7002DW-T/R7_SOT363-6

53VSdelay_gate
C719
0.1U_0603_25V7K
DIS@

DIS@

0.1U_0402_16V4Z

C78
DIS@

0.47U_0402_6.3V6K

100mil(1.5A)
1

C488

1
DIS@
C483

1
C710 +
@
330U_X_2VM_R6M
2

2 0_0805_5%

AO3413_SOT23-3
Q10
3
1 DIS@

R673
100K_0402_5%

DIS@

470P_0402_50V7K

IFPC_IOVDD

0.47U_0402_6.3V6K

4.7U_0603_6.3V6M

1U_0603_10V4Z

0.1U_0402_16V4Z

4.7U_0603_6.3V6M

DIS@

+3VS_DELAY

0.47U_0402_6.3V6K

R744 1 @

1U_0603_10V4Z

0.47U_0402_6.3V6K

10U_0805_6.3V6M

0.1U_0402_16V4Z

1 +3VS_DELAY

0_0603_5%
DIS@

DIS@

22U_0805_6.3V6M

DIS@
10U_0805_10V4Z
2

385 mA
4700P_0402_25V7K

DIS@

C486

BLM18PG181SN1D_0603
2
1
L36 DIS@
1
4.7U_0603_6.3V6M

1U_0402_6.3V6K

22U_0805_6.3V6M

+3VS_DELAY
C718

+1.05VSDGPU

22U_0805_6.3V6M

3VSdelay_gate

C83

C175

+3VS

470P_0402_50V7K

C163
DIS@

4700P_0402_25V7K

4.7U_0603_6.3V6M

C491

C166

C111
DIS@

R91

C176
DIS@
2

+VGA_CORE
DIS@
C157

DIS@

C99
DIS@

120mA

C489
DIS@

160 mA

U35G

C127
DIS@

C119

1
L37 DIS@
BLM18PG181SN1D_0603

+1.8VS

+1.05VSDGPU

+3VS_DELAY

+3VALW

+1.05VSDGPU

C485
DIS@

IFPC_PLLVDD

C142
DIS@

+VGA_CORE

AA9
AB9
W9
Y9

DIS@

DIS@

1U_0402_6.3V6K

DIS@

VDD33

N11M-GE1-B-A2_BGA969

1
L3

C148
DIS@

+VGA_CORE

BLM18PG181SN1D_0603

C70
DIS@

1.920 Amps

VDD33

J10
J11
J12
J13
J9

+3VS_DELAY

+3VS_DELAY

C484
DIS@

0.01U_0402_25V7K

PEX_SVDD_3V3

AG19
F7

C167
DIS@

follow the DS04644

4.7U_0603_6.3V6M

1U_0603_10V4Z

0.1U_0402_16V4Z
0.1U_0402_16V4Z

PEX_PLLDVDD

PWR Sequence
B

+VGA_CORE

AJ6
AL1

AD7

AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB25
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AD12
AD14
AD16
AD18
AD22
AD24
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
M12
M14
M16
M18
M20
M22
M24
P11
P13
P15
P17
P19

VDD_0
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55

Part 7 of 7

POWER

DIS@

0.1U_0402_16V4Z

C150

DIS@

1U_0402_6.3V6K

4.7U_0603_6.3V6M

C168
DIS@

1 C162

NC
NC
NC
NC

C493
DIS@

0.1U_0402_16V4Z

IFPA_IOVDD
1K_0402_1% 2

IFPC_IOVDD

C89
DIS@

0.47U_0402_6.3V6K

2
1
L4 DIS@
BLM18PG181SN1D_0603

AJ8

0.1U_0402_16V4Z

100 mA #SI Change to +VDDMEM18

IFPC_PLLVDD
IFPC_RSET

0.47U_0402_6.3V6K

+1.8VSDGPU

AJ9
AK7

VDD33_0
VDD33_1
VDD33_2
VDD33_3
VDD33_4

1U_0603_10V4Z

IFPC_PLLVDD
2
1 IFPC_RSET
DIS@ R467 1K_0402_1%
IFPC_IOVDD

IFPA_IOVDD
IFPB_IOVDD

C132
DIS@

0.1U_0402_16V4Z

AG9
AG10

C158
DIS@

0.47U_0402_6.3V6K

IFPA_IOVDD
IFPB_IOVDD

PEX_SVDD_3V3_0
PEX_SVDD_3V3_1

PEX_PLLDVDD

PEX_SVDD_3V3

IFPAB_PLLVDD
IFPAB_RSET

0.1U_0402_16V4Z

IFPAB_PLLVDD
AK9
IFPAB_RSET AJ11
1

C93
DIS@

0.1U_0402_16V4Z

1K_0402_1% 2
R488 @

C459
DIS@

0.47U_0402_6.3V6K

AG14

0.1U_0402_16V4Z

1 C445

PEX_PLLVDD

600 mA

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1 C444

IFPAB_PLLVDD

C115
DIS@

0.1U_0402_16V4Z

follow the DS04644

AK16
AK17
AK21
AK24
AK27

PEX_IOVDD

PEX_IOVDD

PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4

+1.05VSDGPU

PEX_IOVDDQ

0.47U_0402_6.3V6K

DIS@

C64

FBVDDQ

PEX_IOVDDQ

AG11
AG12
AG13
AG15
AG16
AG17
AG18
AG22
AG23
AG24
AG25
AG26
AJ14
AJ15
AJ19
AJ21
AJ22
AJ24
AJ25
AJ27
AK18
AK20
AK23
AK26
AL16

0.1U_0402_16V4Z

DIS@

C66

DIS@

PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8
PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13
PEX_IOVDDQ_14
PEX_IOVDDQ_15
PEX_IOVDDQ_16
PEX_IOVDDQ_17
PEX_IOVDDQ_18
PEX_IOVDDQ_19
PEX_IOVDDQ_20
PEX_IOVDDQ_21
PEX_IOVDDQ_22
PEX_IOVDDQ_23
PEX_IOVDDQ_24

0.47U_0402_6.3V6K

C69

DIS@

C75

0.022U_0402_16V7K

C114

DIS@

C77
DIS@
C108

4700P_0402_25V7K

DIS@

FBVDDQ

4700P_0402_25V7K

DIS@

0.022U_0402_16V7K

DIS@

C100
DIS@
C144

4700P_0402_25V7K

DIS@

4700P_0402_25V7K

C68

0.022U_0402_16V7K

DIS@

C87
DIS@

1
C446
DIS@

4700P_0402_25V7K

C436

100mA

4.7U_0603_6.3V6M

BLM18PG181SN1D_0603
1
L35
DIS@

4.7U_0603_6.3V6M

1
C453
DIS@

1U_0402_6.3V6K

DIS@

C55

+1.05VSDGPU

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DIS@

C103

C71
DIS@

0.022U_0402_16V7K

DIS@

C58
DIS@

4.7U_0603_6.3V6M

C88

1U_0402_6.3V6K

0.1U_0402_16V4Z

0.022U_0402_16V7K

1U_0402_6.3V6K

DIS@

0.1U_0402_16V4Z

C76

DIS@

4.7U_0603_6.3V6M

FBVDDQ

FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37

0.1U_0402_16V4Z

J23
J24
J29
AA27
AA29
AA31
AB27
AB29
AC27
AD27
AE27
AJ28
B18
E21
G17
G18
G22
G8
G9
H29
J14
J15
J16
J17
J20
J21
J22
N27
P27
R27
T27
U27
U29
V27
V29
V34
W27
Y27

+1.5VSDGPU

POWER

FBVDDQ

VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
VDD_72
VDD_73
VDD_74
VDD_75
VDD_76
VDD_77
VDD_78
VDD_79
VDD_80
VDD_81
VDD_82
VDD_83
VDD_84
VDD_85
VDD_86
VDD_87
VDD_88
VDD_89
VDD_90
VDD_91
VDD_92
VDD_93
VDD_94
VDD_95
VDD_96
VDD_97
VDD_98
VDD_99
VDD_100
VDD_101
VDD_102
VDD_103
VDD_104
VDD_105
VDD_106
VDD_107
VDD_108
VDD_109
VDD_110

P21
P23
P25
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
T12
T14
T16
T18
T20
T22
T24
V11
V13
V15
V17
V19
V21
V23
V25
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
W21
W22
W23
W24
W25
Y12
Y14
Y16
Y18
Y20
Y22
Y24

2
N11M-GE1-B-A2_BGA969

Compal Secret Data

Security Classification
Issued Date

2009/5/12

Deciphered Date

2009/12/31

Title

Compal Electronics, Inc.


N11M POWER & GND 3/6

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rev
1.0

NALG0 M/B LA-5681P Schematic

Date:

Friday, October 23, 2009

Sheet
1

24

of

60

26

MDA[31..16]

27

MDA[47..32]

27

MDA[63..48]

U35C

MDA[15..0]

MDA[31..16]
MDA[47..32]
MDA[63..48]

U35B

CMDA[30..0]
Part 2 of 7

FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

AG27
AF27

FB_DLLAVDD
FB_PLLAVDD

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30

V32
W31
U31
Y32
AB35
AB34
W35
W33
W30
T34
T35
AB31
Y30
Y34
W32
AA30
AA32
Y33
U32
Y31
U34
Y35
W34
V30
U35
U30
U33
AB30
AB33
T33
W29

CMDA0
CMDA1
CMDA2
CMDA3
CMDA4
CMDA5
CMDA6
CMDA7
CMDA8
CMDA9
CMDA10
CMDA11
CMDA12
CMDA13
CMDA14
CMDA15
CMDA16
CMDA17
CMDA18
CMDA19
CMDA20
CMDA21
CMDA22
CMDA23
CMDA24
CMDA25
CMDA26
CMDA27
CMDA28
CMDA29
CMDA30

FBA_DQM0
FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4
FBA_DQM5
FBA_DQM6
FBA_DQM7

P32
H34
J30
P30
AF32
AL32
AL34
AF35

DQMA0
DQMA1
DQMA2
DQMA3
DQMA4
DQMA5
DQMA6
DQMA7

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

L35
G35
H31
N32
AD32
AJ31
AJ35
AC34

DQSA#0
DQSA#1
DQSA#2
DQSA#3
DQSA#4
DQSA#5
DQSA#6
DQSA#7

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

L34
H35
J32
N31
AE31
AJ32
AJ34
AC33

DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7

MEMORY INTERFACE
A

L32
N33
L33
N34
N35
P35
P33
P34
K35
K33
K34
H33
G34
G33
E34
E33
G31
F30
G30
G32
K30
K32
H30
K31
L31
L30
M32
N30
M30
P31
R32
R30
AG30
AG32
AH31
AF31
AF30
AE30
AC32
AD30
AN33
AL31
AM33
AL33
AK30
AK32
AJ30
AH30
AH33
AH35
AH34
AH32
AJ33
AL35
AM34
AM35
AF33
AE32
AF34
AE35
AE34
AE33
AB32
AC35

26,27

DQMA[3..0] 26

DQMA[7..4] 27

DQSA#[3..0]

26

DQSA#[7..4]

27

DQSA[3..0]

26

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

K27

FBCAL_PD_VDDQ

40.2_0402_1%2

DIS@ 1 R41

L27

FBCAL_PU_GND

DIS@ 1 R40

M27

FBCAL_TERM_GND

+1.5VSDGPU

DQSA[7..4]

40.2_0402_1%
2 DIS@
1 R42

B13
D13
A13
A14
C16
B16
A17
D16
C13
B11
C11
A11
C10
C8
B8
A8
E8
F8
F10
F9
F12
D8
D11
E11
D12
E13
F13
F14
F15
E16
F16
F17
D29
F27
F28
E28
D26
F25
D24
E25
E32
F32
D33
E31
C33
F29
D30
E29
B29
C31
C29
B31
C32
B32
B35
B34
A29
B28
A28
C28
C26
D25
B25
A25

27

60.4_0402_1%

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

C17
B19
D18
F21
A23
D21
B23
E20
G21
F20
F19
F23
A22
C22
B17
F24
C25
E22
C20
B22
A19
D22
D20
E19
D19
F18
C19
F22
C23
B20
A20

NC
NC
NC
NC
NC
NC
NC
NC

A16
D10
F11
D15
D27
D34
A34
D28

NC
NC
NC
NC
NC
NC
NC
NC

B14
B10
D9
E14
F26
D31
A31
A26

NC
NC
NC
NC
NC
NC
NC
NC

C14
A10
E10
D14
E26
D32
A32
B26

NC
NC

E17
D17

NC
NC

D23
E23

NC

G19

B3
B6
B9
B12
B15
B21
B24
B27
B30
B33
C2
C34
E6
E9
E12
E15
E18
E24
E27
E30
F2
F31
F34
F5
J2
J5
J31
J34
K9
L9
M2
M5
M11
M13
M15
M17
M19
M21
M23
M25
M31
M34
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
P12
P14
P16
P18
P20
P22
P24
R2
R5
R31
R34
T11
T13
T15
T17
T19
T21
T23
T25
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
U21
U22
U23
U24
U25
V2
V5
V9
V12
V14
V16

N11M-GE1-B-A2_BGA969
FB_PLLAVDD

FB_VREF
J27
+1.5VSDGPU
2
1
T30
R35 10K_0402_5% @

FBA_CLK0
FBA_CLK0_N

T32
T31

CLKA0
CLKA0#

26
26

FBA_CLK1
FBA_CLK1_N

AC31
AC30

CLKA1
CLKA1#

27
27

FB_VREF
FBA_DEBUG

N11M-GE1-B-A2_BGA969

1
R47
@
1K_0402_1%

GND_0
GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96

Rt

Part 6 of 7

GND_97
GND_98
GND_99
GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191
GND_192

V18
V20
V22
V24
V31
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y25
AA2
AA5
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA34
AB12
AB14
AB16
AB18
AB20
AB22
AB24
AC9
AD2
AD5
AD11
AD13
AD15
AD17
AD21
AD23
AD25
AD31
AD34
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AG2
AG5
AG31
AG34
AK2
AK5
AK14
AK31
AK34
AL6
AL9
AL12
AL15
AL18
AL21
AL24
AL27
AL30
AN2
AN34
AP3
AP6
AP9
AP12
AP15
AP18
AP21
AP24
AP27
AP30
AP33

FB_VREF
N11M-GE1-B-A2_BGA969

1
R45
@
1K_0402_1%

Rb

0.1U_0402_16V4Z

C147

C72

+1.5VSDGPU

1
+1.05VSDGPU
L2 DIS@
BLM18PG181SN1D_0603

DIS@

DIS@

C138
DIS@

4.7U_0603_6.3V6M

1U_0402_6.3V6K

DIS@
C73
0.01U_0402_25V7K

2
1

FB_PLLAVDD
0.1U_0402_16V4Z

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43
MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

U35F
Part 3 of 7

MEMORY INTERFACE C

MDA[15..0]

GND

VRAM Interface
26

C74
@

Compal Secret Data

Security Classification
2009/5/12

Issued Date

Deciphered Date

2009/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.


N11M VRAM 4/6

Size
Document Number
Custom NALG0 M/B LA-5681P
Date:

Friday, October 23, 2009

Rev
1.0

Schematic
Sheet

25

of

60

VRAM gDDR3 chips (256MB & 512MB)


32Mx16 gDDR2 *4==>256MB
64Mx16 gDDR3 *4==>512MB
+1.5VSDGPU

+1.5VSDGPU

Address

DQSA[7..0]

DQMA[7..0]

R401
1K_0402_1%

CMDA[30..0]

K1
L2
J3
K3
L3

ODT/ODT0
CS/CS0
RAS
CAS
WE

A1
A8
C1
C9
D2
E9
F1
H2
H9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

DQSA3
DQSA1

F3
C7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ

DQMA3
DQMA1

E7
D3

DML
DMU

DQSA#3
DQSA#1

G3
B7

DQSL
DQSU

RESET

L8

ZQ/ZQ0

243_0402_1%

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

T2

+1.5VSDGPU
DIS@

25

CMDA7
CMDA18
CMDA28
CMDA30
CMDA15

C25
DIS@

1
C408
DIS@

1
C409
DIS@

1
C404
DIS@

1
C405
DIS@

1
C406
DIS@

0.1U_0402_16V4Z

C23
DIS@

0.1U_0402_16V4Z

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

C18
DIS@
0.1U_0402_16V4Z

C22
DIS@

2
2
2
2
2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B1
B9
D1
D8
E2
E8
F9
G1
G9

K1
L2
J3
K3
L3

DQSA0
DQSA2

F3
C7

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
DQSL
VDDQ
DQSU
VDDQ

DQMA0
DQMA2

E7
D3

DML
DMU

DQSA#0
DQSA#2

G3
B7

DQSL
DQSU

ODT/ODT0
CS/CS0
RAS
CAS
WE

CMDA15

T2

RESET

ZQ1

L8

ZQ/ZQ0

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

DIS@

CMD3

BA1

RAS#
D

BA1

CMD4

A2

CMD5

A4

CMD6

A3

CMD7

CKE
CS#

CMD9

A11

A11

CMD10

CAS#

CAS#

CMD11

WE#

WE#

CMD12

BA0

BA0

CMD14

A12

A12

CMD15

RST

RST

CMD16

A7

A7

CMD17

A10

A10

CMD13

+1.5VSDGPU

A5

CMD18

CKE

CMD19

A0

A0

CMD20

A9

A9

CMD21

A6

A6

CMD22

A2

CMD23

A8

CMD24

A3

CMD25

A1

A1

CMD26

A13

A13

CMD27

BA2

BA2

A8

ODT

CMD28
CMD29

CS#

CMD30

ODT
LOW

1
C19
DIS@

1
C35
DIS@

1
C20
DIS@

1
C17
DIS@

1
C15
DIS@

1
C399
DIS@

1
C398
DIS@

1
C400
DIS@

HIGH

2009/5/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2010/04/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

A5

+1.5VSDGPU

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C21
DIS@

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1000P_0402_50V7K

1
1
1 DIS@
1 DIS@
1 DIS@
DIS@
DIS@

A1
A8
C1
C9
D2
E9
F1
H2
H9

CMDA30
CMDA29
CMDA1
CMDA10
CMDA11

CK
CK
CKE/CKE0

RAS#

CMD2

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

C26
DIS@

R18
R27
R25
R19
R21

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

+1.5VSDGPU

CLKA0#

B2
D9
G7
K2
K8
N1
N9
R1
R9

J7
K7
K9

R399
240_0402_1%

CLKA0#

0.1U_0402_16V4Z

R13
DIS@

CLKA0

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

BA0
BA1
BA2

CMD1

4.7U_0603_6.3V6M

CMDA30
CMDA29
CMDA1
CMDA10
CMDA11

25

D7
C3
C8
C2
A7
A2
B8
A3

MDA20
MDA17
MDA23
MDA19
MDA22
MDA18
MDA21
MDA16

A4

CMD8

4.7U_0603_6.3V6M

CK
CK
CKE/CKE0

MDA3
MDA7
MDA0
MDA5
MDA2
MDA6
MDA1
MDA4

4.7U_0603_6.3V6M

J7
K7
K9

CLKA0

E3
F7
F2
F8
H3
H8
G2
H7

+1.5VSDGPU

4.7U_0603_6.3V6M

B2
D9
G7
K2
K8
N1
N9
R1
R9

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

CLKA0
CLKA0#
CMDA18

R12

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M2
N8
M3

CLKA0
CLKA0#
CMDA18

ZQ0

CMDA12
CMDA3
CMDA27

+1.5VSDGPU

BA0
BA1
BA2

CMDA15

MDA15
MDA9
MDA13
MDA11
MDA12
MDA10
MDA14
MDA8

D7
C3
C8
C2
A7
A2
B8
A3

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

4.7U_0603_6.3V6M

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VREFCA
VREFDQ

4.7U_0603_6.3V6M

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

M8
H1

243_0402_1%

M2
N8
M3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

X76@

CMDA12
CMDA3
CMDA27

VREFCA
VREFDQ

0.1U_0402_16V4Z

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

MDA27
MDA26
MDA29
MDA25
MDA30
MDA28
MDA31
MDA24

MEM_VREF1
1

DIS@
R9
C24
1K_0402_1% DIS@

4.7U_0603_6.3V6M

CMDA19
CMDA25
CMDA22
CMDA24
CMDA0
CMDA2
CMDA21
CMDA16
CMDA23
CMDA20
CMDA17
CMDA9
CMDA14
CMDA26

X76@

MEM_VREF0
1

CMDA19
CMDA25
CMDA22
CMDA24
CMDA0
CMDA2
CMDA21
CMDA16
CMDA23
CMDA20
CMDA17
CMDA9
CMDA14
CMDA26

0.1U_0402_10V6K~D

U32
MEM_VREF0 M8
H1

DIS@
R397
C407
1K_0402_1% DIS@

0.1U_0402_10V6K~D

25,27 CMDA[30..0]

MEM_VREF1

4.7U_0603_6.3V6M

25,27 MDA[63..0]

MDA[63..0]

R16
1K_0402_1% DIS@

DIS@

4.7U_0603_6.3V6M

25,27 DQMA[7..0]

25,27 DQSA#[7..0]

U2

DQSA#[7..0]

25,27 DQSA[7..0]

32..63

0..31

CMD0

Title

N11M gDDR3 5/6


Size
Document Number
Custom

Rev

NALG0 M/B LA-5681P Schematic

Date:

Friday, October 23, 2009

Sheet
1

26

of

60

VRAM DDR3 chips (256MB & 512MB)


Address

MDA[63..0]

CMDA12
CMDA3
CMDA27

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

M2
N8
M3

CLKA1
CLKA1#
CMDA7

J7
K7
K9

CMDA28
CMDA8
CMDA1
CMDA10
CMDA11

K1
L2
J3
K3
L3

DQSA7
DQSA4

F3
C7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

E3
F7
F2
F8
H3
H8
G2
H7

MDA57
MDA63
MDA61
MDA58
MDA56
MDA60
MDA62
MDA59

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

MDA35
MDA39
MDA32
MDA36
MDA33
MDA38
MDA34
MDA37

CMDA12
CMDA3
CMDA27

M2
N8
M3

BA0
BA1
BA2

CLKA1
CLKA1#
CMDA7

J7
K7
K9

CK
CK
CKE/CKE0

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ

CMDA28
CMDA8
CMDA1
CMDA10
CMDA11

B2
D9
G7
K2
K8
N1
N9
R1
R9

25

CLKA1

CLKA1

A1
A8
C1
C9
D2
E9
F1
H2
H9

DIS@

R14
240_0402_1%

RESET

ZQ2

L8

ZQ/ZQ0

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

243_0402_1%

R17

DML
DMU

DQSA#5
DQSA#6

G3
B7

DQSL
DQSU

CLKA1#

DIS@

RESET

L8

ZQ/ZQ0

J1
L1
J9
L9

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

DIS@

0.1U_0402_16V7K

C415

DIS@

0.1U_0402_16V7K

C410

DIS@

0.1U_0402_16V7K

DIS@

C413

0.1U_0402_16V7K

DIS@

1
C403
DIS@

BA1

+1.5VSDGPU

BA1

CMD4

A2

CMD5

A4

CMD6

A3

CMD7

CKE
CS#

CMD9

A11

A11

CMD10

CAS#

CAS#

CMD11

WE#

WE#

CMD12

BA0

BA0

CMD14

A12

A12

CMD15

RST

RST

CMD16

A7

A7

CMD17

A10

A10

CMD18

CKE

CMD19

A0

A0

CMD20

A9

A9

CMD21

A6

A6

CMD22

A2

CMD23

A8

CMD24

A3

CMD25

A1

A1

CMD26

A13

A13

CMD27

BA2

BA2

A5

A8

CMD28

ODT

CMD29

CS#

CMD30

ODT
LOW

HIGH

1
C402
DIS@

1
C39
DIS@

1
C401
DIS@

1
C36
DIS@

1
C397
DIS@

1
C416
DIS@

1
C16
DIS@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/5/12

Deciphered Date

2010/04/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Issued Date

CMD3

RAS#

+1.5VSDGPU

C414

DIS@

T2

A5

32..63

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

0.1U_0402_16V7K

B1
B9
D1
D8
E2
E8
F9
G1
G9

E7
D3

CLKA1#

C417
DIS@

C27

DIS@

0.1U_0402_16V7K

C28

DIS@

1U_0402_6.3V6K

C29

DIS@

1U_0402_6.3V6K

C411

1U_0402_6.3V6K

DIS@

C31

1U_0402_6.3V6K

C32

B1
B9
D1
D8
E2
E8
F9
G1
G9

25

96-BALL
SDRAM DDR3
K4B1G1646E-HC12_FBGA96

+1.5VSDGPU

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

ODT/ODT0
CS/CS0
RAS
CAS
WE

T2

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMA5
DQMA6

4.7U_0603_6.3V6M

CMDA15

DQSL
DQSU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

F3
C7

R400

G3
B7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

A1
A8
C1
C9
D2
E9
F1
H2
H9

DQSA5
DQSA6

243_0402_1%

DQSA#7
DQSA#4

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

K1
L2
J3
K3
L3

RAS#

CMD2

CMD13

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CMD1

CMD8

+1.5VSDGPU

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
310mAVDDQ
VDDQ
DQSL
VDDQ
DQSU
VDDQ

CMDA15

4.7U_0603_6.3V6M

DML
DMU

DIS@

MDA51
MDA53
MDA48
MDA54
MDA49
MDA55
MDA50
MDA52

+1.5VSDGPU

4.7U_0603_6.3V6M

E7
D3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

D7
C3
C8
C2
A7
A2
B8
A3

A4

+1.5VSDGPU

ZQ3
DQMA7
DQMA4

E3
F7
F2
F8
H3
H8
G2
H7

0..31

CMD0

4.7U_0603_6.3V6M

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

4.7U_0603_6.3V6M

CMDA19
CMDA25
CMDA4
CMDA6
CMDA5
CMDA13
CMDA21
CMDA16
CMDA23
CMDA20
CMDA17
CMDA9
CMDA14
CMDA26

M8
H1

VREFCA
VREFDQ

4.7U_0603_6.3V6M

MEM_VREF2

X76@

MEM_VREF3
1

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

MDA40
MDA41
MDA43
MDA44
MDA45
MDA47
MDA42
MDA46

4.7U_0603_6.3V6M

U5

DIS@
R398
C412
1K_0402_1% DIS@

M8
H1

CMDA19
CMDA25
CMDA4
CMDA6
CMDA5
CMDA13
CMDA21
CMDA16
CMDA23
CMDA20
CMDA17
CMDA9
CMDA14
CMDA26

X76@

4.7U_0603_6.3V6M

25,26 MDA[63..0]

MEM_VREF2
1

MEM_VREF3

4.7U_0603_6.3V6M

25,26 DQSA[7..0]

DIS@
R10
C30
1K_0402_1% DIS@

0.1U_0402_10V6K~D

DQSA[7..0]

0.1U_0402_10V6K~D

DQSA#[7..0]

25,26 DQSA#[7..0]

1
2

CMDA[30..0]

25,26 CMDA[30..0]

U31

R402
1K_0402_1% DIS@

25,26 DQMA[7..0]

+1.5VSDGPU

R15
1K_0402_1% DIS@

DQMA[7..0]

+1.5VSDGPU

32Mx16 DDR3 *4==>256MB


64Mx16 DDR3 *4==>512MB

Title

N11M gDDR3 6/6


Size
Document Number
Custom

Rev
1.0

NALG0 M/B LA-5681P Schematic

Date:

Friday, October 23, 2009

Sheet
1

27

of

60

5
P
3

5
P

C4

U44

INVTPWM

37

R513
R505
0_0402_5%
2.2K_0402_5%
1 @
2
@
R521
PWM_R 2
SG@
1
2
INVT_PWM
DPST_PWM_1
0_0402_5%
5
PWMSEL_1#
1
16 PWMSEL_1#
IGPU_PWM_SELECT#
7
16 IGPU_PWM_SELECT#

22 VGA_PNL_PWM

1A
2A
1OE#
2OE#

VCC
1B
2B
GND

R516

5
P

DPST_PWM_1

U45
Y

INVTPWM

VGA_PNL_PWM 0_0402_5% 2

74AHCT1G125GW_SOT353-5

LED PANEL Conn.

@ 1

R533

INVT_PWM 0_0402_5% 2 DIS only@


1

R523

INVTPWM

Reserved for DIS Only


+3VS

JLVDS1

2009/04/14 UPDATE
16

Reserved for UMA Only


Y

DPST_PWM_1

W=60mils

U38
NC7SZ14P5X_NL_SC70-5
UMA@
2
DPST_PWM

+3VS

PCH_LCD_CLK
PCH_LCD_DATA

2 4.7K_0402_5%
2 4.7K_0402_5%

+LCDVDD

TXOUT1TXOUT1+

IGPU_EDIDSEL#

1
R543

R99
4.7K_0402_5%

2
0_0402_5%

TXOUT2+
TXOUT2-

INVTPWM
1 UMA only@
2
R542
0_0402_5%

+3VS

TXOUT0TXOUT0+

SG For LVDS

SEL=LOW, B1
SEL=High, B2

R82
0_0603_5%
SG@

CONN@

+3VS

IGPU_EDIDSEL#

37

BKOFF#

BKOFF#

R2
R5

1
1

C369
68P_0402_50V8J

VGA_LCD_CLK

22 VGA_LCD_CLK

1
D

R374
@
4.7K_0402_5%

D1
CH751H-40PT_SOD323-2
@
1
2

I2CC_SCL

Q19
2N7002_SOT23
SG@

DISPOFF#

VGA_TXOUT0-48
VGA_TXOUT0+47
VGA_TXOUT1-43
VGA_TXOUT1+42
VGA_TXOUT2-37
VGA_TXOUT2+36
VGA_TXCLK- 32
VGA_TXCLK+ 31
2 0_0402_5%
22
2 0_0402_5%
23

23 VGA_TXOUT023 VGA_TXOUT0+
23 VGA_TXOUT123 VGA_TXOUT1+
23 VGA_TXOUT223 VGA_TXOUT2+
23 VGA_TXCLK23 VGA_TXCLK+
VGA_LCD_CLK
R486 1 @
VGA_LCD_DAT
R485 1 @

B+

L19 2
1
FBMA-L11-201209-221LMA30T_0805
C370
680P_0402_50V7K

SG@ U12

L20 2
1
FBMA-L11-201209-221LMA30T_0805

W=40mils

R102
4.7K_0402_5%
2

+INVPWR_B+

2 0_0402_5%
2 10K_0402_5%

VCC
VCC
VCC
VCC
VCC
VCC
VCC

0B1
1B1
2B1
3B1
4B1
5B1
6B1
7B1
8B1
9B1

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

+LCDVDD
+3VS

DISPOFF#

220P_0402_50V7K

C2

C3

DGPU_EDIDSEL_R#

2
220P_0402_50V7K

10U_0805_10V4Z

0.1U_0402_16V4Z

2
0.1U_0402_16V4Z

1 0_0404_4P2R_5%TXCLK+
TXCLK2

16 PCH_LCD_CLK

PCH_LCD_CLK

R501 1 UMA only@


2 0_0402_5%
R483 1 UMA only@
2 0_0402_5%

I2CC_SCL
I2CC_SDA

VGA_LCD_CLK
VGA_LCD_DAT

R502 1 DIS only@


2 0_0402_5%
R484 1 DIS only@
2 0_0402_5%

I2CC_SCL
I2CC_SDA

I2CC_SCL

57

0B2
1B2
2B2
3B2
4B2
5B2
6B2
7B2
8B2
9B2

SEL

NC
NC
NC
NC
Thermal_GND

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

+3VS_SWITCH
1
1
1

4
10
18
27
38
50
56

SG@SG@SG@
2
2
2

2
3
7
8
11
12
14
15
19
20

C182 C188 C177


TXOUT0TXOUT0+
TXOUT1TXOUT1+
TXOUT2TXOUT2+
TXCLKTXCLK+
I2CC_SCL
I2CC_SDA

17

DGPU_SELECT#

1
6
9
13
16
21
24
28
33
39
44
49
53
55
A

Q20
2N7002_SOT23
SG@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/5/12

2010/04/15

Deciphered Date

Title

LVDS Connector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

NALG0 M/B LA-5681P Schematic

Date:

TS3DV520ERHUR_WQFN56_11X5

Issued Date
PCH_LCD_CLK
PCH_LCD_DATA

@
@

52
5
54
51
D

PCH_TXCLK+
PCH_TXCLK-

TXOUT2+
1 0_0404_4P2R_5%
TXOUT22

TXOUT0+
3 DIS only@
TXOUT04
0_0404_4P2R_5%
TXOUT1+
DIS
only@
3
TXOUT14
0_0404_4P2R_5%
TXOUT2+
3 DIS only@
TXOUT24
0_0404_4P2R_5%
TXCLK+
3 DIS only@
TXCLK4
0_0404_4P2R_5%

PCH_TXOUT2+
PCH_TXOUT2-

TXOUT1+
1 0_0404_4P2R_5%
TXOUT12

I2CC_SDA

PCH_TXOUT1+
PCH_TXOUT1-

VGA_TXOUT0+
2
VGA_TXOUT01
RP1
VGA_TXOUT1+
2
VGA_TXOUT11
RP2
VGA_TXOUT2+
2
VGA_TXOUT21
RP3
VGA_TXCLK+
2
VGA_TXCLK1
RP4

PCH_TXOUT0-46
PCH_TXOUT0+45
PCH_TXOUT1-41
PCH_TXOUT1+40
PCH_TXOUT2-35
PCH_TXOUT2+34
PCH_TXCLK- 30
PCH_TXCLK+ 29
2 0_0402_5% 25
2 0_0402_5% 26

Q12
2N7002_SOT23
SG@
DGPU_EDIDSEL_R#

DIS ONLY

10_0404_4P2R_5% TXOUT0+
TXOUT02

4
RP13 3
UMA only@
4
RP14 3
UMA only@
4
RP15 3
UMA only@
4
RP16 3
UMA only@

UMA ONLY

PCH_LCD_DATA

16 PCH_LCD_DATA

PCH_TXOUT0+
PCH_TXOUT0-

16 PCH_TXOUT016 PCH_TXOUT0+
16 PCH_TXOUT116 PCH_TXOUT1+
16 PCH_TXOUT216 PCH_TXOUT2+
16 PCH_TXCLK16 PCH_TXCLK+
PCH_LCD_CLK R159 1
PCH_LCD_DATA R160 1

C377
G

1
C374
1
C373

INVTPWM

+3VS

0.1U_0402_16V4Z

Q11
2N7002_SOT23
SG@

+3VS

+3VS

I2CC_SDA

4.7U_0603_6.3V6K

VGA_LCD_DAT

22 VGA_LCD_DAT

TXCLKTXCLK+

0.1U_0402_16V4Z

LED PANEL PIN1&34 SHORT

17
17

DAC_BRIG 37

R500 1
R489 1

DAC_BRIG
INVTPWM
DISPOFF#

42 GND GND 41
40 40
+INVPWR_B+
39 39
38 38
37 37
36 36
+3VS
35 35
I2CC_SCL
34 34
33 33
I2CC_SDA
32 32
31 31
30 30
29 29
@
1
2
28 28
27 27
R370
0_0402_5%
26 26
25 25
24 24
23 23
22 22
21 21
20 20
19 19
18 18
17 17
16 16
15 15
14 14
13 13
12 12
11 11
10 10
9 9
8 8
7 7
R369 0_0402_5%
6
5
6
5
1
2 USB20_CMOS_N3 4 4
USB20_N3
3 3
USB20_CMOS_P3 2
1
2
USB20_P3
2
1 1
R368
0_0402_5%
ACES_88242-4001

NC

INVTPWM

10K_0402_5%<BOM Structure>

R1
100K_0402_5% DIS@

8
3
6
4

SN74CBTD3306CPWR_TSSOP8
SG@

IGPU_PWM_SELECT#

+5VS

+5VS C495
SG@
0.1U_0402_16V4Z
1
2

U15

0.1U_0402_16V4Z

1
3

+3VS

SG@

NC7SZ14P5X_NL_SC70-5
SG@

PWMSEL_1#

+5VS
5

74AHCT1G125GW_SOT353-5
Q3
2N7002_SOT23
DIS@
S

IGPU_EDIDSEL#

+LCDVDD

PWM_R

ENVDD

U37
NC7SZ14P5X_NL_SC70-5
IGPU_PWM_SELECT#
4

29 DGPU_EDIDSEL_R#

OE#

C1

U36
Y

W=60mils

4.7U_0805_10V4Z

2
G

R391
100K_0402_5%

22

R498

Q4
2N7002_SOT23
UMA@
S

2
0_0402_5%

OE#

1
1

2
G

16 PCH_ENVDD

0.047U_0402_16V7K

C381
D

Q2
AO3413_SOT23-3

18 DGPU_EDIDSEL#

SG@ 2 DGPU_EDIDSEL_R#2
0_0402_5%

3
G

2
G

R390
1K_0402_5%
2
1

D
Q1
2N7002_SOT23

4.7U_0805_10V4Z

DGPU_SELECT# 1
R490

17,29 DGPU_SELECT#

C7

NC

R393
100K_0402_5%

<BOM Structure>

17 DGPU_PWMSEL#

R504
0_0402_5%
@
1
2 PWMSEL_1#
SG@ 2
1
R503
0_0402_5%

1
R387

DGPU_SELECT#

NC

+3VS C494
SG@
0.1U_0402_16V4Z
1
2

W=60mils

+3VS

+3VALW

+3VS C496
SG@
0.1U_0402_16V4Z
1
2

LCD POWER CIRCUIT

+LCDVDD

300_0603_5%

Friday, October 23, 2009

Sheet
1

28

of

60

Rev
1.0

CRT Connector

D8

D7

W=40mils

D6

+5VS

+R_CRT_VCC

+CRT_VCC

D20

DAN217_SC59 DAN217_SC59 DAN217_SC59


F1

RB491D_SC59-3

C49
0.1U_0402_16V4Z

2
1.1A_6VDC_FUSE
1

Change to 0 ohm for Discrete


2

W=40mils

+3VS

CRT_R_1

CRT_G

1
L32

2
FCM2012CF-800T06_2P

CRT_B

1
L30

2
FCM2012CF-800T06_2P

2
FCM2012CF-800T06_2P

CRT_R_2

CRT_G_1

1
L31

2
FCM2012CF-800T06_2P

CRT_G_2

CRT_B_1

1
L29

2
FCM2012CF-800T06_2P

CRT_B_2

JCRT1
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

1
C431

R442

150_0402_1%

C429

2
2
10P_0402_50V8J

150_0402_1%

C424

C432

2
10P_0402_50V8J

C430

C425

1
C79
10P_0402_50V8J

2
2
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J

10P_0402_50V8J

C61
10P_0402_50V8J
2

C52
10P_0402_50V8J

Change to 12pf for Discrete

Change to 15pf for Discrete


1
L28

+CRT_VCC

R26

CRT_HSYNC

1 10K_0402_5%

1
L27

2
MBC1608121YZF_0603

CRT_HSYNC_2

2
MBC1608121YZF_0603

CRT_VSYNC_2
1
1

U7
Y

C423
10P_0402_50V8J
CRT_HSYNC_1

C47
16
17

100P_0402_50V8J

GND
GND

SUYIN_070546FR015S263ZR
DSUB_12

CONN@
1
CRT_DET# 18

C422
10P_0402_50V8J

2
C59
68P_0402_50V8J 1

2 0.1U_0402_16V4Z

OE#

C44

RGND
ID0
Red
GGND
SDA
Green
BGND
Hsync
Blue
+5V
Vsync
res
SGND
SCL
GND

74AHCT1G125GW_SOT353-5

DSUB_15
2

R445

150_0402_1%
2

1
L33

R24
100K_0402_5%

C45
68P_0402_50V8J
1

R450

2
FCM2012CF-800T06_2P

1
L34

CRT_R

+CRT_VCC

CRT_VSYNC_1

+CRT_VCC
U6

D22
DIS@
DAN217_SC59

D21
DIS@
DAN217_SC59

+3VS

74AHCT1G125GW_SOT353-5

SG@
2
+CRT_VCC

30

2 @
2 @

1 0_0402_5%
1 0_0402_5%

DGPU_EDIDSEL_R# 28

1
R34
2.2K_0402_5%

DSUB_12
DSUB_15
2 DIS only@
1

0_0402_5%

PCH_CRT_DATA R29

2 UMA only@
1

0_0402_5%

DSUB_12_R

DSUB_15_R

Q6
2N7002_SOT23

1
D

VGA_DDC_DATA R28

R33
2.2K_0402_5%
2

R22
R23

DSUB_12

3
11
28
31
33

VGA_DDC_CLK R30

2 DIS only@
1

0_0402_5%

PCH_CRT_CLK R31

2 UMA only@
1

0_0402_5%

Q7
1 2N7002_SOT23

DSUB_15

GND
GND
GND
GND
GPAD

9
10

+3VS

DGPU_SELECT# 17,28
DSUB_12_R
DSUB_15_R

16 PCH_CRT_DATA
16 PCH_CRT_CLK

0B2
1B2
2B2
3B2
4B2
5B2
6B2

SEL2

+CRT_VCC

pull-up 2k on GPU SIDE

26
24
21
19
17
13
15

16 PCH_CRT_R
16 PCH_CRT_G
16 PCH_CRT_B
16 PCH_CRT_HSYNC
16 PCH_CRT_VSYNC

A5
A6

CRT_R
CRT_G
CRT_B
CRT_HSYNC
CRT_VSYNC

pull-up 2.2k on PCH side

SEL1

1
2
5
6
7

22 VGA_DDC_DATA
22 VGA_DDC_CLK

0B1
1B1
2B1
3B1
4B1
5B1
6B1

A0
A1
A2
A3
A4

27
25
22
20
18
12
14

22 VGA_CRT_R
22 VGA_CRT_G
22 VGA_CRT_B
22 VGA_CRT_HSYNC
22 VGA_CRT_VSYNC

VDD
VDD
VDD
VDD
VDD

4
16
23
29
32

+3VS

SG@

U4
3

1
C46
2

SG@
2

1
C43

SG@
2

0.1U_0402_16V4Z

1
C40

0.1U_0402_16V4Z

SG@
2

0.1U_0402_16V4Z

0.1U_0402_16V4Z

1
C42

P
CRT_VSYNC

OE#

C48 <BOM
Structure>
1
2 0.1U_0402_16V4Z

PI3V712-AZLEX_TQFN32_6X3~D

Reserved for UMA only

B1

DIS

B2

UMA

PCH_CRT_R
PCH_CRT_G
PCH_CRT_B
PCH_CRT_HSYNC
PCH_CRT_VSYNC

2
2
2
2
2

CRT_R
CRT_G
CRT_B
CRT_HSYNC
CRT_VSYNC

UMA only@
1 0_0402_5%
UMA only@
1 0_0402_5%
UMA only@
1 0_0402_5%
UMA only@
1 0_0402_5%
UMA only@
1 0_0402_5%

VGA_CRT_R
VGA_CRT_G
VGA_CRT_B
VGA_CRT_HSYNC
VGA_CRT_VSYNC

2009/5/12

2010/04/15

Deciphered Date

Date:

2
2
2
2
2

DIS only@
1
DIS only@
1
DIS only@
1
DIS only@
1
DIS only@
1

CRT_R
CRT_G
CRT_B
CRT_HSYNC
CRT_VSYNC

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

R410
R414
R418
R424
R430

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

R411
R417
R421
R427
R434

Reserved for DIS only

CRT Connector
Document Number

NALG0 M/B LA-5681P Schematic


Friday, October 23, 2009

Sheet
E

29

of

60

Rev
1.0

+3VS
+3VS
0.1U_0402_16V4Z

1
C609
UMA only@

1
C612
UMA only@

1
C610
UMA only@

D13

+5VS

F2

+HDMI_5V

RB491D_SC59-3
0.1U_0402_16V4Z

0.1U_0402_16V4Z

W=40mils

18

0.1U_0402_16V4Z

HDMI_HPD#

HDMI_HPD#

1.1A_6VDC_FUSE
C592
0.1U_0402_16V4Z

2
11
15
21
26
33
40
46

2.2K_0402_5%
1
2

2.2K_0402_5%
1
2
UMA only@
R262 1
@
R274 1 @

UMA only@

R265

2 2.2K_0402_5%
2 2.2K_0402_5%

UMA only@
R656
3.6K_0402_5%

16 SDVO_SCLK
R253 1
@
2
2.2K_0402_5%

HDMI_CG3
R248
HDMI_TX2+
0_0402_5%HDMI_TX2-

UMA only@

+3VS

R657 1

2 2.2K_0402_5%

SDA_SINK

29

HDMI_SDATA

R655 1

2 2.2K_0402_5%

HPD_SINK

30

DDC_EN

32

EQ_0
EQ_1

34
35

EQ_S1

R276
R283
R277
R284

1
1
1
1

@
@
@
@

2
2
2
2

HDMI_CLK-

R637 1

1
L40
W CM-2012-900T_0805
@
4

+3VS

REXT

0_0402_5%

HDMI_R_CK-

2
3

HDMI_CLK+

R640 1

0_0402_5%

HDMI_R_CK+

HDMI_TX0-

R631 1

0_0402_5%

HDMI_R_D0-

HPD#
SDA

SCL

10

L39
W CM-2012-900T_0805
@
4

CG_2

OUT_D3+
OUT_D3-

IN_D3+
IN_D3-

45
44

PCH_TMDS_D1 16
PCH_TMDS_D1# 16

HDMI_CLK+
HDMI_CLK-

19
20

OUT_D2+
OUT_D2-

IN_D2+
IN_D2-

42
41

HDMI_TX0+
HDMI_TX0-

22
23

OUT_D1+
OUT_D1-

IN_D1+
IN_D1-

39
38

1
5
12
18
24
27
31
36
37
43

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GND

R633 1

HDMI_TX1-

R650 1

L42
W CM-2012-900T_0805
@
4

PCH_TMDS_CK 16
PCH_TMDS_CK# 16
PCH_TMDS_D0 16
PCH_TMDS_D0# 16

HDMI_TX0+

HDMI_TX1+

R651

HDMI_TX2-

R652

1
L44
W CM-2012-900T_0805
@
4

49

HDMI_TX2+

R653 1

3
2

2
3
0_0402_5%

HDMI_R_D0+

0_0402_5%

HDMI_R_D1-

2
3
0_0402_5%

HDMI_R_D1+

0_0402_5%

HDMI_R_D2-

2
3
0_0402_5%

HDMI_R_D2+

p/n: SA00003GT00

+3VS_delay

3
2
1

S
G
DIS@
3

HDMI_SCLK

1 0.1U_0402_16V7K HDMI_C_TX2-R643 1 DIS@


1 0.1U_0402_16V7K HDMI_C_TX2+R642 1 DIS@

2 499_0402_1%
2 499_0402_1%

23 VGA_HDMI_TXD123 VGA_HDMI_TXD1+

C603 DIS@ 2
C602 DIS@ 2

1 0.1U_0402_16V7K HDMI_C_TX1-R645 1 DIS@


1 0.1U_0402_16V7K HDMI_C_TX1+R644 1 DIS@

2 499_0402_1%
2 499_0402_1%

HDMI_CLKHDMI_CLK+

23 VGA_HDMI_TXD023 VGA_HDMI_TXD0+

C607 DIS@ 2
C606 DIS@ 2

1 0.1U_0402_16V7K HDMI_C_TX0-R649 1 DIS@


1 0.1U_0402_16V7K HDMI_C_TX0+R648 1 DIS@

2 499_0402_1%
2 499_0402_1%

HDMI_TX0HDMI_TX0+

23 VGA_HDMI_TXC23 VGA_HDMI_TXC+

C605 DIS@ 2
C604 DIS@ 2

1 0.1U_0402_16V7K HDMI_C_CLK-R647 1 DIS@


1 0.1U_0402_16V7K HDMI_C_CLK+R646 1 DIS@

2 499_0402_1%
2 499_0402_1%
Q44

Q47

HDMI_HPD

+3VS_DELAY

2N7002_SOT23

C601 DIS@ 2
C600 DIS@ 2

+HDMI_5V_OUT

23 VGA_HDMI_SCLK

DIS@
HDMI_SDATA
1
2N7002_SOT23
Q45

23 VGA_HDMI_TXD223 VGA_HDMI_TXD2+

Q67

G
SG@
3

HDMI_SDATA
2N7002_SOT23

74AHCT1G125GW _SOT353-5

Q68
5

R626
@
100K_0402_5%

+3VS_delay

HDMI_TX2HDMI_TX2+

HDMI_C_CLK2
HDMI_C_CLK+
1
0_0404_4P2R_5%
HDMI_C_TX02
HDMI_C_TX0+
1
0_0404_4P2R_5%
HDMI_C_TX12
HDMI_C_TX1+
1
0_0404_4P2R_5%
HDMI_C_TX22
HDMI_C_TX2+
1
0_0404_4P2R_5%

U21

2 DIS@
1
R237
2.2K_0402_5%

DIS@
2
G
2N7002_SOT23

VGA_HDMI_DET 22

DIS@

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/4/15

Issued Date

Deciphered Date

2010/04/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HDMI_SCLK

S
2N7002_SOT23

A
3

SG@
1

SDVO_SDATA

R231
0_0402_5%
@

DIS@ 3
4
RP6
DIS@ 3
4
RP5
DIS@ 3
4
RP7
DIS@ 3
4
RP8

0.1U_0402_16V4Z
2

1
DIS@

OE#

C247

+3VS

HDMI_TX1HDMI_TX1+

is ASM1442

ASM1442T_QFN48_7X7
UMA only@
default

23 VGA_HDMI_SDATA

SDVO_SCLK

HDMI_R_D1+
HDMI_R_D2-

CH7318C-BF PN: SA00001U920

Discrete use

HDMI_R_D0+
HDMI_R_D1-

20
21
22
23

TYCO_1939864-1
CONN@

+3VS
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%
2.2K_0402_5%

16
17

16

100K_0402_5%

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

HDMI_HPD
R282 1 UMA only@
2 0_0402_5%

HDMI_TX1+
HDMI_TX1-

2
1

HDMI_SCLK

PCH_TMDS_D2 16
PCH_TMDS_D2# 16

28

48
47

Q27

R278
20K_0402_5%
@

SCL_SINK

IN_D4+
IN_D4-

2
G

OE#

OUT_D4+
OUT_D4-

PCH_DPB_HPD

2N7002_SOT23

LS_HDMI_DET

R254

+HDMI_5V_OUT

HDMI_HPD#

25

13
14

R280
20K_0402_5%
@

1 UMA only@
2
R279
0_0402_5%

+3VS

+3VS

CG_0
CG_1

LS_HDMI_DET
7
R260 1 UMA only@
2 2.2K_0402_5%
SDVO_SDATA 8
R258 1 UMA only@
2 2.2K_0402_5%
SDVO_SCLK 9

16 SDVO_SDATA
C

OC_S2

HDMI_R_CK+
HDMI_R_D0-

HDMI_R_D2+

VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V

HDMI_CG0 3
HDMI_CG1 4

C268
0.1U_0402_16V4Z

+3VS

R271

HDMI_R_CKHDMI_HPD

2
G

U22
+3VS

HDMI_SDATA
HDMI_SCLK

D
Q26
2N7002_SOT23

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

+HDMI_5V_OUT

1
C619
UMA only@

2
0.1U_0402_16V4Z

1
C623
UMA only@

JHDMI1
HDMI_HPD
R263
10K_0402_5%
UMA only@

1
C622
UMA only@

2 0_0603_5%

1
C621
UMA only@

R189 1

0.1U_0402_16V4Z

+HDMI_5V_OUT
0.1U_0402_16V4Z

Title

HDMI Level Shife & Conn


Size
Document Number
Custom

NALG0 M/B LA-5681P Schematic

Date:

Friday, October 23, 2009

Sheet
1

30

of

60

Rev
1.0

+3VS
1

+5VS_HDD1

0.1U_0402_16V4Z
1

C143
0.1U_0402_16V4Z

C145

1000P_0402_50V7K

13 SATA_PTX_DRX_P0
13 SATA_PTX_DRX_N0
13 SATA_DTX_C_PRX_N0
13 SATA_DTX_C_PRX_P0

C137

10U_0805_10V4Z
1

C153

C141

SATA HDD1 Conn.

CL 4.0 mm

1U_0402_6.3V4Z

JSATA1

C439 1
C438 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PTX_C_DRX_P0
SATA_PTX_C_DRX_N0

C441 1
C440 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_DTX_PRX_N0
SATA_DTX_PRX_P0

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS

+5VS

R64

1
2
3
4
5
6
7

+5VS_HDD1
2
0_0805_5%

GND
HTX+
HTXGND
HRXHRX+
GND

VCC3.3
VCC3.3
VCC3.3
GND
GND
GND
VCC5
VCC5
VCC5
GND
RESERVED
GND
VCC12
VCC12
GND
VCC12
GND

24
23

OCTEK_SAT-22SU1G_NR
CONN@

Placea caps. near ODD CONN.


+5VS_HDD

0.1U_0402_16V4Z
1

C273

1000P_0402_50V7K

C272

10U_0805_10V4Z
1

C266

C267

SATA ODD Conn.

1U_0402_6.3V4Z

JSATA2

13 SATA_PTX_DRX_P1
13 SATA_PTX_DRX_N1
13 SATA_DTX_C_PRX_N1
13 SATA_DTX_C_PRX_P1

C292 1
C288 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_PTX_C_DRX_P1
SATA_PTX_C_DRX_N1

C284 1
C283 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_DTX_PRX_N1
SATA_DTX_PRX_P1

R270 1
+5VS

1
R239

2 1K_0402_1%

+5VS_HDD
2
0_0805_5%

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

GND
GND

16
17

OCTEK_SLS-13DB1G_NR
CONN@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/5/12

2010/04/15

Deciphered Date

Title

HDD & ODD & MINI CARD &CARDREADER Connector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Document Number

NALG0 M/B LA-5681P Schematic

Date:

Friday, October 23, 2009


G

Sheet

31
H

of

60

Rev
1.0

For Wireless LAN


+3VS

For TV-Tuner/HW MPEG

+1.5VS

+3VS
+3VS

C653
4.7U_0805_10V4Z

C348
0.1U_0402_16V4Z

C670
4.7U_0805_10V4Z

C349
0.1U_0402_16V4Z

C358
0.1U_0402_16V4Z

C320

0.1U_0402_16V4Z

+1.5VS

C641
mini2@
4.7U_0805_10V4Z

C642
mini2@
0.1U_0402_16V4Z

+5VS

C664
mini2@
4.7U_0805_10V4Z

C644
mini2@
0.1U_0402_16V4Z

C677
mini2@
0.1U_0402_16V4Z

C681
mini2@
0.1U_0402_16V4Z

+5VS

JMINI1
2 0_0402_5%

14 MINI1_CLKREQ#
14 CLK_PCIE_MINI1#
14 CLK_PCIE_MINI1

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

14 PCIE_DTX_C_PRX_N2
14 PCIE_DTX_C_PRX_P2
14 PCIE_PTX_C_DRX_N2
14 PCIE_PTX_C_DRX_P2
+3VS

R668 1

37 E51TXD_P80DATA

0_0402_5%
2

37 E51RXD_P80CLK

1
3
5
7
9
11
13
15

E51TXD_P80DATA_R
E51RXD_P80CLK

2
4
6
8
10
12
14
16

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

PCH_PCIE_WAKE#
@
1
2
R679 0_0402_5%

+3VS
+1.5VS

14 MINI2_CLKREQ#
14 CLK_PCIE_MINI2#
14 CLK_PCIE_MINI2

WL_OFF#
PCIE_RST#
R680 1
R682 1

2 0_0603_5%
2 0_0603_5%
@

PCH_SMBCLK
PCH_SMBDATA

WL_OFF# 37
PLT_RST_BUF# 17
+3VS
14 PCIE_DTX_C_PRX_N4
+3VALW
14 PCIE_DTX_C_PRX_P4

PCH_SMBCLK 12,14
PCH_SMBDATA 12,14

14 PCIE_PTX_C_DRX_N4
14 PCIE_PTX_C_DRX_P4

USB20_N4 17
USB20_P4 17
+3VS

(MINI1_LED#)
Mini1_LED# 38

(9~16mA)

E51TXD_P80DATA_R
E51RXD_P80CLK

R694
100K_0402_5%

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

1
3
5
7
9
11
13
15

2
4
6
8
10
12
14
16

17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

5.2 mm

FOX_AS0B226-S99N-7F
CONN@

53
54
55
56

53
54
55
56

G1
G2
G3
G3

1
3
5
7
9
11
13
15

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

+3VS
+1.5VS

PCIE_RST#

PCH_SMBCLK
PCH_SMBDATA
USB20_N5 17
USB20_P5 17

(MINI1_LED#)

G1
G2
G3
G3

PCH_PCIE_WAKE# R677 1

15,33 PCH_PCIE_WAKE#

JMINI2

FOX_AS0B226-S99N-7F
CONN@

+3VALW

9.2 mm

Mini Card Power Rating


Power

Primary Power (mA)

Auxiliary Power (mA)

Peak

Normal

+3VS

1000

750

Normal

+3V

330

250

250 (wake enable)

+1.5VS

500

375

5 (Not wake enable)

2009/5/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2007/12/25

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

MINI CARD (WLAN & TV-Tuner)


Document Number

NALG0 M/B LA-5681P Schematic


Friday, October 23, 2009

Sheet
E

32

of

60

Rev
1.0

+3V_LAN
+3VALW

R8

60mil

0_1206_5%
1

U30

VDDC
VDDC
VDDC

XTALVDDH

14

AVDDH

30

AVDDH

36

2
0.1U_0402_16V4Z
+LAN_AVDDL

27
33
39

AVDDL
AVDDL
AVDDL

37
38

LAN_MIDI3+

35

LAN_MIDI2-

34

LAN_MIDI2+

TRD1_N

31

LAN_MIDI1-

TRD1_P

32

LAN_MIDI1+

TRD0_N

29

LAN_MIDI0-

28

LAN_MIDI0+

TRD3_N

TRD2_N

+LAN_PCIEPLLVDD 18
21

+LAN_AVDDH

LAN_MIDI3-

TRD3_P

+LAN_GPHYPLLVDDL24

+LAN_XTALVDDH

TRD2_P

LAN_MIDI3- 34
LAN_MIDI3+ 34
LAN_MIDI2- 34

0.1U_0402_16V7K
14 PCIE_PTX_C_DRX_P1
14 PCIE_PTX_C_DRX_N1
15,32 PCH_PCIE_WAKE#
37
EC_PME#
+3V_LAN
5,17,37 PLT_RST#

R388 1
R384 1
R382 1

R389

AT24C02

LAN_MIDI2+ 34

C8

PCIE_PLLVDDL

LAN_MIDI1+ 34

SPD1000LED#
TRAFFICLED#

LAN_MIDI0+ 34

2
1
R378
0_0402_5%

47

LAN_LINK# 34

R6
1K_0402_5%

46
45

R4
1K_0402_5%

2
1
R379
0_0402_5%

+3VS

R380 1

2 1K_0402_5%

40

R385 1

2 10K_0402_5%

EECLK

LAN_XTALI

12

XTALO

SR_VFB

11

+1.2V_LAN_L

XTALI

LAN_RDAC

26

RDAC
SR_VDDP

1.24K_0402_1%
SR_VDD
14 LAN_CLKREQ#

0.1U_0402_16V4Z
L21
1
2
BLM18AG601SN1D_2P
B

1
2
+1.2V_LAN
L1 S INDUC_ 4.7UH +-20% SIA4012-4R7M
1
1
C384
C11
10U_0805_10V4Z
0.1U_0402_16V4Z
2
2

10

0.1U_0402_16V4Z
2

C10

0.1U_0402_16V4Z

L25
1
2
BLM18AG601SN1D_2P
C395

+1.2V_LAN

4.7U_0603_6.3V6K

20mil

L26
+LAN_GPHYPLLVDDL
1
2
BLM18AG601SN1D_2P
1
1
C391
C396

0.1U_0402_16V4Z

49

BCM57780A0KMLG_QFN48_7X7

C386

PAD

NC

0.1U_0402_16V4Z

+LAN_PCIEPLLVDD
1
C390

2
2
4.7U_0805_10V4Z 0.1U_0402_16V4Z

CLKREQ#

20mil

+3V_LAN
1

+3V_LAN

L23
1
2
BLM18AG601SN1D_2P

+LAN_AVDDH
1
1
C378
C383

R392
1

20mil

LOW_PWR
SR_LX

13

L24
1
2
BLM18AG601SN1D_2P
0.1U_0402_16V4Z

+LAN_BIASVDDH 1
C387

VMAIN_PRSINT

XTALO

44

SPROM_CLK

20mil
SPROM_DOUT

1
2
3
4

R7
1K_0402_5%
@

+LAN_XTALVDDH 1
C388

43

A0
A1
NC
GND

AT24C02_SO8

20mil
5

14 CLK_PCIE_LAN
14 CLK_PCIE_LAN#

EEDATA

VCC
WP
SCL
SDA

LAN_ACTIVITY# 34

20_0402_5%
MODE

U1 @
8
7
6
5

SPROM_CLK
SPROM_DOUT
1

48

R3
1K_0402_5%

LAN_MIDI0- 34

SPD100LED#
PCIE_TXD_P
PCIE_TXD_N
PCIE_RXD_P
PCIE_RXD_N
WAKE#
REST#
PCIE_REFCLK_P
PCIE_REFCLK_N

2 0.1U_0402_16V4Z

LAN_MIDI1- 34

PCIE_PLLVDDL

LINKLED#
17
16
22
23
LAN_PME#
4
LAN_RESET# 2
20
2 0_0402_5%
19
2 0_0402_5%
24.7K_0402_5%

+3V_LAN

0.1U_0402_16V7K
1
2 C394 PCIE_DTX_PRX_P1
1
2 C393 PCIE_DTX_PRX_N1

SPROM_DOUT
(EEDATA)

GPHY_PLLVDDL

TRD0_P

14 PCIE_DTX_C_PRX_P1
14 PCIE_DTX_C_PRX_N1

SPROM_CLK
(EECLK)
On chip

2
2
0.1U_0402_16V4Z

BIASVDDH

6
15
41

+LAN_BIASVDDH

4.7U_0603_6.3V6K
2

VDDC

25

C382

42

0.1U_0402_16V4Z
1
1
1
C385
C389
C376

+1.2V_LAN

C375

+3V_LAN

C9

4.7U_0805_10V4Z
2
2
0.1U_0402_16V4Z

20mil
+LAN_AVDDL
1
C379

LAN_XTALI

0.1U_0402_16V4Z

+1.2V_LAN

4.7U_0603_6.3V6K

L22
1
2
BLM18AG601SN1D_2P
C380

+1.2V_LAN

4.7U_0603_6.3V6K

XTALO
A

R11
200_0402_1%
Y1
1
1

2 LAN_XTALO

Compal Secret Data

Security Classification

1
25MHZ_20PF_7A25000012
C14
C34
27P_0402_50V8J
27P_0402_50V8J
2

Issued Date

2009/5/12

2010/04/15

Deciphered Date

Title

Compal Electronics, Inc.


Broadcom BCM57780

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Friday, October 23, 2009
Date:

Rev
1.0

NALG0 M/B LA-5681P Schematic

Sheet
1

33

of

60

JRJ1

33
33

LAN_MIDI1+
LAN_MIDI1-

LAN_MIDI1+
LAN_MIDI1-

33
33

LAN_MIDI2+
LAN_MIDI2-

LAN_MIDI2+
LAN_MIDI2-

LAN_MIDI3+
LAN_MIDI3-

LAN_MIDI3+
LAN_MIDI3-

33
33

1
2
3
4
5
6
7
8
9
10
11
12

TCT1
TD1+
TD1TCT2
TD2+
TD2TCT3
TD3+
TD3TCT4
TD4+
TD4-

MCT1
MX1+
MX1MCT2
MX2+
MX2MCT3
MX3+
MX3MCT4
MX4+
MX4-

24
23
22
21
20
19
18
17
16
15
14
13

+3V_LAN

RJ45_MIDI0+
RJ45_MIDI0-

2
R394

12

1
1K_0402_5%

RJ45_MIDI1+
RJ45_MIDI1-

11

1
220P_0402_50V7K

LAN_MIDI0+
LAN_MIDI0-

LAN_ACTIVITY#

33 LAN_ACTIVITY#

T1
LAN_MIDI0+
LAN_MIDI0-

33
33

RJ45_MIDI2+
RJ45_MIDI2RJ45_MIDI3+
RJ45_MIDI3-

C392
2

RJ45_MIDI3-

RJ45_MIDI3+

RJ45_MIDI1-

RJ45_MIDI2-

RJ45_MIDI2+

RJ45_MIDI1+

RJ45_MIDI0-

RJ45_MIDI0+

350uH_GSL5009-1 LF

LAN_LINK#

33 LAN_LINK#
C12

0.1U_0402_16V4Z
2

+3V_LAN

2
R409

1
1K_0402_5%

1
R403
75_0402_1%

0.1U_0402_16V4Z

R408
75_0402_1%

LAN_ACTIVITY#
LAN_LINK#

Yellow LED+

Guide Pin

PR4PR4+
PR2PR3PR3+
PR2+
PR1SHLD2
PR1+
SHLD1

14
13

Green LEDGreen LED+


SUYIN_100073FR012G101ZL
conn@
2

C13

R396
75_0402_1%

0.1U_0402_16V4Z

R395
75_0402_1%
2

C33

0.1U_0402_16V4Z
2

C37

10

Yellow LED-

C419
220P_0402_50V7K

40mil

Place close to TCT pin


C

RJ45_GND
RJ45_GND

LANGND
1

D2
C420
1000P_1206_2KV7K

PJDLC05_SOT23-3
@

1
C418
2

40mil

C421
4.7U_0805_10V4Z

0.1U_0402_16V4Z

LAN_ACTIVITY#

1
2
C5
68P_0402_50V8J
@

LAN_LINK#

1
2
C6
68P_0402_50V8J
@

Compal Secret Data

Security Classification
Issued Date

2009/5/12

Deciphered Date

2010/04/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size

Document Number

Rev
1.0

NALG0 M/B LA-5681P Schematic


Date:

Compal Electronics, Inc.


LAN Magnetic & RJ45
Friday, October 23, 2009

Sheet
1

34

of

60

ESATA CONN

Finger Print Conn.

R717 1

D0

D1

L69

Function
defalut; CH0/CH1 ->0dB

17

USB20_N8

USB20_P8

2 0_0402_5%
D23

USB20_N8_R

USB20_P8_R

+USB_VCCA
USB20_N8

CH0->2.5dB pre-emphasis;CH1->0dB

CH1->2.5dB pre-emphasis;CH0->0dB

WCM2012F2S-900T04_0805

CH0/CH1->2.5dB pre-emphasis

1
R718

17

VIN

USB20_P8

IO1

IO2 GND

PRTR5V0U2X_SOT143-4
@

2
0_0402_5%

+3VS
1U_0402_6.3V4Z
1
1
C589
C538

JFP1

USB20_N11
USB20_P11
D12
SM05T1G_SOT23-3

2
1

JUSB2

0.1U_0402_16V4Z
5
6
7
8

+USB_VCCA

W=60mils

R601
SATA_PTX_DRX_P4
SATA_PTX_DRX_N4

eDriver@
eDriver@
R597 1
R600 1

2 470_0402_5%

GND1
GND2
GND3
GND4

SUYIN_020173MR004G565ZR
CONN@

1000P_0402_50V7K

C511

C519

1
C461

150U_B_6.3VM_R40M
2
2
470P_0402_50V7K

SATA_PTX_RPO_DRX_P4
SATA_PTX_RPO_DRX_N4

2 0_0402_5%
2 0_0402_5%

SATA_DTX_C_PRX_N4R603 1
2 0_0402_5% SATA_DTX_RPI_PRX_N4
SATA_DTX_C_PRX_P4R607 1
2 0_0402_5% SATA_DTX_RPI_PRX_P4
eDriver@
eDriver@
eDriver@
U39
2
1
7 EN
+3VS
VCC 6
eDriver@
R610
10K_0402_5%
VCC 10
SATA_PTX_DRX_P4
SATA_PTX_RPI_DRX_P4
C545 2
1 0.01U_0402_25V7K
1 RX_0P
VCC 16
SATA_PTX_DRX_N4
C551 2
1 0.01U_0402_25V7K SATA_PTX_RPI_DRX_N4 2 RX_0N
VCC 20
eDriver@
SATA_DTX_C_PRX_P4 C560 2
1 0.01U_0402_25V7K SATA_DTX_RPO_PRX_P4 5 TX_1P
D0 9
SATA_DTX_C_PRX_N4 C553 2
1 0.01U_0402_25V7K SATA_DTX_RPO_PRX_N4 4 TX_1N
D1 8
eDriver@
eDriver@
3 GND
TX_0P 15
13 GND
TX_0N 14
R721 1
@
2 0_0402_5%
17 GND
+3VS
R722 1 eDriver@2 0_0402_5%
18 GND
RX_1N 12
R723 1 eDriver@2 0_0402_5%
19 GND
RX_1P 11
21 PAD

13 SATA_DTX_C_PRX_N4
13 SATA_DTX_C_PRX_P4
1

VCC
DD+
GND

13 SATA_PTX_DRX_P4
13 SATA_PTX_DRX_N4

JESAT1

1
2
3
4

USB20_N8_R
USB20_P8_R

VBUS
DD+
GND

USB

eDriver@
eDriver@
5 GND
SATA_PTX_C_DRX_P4
10.01U_0402_25V7K
6 A+
ESATA
SATA_PTX_C_DRX_N4
10.01U_0402_25V7K
7 A8 GND SHIELD
SATA_DTX_RPI_PRX_N4 C552 2
SATA_IRX_DTX_N5
0.01U_0402_25V7K
1
9 BSHIELD
SATA_DTX_RPI_PRX_P4 C557 2
SATA_IRX_DTX_P5
10.01U_0402_25V7K
10 B+
SHIELD
11 GND SHIELD
eDriver@
eDriver@
TYCO_1909574-1
CONN@

SATA_PTX_RPO_DRX_P4C543 2
SATA_PTX_RPO_DRX_N4C548 2

+3VS

ESATA_D0
ESATA_D1

12
13
14
15

SATA_PTX_RPO_DRX_P4
SATA_PTX_RPO_DRX_N4
SATA_DTX_RPI_PRX_N4
SATA_DTX_RPI_PRX_P4

1
2
3
4

USB20_N8_R
USB20_P8_R

eDriver@
2

R611 eDriver@
0_0402_5%

eDriver@

ACES_85201-04051
CONN@

eDriver@
2

COAL LAY JeSATA1

+USB_VCCA

ESATA_D1

R612
0_0402_5%

G2
G1
4
3
2
1

0.1U_0402_16V4Z
1
C539

6
5
4
3
2
1

R613
4.7K_0402_5%
@

C264
0.1U_0402_16V4Z
2
1

17
17

ESATA_D0

FP@

R614
4.7K_0402_5%
@
R255
0_0603_5%
FP@

R256
0_0603_5%
@

eDriver@
2

+3VS

+3VALW

+3VS

SN75LVCP412RTJR_QFN20_4X4~D
eDriver@

R724
0_0402_5%
eDriver@

Bluetooth Conn.

To USB/B Connector

USB CONN.

R719 1
+3VALW

+3VS

L70
17

USB20_N0

USB20_P0

2 0_0402_5%
D9

USB20_N0_R

USB20_P0_R

+USB_VCCA
USB20_N0

C687

17

C694

+BT_VCC
C683

C678

0.1U_0402_16V4Z
2

43

USB20_N1 17
USB20_P1 17
USB_OC#0 17

ACES_85201-08051

4.7U_0805_10V4Z
2
2
0.1U_0402_16V4Z

R689
300_0603_5%

SYSON#

CONN@
Q54
2N7002_SOT23
3

C346

1
+

C708
2

+BT_VCC

USB20_P10
USB20_N10

8
7
6
5
4
3
2
1

8 GND
7
6
5
4
3
2
1 GND
JBT1

1
2
3
4

GND1
GND2
GND3
GND4

80mil

+5VALW

C239

1
2
3
4

GND
IN
IN
EN#

8
7
6
5

OUT
OUT
OUT
FLG

R168
0_0402_5%
1
2

TPS2061DRG4_SO8

R164
100K_0402_5%
1
2
R169
10K_0402_5%

4.7U_0805_10V4Z
2

USB_OC#2 17
USB_OC#4 17

C201
4

0.1U_0402_16V4Z

SYSON#

10

2009/5/12

Issued Date
9

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/12/31

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

+3VALW

U20

VCC
DD+
GND

SUYIN_020173MR004G565ZR
CONN@
43

CONN@
ACES_87213-0800G

17
17

+USB_VCCA

JUSB1

5
6
7
8

4.7U_0805_10V4Z
2

USB20_P0

2
0_0402_5%

C709

USB20_N0_R
USB20_P0_R

+5VALW

2
G

IO1

IO2 GND

+USB_VCCA

W=40mils

VIN

1
R720

+5VALW

470P_0402_50V7K

Q53
AO3413_SOT23-3

80mil

150U_B_6.3VM_R40M

JUSB3
1
1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
GND 9
GND 10

1
C684

1U_0603_10V4Z

2
10K_0402_5%

1
R690

BT_ON#

37

PRTR5V0U2X_SOT143-4
@

WCM2012F2S-900T04_0805
0.1U_0402_16V4Z
2

NEW CARD & eSATA Connector


Document Number

NALG0 M/B LA-5681P Schematic


Friday, October 23, 2009

Sheet
E

35

of

60

Rev
1.0

+3VS

+3VS_READER

R364 1

+REG18_PLL

2 0_1206_5%

C362
@
4.7U_0603_6.3V6K

1 C693
0.1U_0402_16V4Z

RST#
MODE_SEL
XTLO
XTLI

+3VS_READER

1 0.1U_0402_16V4Z
+XDPW R_SDPW R_MSPW R

+XDPW R_SDPW R_MSPW R


+3VS_READER

R343
100K_0402_5%

17
17
44

Internal 200K Pull UP


R345 1

Vender suggesttion

2
R361

2 0_0402_5%

USB20_N9
USB20_P9
5IN1_LED#

1
3
7
9
11
33

AV_PLL
NC
NC
CARD_3V3
D3V3
D3V3

8
44
45
47
48

3V3_IN
RST#
MODE_SEL
XTLO
XTLI

4
5
14

DM
DP
GPIO0

RST#

C352
1U_0402_6.3V4Z

R356 2

1 6.19K_0402_1% 2

RREF

12
32

DGND
DGND

6
46

AGND
AGND

MODE_SEL

CARD_AGND

10
22
30

XD_CLE_SP19
XD_CE#_SP18
XD_ALE_SP17
SD_DAT2/XD_RE#_SP16
SD_DAT3/XD_WE#_SP15
XD_RDY_SP14
SD_DAT4/XD_WP#/MS_D7_SP13
SD_DAT5/XD_D0/MS_D6_SP12
SD_CLK/XD_D1/MS_CLK_SP11
SD_DAT6/XD_D7/MS_D3_SP10
MS_INS#_SP9
SD_DAT7/XD_D2/MS_D2_SP8
SD_DAT0/XD_D6/MS_D0_SP7
SD_DAT1/XD_D3/MS_D1_SP6
XD_D5_SP5
XD_D4/SD_DAT1_SP4
SD_CD#_SP3
SD_WP_SP2
XD_CD#_SP1
EEDI

43
42
41
40
39
38
37
35
34
31
29
28
27
26
25
23
21
20
19
18

XTAL_CTR
MS_D5

13
24

EEDO
EECS
EESK
SD_CMD

15
16
17
36

C367 1

2 1U_0402_6.3V4Z

XDCLE
XDCE#
XDALE
SDDAT2_XDRE#
SDDAT3_XDW E#
XD_RDY
SDDAT4_XDW P#_MSD7
SDDAT5_XDD0_MSD6
SDCLK_XDD1_MSCLK_L
SDDAT6_XDD7_MSD3
MS_INS#
SDDAT7_XDD2_MSD2
SDDAT0_XDD6_MSD0
SDDAT1_XDD3_MSD1
XDD5_MSBS
XDD4_SDDAT1
SDCD
SDW P
XDCD
XTAL_CTR R348 2

R330 2

1 0_0603_5%

1 0_0402_5%

SDCLK_XDD1_MSCLK

+3VS_READER

SD_CMD

VREG
MS_D4
NC

R363
RTS5159-GR_LQFP48_7X7
<BOM Structure>

0_0603_5%

R347
0_0402_5%
<BOM Structure>

C357
@
47P_0402_50V8J

+REG18

1
0_0402_5%

U29
C363 2

R353 1

CLK_SD_48M

Y5
12MHZ_16PF_6X12000012
@

C366
22P_0402_50V8J

1
C359

JREAD1

XTLO

2
6P_0402_50V8D

EMI

R354

32
10
9
8
7
6
5
4

XD-D0
XD-D1
XD-D2
XD-D3
XD-D4
XD-D5
XD-D6
XD-D7

SDDAT3_XDW E#
SDDAT4_XDW P#_MSD7
XDALE
XDCD
XD_RDY
SDDAT2_XDRE#
XDCE#
XDCLE

34
33
35
40
39
38
37
36

XD-WE
XD-WP
XD-ALE
XD-CD
XD-R/B
XD-RE
XD-CE
XD-CLE

11
31

7IN1 GND
7IN1 GND

2
0_0603_5%

41
42

1
R362
100K_0402_5%

XD-VCC

SDDAT5_XDD0_MSD6
SDCLK_XDD1_MSCLK
SDDAT7_XDD2_MSD2
SDDAT1_XDD3_MSD1
XDD4_SDDAT1
XDD5_MSBS
SDDAT0_XDD6_MSD0
SDDAT6_XDD7_MSD3

+CARDPW R

40~60 mil 1

+CARDPW R

+XDPW R_SDPW R_MSPW R

+CARDPW R
+CARDPW R

XTLI

R355
33_0402_5%

1126. RTS5158E,RTS5159
add C345 will have power drop
issue when insert Card.

2 0_0402_5%
@
1
2
C361
6P_0402_50V8D

12

7 IN 1 CONN

SD-VCC
MS-VCC

21
28

SD_CLK
SD-DAT0
SD-DAT1
SD-DAT2
SD-DAT3
SD-DAT4
SD-DAT5
SD-DAT6
SD-DAT7
SD-CMD
SD-CD-SW

20
14
12
30
29
27
23
18
16
25
1

SD-WP-SW

MS-SCLK
MS-DATA0
MS-DATA1
MS-DATA2
MS-DATA3
MS-INS
MS-BS

26
17
15
19
24
22
13

C328
@
10U_0805_10V4Z
SDCLK_XDD1_MSCLK
SDDAT0_XDD6_MSD0
XDD4_SDDAT1
SDDAT2_XDRE#
SDDAT3_XDW E#
SDDAT4_XDW P#_MSD7
SDDAT5_XDD0_MSD6
SDDAT6_XDD7_MSD3
SDDAT7_XDD2_MSD2
SD_CMD
SDCD

1
C306

C327
0.1U_0402_16V4Z

SDW P
SDCLK_XDD1_MSCLK
SDDAT0_XDD6_MSD0
SDDAT1_XDD3_MSD1
SDDAT7_XDD2_MSD2
SDDAT6_XDD7_MSD3
MS_INS#
XDD5_MSBS

1
@

C337
22P_0402_50V8J

7IN1 GND
7IN1 GND
A

Compal Electronics, Inc.

Compal Secret Data


2009/5/12

Issued Date

Deciphered Date

2009/08/10

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

0.1U_0402_16V4Z

TAITW _R015-A10-LM_NR
CONN@

C364
0.1U_0402_16V4Z

Security Classification

Title

Card Reader RTS5159


Size
Document Number
Custom

Rev
1.0

NALG0 M/B LA-5681P Schematic

Date:

Friday, October 23, 2009

Sheet
1

36

of

60

For EC Tools
C275

<BOM Structure>
1

1000P_0402_50V7K

C302

EC_RST#
EC_SCI#

12
13
37
20
38

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

R309 2
C313

5,17,33 PLT_RST#

1 47K_0402_5%
2

18
EC_SCI#
15 PM_CLKRUN#

0.1U_0402_16V4Z

+3VALW

2 EC_SMB_CK1
2.2K_0402_5%
2 EC_SMB_DA1
2.2K_0402_5%

1
R285
1
R291

1
R267

2 LID_SW #
100K_0402_5%

1
R313
1
R314

2 KSO1
47K_0402_5%
2 KSO2
47K_0402_5%

10/1 ENE Recommand


1
R266

2 EC_PME#
10K_0402_5%

+3VALW

38 EC_I2C_DA

EC_SMB_DA1

Q28B
2N7002DW -T/R7_SOT363-6
38

EC_I2C_CK

2N7002DW -T/R7_SOT363-6

46
46
14,22
14,22

EC_SMB_CK1

Q28A

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

77
78
79
80

SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47

+3VALW

Rc
21
23
26
27

R293
@
2
BEEP#

0_0402_5%
INVT_PW M
1
BEEP#

INVT_PW M 28

R713
100K_0402_5%
DIS@

ACOFF

AD_ProjectID

40

ACOFF

BATT_TEMP
BATT_OVP
ADP_I
AD_BID0

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

63
64
65
66
75
76

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

68
70
71
72

EN_DFAN1
IREF
CALIBRATE#

PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F

83
84
85
86
87
88

EC_MUTE#
VGA_idle
PW R_SAVE_LED#
T/P_LOCK_LED#
TP_CLK
TP_DATA

SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0

97
98
99
109

3S/4S#
65W /90W #

SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#

119
120
126
128

EC_SI_SPI_SO
EC_SO_SPI_SI
EC_SPICLK
EC_SPICS#/FSEL#

48,49
ECAGND
2
1
C314 0.01U_0402_16V7K
BATT_TEMP 46

BATT_OVP 48
ADP_I
48

AD_ProjectID

+3VALW
DAC_BRIG 28
EN_DFAN1 42
IREF
48
CALIBRATE# 48

+3VALW

R307
100K_0402_5%

Ra

PS2 Interface

R741

EC_MUTE 41
VGA_idle 22
PW R_SAVE_LED# 38
T/P_LOCK_LED# 38
TP_CLK 38
TP_DATA 38

100K_0402_5%
VGA_idle

AD_BID0
C

R306
33K_0402_1%

Rb

3S/4S# 48
65W /90W # 48
Program_LED# 38
LID_SW # 38

LID_SW #

SPI Device Interface


SPI Flash ROM

+5VS
TP_CLK
TP_DATA

EC_SI_SPI_SO 38
EC_SO_SPI_SI 38
EC_SPICLK 38
EC_SPICS#/FSEL# 38

2
4.7K_0402_5%
2
4.7K_0402_5%

+3VALW

10/1 EC Recommand

GPIO
SM Bus

CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59

73
74
89
90
91
92
93
95
121
127

EC_RCIRRX
PCH_TEMP_ALERT#
FSTCHG

PCH_TEMP_ALERT# 18
FSTCHG 48
BATT_Blue_LED# 44
CAPS_LED# 44
BATT_Amber_LED# 44
PW R_LED 44
SYSON
43,51
VR_ON
55
ACIN
15,43,44,45

CAPS_LED#
PW R_LED
SYSON
VR_ON
ACIN

3S/4S#

2
R269

1
100K_0402_5%

65W /90W #

2
R268

1
100K_0402_5%

EC_RCIRRX 1

122
123

11
24
35
94
113
A

+3VALW
38,39 EC_I2C_INT1

2
100K_0402_5%
2
D29
CH751H-40PT_SOD323-2
caps@

KB926QFD3_LQFP128_14X14

C277
15P_0402_50V8J

X2
32.768KHZ_12.5P_MC-306

C276
4.7U_0805_10V4Z

C315
BATT_TEMP
2
C316
BATT_OVP
2
C280
ACIN
2

20mil

L15
ECAGND 2
1
FBMA-L11-160808-800LMT_0603

100P_0402_50V8J
1
100P_0402_50V8J
1
100P_0402_50V8J
1

EC_I2C_INT1_D

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/4/15

Issued Date

Deciphered Date

2010/04/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

15P_0402_50V8J

1
R598

EC_CRY2

1
4

124

XCLK1
XCLK0
GND
GND
GND
GND
GND

EC_CRY1
EC_CRY2

EC_CRY1
C278

PM_SLP_S4# 15
ENBKL
16
EAPD
40
SUS_PW R_ACK 15
SUSP#
39,43,48,50
PBTN_OUT# 5,15
EC_PME# 33

ENBKL
EAPD
SUS_PW R_ACK
SUSP#
PBTN_OUT#
EC_PME#

+3VALW

Analog Board ID definition,


Please see page 3.

V18R

GPI

2 PCH_TEMP_ALERT#
2.2K_0402_5%

EC_RSMRST# 15
EC_LID_OUT# 14
EC_ON
39
EC_SW I# 15
EC_PW ROK 15
BKOFF# 28
W L_OFF# 32
EC_CYP_RST# 38
PCH_SPKR 13,40

IN

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

110
112
114
115
116
117
118

EC_RSMRST#
EC_LID_OUT#
EC_ON
EC_SW I#
EC_PW ROK
BKOFF#
W L_OFF#
EC_CYP_RST#
PCH_SPKR

AGND

R300 2
42 FAN_SPEED1
35
BT_ON#
32 E51TXD_P80DATA
32 E51RXD_P80CLK
39
ON/OFF
44 PW R_SUSP_LED
44
NUM_LED#

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

69

1
R298

INVT_PW M

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

100
101
102
103
104
105
106
107
108

10K_0402_5%

OUT

2 EC_SMB_CK2
2.2K_0402_5%
2 EC_SMB_DA2
2.2K_0402_5%

1
R292
1
R290

1
R288
1
R286

NC

EC suggested 2.2K for SMBus...

C304

2
0.1U_0402_16V4Z

NC

38 BACKUP_LED#
38
BT_LED#

+3VS

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#

ME_EN

C701
@

2
0.1U_0402_16V4Z

15
15
18
13

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

R712
0_0402_5%
UMA only@

Rd

R303
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
ME_EN
BACKUP_LED#
BT_LED#
EC_I2C_INT1_D
1 0_0402_5%
FAN_SPEED1
BT_ON#
E51TXD_P80DATA
E51RXD_P80CLK
ON/OFF
PW R_SUSP_LED
NUM_LED#

Switchable
DIS only
D
UMA

100k_0402_5%

PWM Output

DA Output

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

SD028100380

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

AD

3.3V
1.5V
0V

DIS only@

17 CLK_PCI_LPC

AD_ProjectID

ACES_85205-0400
@

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

R712

E51RXD_P80CLK
E51TXD_P80DATA

C289
@ 22P_0402_50V8J
R289 2
2
1

1
2
3
4
5
7
8
10

0.1U_0402_16V4Z

1
2
3
4

AVCC

VCC
VCC
VCC
VCC
VCC
VCC
18
EC_GA20
18 EC_KBRST#
13
SERIRQ
13 LPC_FRAME#
13
LPC_AD3
13
LPC_AD2
1 @ 33_0402_5% 13
LPC_AD1
13
LPC_AD0

EC_GA20
EC_KBRST#
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

67

9
22
33
96
111
125

U25

1
2
3
4

1
1
1000P_0402_50V7K

+3VALW
JP29

KSO[0..17] 38

2
2
0.1U_0402_16V4Z

KSO[0..17]

38

2
2
0.1U_0402_16V4Z

+3VALW _EC

KSI[0..7]

KSI[0..7]

0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
2
C287
C299
C312
C282
C274

ECAGND

1
R272
0_0805_5%

L16
FBMA-L11-160808-800LMT_0603
1
2 +EC_VCCA

+3VALW

+3VALW

Title

EC ENE KB926
Size
B
Date:

Document Number

Rev
1.0

NALG0 M/B LA-5681P Schematic


Friday, October 23, 2009

Sheet
1

37

of

60

U23
1
3
7
4

+SPI_VCC
U24
37 EC_SPICS#/FSEL#

EC_SPICS#/FSEL#
2 4.7K_0402_5% SPI_WP#
2 4.7K_0402_5% SPI_HOLD#

R275 1
R264 1

+3VALW

1
3
7
4

CE#
WP#
HOLD#
VSS

CS#
WP#
HOLD#
GND

MX25L512AMC-12G_SO8
VDD
SCK
SI
SO

8
6
5
2

EC_SPICLK_R

R261 1
R259 1
R273 1

2 0_0402_5%
2 0_0402_5%
2 0_0402_5%

To TP/B Conn.

+SPI_VCC
EC_SPICLK_R
EC_SO_SPI_SI
EC_SI_SPI_SO

8
6
5
2

VCC
SCLK
SI
SO

use 128KB EC ROM SA00002C100

JTP1
+5VS
37
37

EC_SPICLK 37
EC_SO_SPI_SI 37
EC_SI_SPI_SO 37

C263

MX25L8005M2C-15G_SOP8
100P_0402_50V8J

ENE suggestion SPI Frequency over 66MHz


SST: 50MHz
MXIC: 70MHz
ST: 40MHz

6
5
4
3
2
1

TP_CLK
TP_DATA
LEFT_BTN#
RIGHT_BTN#

TP_CLK
TP_DATA

C270
100P_0402_50V8J

6
5
4
3
2
1

8
7

8
7

SW4
SMT1-05-A_4P
1

RIGHT_BTN# 3

SW5
SMT1-05-A_4P
1

ACES_85201-0605
LEFT_BTN#
CONN@

TP_CLK
+5VS

5
6

EC_SPICS#/FSEL#
SPI_WP#
SPI_HOLD#

2 0.1U_0402_16V4Z

5
6

C265 1

2
0_0603_5%

TP_DATA
3

1
R257

+3VALW

C245
D16
@
PSOT24C_SOT23
1

0.1U_0402_16V4Z

KSI[0..7]

KSI[0..7]

KSO[0..17]

+5VS

37

+3VS

MCVCC
+3VS

KSO[0..17]

37
3

SW3
SMT1-05-A_4P
1

JKB1
KSO0

(Right)

37 EC_I2C_CK
37,39 EC_I2C_INT1
37 EC_I2C_DA
37 EC_CYP_RST#

2 0_0402_5% MEDIA_CK

R247 1
1

2 0_0402_5% MEDIA_DA
MC_RST+#
2
R240
0_0402_5%
R249
10K_0402_5%
@

@
+3VALW

27
28

G1
G2

2
R241

1
10K_0402_5%

1
2
3
4
5
6
7
8
9
10

1
2
3
4
5
6
7
8
GND
GND

ACES_85201-08051
CONN@

ACES_85201-26051
CONN@

KSO16

C570 1

100P_0402_50V8J

KSO17

C569 1

100P_0402_50V8J

100P_0402_50V8J

KSO0

C572 1

100P_0402_50V8J

KSO13

C573 1

100P_0402_50V8J

KSO7

C579 1

100P_0402_50V8J

KSI2 T/P lock_BTN#

KSO12

C574 1

100P_0402_50V8J

KSO6

C580 1

100P_0402_50V8J

KSI3 Back up_BTN#

KSO5

C581 1

100P_0402_50V8J

KSI0

C568 1

100P_0402_50V8J

KSI4

KSO4

C582 1

100P_0402_50V8J

KSO11

C575 1

100P_0402_50V8J

KSI5 Power save_BTN#

KSO10

C576 1

100P_0402_50V8J

KSO3

C583 1

100P_0402_50V8J

KSI1

C567 1

100P_0402_50V8J

KSI4

C564 1

100P_0402_50V8J

KSO2

C584 1

100P_0402_50V8J

KSO1

C585 1

100P_0402_50V8J

KSO0

C586 1

100P_0402_50V8J

KSO8

C578 1

100P_0402_50V8J

KSI5

C563 1

100P_0402_50V8J

KSI6

C562 1

100P_0402_50V8J

KSI7

C561 1

100P_0402_50V8J

BT_LED# 37
BACKUP_LED# 37
PWR_SAVE_LED# 37

WL_BTN#

BT_BTN#

Program_BTN#
Volum up_BTN#
Volum down_BTN#

NALG0

13
14

Lid Switch

GND
GND

1
2
3
4
5
6
7
8
9
10
11
12

1
2
3
4
5
6
7
8
9
10
11
12

KSO0
KSO3
KSI1
KSI3
KSI4
BACKUP_LED#
BT_LED#
MINI1_LED#
Program_LED#

+3VS

Program_LED#

37

ACES_85201-1205N
CONN@

(Hall Effect Switch)


+3VALW

100P_0402_50V8J

C38
0.1U_0402_16V4Z

R20

47K_0402_5%

OUTPUT

U3
A3212ELHLT-T_SOT23W-3

D3

C565 1

C577 1

KSI3

VDD

KSO9

100P_0402_50V8J

32

+3VS

KSO0
MINI1_LED#
KSI1
KSI5
KSI3
KSI4
BT_LED#

ACES_85201-1205N
CONN@

100P_0402_50V8J

GND

1
2
3
4
5
6
7
8
9
10
11
12

JFunc1

LID_SW#

LID_SW#

37

CH751H-40PT_SOD323-2
1

C566 1

KSI1

GND
GND

1
2
3
4
5
6
7
8
9
10
11
12

KSO3

KSO14

KSI2

MINI1_LED#

NAL90

To BTN/B Conn.
C571 1

37

Jfunc2

13
14

KSO15

T/P_lock_LED#

499_0402_1%

FN/B

JMedi1
R246 1

2ON_0FF_TP LED#

5
6

@
2

To Media/B Conn.

R304
1

HT-121UD_AMBER

2
0_0603_5%

R252
0_0603_5%

LED9
2

R250

R251

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

2
0_0603_5%

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

(Left)

KSI2

C41
10P_0402_50V8J

Anpec p/n:SA00003B900
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/5/12

Deciphered Date

2009/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

BIOS, I/O Port & K/B Connector


Size
C
Date:

Document Number

Rev
0.3

NALG0 M/B LA-5681P Schematic


Friday, October 23, 2009

Sheet

38

of

60

Power Button
HDA MDC Conn.
+3VALW
+3VALW

ON/OFF switch
100K_0402_5%

13 HDA_SYNC_MDC
13 HDA_SDIN1
13 HDA_RST_MDC#

SW1
EVQPLHA15_4P
3
1

D17
2
1

51ON#

ON/OFF

37

51ON#

45

R701

HDA_SDIN1_MDC
33_0402_5%

2
4
6
8
10
12

2
4
6
8
10
12

+MDC_VCC
1
R706

2
0_0402_5%

C700
1

1U_0603_10V4Z

+3VALW
HDA_BITCLK_MDC 13

ACES_88018-124N
CONN@

R710
0_0402_5%

DAN202UT106_SC70-3
2

5
6

13 HDA_SDOUT_MDC

1
3
5
7
9
11

R308

1
3
5
7
9
11

15mil

JMDC1

1
2

RLZ20A_LL34

10K_0402_5%
1

2
D

S 2N7002_SOT23

Q23

2
G

37,38 EC_I2C_INT1

2
@

10K_0402_5%
1

S 2N7002_SOT23

S 2N7002_SOT23

Q24

2
G

2
R322

R175 Caps@

10K_0402_5%

2
Q32

For EMI
D

2
G

R177
1

1
EC_ON

EC_ON

22P_0402_50V8J

51ON#
R173 Caps@
510K_0402_5%

MCVCC +3VS

37

MCVCC

D18

1000P_0402_50V7K
1

C305

C698

Caps@

Caps@
2

Power ON Circuit
+3VALW

+3VALW

14
I

For PCH
O

DGPU_PWROK_BUF 18

C190
1U_0603_10V6K
@

I
G

14,52 VGA_PWROK

U16B
SN74LVC14APWLE_TSSOP14

14

U16A
SN74LVC14APWLE_TSSOP14

+5VALW
2

+3VS
+3VALW

R448
100K_0402_5%
DIS@

DGPU_PWR_EN#
8

VS_ON

+RTCBATT

50,51,53
1

For +VCCP/+1.05VS
DGPU_PWR_EN

2
G
Q38
S
2N7002_SOT23
DIS@

R329
1K_0402_5%

D19

R447
100K_0402_5%
DIS@

D
2

1 1

14
P
I
G

2
G
Q22
2N7002_SOT23

SUSP

C184
0.1U_0402_16V7K

U16D
SN74LVC14APWLE_TSSOP14

SUSP

43,50

I
7

5
2

U16C
SN74LVC14APWLE_TSSOP14

R154
10K_0402_1%
1
2

37,43,48,50 SUSP#

14

R158
@
10K_0402_1%

+3VALW
3

+3VS

14
P

14

12

VGA_ON

24,43,52

13

2
DIS@

BAS40-04_SOT23-3

U16F
SN74LVC14APWLE_TSSOP14

+CHGRTC
C319
0.1U_0402_16V4Z

C179
3

2
G
Q13
2N7002_SOT23

10

DGPU_PWR_EN#

U16E
SN74LVC14APWLE_TSSOP14

11

+RTCVCC

2 0.1U_0402_16V4Z

1
1

18 DGPU_PWR_EN

R85
10K_0402_1%
1
2
DIS@

+3VALW

C180

+3VALW

R86
31.6K_0402_1%
@

1U_0603_10V6K
1

DIS@
DGPU_PWR_EN
1
R84

2
0_0402_5%

2009/5/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/12/31

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Power OK, Reset,RTC, CIR, MDC


Document Number

NALG0 M/B LA-5681P Schematic


Friday, October 23, 2009

Sheet
E

39

of

60

Rev
1.0

1
R683

+5VAMP
+VDDA

C645
1

R672

1
1
L52 1
C652
C648
2
FBMA-L11-201209-221LMA30T_0805
10U_0805_10V4Z
2
2
0.1U_0402_16V4Z

Q50

2
B
E

LINE_L

41

LINE_R

1
C343 AMIC@
1
C342 AMIC@
LINE_L
1
C339
LINE_R
1
C338

MIC2_C_L
2
4.7U_0603_6.3V6M
MIC2_C_R
2
4.7U_0603_6.3V6M
LINE_C_L
2
4.7U_0603_6.3V6M
LINE_C_R
2
4.7U_0603_6.3V6M

MIC1_L

41

MIC1_R

MIC1_L
MIC1_R

MIC1_C_L
2
4.7U_0603_6.3V6M
MIC1_C_R
2
4.7U_0603_6.3V6M
MONO_IN

1
C341
1
C340

16

MIC2_L

SURR_L

39

HP_LEFT

17

MIC2_R

SURR_R

41

HP_RIGHT

LINE1_L

SIDE_L

LINE1_R

SIDE_R

2 10K_0402_1%
1 20K_0402_1%

R338 2

1 39.2K_0402_1%

PORT-A (PIN 39, 41)

20K

PORT-B (PIN 21, 22)

10K

PORT-C (PIN 23, 24)

39.2K
SENSE B

Codec Signals

39.2K

5.1K

HDA_GPIO0
HDA_GPIO3
SENSE_A

R334 1
R337 2

37

10K

PORT-G (PIN 43, 44)

5.1K

PORT-H (PIN 45, 46)

12

CD_L

CENTER

CD_R

LFE

CD_GND
BITCLK
MIC1_R

SDATA_IN

PCBEEP

PIN37_VREFO
LINE1_VREFO

RESET#
LINE2_VREFO
SYNC
MIC1_VREFO_L
SDATA_OUT

2
3
13
34

MIC1_VREFO_R
SPDIFO2
GPIO0/DMIC_CLK MIC2_VREFO
SENSE A
SENSE B
VREF

47

SPDIFI/EAPD

2 SPDIF_R 48
0_0402_5%
4
7

3
4

AMP_LEFT 41

1
R359 @

For EMI

44

DMIC_CLK_R

HP_RIGHT 41

DMIC_CLK_268

43

15mil

HP_LEFT 41

PAD

46

1
R346

DMIC_DATA_R
R366 AMIC@ 0_0603_5%

T7

SPDIFO

C368
220P_0402_50V7K
2 AMIC@

2 C356
22P_0402_50V8J

2
1
0_0402_5%

HDA_BITCLK_AUDIO 13
HDA_SDIN0_AUDIO

1
R344

2
33_0402_5%

Digital MIC

HDA_SDIN0 13

+3VS

37

JMIC2

29
DMIC_CLK
DMIC_DATA

31

10mil

28

MIC1_VREFO_R

30

MIC2_VREFO
CODEC_VREF

27
40

SENSE C

33

AVSS1
AVSS2

26
42

DMIC@
R372
R371
DMIC@

MIC1_VREFO_L

32

JDREF

GPIO1/DMIC_DATA
DVSS

0_0603_5%
0_0603_5%

10mil
1

@
C371
220P_0402_50V8J

C353
10U_0805_10V4Z
0.1U_0402_16V4Z
2
2
R358
20K_0402_1%

SPDIF_HDMI

AGND

DMIC_DATA
1
R700 @
SPDIF_HDMI 1
R702
DMIC_DATA
1
R698
DMIC_CLK
1
R357

5
6

G1
G2

2
@

C372
220P_0402_50V8J

1
R674

2
0_0805_5%

1
R691

2
0_0805_5%

1
R287

2
0_0805_5%

1
R663

2
0_0805_5%

HDA_GPIO0
0_0402_5%

1
R704

2
0_0805_5%

1
R658

2
0_0805_5%

2
0_0402_5%
@

HDA_GPIO3
0_0402_5%

GND

GNDA

GNDA

FBMA-L10-160808-301LMT_0603

Compal Electronics, Inc.

Compal Secret Data


2009/5/12

2009/12/31

Deciphered Date

Title

HD Audio Codec ALC888S-VC


Document Number

NALG0 M/B LA-5681P Schematic

Date:

GND

Issued Date

1
2
3
4

0_0402_5%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

1
2
3
4

DMIC_CLK_R
DMIC_DATA_R

ACES_88266-04001
CONN@

C351

Security Classification

DMIC_CLK
0_0402_5%

6
8

R365
2.2K_0402_5%
AMIC@

AMP_RIGHT 41

2
@

G1
G2
ACES_88266-02001
CONN@

MIC1_L

DGND

PORT-E (PIN 14, 15)


PORT-F (PIN 16, 17)

22

1
2

C360

45

ALC888S-VC_LQFP48_7x7
1
R695

PORT-D (PIN 35, 36)

20K

EAPD

C365
100P_0402_50V8J
1
R360
1
2
DMIC_DATA
1
2
0_0402_5%
1 R697
2
R696
@
0_0402_5%

21

1
2

AMP_RIGHT

13 HDA_SDOUT_AUDIO

Place close to Codec

AMP_LEFT

36

10

13 HDA_SYNC_AUDIO

DVDD

35

FRONT_R

11

13 HDA_RST_AUDIO#

DVDD_IO

FRONT_L

LINE2-R

19

JMIC3
DMIC_DATA_R
DMIC_CLK_R

MIC2_VREFO

LINE2-L

24

C679

15

20

41

C682

14

23

L18
1
2
+3VS
MBK1608121YZF_0603

+3VS_DVDD

R331 1K_0402_5%
1 INT_MIC_R
AMIC@

41

SPDIF

38

U28

25

40mil

18

41

C662

DMIC_CLK_R 2

4.75V

4.7U_0805_10V4Z

0.1U_0402_16V4Z
10U_0805_10V4Z
2
2
2
10U_0805_10V4Z

AVDD2

L53
FBMA-L11-160808-800LMT_0603
0.1U_0402_16V4Z
1
2
1
1
C350
C699
10U_0805_10V4Z
2
2

AVDD1

SENSE A

BYP

G9191-475T1U_SOT23-5
@

C669

ANALOG MIC
10mil

+VDDA

Impedance

SHDN

+VDDA
1

HD Audio Codec

+AVDD_HDA

Sense Pin

GND

268@
888VB@
888VC@

HP_PLUG#

40mil

2SC2411K_SOT23

D28
CH751H-40PT_SOD323-2

41

OUT

560_0402_5%

41 LINEIN_PLUG#
41 MIC_PLUG#

IN

0.01U_0402_16V7K

BOM Option
ALC268
ALC888S-VB
ALC888S-VC

MONO_IN

1U_0402_6.3V6K
1
2
R675
2.4K_0402_1%

560_0402_5%

1U_0402_6.3V6K

L51 1
2
FBMA-L11-201209-221LMA30T_0805

13,37 PCH_SPKR

C646
1
2
1

1U_0402_6.3V6K

R671

(output = 300 mA)

U40

C643
1

2
0_0805_5%

60mil

R676
20K_0402_5%

BEEP#

2
37

+5VS

D30
CH751H-40PT_SOD323-2
1

R781
10K_0402_5%

+3VS

Friday, October 23, 2009


G

Sheet

40
H

of

60

Rev
1.0

40
40

HP_LEFT

HP_RIGHT_C 1
2
2.2U_0805_10V6K
R340
HP_LEFT_C
2
1
2.2U_0805_10V6K
R339

2 100K_0402_5%

24

HP_EN

21

HP_RIGHT_R
39K_0402_5% HP_LEFT_R

VOL_AMP

39K_0402_5%

28
2
23

25

INR_A
INL_A

ROUT+
ROUT-

19
18

SPKR+
SPKR-

/AMP EN

LOUT+
LOUT-

5
6

SPKL+
SPKL-

HP_R
HP_L

13
16

HPOUT_R
HPOUT_L

NC
NC

3
14

HP_EN
INR_H
INL_H
SET

D5
SM05T1G_SOT23-3
@

HP_PLUG#

2
0.01U_0402_16V7K

4
1

SPDIF_PLUG#

APA2051QBI-TRG_TQFN28_4X4
C651
2.2U_0603_10V6K

Q49A
2N7002DW-T/R7_SOT363-6

D25
PJDLC05_SOT23-3

+5VSPDIF

20mil

C627
1
R662
56.2_0603_1%
HPOUT_L 1
HPOUT_L_1 1
2
L46
HPOUT_R 1
HPOUT_R_1 1
2
L45
R661
56.2_0603_1%

C707
0.047U_0402_16V7K

D24
PJDLC05_SOT23-3
@

C626

330P_0402_50V7K 330P_0402_50V7K
1
1

HPOUT_L_2
2
FBM-11-160808-700T_0603
HPOUT_R_2
2
FBM-11-160808-700T_0603

1
2
6
3

SPDIF_PLUG#

40

5
4
7
8
10

SPDIF

SPDIF
+5VSPDIF

C635
100P_0402_50V8J

JHP1

HP_EN

S/PDIF Out JACK


LINE Out/Headphone Out

Gain= 11dB
VOL_AMP 1
2
R681
5.1K_0402_5%

Q49B
2N7002DW-T/R7_SOT363-6

6 1

R659
100K_0402_5%

Q48
AO3413_SOT23-3

BIAS

EC_MUTE 37

C654
1U_0603_10V4Z

HP_PLUG# 40

C347

2
G
Q35
2N7002_SOT23

26
4
20
10
29

GND
PGND
PGND
CGND
GND

12

R660
100K_0402_5%

39K_0402_5%

CP+
CP-

CONN@

+5VAMP

D
R336

22

5
6

+5VAMP

C668
1U_0603_10V4Z
2

G1
G2

For ESD 10/11

9
11

1
VOL_AMP

1
2
3
4

15K_0402_5%
VSS

1
2
3
4

ACES_88266-04001

D4
SM05T1G_SOT23-3
@

VDD

7
17

15

SPK_L+
SPK_LSPK_R+
SPK_R-

0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%

2
2
2
2

R333

HP_RIGHT
1
C355
HP_LEFT
1
C354

HP_RIGHT

R684 1

1
1
1
1

HPF Fc = 604Hz

+5VAMP

27
1

JSPK1
R407
R406
R405
R404

2.2K_0402_5%
2

2.2K_0402_5%

SPKL+
SPKLSPKR+
SPKR-

PVDD
PVDD

U41

2 AMP_RIGHT_C
1U_0402_6.3V6K
2 AMP_LEFT_C
1U_0402_6.3V6K

HVDD

AMP_RIGHT_C-1
1
C673
AMP_LEFT_C-1
1
2
1
C689
C674
0.47U_0603_16V4Z
R693
R692

CVDD

AMP_LEFT

C688
0.47U_0603_16V4Z
1
2

AMP_RIGHT

C650
0.1U_0402_16V4Z
2

40
40

C649
C672
0.1U_0402_16V4Z
2
2
4.7U_0805_10V4Z

20mil

W=40mil
+3VS

Int. Speaker Conn.

+5VAMP

9
2

SINGA_2SJ-E373-T01
CONN@

40 LINEIN_PLUG#

LINE-IN JACK
JLINE1
8
7

D27
PJDLC05_SOT23-3
LINEIN_PLUG# 5
@

LINE_L

LINE_L_1 1
2
L49
FBM-11-160808-700T_06031
C639
220P_0402_50V7K

1
MIC1_R

40

MIC1_L

40

R664
2.2K_0402_5%
R666
L48
75_0603_1%
FBM-11-160808-700T_0603
1
2 MIC1_R_1 1
2

R665
75_0603_1%

MIC1_L_1

1
2
L47
FBM-11-160808-700T_0603
1
C637
220P_0402_50V7K

(HDA Jack)

MIC JACK

MIC_PLUG#
JMIC1

MIC1_VREFO_R

8
7

R667
2.2K_0402_5%

5
4

MIC1_R_R

3
6
2
1

MIC1_L_R
1

SINGA_2SJ-E351-S01
CONN@
D26
@
PJDLC05_SOT23-3

C638
2

SINGA_2SJ-E351-S03
CONN@

C640
220P_0402_50V7K

40
MIC1_VREFO_L

For ESD
I/O status:
a. input/output mount 75 ohm
b. input only mount 1K ohm

LINE_L_R

3
6
2
1

2
R669
75_0603_1%

40

4
LINE_R_R

LINE_R

40

R670
L50
75_0603_1%
FBM-11-160808-700T_0603
LINE_R_1 1
1
2
2

(HDA Jack)

220P_0402_50V7K

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/5/12

Issued Date

Deciphered Date

2009/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Amplifier & Audio Jack


Document Number

NALG0 M/B LA-5681P Schematic


Friday, October 23, 2009

41

Sheet
E

of

60

Rev
1.0

FAN1 Conn
+5VS
C105
1

10U_0805_10V4Z
2

U10

+3VS

H9
H_4P2

H10
H_4P2
@

H16
H_3P2
@
1

H13
H_4P2
@

H11
H_3P2
@

H12
H_4P2
@

C123
1000P_0402_50V7K
1
2

H3
H_3P2
@

H4
H_3P7
@

@
1

C134
10U_0805_10V4Z
1
2

H2
H_3P2
@

APL5607KI-TRG_SO8

H15
H_3P2
@

H8
H_3P2
@

H1
H_3P2

8
7
6
5

EN_DFAN1

GND
GND
GND
GND

R60
10K_0402_5%
H14
H_3P2
@

Issued Date

FIDUCIAL_C40M80

FD4
@

FIDUCIAL_C40M80

FD3
@

FIDUCIAL_C40M80

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/5/12

H_3P3

FIDUCIAL_C40M80

H_3P3

1
FD1

FD2

H7
H_10P0X6P0N
@

H18
H21
H_4P7X3P7N H_5P1X4P1N
@
@

H22
H_3P2
@

H19
H_3P2
@

H23
H_3P2
@

ACES_85205-03001
CONN@

H20
H_3P2
@

H24
H_3P2
@

C131
1000P_0402_50V7K

H17
H_3P2

1
2
3

Jfan1

FAN_SPEED1

37

+VCC_FAN1

40mil
2

37

EN
VIN
VOUT
VSET

+VCC_FAN1

1
2
3
4

Deciphered Date

2009/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

FAN & COVER LIGHT& Screw Hole


Document Number

NALG0 M/B LA-5681P Schematic


Friday, October 23, 2009

Sheet

42

of

60

Rev
1.0

+1.5V to +1.5VSDGPU Transfer


+5VALW
4

C691

C434
10U_0805_10V4Z
DIS@

Q56A
0.1U_0603_25V7K
2
2N7002DW-T/R7_SOT363-6

D
D
D
D

1
2
3
4

S
S
S
G

6
Q57A
DIS@

37,51

SYSON

SYSON

2N7002DW-T/R7_SOT363-6
1

R708
100K_0402_5%

1
1
C427
C426
DIS@
DIS@
10U_0805_10V4Z
2
2
0.1U_0402_16V4Z

SI4856ADY_SO8
DIS@

R441
470_0603_5%
DIS@

8
7
6
5

SYSON#

SYSON#

C706

250mil(6A)

U33

SUSP

35
1

10U_0805_6.3V6M

JUMP_43X118

10U_0805_6.3V6M

2
470_0603_5%

DIS@

C705

R709

3 1

SUSP

Q56B
2N7002DW-T/R7_SOT363-6

5VS_GATE

2
1
R699
200K_0402_5%

+VSB

SI4800BDY-T1-E3_SO8

C697

1U_0603_10V4Z

@
3
2
1
1 C696

10U_0805_10V4Z

C676

R711
100K_0402_5%
PJ25

5
6
7
8

10U_0805_10V4Z

10U_0805_10V4Z

C675
1

+5VALW

+1.5VSDGPU

+5VS
U42

+1.5V

+5VALW TO +5VS

1.5VSDGPU_GATE
DIS@ 2
510K_0402_1%

Q37B

Q37A

+3VALW TO +3VS
+3VALW

DIS@ 2
0_0402_5%

2
DIS@
2N7002DW-T/R7_SOT363-6

DIS@ 2 VGA_ON#
0_0402_5%

R728

2.2M_0402_1%

2
ACIN

2
G

R703
100K_0402_5%

39,50

SUSP

SUSP

Q57B
5

37,39,48,50 SUSP#
1

2N7002DW-T/R7_SOT363-6
R705
10K_0402_5%

+1.8VS to +1.8VSDGPU Transfer

SUSP
1

+VSB

R451
510K_0402_1%
DIS@ 2

VGA_ON#

1
R454

DIS@ 2
0_0402_5%

+5VALW
2N7002DW-T/R7_SOT363-6

1.8VSDGPU_GATE

Q40B
5
1

0.1U_0603_25V7K
2
Q31A
2N7002DW-T/R7_SOT363-6

R458
470_0603_5%
DIS@

Q40A
2
DIS@
2N7002DW-T/R7_SOT363-6

1
R449

DIS@
C433
0.1U_0603_25V7K
DIS@

VGA_ON#
DIS@ 2
0_0402_5%

DIS@

R326

2
1

VGA_ON#

VGA_ON#

R299
2.2M_0402_1%
@

2.2M_0402_1%

D
Q58
@

2
G

1
R459
100K_0402_5% DIS@

ACIN

+1.05VSDGPU

2N7002_SOT23

2N7002_SOT23
Q30
@

2
G
DIS@
Q41
S
2N7002_SOT23

24,39,52 VGA_ON
1

2
G

15,37,44,45 ACIN

R456
100K_0402_5%
1

C296

1
C443
C437
DIS@
DIS@
10U_0805_10V4Z
2
2
0.1U_0402_16V4Z

100mil(1.5A)
1

3 1

3 1

470_0603_5%

Q31B
2N7002DW-T/R7_SOT363-6
1

U34
8
7
6
5

C442
10U_0805_10V4Z
DIS@

DIS@
SI4800BDY-T1-E3_SO8
1
2
3

R295

1.5VS_GATE

SUSP

C294

10U_0805_10V4Z
2
2
1U_0603_10V4Z

C293

U26

2
1
R296
47K_0402_5%

JUMP_43X118

10U_0805_10V4Z
2
2
10U_0805_10V4Z

+VSB

C279

SI4856ADY_SO8
D
G 4
D
S 3
2
D
S
D
S 1

5
6
7
8

+1.8VSDGPU
PJ26
2

C281

+1.8VS

+1.5VS

+1.5V to +1.5VS
+1.5V

2 SUSP
G
Q55
2N7002_SOT23

S
5VS_GATE

2N7002_SOT23
Q59
@

R707

1 1

+5VALW

D
470_0603_5%

SI4800BDY-T1-E3_SO8

C692

1U_0603_10V4Z

3
2
1
1 C695

10U_0805_10V4Z

C685

1
R440

5
6
7
8

10U_0805_10V4Z

10U_0805_10V4Z

U43

C686

VGA_ON#

+3VS

2N7002DW-T/R7_SOT363-6
5
1
R439

DIS@
C428
0.1U_0603_25V7K
DIS@

1
R444

+VSB

+1.05VS

+0.75VS

+1.8VS

DIS@

+1.5V

R499
470_0603_5%

D
DIS@

2 VGA_ON#
G
Q42
2N7002_SOT23

D
2 SUSP
G
Q52
2N7002_SOT23

R687
470_0603_5%
@

D
2 SUSP
G
Q39
2N7002_SOT23

2
1
1

1
D
2 SUSP
G
Q46
2N7002_SOT23

R453
470_0603_5%

D
2 SUSP
G
Q5
2N7002_SOT23

R688
22_0402_5%

R654
470_0603_5%

R32
470_0603_5%
4

+1.1VS_VTT

2 SYSON#
G
Q51
2N7002_SOT23
@

2009/5/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2009/12/31

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

DC Interface
Document Number

NALG0 M/B LA-5681P Schematic


Friday, October 23, 2009

Sheet
E

43

of

60

Rev
1.0

MEDIA_LED

Enlightener LED
+3VALW

2
191_0402_1%

(BLUE)

R377
243_0402_1%

R375
470_0402_5%
D

2
191_0402_1%

LED1

1
LED2
HT-191NBQA_BLUE_0603

PW R_LED#
1
HT-191NBQA_BLUE_0603

1
R367

PW R_LED#
1
HT-191NBQA_BLUE_0603

LED3
HT-191NBQA_BLUE_0603

MEDIA_LED#

NUM_LED#

ACIN#

LED4
HT-191NBQA_BLUE_0603

2
243_0402_1%

1
R373

1
1

R376
470_0402_5%

LED5

LED6
HT-191NBQA_BLUE_0603

ACIN#

2
PW R_LED#
1
HT-191NBQA_BLUE_0603

1
R386

+3VS

+3VS

(BLUE)

LED8

R383
100_0402_1%

LED7
HT-191NBQA_BLUE_0603

CAPS_LED

+3VS

(BLUE)

(BLUE)

R381
100_0402_1%
D

NUM_LED

+3VS

ON/OFF LED LEFT

+3VALW

(BLUE)

NUM_LED# 37

CAPS_LED#

CAPS_LED# 37

+3VS

5IN1_LED#
SATA_LED#

ACIN#

+3VS

1
3

S 2N7002_SOT23

MEDIA_LED#

Q14B
2N7002DW -T/R7_SOT363-6
C

Q18

2
G

15,37,43,45 ACIN

1
SATA_LED#

36
13

Q14A
2N7002DW -T/R7_SOT363-6

PW R_LED#
Q36A
2N7002DW -T/R7_SOT363-6

PW R_LED

37

R342

10K_0402_5%

PW R_SUSP_LED#
B

Q36B
2N7002DW -T/R7_SOT363-6

5
4

37 PW R_SUSP_LED
R341

10K_0402_5%

Compal Footprint
3

Blue

Amber

LED11
+3VALW
+3VALW

1
R349
1
R350

2
2
100_0402_1%
2
4
191_0402_1%

PW R_LED#

LED10

3PW R_SUSP_LED#

1
R351

2
2
191_0402_1%

BATT_Blue_LED# 37

+3VALW

1
R352

2
4
470_0402_5%

BATT_Amber_LED# 37

HT-297UD/CB _BLUE/AMB_0603

Blue

+3VALW

AMB
HT-297UD/CB _BLUE/AMB_0603

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/5/12

Issued Date

Deciphered Date

2009/12/31

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

PWR/B
Size
Document Number
Custom

Rev

1.0
NALG0 M/B LA-5681P Schematic

Date:

Friday, October 23, 2009

Sheet
1

44

of

60

MCVCC

2
G

Min.
H-->L 16.976V
L-->H 17.430V

Max.
17.728V
18.384V

1
PQ4
@ 2N7002W -T/R7_SOT323-3
2
SPOK
G

PJ1

+1.05VSP
3

Typ
17.525V
17.901V

PR12
@ 200K_0402_1%

2
G
D

RTCVREF

Vin Dectector

RTCVREF

@ PR11
200K_0402_1%

PC6
1000P_0402_50V7K

PQ2
@ SI2301BDS-T1-E3_SOT23-3

+3VALWP

PR10
10K_0402_1%
1
2

2
10_0603_5%

PQ1
@ SI2301BDS-T1-E3_SOT23-3

PR7
20K_0402_1%

PR9
1

8
+

PU1A
LM358DT_SO8
PD1
GLZ4.3B_LL34-2

PR8
10K_0402_1%

PR4
22K_0402_5%
1
2

PC5
0.1U_0603_25V7K
2
1

2 1

P
1

15,37,43,44 ACIN

PR3
84.5K_0402_1%
PR6
10K_0402_1%

PC4
1000P_0402_50V7K

PR5
0_0402_5%
1
2
1

PC2
100P_0402_50V8J

VIN

VS

@ PR2
10K_0402_5%

48,49 PACIN

1
PC1
1000P_0402_50V7K

PC3
100P_0402_50V8J

PJP1

VIN

VIN
2DC_IN_S2

2
1

G
G

PL1
SMB3025500YA_2P
1

DC_IN_S1

<BOM Structure>
SINGA_2DC-G756I200

PR1
1M_0402_1%
1
2

DC231000500

@ PQ3
2N7002W -T/R7_SOT323-3

PJ4

+1.05VS

+VGFX_COREP

+VGFX_CORE

JUMP_43X118
PJ2
2 2
1 1

JUMP_43X118
PJ5
2 2
1 1

JUMP_43X118

JUMP_43X118

46,47

VIN

PJ7

+3VALWP

PD2
LL4148_LL34-2

JUMP_43X118

JUMP_43X118

1
PQ5
TP0610K-T1-E3_SOT23-3
N1

PR13
68_1206_5%

+5VALWP

PJ10

+5VALW

+1.1VS_VTTP

JUMP_43X118

39

51ON#

VS
1

+1.1VS_VTT

PJ31

+VSB

+1.1VS_VTT

JUMP_43X39

+1.05VS

JUMP_43X118

JUMP_43X118

PJ8

+VSBP

PC8
0.1U_0603_25V7K

PC7
0.22U_0603_25V7K

PR16
100K_0402_1%

JUMP_43X118
PJ12
2 2
1 1

PJ6
PR14
68_1206_5%

PR15
200_0603_5%
CHGRTCP 1
2

PR17
22K_0402_1%
1
2

+1.5V

JUMP_43X118
PJ9
2 2
1 1

+3VALW

BATT+

PD3
LL4148_LL34-2
2
1

+1.5VP

PJ3

PJ32
2

JUMP_43X118
PJ11

+1.8VSP

OUT

IN
GND

PC9
10U_0805_10V4Z

+1.8VS

+VGA_COREP

PJ14
2

PJ13

+0.75VSP

+VGA_CORE

JUMP_43X118
1

+0.75VS

JUMP_43X79
PC10
1U_0805_25V4Z

PBJ1
2

+
1

ML1220T13RE
<BOM Structure>

+RTCBATT
+RTCBATT

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

2007/09/20

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

JUMP_43X118
PJ15
2 2
1 1

N2

PR18
200_0603_5%

PU2
G920AT24U_SOT89-3

3.3V

JUMP_43X118

PR20
560_0603_5%
1
2

+CHGRTC

PR19
560_0603_5%
1
2

RTCVREF

DCIN & DETECTOR


Rev
0.1

NALG0

Friday, October 23, 2009


D

Sheet

45

of

60

PH1 under CPU botten side :


CPU thermal protection at 92 degree C
VL
VL
VL
2

VMB
PR21
47K_0402_1%

PR22
47K_0402_1%
1
2
3

PQ6
2
G

1
LL4148_LL34-2

2N7002W -T/R7_SOT323-3

PR169
1M_0402_1%
VL

PR29
100K_0402_1%

PR30
1K_0402_1%

PR27
100K_0402_1%
2
1

1
2

+3VALWP

PC15
1000P_0402_50V7K

1
2

PR26
15.8K_0402_1%

PR28
6.49K_0402_1%
2
1

PR25
100_0402_1%

PC14
0.22U_0603_16V7K

PU3A
LM393DG_SO8

2
PR24
100_0402_1%
1

PD4
1

TM_REF1

SUYIN_250133MR007G115ZL

PR23
12.4K_0402_1%
1
2

PC13
0.01U_0402_25V7K

PC12
1000P_0402_50V7K

MAINPW ON 18,47,49
1

PC11
0.1U_0603_25V7K

PH1
100K_0402_1%_NCP15W F104F03RC
2

EC_SMCA
EC_SMDA

BATT+
1

BATT_S1

1
2
3
4
5
6
7

1
2
3
4
5
6
7

PL2
SMB3025500YA_2P
1
2

PJP2

BATT_TEMP 37

PH2 near main Battery CONN :


BAT. thermal protection at 79 degree C

EC_SMB_CK1 37
EC_SMB_DA1 37

VL

@ PR31
47K_0402_1%

@ PR32
47K_0402_1%
1
2

PQ7
TP0610K-T1-E3_SOT23-3
@ PH2
100K_0402_1%_NCP15W F104F03RC

8
O
-

@ PR36
15.4K_0402_1%

PU3B
LM393DG_SO8

@ PC18
0.22U_0603_16V7K

@ PD5
LL4148_LL34-2
2
1

5
TM_REF1

1
2

@ PR34
13.7K_0402_1%
1
2

PC17
0.1U_0603_25V7K

PR35
22K_0402_1%
1
2

VL

VL

+VSBP

1
PR33
100K_0402_1%

PC16
0.22U_1206_25V7K

B+

VL

PQ8
2
G

PR38
0_0402_5%
2

45,47 SPOK

PC19
0.1U_0402_16V7K

PR37
100K_0402_1%

2N7002W -T/R7_SOT323-3

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Deciphered Date

2008/09/20

Title

BATTERY CONN / OTP

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
0.1

NALG0

Friday, October 23, 2009


D

Sheet

46

of

60

ISL6237_B+

ISL6237_B+
PR39
0_0805_5%
1
2

PJ16

PHASE2

PHASE1

16

LX5

LGATE1

18

DL5

23

LGATE2

2
1

Rds(on)=15m ohm(typ)
18m ohm(max)

VL

30

OUT2

32

REFIN2

PGND

22

OUT1

10

FB1

11

BYP

SKIP

29

Rds(on)=15m ohm(typ)
18m ohm(max)

LDOREFIN

@ PR48
2

GND

ILIM1

12

ILIM2

31

ILIM2

PR52
330K_0402_1%
2
1

PC27
2200P_0402_50V7K
2
1

45,46

pull high VL=5V


B

PR53
330K_0402_1%

ISL6237IRZ-T_QFN32_5X5

PR57
0_0402_5%

+5VALWP Ipeak=7A ; Imax=4.9A


Choke DCRmax=40m ohm, DCRtyp=37m ohm
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Vlimit=(5E-06 * 330K)/10=165mV
Ilimit=165mV/18m ~ 165mV/15m
=9.167A ~ 11A
Iocp=Ilimit+Delta I/2
=10.147A ~ 11.980A
Delta I=1.96A (Freq=400KHz)

PC40
1U_0603_10V6K
1
2

2VREF_ISL6237

VL

SPOK
ILM1

21

EN2

27

TON

13

1
1
2

POK1

0_0402_5%
1
0_0402_5%
2

@ PC42
0.047U_0402_16V7K

PQ13
TP0610K-T1-E3_SOT23-3

EN_LDO
EN1

2
PR55
0_0402_5%
1
2

2
1

@ PR59
47K_0402_5%
1
2

PC41
0.047U_0402_16V7K

18,46,49 MAINPWON

28

14

@ PR54
0_0402_5%

PR56
806K_0603_1%

POK2

2VREF_ISL6237

2
1

PC39
0.22U_0603_25V7K

NC

PR51
200K_0402_5%
1
2

PR58
0_0402_5%
2

PC26
4.7U_1206_25V6K
2
1

REF

NC

20

PR50
100K_0402_1%
1
2

VL

+ PC37
C
150U_D2E_6.3VM_R18

FB5

PR49
1

PD15
1SS355_SOD323-2

0.22U_0603_10V7K

PD6
GLZ5.1B_LL34-2
1
2

PQ12
AO4712_SO8

25

DL3

PC38

PR44 2.2_0603_5%
BST5A 2
1

PR45
63.4K_0402_1%

17

PR47
10K_0402_1%
1
2

BOOT1

DCR=37m ohm(typ)
40m ohm(max)

PR42
4.7_1206_5%
2
1

BOOT2

DH5

PL4
4.7UH_PCMC063T-4R7MN_5.5A_20%
2
1

PC36
680P_0402_50V7K
2
1

15

2VREF_ISL6237

+3.3VALWP Ipeak=7A ; Imax=4.9A


Choke DCRmax=40m ohm, DCRtyp=37m ohm
Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
Vlimit=(5E-06 * 330K)/10=165mV
Ilimit=165mV/18m ~ 165mV/15m
=9.167A ~ 11A
VS
Iocp=Ilimit+Delta I/2
=10.134A ~ 11.967A
Delta I=1.934A (Freq=300KHz)

3
2
1

UGATE1

5
6
7
8

7
LDO

UGATE2

PC31
1U_0603_10V6K
1
2

PC34
0.1U_0603_25V7K
LX3

FB3
@ PR46
10K_0402_1%

5
6
7
8

PC30
4.7U_0603_6.3V6M
2
1

PC29
1U_0603_10V6K
1
2

3
VCC

24

19

PC33
0.1U_0603_25V7K

1
2
3

PC35
680P_0402_50V7K

PVCC

3
2
1

2
C

PR43
2
1 BST3A
2.2_0603_5%

26

+5VALWP

PQ11
AO4712_SO8

PR40
0_0402_5%

PC32
330U_D2E_6.3VM_R25M

DH3

TP

PQ10
AO4466_SO8
4

PR41
4.7_1206_5%

1
1

8
7
6
5

PU4

33

VIN

PL3
4.7UH_PCMC063T-4R7MN_5.5A_20%
1
2

+3VALWP

1
2
3

DCR=37m ohm(typ)
40m ohm(max)

PC28
0.1U_0603_25V7K

PQ9
AO4466_SO8
4

8
7
6
5

PC22
4.7U_1206_25V6K
2
1

PC21
2200P_0402_50V7K
2
1

VL

PC25
4.7U_1206_25V6K
2
1

PC24
2200P_0402_50V7K
2
1

PC23
4.7U_1206_25V6K
2
1

JUMP_43X118
PC20
2200P_0402_50V7K
2
1

B+

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Issued Date

Deciphered Date

2008/09/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

+5VALWP/+3VALWP
Size
Document Number
Custom
Date:

Rev
0.1

NALG0

Friday, October 23, 2009

Sheet
1

47

of

60

Iada=0~4.74A(90W/19V=4.736A)
Iada=0~3.42A(90W/19V=3.421A)

P2

B+

P3

PQ15 AO4407A_SO8

CHG_B+

B+

PR60 0.02_2512_1%

PQ16 AO4407A_SO8

PJ17

23

EN

CSON

22

CELLS

CSOP

21

ICOMP

CSIN

20

VCOMP

CSIP

19

ICM

PHASE

18

PR72
20_0402_5%
1
2
PC53
0.047U_0402_16V7K
1
2
PR73
20_0402_5%
2
1
PR74
PC56
20_0402_5%
0.1U_0603_25V7K
1
2
PR76
2_0402_5%
LX_CHG

PR77
100_0402_1%
1
2

VREF

UGATE

17

DH_CHG

CHLIM

BOOT

16

ACLIM

VDDP

15

VADJ

LGATE

14

GND

PGND

13

CP mode
Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05)
where Vaclm=1.502V, Iinput=4.07A

37 65W/90W#

PQ29
2
G

12

3
5
6
7
8

PR86
4.7_0603_5%
PC64
4.7U_0603_6.3V6M

2N7002W -T/R7_SOT323-3

<40,41>

Per cell=3.5V

Vcell = (0.175 * Vadj) + 3.99


2

4.35V
37 BATT_OVP

PR91
499K_0402_1%

Normal 3S LI-ON Cells

12600mV

PC66
0.01U_0402_25V7K

PR93
105K_0402_1%

CV mode

4.20V

PU1B
LM358DT_SO8
7 0

1.899V

PR92
10K_0402_1%
1
2

3.3V

Pre Cell

CALIBRATE#

PR89
340K_0402_1%
2

BATT-OVP=0.1112*VMB

IREF=0.7224*Icharge

VS

LI-3S :13.5V----BATT-OVP=1.5012V
PC65
0.01U_0402_25V7K

PR88
15.4K_0402_1%
1
2

VMB

0826 PR88 18.2K change to 15.4K


CALIBRATE# = 1.899V
Kv=9.451
PR90
31.6K_0402_1%

Charging Voltage
(0x15)

ISL6251AHAZ-T_QSOP24

CC=0.6~4.48A

BATT Type

2
1

RB751V-40_SOD323-2
1
26251VDD

6251VDDP
DL_CHG

12.60V

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2007/09/20

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

BATT+

4 PR78
0.02_1206_1%
3

PQ27
@
AO4466_SO8

3
2
1

11

CHG

37 CALIBRATE#

IREF=0.43V~3.24V

PL5
10UH_PCMB104T-100MS_6A_20%
1
2

10

<40,41>

TCR=50ppm / C

PC59
0.1U_0603_25V7K
2 BST_CHGA 2
1
PD12

6251aclim
20K_0402_1%
PR87

11.5K_0402_1%

2 PACIN
2N7002W
-T/R7_SOT323-3
G
S

PR84
6251VREF 1

PQ23D

5
6
7
8

0.1U_0402_16V7K

PR82
0_0603_5%
BST_CHG 1

PQ25
AO4466_SO8

6251VREF

PC58
1
2

PR85
2.37K_0402_1%

PR83
100K_0402_1%

CSOP

IREF

ADP_I

37

CSON

3
2
1

2 10K_0402_1%

2
PC57
@ 100P_0402_50V8J

PR81
80.6K_0402_1%
2
1

PC63
10U_1206_25V6M
2
1

ACSET ACPRN

PC62
10U_1206_25V6M
2
1

24

VIN

PD11

PR80
4.7_1206_5%

DCIN

ACOFF

1SS355_SOD323-2
PR67
200K_0402_1%
1
2

1SS355_SOD323-2

VDD

PD8

PC61
680P_0402_50V7K

DCIN

wrong Value
PC50
0.1U_0603_25V7K
2
1

37

PR79
22K_0402_5%
1
2

ACOFF

1 PR75

PC55
0.01U_0402_25V7K

2
1
PC60
0.01U_0402_25V7K
2
1

PACIN

PQ20
PDTC115EU_SOT323

VIN

FSTCHG 37
SUSP# 37,39,43,50

6251_EN

6800P_0402_25V7K
2

ACON

PQ28
PDTC115EU_SOT323

ACOFF

2N7002W -T/R7_SOT323-3
3

PACIN

SUSP#

PC54
1

FSTCHG

PR61
47K_0402_1%
1
2

1
3
PU5

3S/4S#

2
1

8
7
6
5

PR65
10K_0402_1%

BAS40CW _SOT323-3

PC49
2.2U_0603_6.3V6K
2
1

1
2

100K_0402_1%

ACON

37,49

37

PQ26
2
G

45,49

PQ24
PDTC115EU_SOT323

49

PR66
2

D
2N7002W -T/R7_SOT323-3

PQ22
2
G

1
2
PC51
0.1U_0402_16V7K

PR70 47K_0402_5%
2

100K_0402_1%

PR69
150K_0402_1%

PR68
10K_0402_5%
2
1

FSTCHG

PQ18
PDTC115EU_SOT323
PD9

PR71

37
6251VDD

DCIN

PD10 1SS355_SOD323-2
6251VDD
1
2

47K

PQ21
PDTC115EU_SOT323

P3

PR64
100K_0402_1%
2
1

1
1
2
3

PC48
0.1U_0603_25V7K
2

PR63
200K_0402_1%

PQ17 TP0610K-T1-E3_SOT23-3

PQ19
PDTA144EU_SOT323-3

47K
2

CSIP

PC43
5600P_0402_25V7K
1
2

4
1
PR62
47K_0402_1%

CSIN

JUMP_43X118

1
2
3

PC52
0.1U_0603_25V7K
2
1

1 1

PC47
2200P_0402_25V7K
2
1

8
7
6
5

PC46
0.1U_0603_25V7K
2
1

1
2
3

1
2
3

PC45
10U_1206_25V6M
2
1

8
7
6
5

PC44
10U_1206_25V6M
2
1

VIN

CP = 85%*Iada ; CP = 4.07A
CP = 85%*Iada ; CP = 2.91A

ADP_I = 19.9*Iadapter*Rsense

PQ14 AO4407A_SO8

CHARGER
Rev
0.1

NALG0

Friday, October 23, 2009


D

Sheet

48

of

60

VS

PU6A

LM393DG_SO8

B+

PR95
2.2M_0402_5%
1

PR94
1K_1206_5%
1
2

PR102

PR105
100K_0402_5%

1
2
2

PQ31
PDTC115EU_SOT323
PR107
47K_0402_5%
2
2
1
2N7002W
-T/R7_SOT323-3
G

37,48

ACOFF

PQ33
PDTC115EU_SOT323

PACIN 45,48

PQ32D

B+

1 2

PR106
34K_0402_1%
2
1

PC69
0.01U_0402_25V7K

PR104
499K_0402_1%

2
1
PR103
191K_0402_1%
PRG++ 2

LM393DG_SO8

PC67
0.1U_0603_25V7K

RTCVREF

6
32.4

BAS40CW _SOT323-3

PC68
1000P_0402_50V7K

ACON

48

PR100
1K_1206_5%
1
2

PU6B

PR99
1K_1206_5%
1
2

PD14

1
LL4148_LL34-2

18,46,47 MAINPWON

TP0610K-T1-E3_SOT23-3
PQ30

PR97
1K_1206_5%
1
2

PD13
2

100K_0402_5%

VS

PR98
100K_0402_1%

VIN

PR96
499K_0402_1%

100K_0402_5%

PR101
1

VL

PQ57
PDTC115EU_SOT323

@ PR108
66.5K_0402_1%

+5VALW

ACIN

Precharge detector
Min.
typ.
Max.
H-->L 14.589V 14.84V 15.243V
L-->H 15.562V 15.97V 16.388V

BATT ONLY
Precharge detector
Min.
typ.
Max.
H-->L 6.138V 6.214V 6.359V
L-->H 7.196V 7.349V 7.505V

2007/09/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2008/09/20

Title

PRECHARGE

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Rev
0.1

NALG0

Friday, October 23, 2009

Sheet
1

49

of

60

B+

3
2
1

1
2

PC71
4.7U_0805_25V6-K

PC76
4.7U_0805_10V6K

Rds(on)=15m ohm(typ)
18m ohm(max)

1
2

+1.5V

GND

EN/SYNC

SW

IN

SW

IN

POK

2
PC79
4.7U_0603_6.3V6M

NC

REFEN

NC

VOUT

NC

PR119
1K_0402_1%

GND

PR120

change to 12.4K

PC82
0.1U_0402_16V7K

PR121
2N7002W -T/R7_SOT323-3
S
1K_0402_1%

+0.75VSP
1

39,43 SUSP

PQ60
2
G

PC81
0.1U_0402_16V7K
2
1

MP2121DQ-LF-Z_QFN10_3X3

PR120
12.4K_0402_1%
1
2

B340A_SMA2

@ PD16

11

TP

BS

PC124
10U_0805_10V4Z

PC123
10U_0805_10V4Z

PC80
1U_0402_6.3V6K

APL5336KAI-TRL SO8

+5VALW

+3VALW
1

VS_ON 39,51,53

@ PC73
0.1U_0402_16V7K

VCNTL

GND

10

GND

VIN

FB

PU8
1

SUSP# 37,39,43,48

1
.1U_0402_16V7K
1

PC127

PJ19
JUMP_43X79

PU17

@ PR111
0_0402_5%
2
1

+1.8VSP

PR110
0_0402_5%
2
1

@ PR171
0_0402_5%

PR173
402K_0402_1%
1
2

JUMP_43X118
1.8V_EN
2

PR174
316K_0402_1%

VFB=0.8V

LX_1.8V-1

PR113
47K_0402_5%
2
1

Cesr=15m ohm
Ipeak=3.98A Imax=2.786A
Delta I=((19-1.8)*(1.8/19))/(L*Freq)=2.469A
Vtrip=Rtrip*10uA=0.0768V
Iocp-min=Vtrip/(Rds(on)(max)*1.2)+Delta I / 2 = 4.79A
Iocp-max=Vtrip/(Rds(on)(typ)*1.2)+Delta I / 2 = 5.5A
Iocp=4.79~5.5A

@ PJ33
1

PC219
22U_0805_6.3V6M

VFB=0.75V
Vo=VFB*(1+PR117/PR118)=1.8V
Ton=19E-12*Ron*(((2/3)*Vo+100mV)/Vin)+50ns=4.14E-7
Freq=282KHz

@ PR118
41.2K_0402_1%

PC218
22U_0805_6.3V6M

@ PC75
680P_0603_50V8J

VFB=0.75V

PC74
330U_6.3V_M

+
2

RT8209BGQW _W QFN14_3P5X3P5

LG_1.8V

@ PR114
4.7_1206_5%

@ PQ59
AO4712_SO8

LGATE

+5VALW

VDDP

10

0_0603_5%

11

CS

@ PR170
1

LX_1.8V

+1.8VSP

12

5
6
7
8

PHASE

PL6
2.2UH_MSCDRI-74A-2R2M-E_6.5A_20%
1
2

LX_1.8V-1

0.1U_0603_25V7K

2
@ PR117
59K_0402_1%
1
2

3
2
1

14

NC
8

PGND

FB

UG_1.8V

PC72
2

VDD

UGATE

13

@
BST_1.8V-1 1

PR112
0_0603_5%
1
2

BOOT

VOUT

@ PC78
47P_0402_50V8J
1
2

DCR=18m ohm(typ)
20m ohm(max)

@ PC77
4.7U_0603_6.3V6K

15

TON

6
open-drain PGOOD

Layout Note:
Place near V5FILT Pin

EN/DEM

GND

@ PR115 100_0603_1%
1
2

BST_1.8V

@ PU7

JUMP_43X118

1.8V_EN

+5VALW

5
6
7
8

PR109
280K_0402_1%
1
2

@ PQ58
AO4466_SO8

PR116
7.68K_0402_1%

EN_PSV
1. GND=>Disable SMPS
2. FLOAT=>PWM_only mode
3. HIGH=>Auto_skip mode

PC70
4.7U_0805_25V6-K

@ PJ18
51117_1.8V_B+

PC83
10U_0805_6.3V6M

PC127 change to SE076104K80

2007/09/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

+1.8VSP/+0.75VSP
Rev
0.1

NALG0

Friday, October 23, 2009

Sheet
1

50

of

60

B+

PC85
4.7U_0805_25V6-K

RT8209BGQW _W QFN14_3P5X3P5

PC90
4.7U_0805_10V6K

1
+
2

4
PR297
11K_0402_1%

LG_1.5V

PC88
330U_D2E_2.5VM

VFB=0.75V
Vo=VFB*(1+PR298/PR299)=1.52V
Ton=19E-12*Ron*(((2/3)*Vo+100mV)/Vin)+50ns=3.8E-7
Freq=282KHz(min) , 300KHz(typ)

@ PC89
680P_0603_50V8J

NC
PGND

LGATE

@ PR295
4.7_1206_5%

PQ62
AO4456_SO8

VDDP

10

+5VALW

+1.5VP

LX_1.5V

11

Cesr=15m ohm
Ipeak=15.58A Imax=10.906A
Delta I=((19-1.5)*(1.5/19))/(L*Freq)=4.61A
Vtrip=Rtrip*10uA=0.11V
Iocp-min=Vtrip/(Rds(on)(max)*1.2)+Delta I / 2= 18.674A
Iocp-max=Vtrip/(Rds(on)(typ)*1.2)+Delta I / 2=22.675A
Iocp=18.674~22.675A

Rds=4.5m(Typ)
5.6m(Max)

VFB=0.75V

PR298
59K_0402_1%
1
2

3
2
1
12

CS

5
6
7
8

PHASE

0.1U_0603_25V7K

PC91
4.7U_0603_6.3V6K

@ PC92
47P_0402_50V8J
1
2

Layout Note:
Place near V5FILT Pin

6
open-drain PGOOD

+5VALW

FB
GND

PR296
100_0603_1%
1
2

3
2
1

VDD

UGATE

UG_1.5V

4
5

PL7
1UH_PCMB103T-1R0MS_13A_20%
1
2

PC86
1

VOUT

BOOT

TON

13

PR125
0_0603_5%
1
2BST_1.5V-1

14

1
EN/DEM

@ PC87
0.1U_0402_16V7K

@ PR124
47K_0402_5%

15

BST_1.5V

PU9
1

37,43 SYSON

JUMP_43X118

1.5V_EN
PR123
0_0402_5%
1
2

PR122
280K_0402_1%
1
2

5
6
7
8
PQ61
AO4466_SO8

51117_1.5V_B+
PC84
4.7U_0805_25V6-K

@ PJ20

EN_PSV
1. GND=>Disable SMPS
2. FLOAT=>PWM_only mode
3. HIGH=>Auto_skip mode

PR299
57.6K_0402_1%

B+

PR300
280K_0402_1%
1
2

LX_1.05V

11

VDDP

10

RT8209BGQW _W QFN14_3P5X3P5

@ PR307
23.7K_0402_1%
2
1

PR308
24K_0402_1%
1
2

1
2

4
PR306
7.32K_0402_1%

PGND
8

LG_1.05V

PC99
4.7U_0805_10V6K

1
PC97
330U_D2E_2.5VM

@ PC98
680P_0603_50V8J

VFB=0.75V
Vo=VFB*(1+PR308/PR309)=1.05V
Ton=19E-12*Ron*(((2/3)*Vo+100mV)/Vin)+50ns=2.74E-07
Freq=282KHz , 300KHz(typ)
Cesr=15m ohm
Ipeak=10.9A Imax=7.63A
Delta I=((19-1.05)*(1.05/19))/(L*Freq)=1.837A
Vtrip=Rtrip*10uA=0.0732V
Iocp-min=Vtrip/(Rds(on)(max)*1.2)+Delta I / 2= 11.81A
Iocp-max=Vtrip/(Rds(on)(typ)*1.2)+Delta I / 2=14.47A
Iocp=11.81~14.47A

PQ64
AO4456_SO8

Rds(on)=4.5m ohm(typ)
5.6m ohm(max)

VFB=0.75V

PR309
59K_0402_1%
2

+1.05VS

@ PC101
47P_0402_50V8J
1
2

LGATE

@ PR304
4.7_1206_5%

+5VALW

PC100
4.7U_0603_6.3V6K

6
open-drain PGOOD

Layout Note:
Place near V5FILT Pin

FB

+1.05VSP

12

CS

+5VALW

PR305 100_0603_1%
1
2

GND

3
2
1

PHASE

0.1U_0603_25V7K

15

14

UG_1.05V

5
6
7
8

VDD

13

3
2
1

VOUT

UGATE

PL8
1.8UH_MSCDRI-104A-1R8N-E_9.5A_30%
1
2

PC95
1

BOOT

TON

PR302
0_0603_5%
1
2BST_1.05V-1

NC

1
PC96
1U_0402_6.3V6K

@ PR303
47K_0402_5%

BST_1.05V

EN/DEM

PU10

,53 VS_ON

1.05V_EN
PR301
9.76K_0402_1%
1
2

JUMP_43X118

PC94
4.7U_1206_25V6K

PQ63
AO4466_SO8

5
6
7
8

EN_PSV
1. GND=>Disable SMPS
2. FLOAT=>PWM_only mode
3. HIGH=>Auto_skip mode

PC93
4.7U_1206_25V6K

@ PJ21
51117_1.05V_B+

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/08/10

Deciphered Date

2009/08/10

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

1.5VP / 1.05VSP
Rev
0.1

NALG0

Friday, October 23, 2009


D

Sheet

51

of

60

B+

VGA@ PJ24
2 2
1

B+_core

VGA_CORE
Ipeak=16A
Imax=11.2A
Delta I / 2 = 3.33A , Freq=1/ 75E-12*PR153=230K Hz
Iocp(min)=1.1*Ipeak+Delta I / 2 = 20.93A
Rsen=Iocp(min)*1.2*Rds(on)(max)/ISEN(min)=3.57K ohm
ISEN(min)=19uA , Rds(on)=5.6m ohm(max) ,4.5m ohm(typ)
Iocp(max)=ISEN(min)*Rsen/(1.2*Rds(on)(typ))=25.12A
Iocp=22.97~25.12A

1
2

VGA@

LX_VCORE
VGA@ PR310
DH_VCORE
1
2
VGA@ PR311 0_0603_5%
BST_VCORE
1
2
2.2_0603_5%

14,39 VGA_PWROK

DH_VCORE-1

VGA@

VGA@ PC104
0.1U_0603_25V7K

+5VS

open-drain

PC103
10U_1206_25V6M

PC102
10U_1206_25V6M

JUMP_43X118

15

16

BOOT

UG

VIN

PVCC

VGA@ PR313
1
2 6269_VCORE

14

6269_VCORE

4.7_0603_5%
1
2VGA@ PC105

VGA@ PQ42

3
2
1

PHASE

+3VS

PGOOD

GND

PU15

VGA@ PR312
0_0603_5%

2.2U_0603_6.3V6K

DCR=1.6m ohm

TPCA8030-H_SOP-ADV8-5

1 2

VGA@ PR315
4.7_1206_5%

4
3.57K_0402_1%

VGA@ PC206

VGA@

3
2
1

680P_0603_50V7K

Rds=4.5m(Typ)
5.6m(Max)

+NVVDD_SENSE 23
C

Material Note:
330uF/6 m, number
are 3, Power 1, HW 2

VGA@ PR151
2.4K_0402_1%

+3VS_DELAY

VFB=0.6V

VGA@ PC208
0.01U_0402_25V7K

VGA@

VGA@ PR154
23.7K_0402_1%

@ PR155

57.6K_0402_1%

GPU_VID1 22
VGA@ PR158
10K_0402_1%

VGA@ PC210
0.022U_0402_25V7K

6.98K_0402_1%

VGA@ PR157
D VGA@ PQ45
10K_0402_1%
2
1
2
2N7002W-T/R7_SOT323-3
G
S

VGA@ PR156

VGA@

10K_0402_5%

1 1

PC209

PR153
2

VGA@ PR152
22K_0402_1%

2200P_0402_25V7K

22P_0402_50V8J

PC207
VGA@

VGA@ PC107
330U_6.3V_M

10_0402_1%

VGA@ ISL6268CAZ-T_SSOP16

1
2
VGA@ PR150

3
2
1

10

0.1U_0402_16V7K

VGA@ PQ44
AO4456_SO8

VO

VGA@ PC108

11

5
6
7
8

5
6
7
8
ISEN

30K_0402_1%

EN
FSET

VGA@ PQ43
AO4456_SO8
VGA@ PR148
ISEN_VCORE
1
2

12

+VGA_COREP

0.56UH_ETQP4LR56WFC_21A_20%
1
2

PR149
1

PGND

DL_VCORE

0_0402_5%

13

FB

VGA_ON

COMP

9,43 VGA_ON

LG

VCC

@ PR314
10K_0402_5%
VGA@ PR316

VGA@ PL15
VGA@ PC106
2.2U_0603_6.3V6K

+1.5V

+3VS_DELAY

VGA@ PR159
6.34K_0402_1%

+3VS

FB

VIN

@
PR164
10K_0402_1%

1
2

VGA@ PC213
22U_0805_6.3V6M

GPU_VID1

Core Voltage Level

0.8 V

0.85 V

1.03 V

reserve

1
2

VGA@
PC214

GPU_VID0

0.01U_0402_25V7K

VGA@ PR166
1.15K_0402_1%

S IC APL5913-KAC-TRL SO 8P

@ PC215
22U_1206_6.3V6M

FB=0.8V

VGA@ PC217
0.022U_0402_25V7K

N11M
+1.05VSDGPU

GPU_VID0 22

VOUT

VGA@ PC212
4.7U_0603_6.3V6M

VOUT

10K_0402_1%

6
VIN

VGA@ PC216
0.1U_0402_16V7K

EN

VGA@ PR162
1
2

2
G
1

VGA@ PC211
1U_0402_6.3V6K

1
2
8

GND

VGA_ON

10K_0402_1%
1
2

24,39,43 VGA_ON

POK

VCNTL

VGA@
PU16

10K_0402_5%

VGA@ PR165

10K_0402_5%

VGA@ PQ46 D
2N7002W-T/R7_SOT323-3
S

@ PR163

0824 PR159 13K(0.9V) change to 6.34K for 1.033V

@ PJ23
JUMP_43X118

VGA@ PR160

@ PR161
4.7K_0402_5%
1
2

+5VS

0824 change to 3.65K for 1.05V

Vout=FB*(1+PR166/PR167)
PR167=3K, Vo=1.1V
PR167=3.65K, Vo=1.05V

VGA@ PR167
3.65K_0402_1%

Compal Secret Data

Security Classification
Issued Date

2007/12/18

2008/12/18

Deciphered Date

Title

Compal Electronics, Inc.


VGA_COREP/+1.1VSDGPU

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Rds=4.5m(Typ)
5.6m(Max)

Date:

Rev
0.1

NALG0

Friday, October 23, 2009

Sheet
1

52

of

60

PJ22
6268_B+

LX_1.1VS_VTT

@ PR130
1K_0402_1%
1
2

DH_1.1VS_VTT

1
VIN

BOOT

PHASE

UG

15

16

PGOOD

PVCC

PGND

12

ISEN

11

Layout Note:
Close IC

PC112
2.2U_0603_6.3V6K
DL_1.1VS_VTT

Rds=2.3m(Typ)
3.2m(Max)

2
1
PR138
57.6K_0402_1%

+3VS

PR145
100K_0402_5%

VTT_SENSE 7

PR146
10K_0402_5%
PR147
100K_0402_5%

2
PC121
0.01U_0402_16V7K

2
3

1
2

PQ37
2N7002W-T/R7_SOT323-3

PC120
0.1U_0402_16V7K

1
2
G

PR143
6.49K_0402_1%

PQ36
TPCA8028-H_SOP-ADVANCE8-5

+1.1VS_VTTP

PR142
180K_0402_1%

2
1
1

PR144
4.7K_0402_5%
2
1

PC116
330U_D2_2V_Y

Pin15

+3VS
PR141
78.7K_0402_1%

Material Note:
330uF/9 m, number
are 3, Power 1, HW 2

PR168
10_0402_1%
1
2

VFB=0.6V

1
@ PC114
680P_0603_50V7K

Layout Note:
Close IC

PQ38
PMBT2222A_SOT23-3

PR137
90.9K_0402_1%

2
1
2

PC119
6800P_0402_25V7K

1
2

22P_0402_50V8J

PC117

PC118
0.01U_0402_25V7K

3
2
1

3
2
1

ISL6268CAZ-T_SSOP16

PR139
0_0402_5%
1
2

PR135
2.05K_0402_1%

PR140
4.99K_0402_1%
1
2

+1.1VS_VTT
Ipeak=18.06A
Imax=12.642A
Delta I / 2 = 2.176A , Freq=230K Hz
Iocp(min)=Ipeak + Delta I / 2 = 20.236A
Rsen=Iocp(min)*1.2*Rds(on)(max)/ISEN(min)=2.05K ohm
ISEN(min)=19uA , Rds(on)=3.2m ohm(max) ,2.3m ohm(typ)
Iocp(max)=ISEN(min)*Rsen/(1.2*Rds(on)(typ))=28.225A
Iocp=20.236~28.225A

1 2

ISEN_1.1VS_VTT
1
2

VO
10

FB

COMP
6

PC115
0.1U_0402_16V7K

FSET

EN

Layout Note:
Close IC

+1.1VS_VTTP

PQ35
TPCA8028-H_SOP-ADVANCE8-5

@ PR136
10K_0402_5%

PL9
1UH_PCMB103E-1R0MS_20A_20%
1
2

@ PR133
4.7_1206_5%

PR134
57.6K_0402_1%
1
2

PC113
2.2U_0603_6.3V6K

39,50,51 VS_ON

DCR=2.7m(Typ)
3.0m(Max)

13

PQ34
SI7686DP-T1-E3_SO8

PR132
4.7_0603_5%
1
2 6268_VCORE_1.1VS_VTT

14

LG

PR131
0_0603_5%

6268_VCORE_1.1VS_VTT
4 VCC

PC111
0.1U_0603_25V7K

+5VS

GND

PU11

DH_1.1VS_VTT-1

1 PR128 2
PR129 0_0603_5%
BST_1.1VS_VTT
1
2
0_0603_5%

H_VTTPWRGD 5

1
2

PC110
10U_1206_25V6M

PC109
10U_1206_25V6M

1
D

Layout Note:
Place near high-side MOS Drain
and low-side MOS Source

+3VS

PR126
0_0402_5%
1
2

3
2
1

JUMP_43X118

PR127
2K_0402_1%

B+

H_VTTVID1 7

Voltage Select
VID

Vout

High

1.06 V

Low

1.1 V

0724 1.05V change to

1.06V

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/4/15

2010/04/15

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

+1.1VS_VTTP
Rev
0.1

NALG0

Friday, October 23, 2009

Sheet
1

53

of

60

Intel Auburndale CPU(Integrate Graphics) Imax=15A


OCP calculation : Assume DCR=1.1m ohm
G1=Rn/(Rn+Rsum)=0.617
where Rn=PR277 // (PR274+PH3)=5.875k ohm
Rsum=PR269=3.65k ohm
LL=2*Rdroop*G1*DCR/Ri= 6.96m V/A
where Rdroop=PR271=8.66k ohm, Ri=PR283=1.69k ohm
Iocp=OCP Threshold*Rdroop/LL=24.89A

B+

@ PJP3
GFX_B+

UMA@ PC191
0.22U_0402_6.3V6K

GFXVR_IMON

ISUMBST_GFX 1
1

14

3
2
1

UMA@ PR274
UMA@ PH3
1
2 1
2

UMA@ PC198
2.2U_0603_6.3V6K

@ PC199
470P_0603_50V8J

Rds=4.5mOHM(typ)
Rds=5.6mOHM(max)

UMA@
PR270
0_0402_5%

+
2

UMA@ PC130
330U 2V M X LESR6M SX H1.9

2.61K_0402_1% 10K +-5% TSM0A103J4302RE 0402

1
2
UMA@ PR277
11K_0402_1%

Layout Note:
Place near Choke

Material Note:
330uF/6 m, number are 3, PW
1, HW 1, 1 of HW is backup

UMA@ PC202
.1U_0402_16V7K

UMA@
1
UMA@
1
UMA@
1
UMA@
1
UMA@
1
UMA@
1
UMA@
1
UMA@
1
UMA@
1

PR280
PR281
PR282
PR285
PR286
PR287
PR289
PR290
PR291

GFXVR_VID_0 8
GFXVR_VID_1 8
GFXVR_VID_2 8
GFXVR_VID_3 8
GFXVR_VID_4 8
GFXVR_VID_5 8
GFXVR_VID_6 8
GFXVR_EN 8
GFXVR_DPRSLPVR

UMA@ PC203
.1U_0402_16V7K
UMA@ PR283
1.69K_0402_1%
UMA@ PR288
82.5_0402_1%
1
2
1
2
UMA@ PC204
0.01U_0402_16V7K

@
PR284
100_0402_1%

2
2
2
2
2
2
2
2
2

1
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

GFX_CORE_PWRGD

+5VALW

@ PR279
10K_0402_1%

UMA@ PR269
3.65K_0805_1%

21

+VGFX_COREP

UMA@
PQ41
AO4456_SO8

VID2

VID3

VID4

@ PR268
2.2_1206_5%

4
UMA@ PR273
1
2
0_0603_5%

1
UMA@ PQ40
AO4456_SO8

19
20

4
5
6
7
8

5
6
7
8
18 DL_GFX

VID1

17

3
2
1

12

11

10

13
IMON

VIN

VDD

RTN

ISUM

ISUM+

BOOT

16 LX_GFX

UMA@ PR276
8.06K_0402_1%

UMA@ PL10
0.45UH_PCMB104T-R45MN_25A_20%

15 DH_GFX

22

UMA@ PR275
17.8K_0402_1%

VID0

CLK_EN#

UMA@ PQ39
FDMS8692 1N

UMA@ PC200
150P_0402_50V8J

PGOOD

23

1 2

VCCP

24

+VGFX_COREP

RBIAS

VID5

UMA@ PC196
100P_0402_50V8J
UMA@ PC201
22P_0402_50V8J
1
2

LGATE

25

147K for CPU


47K for GPU

VSSP

VW

VID6

PHASE

COMP

28

2 1

UMA@ PC197
1000P_0402_50V7K
2
1

VR_ON

4
UMA@ PR294
2
1
47K_0402_1%

UMA@ PC193
0.22U_0603_25V7K

DCR=1.1 mOHM

UGATE
UMA@ PU12
ISL62881HRZ-T_QFN28_4X4

FB

DPRSLPVR

UMA@ PR272
825K_0402_1%

VSEN

26

27

UMA@ PR271
8.66K_0402_1%
2
1

29

UMA@ PC195
330P_0402_50V7K

AGND

UMA@ PR293
2
1
10_0402_1%

UMA@ PR266
0_0603_5%

UMA@ PC194
330P_0402_50V7K

8 VSS_AXG_SENSE
8 VCC_AXG_SENSE

8
5

ISUM+
UMA@ PC192
1000P_0402_50V7K
1
2

+VGFX_COREP

UMA@ PR265
22.6K_0402_1%

3
2
1

UMA@ PR292
2
1
10_0402_1%

UMA@ PC189
1U_0402_6.3V6K

VSS_AXG_SENSE

1 1

UMA@ PR263
0_0603_5%
UMA@ PR264
2
1
1_0603_5%

UMA@ PC190
0.22U_0603_25V7K

+5VALW

@ PC188
0.1U_0402_25V6

1
2

UMA@ PC126
10U_1206_25V6M
2
1

PAD-OPEN 4x4m

UMA@ PC125
10U_1206_25V6M
2
1

UMA@ PC187
2200P_0402_50V7K

ISUM+

@
PC205
180P 50V J NPO 0402

ISUM-

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2009/4/15

Deciphered Date

2010/04/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

GFX_COREP
Size
C
Date:

Document Number

Rev
0.1

NALG0
Friday, October 23, 2009

Sheet
1

54

of

60

PR219 499_0402_1%
1

PC157
0.22U_0603_25V7K
1
2

2
2

3
2
1

3
2
1

VGA@ PQ52
TPCA8028-H_SOP-ADVANCE8-5
@ PD7
RB751V-40TE17_SOD323-2
2
1

Pull up 3V

PR235
1

VSSSENSE

PQ53
TPCA8030-H_SOP-ADV8-5
UGATE1

PR261
1

10_0402_1%
2

2 1

PR251
2.61K_0402_1%
2
1

1
1

PHASE1

PH6
10K_0402_1%_TSM0A103F34D1RZ

1
PR255
1_0402_5%
@ PR259
0_0402_5%
1

PQ56
TPCA8028-H_SOP-ADVANCE8-5

Layout Note:
Place near Phase1 Choke

VSUM+
PC184
680P_0402_50V7K

+CPU_CORE
V1N

1
PR252
2.2_1206_5%
4

LGATE1

PR256
1.21K_0402_1%
1
2

@ PC185
1200P_0402_50V7K

@ PQ54
TPCA8030-H_SOP-ADV8-5

VGA@ PQ55
TPCA8028-H_SOP-ADVANCE8-5
PR258
11K_0402_1%
2
1

1
2

1
2

PC182
1000P_0402_50V7K
0_0402_5%
2

PC183
330P_0402_50V7K

PR260
1

VSSSENSE

PC176
0.22U_0603_25V7K
BOOT1_1 1
2

PL14
0.36UH_PCMC104T-R36MN1R17_30A_20%

GNDA_VCORE

4
PR249
2.2_0603_5%
2
1

PC181

PC180
330P_0402_50V7K

PC179
0.068U_0603_16V7K
2
1

2
0_0402_5%

PC178
0.22U_0603_10V7K
2
1

PR248
PR250

VCCSENSE

@ PC177
2700P_0402_50V7K
2
1

2
10_0402_1%

0.01U_0402_25V7K

1
PR247

+CPU_CORE
C

82.5_0402_1%

VSUM+

1
2

PR246
8.25K_0402_1%

PC175
10U_1206_25V6M
2
1

GNDA_VCORE

PC170
0.22U_0603_25V7K

1
2

VSUM-

PC169
1U_0603_10V6K
2
1

+CPU_B+

PR254
10K_0402_5%

1_0402_5%
2
+5VALW

IMVP_IMON

@ PC172
0.1U_0603_25V7K
2
1

PR245

0_0402_5%
2

0_0402_5%
2
+CPU_B+

3
2
1

PR241

BOOT1

Layout Note:
PH5 place near Phase1 L-MOS

+5VALW

PC163
1U_0603_10V6K

ISEN2
ISEN1

PR240
1

PR242
412K_0402_1%

PR234
0_0402_5%
1

0_0402_5%
2

GNDA_VCORE

1
2

VSUM-

ISL62883HRZ-T_QFN40_5X5~D

11
12
13
14
15
16
17
18
19
20

AGND

30
29
28
27
26
25
24
23
22
21

390P_0402_50V7K
PR239
2.61K_0402_1%
1
2

PC166
150P_0402_50V8J

BOOT2
UGATE2
PHASE2
VSSP2
LGATE2
VCCP
PWM3
LGATE1
VSSP1
PHASE1

PGOOD
PSI#
RBIAS
VR_TT#
NTC
VW
COMP
FB
ISEN3
ISEN2

PC168
0.22U_0402_10V6K

PC164
2

41

PC167
0.22U_0402_10V6K

PR237
8.06K_0402_1%
1
2

PR238
562_0402_1%
1
2
1

2
PC165
10P_0402_50V8J
1

PC161
22P_0402_50V8J

ISEN2
PC158
680P_0402_50V7K

1
1

@ PR236
249K_0402_1%
1

H_PROCHOT#_R

PH5

470KB_0402_5%_ERTJ0EV474J

GNDA_VCORE

1
2
3
4
5
6
7
8
9
10

3
2
1

0_0402_5%

PR232
56P_0402_50V8
2

4.02K_0402_1%
2
2

V1N

VSUM+

PC159
1U_0603_10V6K
1
2

3
2
1

68_0402_5%
1
2

CLK_EN#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0

PU14

PC162
1000P_0402_50V7K

GNDA_VCORE

PR233
1

PR231
5 H_PROCHOT#

PR223
1_0402_5%
@ PR225
0_0402_5%
1

3
2
1

+1.1VS_VTT

@ PC160
1

0_0402_5%
2

PC171
0.22U_0603_25V7K

PR230

40
39
38
37
36
35
34
33
32
31

+1.1VS_VTT
7
H_PSI#
PR229
1
2
147K_0402_1%

GNDA_VCORE

+CPU_CORE
V2N

@ PR228 100K_0402_5%
1
2

ISEN1
VSEN
RTN
ISUMISUM+
VDD
VIN
IMON
BOOT1
UGATE1

LGATE2

5
CLK_ENABLE#

VGATE

PR220
2.2_1206_5%

PR226
1.91K_0402_1%

12,15

PQ51
TPCA8028-H_SOP-ADVANCE8-5

PR224
1.91K_0402_1%
1

PR227
0_0402_5%
1

PC122
220U_25V_M

PHASE2

12 CLK_ENABLE#
+3VS

PL13
0.36UH_PCMC104T-R36MN1R17_30A_20%

UGATE2

PR222
10K_0402_5%

7 H_DPRSLPVR

BOOT2_2

B+

PR217
2.2_0603_5%
2
1

BOOT2

VR_ON

@ PQ50
TPCA8030-H_SOP-ADV8-5
4

PR218 0_0402_5%
37

PC156
10U_1206_25V6M
2
1

PR216 0_0402_5%

PC155
10U_1206_25V6M

PR215 0_0402_5%

PC174
10U_1206_25V6M

CPU_VID6

PQ49
TPCA8030-H_SOP-ADV8-5

CPU_VID5

PR221
3.65K_0805_1%
2
1

PC173
2200P_0402_50V7K
2
1

CPU_VID4

1
PR214 0_0402_5%

PR253
3.65K_0805_1%

1
PR213 0_0402_5%

CPU_VID3

CPU_VID2

PR212 0_0402_5%

3
2
1

PR211 0_0402_5%

PL12
FBMA-L18-453215-900LMA90T_1812

CPU_VID1

+CPU_B+

CPU_VID0

3
2
1

Intel Auburndale CPU(Integrate Graphics) , Ipeak = 48A


OCP calculation : Assume DCR=1.1m ohm
G1=Rn/(Rn+Rsum/2)=0.763
where Rn=PR258 // (PR251+PH6)=5.875k ohm
Rsum=PR221, PR253 =3.65k ohm
LL = 2*Rdroop*G1*(DCR/2)/Ri = 1.81mV/A
where Rdroop=PR239=2.61k ohm , Ri=PR256=1.21k ohm
Iocp= OCP Threshold*Rdroop/LL=40E-06*2.61E03/1.81E-03=57.68A

PR210 0_0402_5%
H

PC154
2200P_0402_50V7K
2
1

@ PC153
0.1U_0603_25V7K
2
1

V2N
VSUM-

ISEN1

VSUM-

@ PR262
100_0402_1%
1
2

PJP5
1

PC186
0.1U_0402_16V7K

GNDA_VCORE

PAD-OPEN1x1m

GNDA_VCORE

GNDA_VCORE

2009/4/15

Issued Date

Deciphered Date

2010/04/15

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

+CPU_CORE
Size
C
Date:

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Document Number

Rev
0.1

NALG0
Friday, October 23, 2009

Sheet

55
1

of

60

Version change list (P.I.R. List)


Item
D

Page 1 of 3
for PWR

Fixed Issue

Reason for change


design change

Rev.

PG#

0.1

48

Modify chager circuit

Modify 1.8V V5FILT PIN

Modify 1.5V V5FILT PIN

Modify 1.05V V5FILT PIN

Modify VGA_COREP circuit

Modify +1.1VS_VTTP circuit

design change

0.1

53

Modify OTP circuit

Link right component

0.1

Modify 5V/3V circuit

Delete component

0.1

Modify List

Date

Change PR60 to SD000001F00(0.02_2512_1%)

Phase

09/06/23

EVT

09/07/21

DVT

09/07/21

DVT

09/07/21

DVT

09/06/23

EVT

Cahnge PR168 to SD034100A80 (S RES 1/16W 10 +-1% 0402)

09/06/23

EVT

46

Add PH1 to SL210031F00 (S THERM_ 100K +-1% TH11-4H104FT 0603)

09/06/25

EVT

47

Delete PC42 to SE076473K80 (S CER CAP .047U 16V K X7R 0402)

09/06/25

EVT

Change PU16, PR165, PR166, PR167, PC211, PC212,


PC213, PC214, PC215, PC216 BOM structure to VGA@

09/06/26

EVT

09/06/26

EVT

09/06/30

EVT

09/06/30

EVT

Cahnge PR115 to SD014100080 (S RES 1/10W 100 +-1% 0603 )

0.1

Avoid 2nd source RT8209B can no power on

50

Cahnge PC77 to SE107475K80 (S CER CAP 4.7U 6.3V K X5R 0603)


Cahnge PR296 to SD014100080 (S RES 1/10W 100 +-1% 0603 )

Avoid 2nd source RT8209B can no power on

0.1

51

Cahnge PC91 to SE107475K80 (S CER CAP 4.7U 6.3V K X5R 0603)


Cahnge PR305 to SD014100080 (S RES 1/10W 100 +-1% 0603 )

0.1

Avoid 2nd source RT8209B can no power on

51

Cahnge PC100 to SE107475K80 (S CER CAP 4.7U 6.3V K X5R 0603)


Cahnge PR149 to SD028000080 (S RES 1/16W 0 +-5% 0402)

design change

0.1

52

Cahnge PR150 to SD034100A80 (S RES 1/16W 10 +-1% 0402)


Cahnge PR139 to SD028000080 (S RES 1/16W 0 +-5% 0402)

Modify 1.1VSDGPU circuit

design change

0.1

52

10

Modify chager circuit

design change

0.1

48

11

Modify VGA_COREP circuit

12

Modify VGA_COREP circuit

13

Modify OTP circuit

design change

0.2

46

Add PR169 to SD034100480 (S RES 1/16W 1M +-1% 0402)

14

Modify 1.5VP circuit

design change

0.2

51

Change PL7 to SH000009U00(S COIL 1UH +-20%


FDUE1040D-1R0M=P3 21.3A)

15

Modify VGA_COREP circuit

design change

0.2

52

16

Modify +1.1VS_VTTP circuit

design change

0.2

53

17

Modify VGA_COREP circuit

design change

0.2

52

18

Modify 1.8V circuit

design change

0.2

50

19

Modify CPU circuit

design change

0.2

55

20

Modify +1.1VS_VTTP circuit

design change

0.2

53

21

Modify CPU circuit

design change

0.2

55

22

Modify chager circuit

design change

0.2

48

23

Modify 1.1VSDGPU circuit

design change

0.2

52

Change PR78 to SD012200D80(S RES 1/2W 0.02 +-1% 1206)

Cahnge PR151 to SD034240180 (S RES 1/16W 2.4K +-1% 0402)

design change(Voltage Level)

0.1

52

Cahnge PR156 to SD000002680 (S RES 1/16W 6.98K +-1% 0402)


Cahnge PR154 to SD034237280 (S RES 1/16W 23.7K +-1% 0402)

design change(Voltage Level)

0.1

52

Cahnge PR159 to SD034130280 (S RES 1/16W 13K +-1% 0402)


Cahnge PQ6 to SB000006800 (S TR 2N7002W T/R7 1N SOT-323)

09/07/13
09/07/20
09/07/20

Cahnge PR153 to SD034576280 (S RES 1/16W 57.6K +-1% 0402)

DVT
DVT
DVT
B

Cahnge PQ35 to SB00000GL00 (S TR TPCA8028-H 1N SOP ADVANCE)

09/07/20

Cahnge PQ36 to SB00000GL00 (S TR TPCA8028-H 1N SOP ADVANCE)


Cahnge PC107 to SF000002000 (S ELE CAP 330U 6.3V M 6.3X5.9 LESR15M VU)

09/07/20

Cahnge PC74 to SF000002000 (S ELE CAP 330U 6.3V M 6.3X5.9 LESR15M VU)
and BOM structure to @

09/07/20

DVT
DVT
DVT

09/07/20

DVT

Cahnge PC116 to SGA20331E10 (S POLY C 330U 2V Y D2 LESR9M EEFSX H1.9)

09/07/21

DVT

Cahnge PC179 to SE026683K80 (S CER CAP .068U 16V K X7R 0603)

09/07/22

DVT

09/07/22

DVT

09/07/22

DVT

Cahnge PR226 to SD000009O80 (S RES 1/16W 1.91K +-1% 0402)

Cahnge PC53 to SE076473K80 (S CER CAP .047U 16V K X7R 0402)

Cahnge PC212 to SE107475M80 (S CER CAP 4.7U 6.3V M X5R 0603 H0.8)

2007/09/20

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

Cahnge PC64 to SE107475M80 (S CER CAP 4.7U 6.3V M X5R 0603 H0.8)

PIR (PWR)

Friday, October 23, 2009

Rev
0.1
Sheet
1

56

of

60

Version change list (P.I.R. List)


Item
D

Fixed Issue

Reason for change


design change

Rev.

PG#

0.2

54

24

Modify GFX_COREP circuit

25

Modify 1.8V circuit

26

Modify 1.8V circuit

design change

0.2

50

27

Modify 1.8V circuit

design change

0.2

50

28

Modify 1.8V circuit

design change

0.2

50

29

Modify 1.8V circuit

design change

0.2

50

30

Modify 5V/3V circuit

31

Modify VGA_COREP circuit

design change

0.2

add snubber(PR42 PC36),(PR41 PC35)


add boost PR43, PR44

0.2

add snubber(PR315 PC206)


add boost PR311

0.2

50

Modify List

Page 2 of 3
for PWR

Date

Cahnge PC189 to SE000000K80 (S CER CAP 1U 6.3V K X5R 0402)


Add PR170 to SD013000080 (S RES 1/10W 0 +-5% 0603)and BOM structure to @
Change PR109, PR117, PC72, PQ58, PQ59 BOM structure to @
Add PU17 to SA00003KL00(S IC MP2121DQ-LF-Z QFN 10P PWM)
Add PD16 to SCS00001I80(S SCH DIO B340A SMA VISHAY) BOM structure to @
Add PR173 to SD034402380(S RES 1/16W 402K +-1% 0402)
Add PR174 to SD034316380(S RES 1/16W 316K +-1% 0402)
Add PR171 to SD028000080(S RES 1/16W 0 +-5% 0402)BOM structure to @
Add PR113 to SD028470280(S RES 1/16W 47K +-5% 0402)
Add PC123,PC124 to SE053106Z80(S CER CAP 10U 10V Z Y5V 0805)
Add PC127 to SE076103K80(S CER CAP .01U 16V K X7R 0402)
Add PC218, PC219 to SE000000I10(S CER CAP 22UF 6.3V M X5R 0805 H1.25)

Phase

09/07/22

DVT

09/07/28

DVT

09/07/28

DVT

09/07/28

DVT

09/07/28

DVT

09/07/28

DVT

47

Add PR41, PR42 to SD001470B80(S RES 1/4W 4.7 +-5% 1206)


Add PC35, PC36 to SE074681K80(S CER CAP 680P 50V K X7R 0402)
Add PR43, PR44 to SD013220B80(S RES 1/10W 2.2 +-5% 0603)

09/07/28

DVT

52

Add PR311 to SD013220B80(S RES 1/10W 2.2 +-5% 0603)and BOM structure to VGA@
Change PR315 PC206 BOM structure to VGA@
09/07/28

DVT

0.2

55

Add PR220, PR252 to SD011220B80(S RES 1/4W 2.2 +-5% 1206)


Add PC158, PC184 to SE074681K80(S CER CAP 680P 50V K X7R 0402)
Add PR217, PR249 to SD013220B80(S RES 1/10W 2.2 +-5% 0603)
Cahnge PR141 to SD034787280(S RES 1/16W 78.7K +-1% 0402)
Cahnge PR143 to SD034649180(S RES 1/16W 6.49K +-1% 0402)

32

Modify CPU circuit

add snubber(PR220 PC158),(PR252 PC184)


add boost PR217, PR249

33

Modify +1.1VS_VTTP circuit

design change

0.2

53

34

Modify OTP circuit

design change

0.2

46

Modify +1.1VS_VTTP circuit

design change(OCP)

0.2

53

36

Modify GFX_COREP circuit

design change

0.2

54

Cahnge PH3 to SL200000Y00(10K +-5% TSM0A103J4302RE 0402)

09/07/29

DVT

37

Modify CPU circuit

design change

0.2

55

Cahnge PH6 to SL200000W00(10K +-1% TSM0A103F34D1RZ 0402)

09/07/29

DVT

38

Modify 1.5V circuit

Change to 3mm height choke for thermal issue

0.2

51

Cahnge PL7 to SH00000AB00(S COIL 1UH +-20% PCMB103T-1R0MS 13A)

09/08/06

DVT

39

Modify VGA_COREP circuit

design change
(GS sample define 1.03V,+1.05VSDGPU Vo=1.05V)

0.3

52

Cahnge PR159 to SD034634180(S RES 1/16W 6.34K +-1% 0402)


Cahnge PR167 to SD034365180(S RES 1/16W 3.65K +-1% 0402)

09/08/24

PVT

40

Modify 1.8V circuit

design change

0.3

50

Cahnge PC127 to SE076104K80(S CER CAP .1U 16V K X7R 0402)

09/08/24

PVT

41

Modify chager circuit

design change

0.3

48

Cahnge PR88 to SD034154280(S RES 1/16W 15.4K +-1% 0402)


Change PR81 to SD034154380(S RES 1/16W 154K +-1% 0402)

09/08/26

PVT

42

Modify VGA_COREP circuit

design change

0.3

52

Change PR160 BOM structure to VGA@


VID pull high voltage change to +3VS_DELAY

09/09/03

PVT

43

Modify +1.1VS_VTTP circuit

design change

0.3

53

09/09/03

PVT

44

Modify 0.75V circuit

design change

0.3

50

Cahnge PR120 to SD034280180(S RES 1/16W 2.8K +-1% 0402)

09/09/11

PVT

45

Modify VGA_COREP circuit

design change

0.3

52

Cahnge PR316 to SD034300280(S RES 1/16W 30K +-1% 0402)


Change PR164 BOM structure to @

09/09/11

PVT

46

Modify +1.1VS_VTTP circuit

design change

0.3

53

Cahnge PR135 to SD034205180(S RES 1/16W 2.05K +-1% 0402)

35

Cahnge PH1 to SL200000U00(S THERM_ 100K +-1% TSM0B104F4251RZ 0402)


Cahnge PH2 to SL200000U00(S THERM_ 100K +-1% TSM0B104F4251RZ 0402)
Cahnge PR135 to SD034280180(S RES 1/16W 2.8K +-1% 0402)

09/07/28

DVT

09/07/28

DVT

09/07/28

DVT

09/07/29

DVT

Change PR130 BOM structure to @

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PIR (PWR)

Friday, October 23, 2009

Rev
0.1
Sheet
1

57

of

60

Version change list (P.I.R. List)


Item

Page 3 of 3
for PWR

Fixed Issue

Reason for change

Rev.

PG#

Modify List

Date

Phase

47

Modify OTP circuit

design change

0.3

46

Change PR23 to SD00000AJ80(S RES 1/16W 12.4K +-1% 0402)


Change PR26 to SD034158280(S RES 1/16W 15.8K +-1% 0402)

09/09/14

PVT

48

Modify 1.8V circuit

design change

0.3

50

Change PL6 to SH000009Q00(S COIL 2.2UH 20%


MSCDRI-74A-2R2M-E 6.5A)

09/09/16

PVT

09/09/16

PVT

09/10/08

PVT

Change PU4 to SA00001TN00(S IC ISL6237IRZ-T QFN 32P)

49

Modify 5V/3V circuit

design change

0.3

47
Change PR120 to SD00000AJ80(S RES 1/16W 12.4K +-1% 0402)

50

Modify 0.75V circuit

design change

0.3

50

51
52
53
C

54

55
56
57
58
59
60
B

61

62
63
64
65
66
67
68
A

69

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2007/09/20

Deciphered Date

2008/09/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PIR (PWR)

Friday, October 23, 2009

Rev
0.1
Sheet
1

58

of

60

Version change list (P.I.R. List)


Item

Page 1 of 3
for HW

Fixed Issue

Reason for change

Rev.

PG#

Modify List

Date

R72 bom structure

Phase
D

7/23

0.2

reserve R735

7/23

0.2

rename CPU VDDQ from +1.5V to +1.5V_CPU

7/23

0.2

R146 BOM structure

7/23

0.2

11

reserve S3 power consumptiosn circuit

7/23

0.2

12

change Y1 Y4 Y6 footprint

7/23

0.2

13

add ME_EN# from EC to PCH

7/23

0.2

14

pop Y6,C254,C255 , and project ID pin

7/23

0.2

17

change USB port 8 to port 1 , port 2 to port 8

7/23

0.2

10

18

GPIO35 pin(VGa presetnt) modfiy

7/23

0.2

11

19

R605 and R628 BOM structure modify

7/23

0.2

12

22

add VGA thermal sensor from EC to VGA

7/23

0.2

13

23

pop R479,del R491

7/23

0.2

14

29

L29~L34 change from 0805 to 0603

7/23

0.2

15

30

Q45,Q47 gate voltage change from +3VS to +3VS_delay 7/23

0.2

16

37

change R306 to 8.2K, add D29, rename EC_MUTE

7/23

0.2

17

38

Jfun1 pin3 change form KSO1 to KSO3

7/23

0.2

18

39

del SW2

7/23

0.2

19

41

change R333, R336 to 39k,15k, add R681,C707

7/23

0.2

20

43

reserve Q58,Q59,R728,R326, change U26,R688

7/23

0.2

21

24

reserve C710

7/23

0.2

22

28

reserve U44,U45

7/23

0.2

23

19

update L7,L8,L10,L11 footprint

7/23

0.2

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/07/01

Deciphered Date

2009/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PIR (HW)
Rev
1.0
NALG0 M/B LA-5681P Schematic

Friday, October 23, 2009

Sheet
1

59

of

60

Version change list (P.I.R. List)


Item

Page 2 of 3
for HW

Fixed Issue

Reason for change

Rev.

PG#

30

Modify List

Date

pop R248, R271,R265

Phase
D

7/23

0.2

pop C165, del C170

7/23

0.2

18

unpop R532, R86

7/23

0.2

add R472 and C713

8/31

0.3

11

add C714

8/31

0.3

12

add C715

8/31

0.3

17

USB20 port 6 change to USB20 port 9

8/31

0.3

24

3VS_delay related circuit

8/31

0.3

30

del R236,C257 , pop R254,C268 in all sku

8/31

0.3

10

33

unpop R3 , U1, pop R6 , change R306 to 18K

8/31

0.3

11

37

ME_EN change from U25,75 to U25.16

8/31

0.3

12

29

pop Q6,Q7 in all sku

8/31

0.3

13

29

change L29~L34 footprint

8/31

0.3

14

41

del D25,D26,D27

8/31

0.3

15

43

update C705,C706 BOM structure

8/31

0.3

16

14

unpop R112

8/31

0.3

17

change C165 p/n

8/31

0.3

18

40

9/10

0.3

pop C353

change R157,R527,R570,R575,R582,R634,R239,R64 to 0 ohm

19

0.3

20

add R746,R747

9/10

0.3

21

12

U27 clk gen change to siligo

9/10

0.3

22

40

del C371,C372

9/10

0.3

23

Modify BOM Config add S3@ on all SKU

10/20

1.0

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/07/01

Deciphered Date

2009/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PIR (HW)
Rev
1.0
NALG0 M/B LA-5681P Schematic

Friday, October 23, 2009

Sheet
1

60

of

60

Version change list (P.I.R. List)


Item

Page 3 of 3
for HW

Fixed Issue

Reason for change

Rev.

PG#

Modify List
Change R209,C254,C255,Y6 BOM config to UMA@

Date

Phase

10/20

1.0

14

19

Added C257

10/20

1.0

22

Change N11 to A2 (P/N SA00003HZ10)

10/20

1.0

22

Added R748 and R749 as I2C pull high resistor.

10/20

1.0

22

Pop R36,R37 as DIS@

10/20

1.0

28

Change Q11,Q19 BOM config to SG@

10/20

1.0

28

Change R502,R484 BOM config to DIS only@

10/20

1.0

37

Change R306 to 33k(Board ID)

10/20

1.0

38

Change LED9 PN to SC5191UD00

10/20

1.0

10

43

Change R296 to 47K,R295 to 470

10/20

1.0

11

44

Change LED Resistors:

10/20

1.0

12

R373 to 243,R381 and R383 to 100,R377 to 243,

13

R375 and R376 to 470,R349 to 100,R350 to 191

14

R304 to 499

1.0

15

17

Change C256 to 22u

10/22

16

18

ADD R750 10K pull hig resistor

10/22

1.0

17
18
19
20
21
22
A

23

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2008/07/01

Deciphered Date

2009/12/31

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Date:

PIR (HW)
Rev
1.0
NALG0 M/B LA-5681P Schematic

Friday, October 23, 2009

Sheet
1

60

of

60