CONTENTS Page No

OBJECTIVES 2

INTRODUCTION TO MICROPROCESSORS 4

HARDWARE ARCHITECTURE 9

CLOCK, POWER SUPPLY AND 18

INSTRUCTION CYCLE

BUS CONCEPT 23

RAM & ROM, ADDRESSING MODES 25

INTERRUPTS 31

I / O CONCEPTS 39
 MODULE ON
MICROPROCESSOR
This topic consists of 8 hours of theory lectures and 6 hours of practical sessions,
one criterion test of one hour duration and two hours of practical test.
OBJECTIVES
Be able to
Lesson 1 Describe the parts of a computer.
• .Understand the Intel 8086 Microprocessor.
Lesson 2
• Describe the architecture of MPU 8086.
• Describe the stack and the stack pointer,PC and Flag register
Lesson Describe the Clock and power supplies
• Describe the 8086 pin diagram Describe the timing, power supply and
Instruction cycle of 8086.
Lesson 4 Describe the meaning of Bus in Microprocessor.
• Describe the types of Bus arrangements.
Lesson 5 Understand ROMs and RAMs.
• Describe the addressing modes in 8086 Microprocessor.
Lesson 6
• Describe the Hardware and Software Interrupts in 8086 Microprocessor.
• Describe the Interrupt response of 8086 Microprocessor.
Lesson 7
• . Describe the concept of memory mapped I/O.
• Describe the types of Data Transfer.
Criterion Test
The test will be held for ½ hour duration. The trainee is expected to secure 60
percent marks without the aid of the material
***********

chapter 1

2
 INTRODUCTION TO 8086 MICROPROCESSOR
Computers
Fig.1 shows a block diagram of a simple computer. The major parts are the central
processing unit or CPU, memory and the input and output circuitry or I/O and three sets
of parallel lines called Buses connecting these parts together. The three buses are called
address bus, data bus and control bus

Input Data Bus

device

Control Control
Bus Bus
I/O Central Memory
Ports Processing (RAM &
Unit ROM)

Output
device
Address Bus

Fig. 1 Block Diagram of a simple Computer

or a Microcomputer.
Memory
The memory section usually consists of RAM and ROM. It may also have
magnetic floppy disks, magnetic hard disks or laser option disks. Memory has two
purposes. The first purpose is to store the binary codes for the sequence of instructions
you want the computer to carryout. The second purpose of the memory is to store the
binary-coded data with which the computer is going to be working.
Input/Output
The input/output or I/O section allows the computer to take in data from the
outside world or send data to the outside world. Peripherals such as keyboards, video
display terminals, printers and modems are connected to the I/O section. These allow the
user and the computer to communicate with each other. The actual physical devices used
to interface the computer buses to external systems are often called ports.

Central Processing Unit

The Central Processing unit or CPU controls the operation of the computer. It
fetches the binary-coded instructions from memory, decodes the instructions into a series

3
of simple actions and carries out these instructions. The CPU contains an arithmetic and
logic unit or ALU which can perform arithmetical and logical calculations like add,
subtract, AND, OR, etc., The CPU also contains an address counter which is used to hold
the address of the next instruction to be fetched from the memory, general purpose
registers which are used for temporary storage of binary data, and circuitry which
generates and the control bus signals.
Address Bus
The address bus consists of 16, 20, 24 or more parallel signal lines. On these lines
the CPU sends out the address of the memory location that is to be written to or read
from. The number of memory locations that the CPU can address is determined by the
number of address lines. If the CPU has N address lines then it can directly address 2N
16
memory locations. For example, a CPU with 16 address lines can address 2 or 65, 536
memory locations.
Data Bus
The data bus consists of 8, 16, 32 or more parallel signal lines. The data bus lines
are bi-directional.
Control Bus
The control bus consists of 4 - 10 parallel signal lines. The CPU sends out signals
on the control bus to enable the outputs of addressed memory devices or port devices.
Typical control bus signals are memory/read, memory write , I/O read, and I/O write. To
read a byte of data from a memory location, for example, the CPU sends out the address
of the desired byte on the address bus and then sends out a memory read signal on the
control bus. The memory read signal enables the addressed memory device to output the
byte of data on the data bus where it is read by the CPU.
Hardware, Software, and Firmware
When working around computers you hear the terms hardware, software and
firmware. Hardware is the name given to the physical devices and circuitry of the
computer. Software refers to the programs written for the computer. Firmware is the term
given to the programs stored in ROMs or in other devices which keep their stored
information when the power is turned off.
What is a Microprocessor ?

4
 The entire CPU with timing and control functions on a single chip is known as
Microprocessor. Therefore a Microprocessor or MPU is an integrated circuit that contains
many processing capabilities of a large computer.
Microprocessor Evolution
A common way of categorizing is by the number of bits that their ALU can work
with at a time. A Microprocessor with a 4 - bit ALU will be referred to as a 4-bit
Microprocessor, regardless of the number of address lines or the number of data bus lines
that it has. The first microprocessor was the Intel 4004 produced in 1971. This 4004 was a
4 - bit device intended to be used with some other devices in making a calculator .Some
logic designers, however, saw that this device could be used to replace PC boards full of
combinational and sequential logic devices. Also, the ability to change the function of a
system by just changing the programming, rather than redesigning the hardware, is very
appealing. It was these factors that pushed the evolution of microprocessors.
In 1972 Intel come out with the 8008 which was capable of working with 8-bit
words. In 1974 Intel announced the 8080 which had a much larger instruction set than
8008. The 8080 is referred to as a second-generation microprocessor.
Soon after Intel produced 8080, Motorola came out with MC 6800, another 8-bit
general purpose CPU. Some of the other competitors were the MOS technology 6502 and
the Zilog Z80. The 16-bit microprocessors entered the marketplace in the late 1970s and
early 1980s. Then came the 32-bit processors.
Most Widely, Microprocessors are divided into two groups based on their origin.
These groups may be tabled as the 6’s group and that of the 8’s . A family tree of the 6’s
group and that of the 8’s group is shown in figure 2.

5
 Motorola
MOS technology, Intel Zilog
68030 Western Design Centre,
Rockwell 80386 Z80000

32-bit
65382 MPUs
68020

80286 16-bit
MPUs
80816/80188
68000/68010
Z-8000

8086/8088
About 1980 65802/65816

65C02 8-bit
MPUs

6809 6502 8085 Z-80

About 1974 6800 8080

6s 8s

Fig.2 Genealogy for 6’s group and 8’s group of microprocessors

We observe that as we progress upward on the family tree the trend is towards greater
complexity. Complexity is noted in the figure, in terms of the bit size of the internal
registers. The 6’s group traces its origin back to the original 6800 Microprocessor
designed by Motorola. The 8’s group traces its origin back to Intel’s 8080
Microprocessor. Each branch in Fig.2 is labeled near the top with the manufacturer
responsible for its development.

6
The INTEL 8086 Microprocessor
Introduction
The 8086 was the first 16-bit Microprocessor to be introduced by Intel
Corporation. It is designed to be upwardly compatible with the older 8080/8085 series of
8-bit microprocessors. The upward compatibility allows programs written for the
8080/8085 to be easily converted to run on the 8086.
The word 16-bit means that its arithmetic logical unit, internal registers, and most
of its instructions are designed to work with 16-bit binary words. The 8086 has a 16-bit
data bus, so it can read data form or write data to memory and ports either 16-bits or 8-
bits at a time. The 8086 has a 20-bit address bus, so it can address any one of 220 or
1,048,576 memory locations. Each of the 1,048,576 memory addresses of the 8086
represents a byte-wide location. Words will be stored in two consecutive memory
locations. If the first byte of a word is at an even address, the 8086 can read the entire
word in one operation. If the first byte of the word is at an odd address, the 8086 will read
the first byte of the word in one operation, and the second byte in another operation.

*****

7
 Chapter 2
HARDWARE ARCHITECTURE
The term architecture, as used in microprocessor circuits, describes the functional
components that make up the MPU and the interaction between them. These include the
temporary storage devices known as registers, which are used to hold data, instructions,
and status information. There are also devices to perform arithmetic and logical
operations. Control devices are used to control the flow of information through the MPU.

MEMORY
INTERFACE

Fig.3 8086 Internal Block Diagram

As shown by the block diagram in fig.3, the 8086 MPU is divided into two
independent functional parts known as the execution unit (EU)and the bus interface unit
(BIU).

8
Execution unit (EU)
The EU is where the actual processing of data takes place inside the 8086 MPU. It
is here that the arithmetic and logic unit (ALU) is located, along with the registers used to
manipulate data and store immediate results. The EU accepts instructions and data that
have been fetched by the BIU and then processes the information. Data processed by the
EU can be transmitted to the memory or peripheral devices through the BIU. EU has no
direct connection with the outside world and relies solely on the BIU to feed it with
instructions and data as indicated in fig.4

Bus Interface Unit (BIU)

The BIU is made up of the address generation and bus-control unit, the
instruction queue, and the instruction pointer. It has the task of making sure that the bus
is used to its fullest capacity in order to speedup operations. This function is carried in two
ways. First, by fetching the instructions before they are needed by the execution unit and
storing them in the instruction queue, the 8086 MPU is able to increase computing speed.
Second, by taking care of all bus-control functions, the EU is free to concentrate on
processing data and carrying out the instructions. The instruction pointer contains the
location or address of the next instruction to be executed.
Inside the EU
The EU is made up of two parts known as the ALU and the general registers. It is
here that instructions are received, decoded, and executed from the instruction queue

9
portion of BIU. The instructions are taken from the top of the instruction queue on the
first-in, first-out, or FIFO, basis.
ALU
The ALU is the calculator part of the execution unit. It consists of electronic
circuitry that performs arithmetic operations or logical operations on the binary
represented electrical signals. The control system for the execution unit can also be
thought of as part of ALU. It provides a path for the flow of instructions into the ALU,
the general registers, and the flag register.
Flag Register
A flag is a flip-flop which indicates some condition produced by the execution of
an instruction or controls certain operations of the EU. The Flag Register is a special
register associated with the ALU. A 16-bit flag register in the EU contains nine active
flags. Fig.5 shows the location of the nine flags in the flag register.

Six flags are status flags- AF, CF, OF, SF, PF and ZF. The remaining three flags are control
flags -DF,IF, and TF. Table 1 presents a flag summary and highlights key concerns. Each
flag is next discussed in detail.
Table 1
Flag summary
Status Flags Description
AF (auxiliary flag) Indicates if the instruction generated a carry out the 4 LSBs.

10
CF (carry flag) Indicates if the instruction generated a carry out the MSB.
OF (overflow flag) Indicates if the instruction generated a signed result that is
out of range.
SF (sign flag) Indicates if the instruction generated a negative result.
PF (parity flag) Indicates if the instruction generated a result having an even
number of 1s.
ZF (zero flag) Indicates if the instruction generated a zero result
DF(direction flag) Controls the direction of the string manipulation instructions.
IF (interrupt-enable Enables or disables external interrupts.
flag)
TF ( trap flag) Puts the processor into a single-step mode for program
debugging

• AF (auxiliary flag). If this flag is set, there has been a carry out or borrow of the 4
least significant bits. This flag is used during decimal arithmetic instructions.
• CF(carry flag). If this flag is set, there has been a carry out or overflow of the most
significant bit. It is used by instructions that add and subtract multi byte numbers.
• OF (overflow flag). If this flag is set, an arithmetic overflow has occurred; that is , a
significant digit has been lost because the size of the result exceeded the capacity of its
destination location.
• SF (sign flag). Since negative binary numbers are represented in the 8086/8088 in
standard 2s complement notation. SF indicates the sign of the result ( 0 = positive, 1
= negative).
• PF (party flag). If this flag is set, the result has even parity, an even number of 1s.
This flag can be used to check for transmission errors.
• ZF (zero flag). If this flag is set, the result of the operation is 0.
• DF(direction flag). Setting DF causes string instructions to auto-decrement (count
down); that is, to process strings from the high address to the low address, or from
right to left. Clearing DF causes string instructions to auto-increment (count up), or
process strings from left to right.
• IF ( interrupt-enable flag) Setting IF allows the MPU to recognize external
(maskable) interrupt requests. Clearing IF disables these interrupts. IF has no effect on
either nonmaskable external or internally generated interrupts.

11
• TF (trap flag) . Setting TF puts the processor into single-step mode for debugging. In
this mode the MPU automatically generates an internal interrupt after each instruction,
allowing a program to be inspected as it executes instruction by instruction.
General Purpose Registers
EU has eight general purpose registers labeled AH, AL, BH, BL, CH, CL, DH and
DL. These registers are a set of data registers, which are used to hold intermediate results.
The H represents the high- order or most- significant byte and the L represents the low-
order or least-significant byte. Each of these registers may be used separately as 8-bit
storage areas or combined to form one 16-bit ( one word) storage area.
The acceptable register pairs are AH and AL, BH and BL, CH and CL and DH and DL.
The AH-AL pair is referred to as the AX register, the BH-BL pair is referred to as the BX
register, the CH-CL pair is referred to as the CX register, and the BH-BL pair is referred
to as the DX register.
The AL register is also called as the Accumulator. For 16-bit operations, AX is
called the accumulator.
The 8086 register set is very similar to those of earlier generation 8080 and 8085
microprocessors. Many programs written for the 8080 and 8085 could easily be translated
to run on the 8086.

12
Stack Pointer Register
A Stack, is a section of memory set aside to store addresses and data while a
subprogram is being executed. An entire 64 K bytes segment is set aside as Stack in 8086
MPU. The upper 16 bits of the starting address for this segment is kept in the stack
segment register. The Stack Pointer (SP) register contain the 16-bit offset from the start of
the segment to the memory location where a word was most recently stored on the Stack.
The memory location where a word was most recently stored is called the top of Stack.
Fig.6 shows the details.

The physical address for a stack read or for a stack write is produced by adding the
contents of the stack pointer register to the segment base address in SS. To do this the
contents of the Stack segment register are shifted four bit positions left and the contents
of SP are added to the shifted result. In the figure 5000 H in SS is shifted left four bit
positions to give 50000H. When FFEOH in the SP is added to this, the resultant physical
address for the top of the stack will be 5FFEOH. The physical address can be represented
either as a single number 5FFEOH, or it can be represented in SS:SP form as
5000:FFEOH.

13
Other pointer and Index Registers
In addition to the Stack Pointer register, SP, the EU contains a 16-bit base pointer
(BP) register. It also contains a 16-bit Source index (SI) register and a 16-bit destination
index (DI) register. These three registers can be used for temporary storage of data just as
the general purpose registers. However, their main use is to hold the 16-bit offset of a data
word in one of the segments. That is, the pointer and index registers are usually used to
point to or index to an address in memory. When used in this manner, these registers are
address registers that designate a specific location in the memory that may be frequently
used by the program. The addresses contained in these registers can be combined with
information from the BIU to physically locate the data in the memory.
The Bus Interface Unit
The BIU sends out addresses, fetches instructions from memory, reads data from
ports and memory. In other words the BIU handles all transfers of data and addresses on
the buses for the execution unit. The BIU can be thought of as three functional blocks;
Bus control, Instruction queue and Address control.
But control
The bus-control unit performs the bus operations for the MPU. It fetches and
transmits instructions, data and control signals between MPU and the other devices of the
system.
Instruction Queue
The instruction queue is used as a temporary memory storage area for data
instructions that are to be executed by the MPU. The BIU, through the bus-control unit,
prefetches instructions and stores them in the instruction queue. This allows the execution
unit to perform its calculations at maximum efficiency. Because the BIU and EU
essentially operate independently, the BIU concentrates on loading instructions into the
instruction queue. This usually takes more time to do than the calculations performed by
the execution unit. In effect, the BIU and the EU work in parallel. The instruction queue is
a first-in, first-out (FIFO) memory. This means that the first instruction loaded into the
instruction queue by the bus control unit will be the first instruction to be used the ALU.
Address control

14
 The address-control unit is used to generate the 20-bit memory address that gives
the physical or actual location of the data or instruction in memory. This unit consists of
the instruction pointer, the segment registers and the address generator as shown in fig 7.

Instruction Pointer
The Instruction Pointer (IP) is a 16- bit register that is used to point to, or tell the
MPU, the instruction to execute next. Therefore, the instruction pointer is used to control
the sequence in which the program is executed. Each time the execution unit accepts an
instruction, the instruction pointer, is incremented to point to the next instruction in the
program.

15
Segment Registers
There are four segment registers. They are the code segment (CS), the data
segment (DS), the stack segment (SS), and the extra segment (ES). These registers are
used to define a logical memory space or memory segment that is set aside for a particular
function.
The CS register points to the current code segment. Instructions are fetched from
this segment. The DS register points to the current data segment. Program variables and
data are held in this area. The SS register points to the current stack segment, stack
operations are performed on locations in the SS segment. The ES register points to the
current extra segment, which is also used for data storage. Each of the segment registers
can be upto 64 kilo bytes long. Each segment is made up of an uninterrupted section of
memory locations. Each segment can be addressed separately using the base address that
is contained in its segment register. The base address is the starting address for that
segment.
Address Generator
The address-generator unit is used with the segment registers to generate the 20-
bit physical address required to identify all the possible memory addresses. The 20 address
lines give a maximum physical memory size of 20 address locations, or 1,048,576 bytes of
memory. But all the registers in the MPU are only 16 bits wide. The physical address is
obtained by shifting the segment base value four bit positions ( one hexa decimal position)
and adding the offset or logical address of the segment.

*****

16
 Chapter 3
CLOCK, POWER SUPPLY AND INSTRUCTION CYCLE
Fig 8 shows the 8086 pin diagram. Vcc is on pin 40 and ground on pins 1 and 20.
8086 requires +5v supply. Clock input labeled CLK is on pin 19. An 8086 requires a clock
signal from some external, crystal- controlled clock generator to synchronize internal
operations in the processor. Different versions of the 8086 have maximum clock
frequencies ranging from MHz to 10 MHz.

Pins 2 through 16 and pins 35 through 39 are used for the address bus. Pins 35
through 38 are used by multiplexing to provide information or status about the MPU. The
status signals are labeled S3, S4, S5 and S6 as shown. The data bus lines AD0 through
AD15 are used at the start of the machine cycle to send out addresses, and later in the
machine cycle they are used to send or receive data. The 8086 sends out a signal called
address latch enable or ALE on pin 25 to let external circuitry know that an address is on
the data bus. The upper 4 bits of an address are sent on the lines labeled A16/ S 3 through
A19/ S 6.

17
 Some of the control bus lines on a microprocessor usually have mnemonics such as
RD, WR and M/ IO. Pin 32 of the 8086 is labeled RD. A tri-state active-low output signal
on pin 32 indicates that the 8086 is reading data from memory or from a port. Pin 29 has a
label WR next to it. However, pin 29 also has a label LOCK next to it, because this pin
has two functions. The function of this pin and the functions of the pins between 24 and
31 depend on the mode in which the 8086 is operating.
The operating mode of the 8086 is determined by the logic level applied to the MN
/ MX input on pin 33. If pin 33 is asserted high, then the 8086 will function in minimum
mode, and pins 24 through 31 will have functions shown in parentheses next to the pins in
fig. 8. If the MN / MX pin is asserted low, then the 8086 is in maximum mode. In this
mode pins 24 through 31 will have the functions described by the mnemonics next to the
pins in fig. 8. A tri-state active-low output signal on pin 29 indicates that MPU has put
valid and stable data on the data bus. Pin 28 will function as M / IO. The 8086 will assert
this signal high if it is reading from or writing to a memory location, and it will assert a
signal low if it is reading from or writing to a port. In the maximum mode the control bus
signals (S0, S1, S2 ) are sent out in encoded form on pins 26,27 and 28. An external bus
controller device decodes these signals to produce the control bus signals required for a
system, which has two or more microprocessors sharing the same buses.
If pin 21, the RESET input is made high, the 8086 will, no matter what it is doing,
reset its DS, SS, ES, IP and flag registers to all 0's. It will set its CS register to FF. When
the RESET signal is removed from pin 21, the 8086 will then fetch its next instruction
from physical address (FFFF0H). This address is produced in the 8086 Bus Interface unit
(BIU) by shifting the FFFFH in the CS register 4 bits left by adding the 0000H in the
instruction pointer to it. The first instruction that has to be executed after a reset is put at
this address FFF0H.
8086 has two interrupt inputs, non-maskable interrupt (NMI) input on pin 17 and
the interrupt (INTR) input on pin 18. An active-high on any one of these pins will cause
the 8086 to stop execution of its current program and go execute a specified procedure.
At the end of the procedure it can return to executing the interrupted program. The NMI
cannot be ignored, or masked, by the MPU. The INTR (interrupt request) is maskable and
can be made to be ignored by the MPU through software control.

18
 A tri-state active-low output signal on pin 26 DEN (data enable) determines
whether the data buffer is enabled or disabled. A tri-state output signal on pin 27 DT / R
(data transmit receive) is used to control the direction of data flow. A logic level 1
indicates data bits are being transmitted from the MPU. A logic level 0 indicates that data
bits are being received into the MPU.
All microprocessors use an oscillator to generate a master frequency clock to
synchronize or time operations. For the 8086 microprocessor the oscillator frequency, or
clock frequency is typically 5 MHz. The period of one clock cycle is then equal to.
T = 1/F
= 1/5 x 106 Hz
= 0.2 x 10-6 sec.
= 200 n sec
The 8086 operates in time periods called bus cycles. Each bus cycle requires 4
clock cycles to complete. Therefore, the bus cycle is completed very 800 ns. A typical bus
cycle is shown in fig 9.

One cycle of this is referred to as a state. A state is measured from the 50 percent
point on the falling edge of one clock pulse to 50 percent point on the falling edge of the
next clock pulse- T1 in the figure is a state. Each basic bus operation such as reading a
byte from memory or writing a word to a port requires some number of states. The group

19
of states required for a basic bus operation is called a machine cycle. The total time it
takes the 8086 to fetch and execute an instruction is called an instruction cycle. An
instruction cycle consists of one or more machine cycles. To summarize, an instruction
cycle is made up of machine cycles, and a machine cycle is made up of states.
Two major bus cycles are the read bus cycle and the write bus cycle. The read bus
cycle is activated when the microprocessor is reading information from the memory or an
I/O device. During the read bus cycle, there are normally four clock cycles T1 ,T2, T3 and
T4. However, if the device outputting data to the MPU needs more time to send the data,
a wait state (Tw) is initiated by placing extra clock cycles (Tw's) between cycles T3 and T4.
Fetch-Execute cycle
The microprocessor has two primary functions. Fetch and execute. First it must
fetch or read the program instruction or data. This can take one or more bus cycles. Once
it has fetched the necessary program instructions and data through the BIU, the
microprocessor's next step is to execute the instructions. The EU receives the instruction
from the instruction queue and executes it. Some instructions may take 2 clock cycles to
execute, where as others may take as many as 100 clock cycles to execute. In older
microprocessors this left the bus idle while the MPU was executing a long instruction, as
shown in the fig. 10. however, since the 8086 MPU is broken up into two functional units,
the BIU and EU, it avoids much of the idle time required by older microprocessors. It
does this by having the BIU pre fetch instructions and place them into the instruction
queue and data registers while the EU is executing the program instructions. Therefore,
while the bus is busy during a read cycle, the EU can be executing the previous
instructions. When the bus is busy during a write cycle, the EU can be executing another
instruction. This greatly increases the effective speed of the entire system.

20
*****

21
 Chapter 4
BUS CONCEPT, DATA BUS, ADDRESS BUS, CONTROL BUS

A Bus is a group of common wires in which signals travel. The three types of buses
used are the Address Bus, the Data Bus and the control Bus.
Address Bus
An address is a unique location in memory. It is like a mailbox in the post office,
where each mail box has its own unique number to identify its location. An address bus
consists of 16,20,24 or more parallel signal lines. On these lines the CPU sends out the
addresses of the memory location that is to be written to or read from. The total number
of memory locations is determined by the number or address lines. In the 8086 the
address is determined by a 20-bit number. This gives us 220 possible address locations, or
1,048,576 bytes of memory.
An address bus is made up of 20 wires, or conductors, labeled A0 through A19 ,
with A0 as the LSB and A19 as the MSB. It is used to locate or find information in
memory. It is also used to define a location in memory where information is to be stored.
The address bus is some times used to identify which I/O port is used for input/output
operations.
Data Bus
A data bus is used to move information ( data and instruction ) from the MPU to
memory and other devices. This is referred to as a write operation. The data bus is also
used to receive information into the MPU. This is called as a read operation. Because the
data bus receives and transmits information, it is known as a bi-directional bus. However,
it cannot receive and transmit data at the same time.
The Intel 8086 has a 16-bit data bus labeled D0 to D15, where D0 is the LSB and
D15 is the MSB. The 8086 microprocessor multiplex the address and data buses.
Multiplexing is the process of using the same wires or pins to do different things at
different times. When acting as a data bus, the signal lines carry read/write information for
memory or input/output information for I/O devices. When acting as an address bus, the
same signal lines are used to locate information.
Control Bus

22
 The CPU sends out signals on the control bus to enable the outputs of addressed
memory devices or port devices. The control line determines the sequence of operations to
be performed. The control bus consists of 4 to 10 parallel signal lines. Typical control bus
signals are memory read, memory write, I/O read, and I/O write. To read a byte of data
from a memory location, for example, the CPU sends out the address of the desired byte
on the address byte and then sends out a memory read signal on the control bus. The
memory read signal enables the addressed memory device to output the byte of data on to
the data bus where it is required by the CPU.

*****

23
 Chapter 5
RAM & ROM, ADDRESSING MODES & CONTEXT SWITCHING
Memory
A memory stores large number of binary words. Since the early 1970s, ICs or semi
conductor memory have been the most widely used type of primary memory found in
micro computers. The simplest form of computer memory is the basic flip-flop and a flip-
flop is called a memory cell which can be used store a single bit ( 0 or 1). 8 or 16 cells are
connected together to form a memory byte or memory word. Each memory byte or word
has a unique location in the memory called an address. Therefore, memory is a place
where data bits ( 0 or 1) can be stored and then later retrieved when the computer needs
it. The process of storing data into the memory is called writing. The process of retrieving
data from the memory is called reading. Accordingly, we say that a microprocessor is in a
write cycle or performing a write operation when it is storing data into memory. The
process by which a microprocessor retrieves data from memory is called a read cycle or
read operation.
Memory classification
Memory can be classified into three general types, ROM and RAM. ROM stands
for read- only memory. ROM generally contains permanently stored data that cannot be
changed. It can be read but not written into. The main feature of ROMs is that they are
non-volatile, which means that the information stored in them is not lost when the power
is removed.
RAM, on the other hand, is memory that can be read from or written to. RAM
stands for random-access memory, but since ROMs are also random access, the major
difference is that RAM is memory that can be read or written to. RAM is actually
read/write memory. RAM memory is volatile memory, that is, it is lost whenever the
power is switched off.
ROM
ROMs can be classified into three general types. A maskable ROM is a ROM that
is programmed with information or data by the manufacturer. Once programmed these
data bits cannot be altered or changed. A programmable ROM, or PROM, is a device that
can be programmed by a user. Once programmed, the data in a PROM, like a ROM,
cannot be altered or changed . An erasable PROM, or EPROM, is a type of ROM that

24
can be programmed by an user but whose data may be erased or changed with use of
specialized equipment.
A summary of the different types of ROMs is given below:
• Mask-programmed ROM -Programmed during manufacture; cannot be
changed.
• PROM- user programs by blowing fuses; cannot be erased except to
blow additional fuses.
• EPROM- Electrically programmable by the user; erased by passing
ultra violet light through a quartz window in the package.
• EEPROM-Electrically programmable by the user; erased with electrical
signals instead of ultra violet light.
RAM
RAM or read/write memory, is a type of volatile memory from which data can be
read and into which data can be written. RAM can be classified as either Static or
dynamic. A Static RAM is essentially a matrix of flip-flops. Therefore, we can write a new
data word in a RAM location at any time by applying the word to the flip-flop data input
and clocking the flip-flops. The stored data word will remain on the flip-flop outputs as
long as the power is left on. This type of memory is volatile because data is lost when the
power is turned off. These types of storage device is called static RAM. In dynamic
RAMs, binary 1's and 0's are stored as an electrical charge or no charge on a tiny capacitor.
The internal capacitance of a MOSFET is great enough to make it appear that a small
capacitor (a few pico-farads ) exists in the MOSFET. Each memory cell is essentially a
single MOSFET. A logic 1 or a charged capacitor must be refreshed, or recharged, at least
once every 2 ms, or the capacitor will lose its charge and the data.
Addressing Modes
The different ways that a processor can access data are referred to as its
addressing modes. It is the way by which the location of the operand is determined. How
an operand is addressed in a program depends on the types and location of the data.
There are three general types of addressing modes:
• Immediate addressing modes.
• Register addressing modes.

25
 • Memory addressing modes.
Immediate Addressing mode
Suppose that in a program we need to put the number 526AH in the CX register.
The MOV CX, 526AH instruction can be used to do this. This instruction will put the
immediate hexadecimal number 526AH in the 16- bit CX register. This is referred to as
immediate addressing mode because the number to be loaded into the CX register will be
put in two memory locations immediately following the code for the MOV instruction.
A similar instruction, MOV CL, 48H could be used to load the 8-bit immediate
number 48H into the 8-bit CL register. It is also possible to write instructions to load an 8-
bit immediate number into an 8-bit memory location or to load a 16-bit number into two
consecutive memory locations.
Register Addressing mode
Register is the source of an operand for an instruction in Register Addressing
mode. For example, the instruction MOV CX, AX copies the contents of the 16-bit AX
register into the 16-bit CX register. Destination register is specified in the instruction
before the source. When it executes, the contents of AX are just copied to CX, not
actually moved. In other words, the previous contents of CX are written over, but the
contents of AX are not changed. For example, if CX contains 2A84H and AX contains
4971H before the execution, then after the execution of the instruction CX will contain
4971H and AX will still contain 4971H. The contents of any 16-bit register can be moved
into any 16-bit register, or the contents of any 8-bit register can be moved into any 8-bit
register. However, an instruction of the type MOV CX, AL cannot be used because this is
an attempt to copy a byte- type operand (AL) into a word type destination (CX). A byte in
AL would fit in CX, but the 8086 would not know which half of CX to put it in. But if the
byte from AL is to be copied into the high byte of CX, the instruction MOV CH, AL could
execute it. The instruction MOV CL, AL will copy the byte from AL to CL, the low byte
of CX.
Memory Addressing Modes
To access data in memory the 8086 must produce a 20-bit physical address. It is
done by adding a 16-bit value called the effective address to one of the four segment
bases. This effective address (EA) represents the displacement or offset of the desired
operand from the segment base. Any of the segment bases can be specified, but the data

26
segment is the one most often used. Fig 11(a) shows a graphic form how EA is added to
the data segment base to point an operand in the memory. The fig 11(b) shows how the
20-bit physical address is generated by the BIU. The starting address for the data segment
in fig 10 (b) is 2000H so that the data segment register will contain 2000 H. The BIU
shifts the 2000 H four bit positions left and adds the effective address, 437AH, to the
result. The 20-bit physical address sent out to memory by the BIU will then be 2437AH.
The physical address can be represented either as a single number, 2437AH, or in the
segment base; offset form as 2000 : 437AH

Direct Addressing Mode

For the simplest memory addressing mode the effective address is just an 8-bit or
16-bit number written directly in the instruction. The instruction MOV CL ,[437AH] is an
example. The brackets around the 437AH are shorthand for "the contents of the memory
location at a displacement from the segment base of". When executed, this instruction will
copy the contents of the memory location, at a displacement of 437AH from the data
segment base into the CL register. The actual 20-bit physical memory address will be
produced by shifting the data segment base in DS four bits left and adding the effective

27
address 437AH to the result. Fig 10(b) shows how the operation is done. This addressing
mode is called direct because the displacement of the operand from the segment base is
specified directly in the instruction.
Another example of this addressing mode is the instruction MOV BX, [437AH].
When executed, this instruction copies a word from memory into BX register. Since each
memory address of the 8086 represents a byte of storage, the word must come from two
memory locations. The byte at a displacement of 437AH from the data segment base will
be copied into BL. The contents of the next higher address, displacement 437BH will be
copied into BH register. The 8086 will automatically access the required number of bytes
in memory for a given instruction.
The previous examples showed how the direct addressing mode can be used to
specify the source of an operand. It can also be used to specify the destination of an
operand. The instruction MOV[437AH], BX for example will copy the contents of the
BX register to two memory locations in the data segment. The contents of BL will be
copied to the memory location as a displacement of 437AH and the contents of BH will be
copied to the memory location at a displacement of 437BH.
Indirect Addressing mode
In the direct addressing mode, either the source or the destination operand is a
specific memory location defined by the address number or a label. For example, in the
instruction MOV AX, MEM 1 the contents of the memory address labeled MEM 1 is
copied or moved into AX register.
In the indirect addressing mode, the memory address is not directly given. A
register is used to indicate the address where the data can be found. Therefore , the
register acts as an indirect address to locate the data. For example, in the instruction
MOV (BX), CX the source of data is the CX register. The destination where the data are
to be placed or copied to, is the address pointed to by the BX register. The brackets ( )
around BX indicate that the BX register contains an address and not a numeric value.
Segmentation
Intel has designed the 8086 family devices to use memory segmentation. By
working with only 64 K bytes segments of memory at a time, the 8086 only has to work
with 16-bit effective addresses to access any location in the segment. In other words,
because of the segmentation scheme the 8086 has to manipulate and store 16-bit address

28
components. Also, in a time-share microcomputer system several users share a CPU. The
CPU works on one user's program for perhaps 20 milliseconds. After working for 20 m
sec on one user's program, it then works on the next user's program for 20 milliseconds.
After working for 20 milliseconds for each of the other users, the CPU comes back to
working on the first user's program again. Each time the CPU switches from one user's
program to the next it must access a new section of code and sections of data.
Segmentation makes this switching quite easy. Each user's program can be assigned a
separate set of logical segments for its code and data. The user's program will contain
offsets or displacements from these segment bases to change from one user's program to a
second user's program all that has to be done is to reload the four segment registers with
the segment base address assigned to the second user's program. In other words,
segmentation makes it easy to keep user's programs and data separate from each other,
and segmentation makes it easy to switch from one user's program to another user's
program.

*****

29
 Chapter 6
INTERRUPT (HW AND SW)
What is an interrupt ?
An interrupt is the method of accessing the MPU by a peripheral device. An
interrupt is used to cause a temporary halt in the execution of a program. The MPU
responds to the interrupt with an interrupt service routine, which is a short program or
subroutine that instructs the MPU on how to handle the interrupt.
When the 8086 is executing a program, it can get interrupted because of one of the
following.
1. Due to an interrupt getting activated. This is called as hardware interrupt.
2. Due to an exceptional happening during an instruction execution, such as
division of a number by zero. This is generally termed as exceptions or Traps.
3. Due to the execution of an Interrupt instruction like "INT 21H". This is called
a Software interrupt.
The action taken by the 8086 is similar for all the three cases, except for minor differences.
There are two basic types of interrupts, maskable and non-maskable. A
nonmaskable interrupt requires an immediate response by the MPU. It is usually used for
serious circumstances like power failure. A maskable interrupt is an interrupt that the
MPU can ignore depending upon some predetermined condition defined by the status
register. Interrupts are also prioritized to allow for the case when more than one interrupt
needs to be serviced at the same time.
Hardware interrupts of 8086
In a microcomputer system whenever an I/O port wants to communicate with the
microprocessor urgently, it interrupts the microprocessor. In such a case, the
microprocessor completes the instruction it is presently executing. Then, it saves the
address of the next instruction on the stack top. Then it branches to an Interrupt Service
Subroutine (ISS), to service the interrupting I/O port. An ISS is also commonly called as
an Interrupt Handler. After completing the ISS, the processor returns to the original
program, making use of the return address that was saved on the stack top.
In 8086 there are two interrupt pins. They are NMI and INTR. NMI stands for
non maskable interrupt. Whenever an external device activates this pin, the
microprocessor will be interrupted. This signal cannot be masked. NMI is a vectored

30
interrupt. This means, the 8086 knows where to branch to service the NMI request. If
both NMI and INTR are activated at the same time, NMI will be serviced first.
In an 8086 system the first 1 K bytes memory from 00000H to 003FFH is set
aside as a table for storing the starting addresses of interrupt service procedures. Since 4
bytes are required to store the CS and IP values for each interrupt service procedure, the
table can store starting addresses for upto 256 interrupt procedures. The starting address
of an Interrupt Service procedure stored in this table is often called as Interrupt Vector
Table or the Interrupt Pointer Table.

Fig. 12 shows how the 256 interrupt pointers are arranged in the memory table.
The lowest five types are dedicated to specific interrupts such as the divide by zero
interrupt and the non maskable interrupt. The next 27 interrupt types, from 5 to 31 are
reserved by Intel for use in future microprocessors. The upper 224 interrupt types, from
32 to 255, are available to use for hardware and software interrupts.
Action taken by 8086 when NMI is activated

31
 When NMI pin interrupts the 8086, a branch takes place to the ISS, whose
interrupt type number is 2. The action taken is as follows:
1. Completes the current instruction that is in progress.
2. Push the Flag register values on to the stack.
3. Push the CS value and IP value of the return address on to the stack.
4. IP is loaded from contents of the word location 00008H.
5. CS is loaded from contents of next word location 0000AH.
6. Interrupt flag and trap Flag are reset to O.
Return from Interrupt Handler (IRET)
The execution of the IRET instruction results in POP from the stack top, the IP,
CS and Flag registers. Thus return back to the interrupted program takes place. When the
control is transferred back to the interrupted program, the register values are not the same
it was before the occurrence of interrupt. To solve this problem, an ISS starts with saving
register values on the stack. Finally, the register values are restored from the stack and a
return to the interrupted program takes place using the IRET instruction.
Action taken by 8086 when INTR line is activated
Whenever an external signal activates the INTR pin, the microprocessor will be
interrupted only if interrupts are enabled using set interrupt Flag instruction. If the
interrupts are disabled using clear interrupt Flag instruction, the microprocessor will not
get interrupted even if INTR is activated. That is, INTR can be masked.
INTR is a non vectored interrupt, which means, the 8086 does not know where to
branch to service the interrupt. The 8086 has to be told by an external device like a
Programmable Interrupt controller regarding the branch.
Whenever the INTR pin is activated by an I/O port, if Interrupts are enabled and
NMI is not active at that time, the microprocessor finishes the current instruction that is
being executed and gives out a ‘0’ on INTA pin twice. When INTA pin goes low for the
first time, it asks the external device to get ready. In response to the second INTA the
microprocessor receives the 8 bit, say N, from a programmable Interrupt controller. The
action taken is as follows.
1. Complete the current instruction.
2. Activates INTA output, and receives type Number, say N.

32
 3. Flag register value, CS value of the return address & IP value of the
return address are pushed on to the stack.
4. IP value is loaded from contents of word location N x 4.
5. CS is loaded from contents of the next word location.
6. Interrupt Flag and trap Flag are reset to 0.
At the end of the ISS, there will be an IRET instruction. This performs popping off
from the stack top to IP, CS and Flag registers. Finally, the register values which are also
saved on the stack at the start of ISS, are restored from the stack and a return to the
interrupted program takes place using the IRET instruction.
Divide-by-zero interrupt - Type 0
The 8086 will automatically do a Type 0 interrupt if the result of a division
operation is too large to fit in the destination register. For example, if we execute DIV BL,
then AX will be divided by BL. The quotient will be stored in AL and the remainder in AH.
If AX content is 4060H and BL is 02H, then the quotient is 2030H. But the 8-bit AL
register cannot hold this data. This results in automatic branching to an ISS. It is an
internal interrupt, and the 8086 branches to an ISS whose interrupt Type number is 0.
Action taken by the 8086 when divide by zero error occurs is as follows.
1. Flag register value is pushed on to the stack.
2. CS value of the Return address and IP value of the Return address are
pushed on to the stack.
3. IP is loaded from contents of word location 0x4 = 00000H.
4. CS loaded from contents of next word location, 00002H.
5. Interrupt Flag and trap Flag are reset to 0.
The action taken by the ISS could be to display a suitable error message on the
CRT and then halt the proceedings. Or, it could be to set a bit in a memory location to
indicate an error, and then return to the interrupted program using the IRET instruction.
Single-Step Interrupt - Type 1
When we tell a System to single- Step , it will execute one instruction and stop.
We can then examine the contents of the registers and memory locations. If they are
correct, we can tell the system to go on and execute the next instruction. In other words,
when in single-Step mode, a system will stop after it executes each instruction and wait for

33
further directions from the user. The 8086 trap flag and type 1 interrupt make it quite easy
to implement a single-Step feature.
If the 8086 trap flag is set, the 8086 will automatically do a type 1 interrupt after
executing each instruction. It is an internal interrupt caused by the completion of an
instruction execution. It is useful for debugging a program.
The action taken by the 8086 when T flag is set to 1, and an instruction execution
is completed is as follows.
1. Flag register values is pushed on to the stack.
2. CS value of the return address and IP value of the return address are pushed on
to the stack.
3. IP is loaded from the contents of the word location, 1x4 = 00004H.
4. CS is loaded from contents of the next word location, 00006H.
5. Interrupt Flag and trap Flag are reset to 0.
The action taken by the ISS could be to display the contents of the various
registers on the CRT and then return to the interrupted program using the IRET program.
Software interrupt Instructions
There are instructions in 8086 which cause an interrupt. They are
1. INT instructions with type number specified.
2. INT 3, Break Point Interrupt instruction.
3. INTO, Interrupt on overflow instruction.
These are instructions at the desired places in a program. When one of these
instructions is executed a branch to an ISS takes place. Because their execution results in
a branch to an ISS, they are called interrupts.
Software Interrupt instructions can be used to test the working of the various
Interrupt handlers- For example, we can execute INTO instruction to execute type 0 ISS,
with out really having to divide a number by 0. Similarly, we can execute INT 2 instruction
to test NMI ISS.
INT-Interrupt Instruction with Type number Specified
The mnemonic for this is INT. It is a 2 byte instruction. The first byte provides the
op-code and the second byte the Interrupt type number. Op-code for this instruction is
CDH.

34
The execution of an INT instruction, say INTN, when N is the value in the range 00H to
FFH, results in the following:
1. Flag register value is pushed on to the stack.
2. CS value of the Return address and IP value of the Return address are pushed
on to the stack.
3. IP is loaded from the contents of the word location N x 4.
4. CS is loaded from the contents of the next word location.
5. Interrupt Flag and Trap Flag are reset to 0.
Thus a branch to the ISS take place. During the ISS, interrupts are disabled
because the Interrupt flag is reset to 0.
At the end of the ISS, there will be an IRET instruction. Thus a return back to the
interrupted program takes place with Flag registers unchanged.
INT 3-Break Point Interrupt Instruction
When a break point is inserted, the system executes the instructions upto the
breakpoint, and then goes to the break point procedure. Unlike the single-Step feature
which stops execution after each instruction, the breakpoint feature executes all the
instructions upto the inserted breakpoint and then stops execution.
The mnemonic for the instruction is INT3. It is a 1 byte instruction Op-code for
this is CCH.
The execution of INT3 instruction results in the following.
1. Flag register value is pushed on to the Stack.
2. CS value of the return address and IP value of the return address are pushed on
to the Stack.
3. IP is loaded from the contents of the word location 3x4 = 0000CH.
4. CS is loaded from the contents of the next word location.
5. Interrupt Flag and Trap Flag are reset to 0.
Thus a branch to the ISS takes place. During the ISS, interrupts are disabled
because Interrupt flag is reset to 0. At the end of the ISS, there will be an IRET instruction
to return back to the interrupted program.
A break point interrupt service procedure usually saves all the register contents on
the Stack. Depending upon the system, it may then send the register contents to the CRT
display and wait for the next command from the user.

35
INTO - Interrupt on overflow instruction
The 8086 overflow flag, OF, will be set if the signed result of an arithmetic
operation on two signed numbers is too large to be represented in the destination register
or memory location. For example, if we add the 8-bit signed number 01101100 and the 8-
bit signed number 01010001, the signed result will be 10111101. This is correct if we add
unsigned binary numbers, but it is not the correct signed result.
There are two ways to detect and respond to an overflow error in a program. One way is
to put the jump if overflow instruction, JO, immediately after the arithmetic instruction. If
the overflow flag is Set, execution will jump to the address specified in the JO instruction.
At this address an error routine may be put which respond to the overflow.
The second way is to put the INTO instruction immediately after the arithmetic
instruction in the program. The mnemonic for the instruction is INTO. It is a 1 byte
instruction. The op-code for this is CEH.
It is a conditional interrupt instruction. Only if the overflow flag is Set, a branch
takes place to an interrupt handler whose interrupt type number is 4. If the overflow flag is
reset, the execution continues with the next instruction.
The execution of INTO results in the following.
1. Flag register values are pushed on to the Stack.
2. CS value of the return address and IP value of the return address and IP value
of the return address are pushed on to the stack.
3. IP is loaded from the contents of word location 4x4 = 00010H.
4. CS is loaded from the contents of next word location.
5. Interrupt flag and Trap flag are reset to 0.
Thus a branch to ISS takes place. During the ISS, interrupts are disabled. At the
end of ISS, there will be an IRET instruction, returning back to the interrupted program.
Instructions in the ISS procedure perform the desired response to the error condition.
Priority of Interrupts
The internal interrupts which result is an error, like Divide by Zero error, as well as
software interrupt instructions have the highest priority. Next priority is NMI. The next
lower priority is assigned to INTR. The lowest priority is assigned to single Step interrupt.
In reality, NMI is always serviced on top most priority.

36
*****

37
 Chapter 7
I/O CONCEPT ( I/O MAPPED AND MEMORY MAPPED)
The I/O Sub System
The I/O Sub System is responsible for the movement of data between the basic
microcomputer system and the peripheral or external devices connected to it. It performs
the same functions as a seaport or airport for a city. Data bits are moved in and out of the
I/O Sub System in the same way as people and goods are moved in and out of the seaport
or airport. The I/O sub system exchanges data with peripheral devices through interface
circuitry known as ports. The peripheral device is physically connected to the port. The
port is physically connected to the control circuitry as shown in fig 13.

The port will then became a path way for data as it is transferred between the
microprocessor and its peripherals.
There are two types of I/O ports; parallel and serial. Parallel port is the easiest to
implement as the microprocessor works with data in 8- or 16- bit groups. All bits
comprising the data word are input and output together in parallel.
A serial I/O port is quite different. The data bits are lined up and transmitted in
single file fashion one bit at a time. This technique will be slower than parallel port design.
Regardless of the I/O port design- parallel or serial- the microprocessor must be
synchronized to the speed of the peripheral. Some peripherals like printers and plotters,

38
cannot accept data as the microprocessor would like to output it. On the other hand
floppy- disk drives and Winchester disks may require data faster than the processor can
supply it.
The major types of I/O operations are;
∗ Parallel I/O.
∗ Serial I/O.
∗ Programmed I/O.
∗ Interrupt-Driven I/O.
∗ Direct Memory Access.
Parallel I/O
The hardware requirements for a Parallel I/O port are similar to those of a RAM or
ROM interface. When the CPU performs an output instruction (I/O write cycle) the data
on the bus must be stored by the port. When an input instruction ( I/O read cycle) is
executed, the I/O port must gate its data on to the data bus lines. Just as each memory
location has its own (memory) address, each I/O port has its own ( port) address.
The 8086 has two I/O instructions IN AL ( or AX),port and OUT port, AL (or
AX). There are two forms each of the instruction. In the direct form, IN AL (or AX) port
or OUT port, AL ( or AX), the I/O port address is supplied within the instruction and
restricts the access to ports with adds between 0 and 255. The indirect Form, IN AL ( or
AX), DX and OUT DX, AL ( or AX) uses register DX to hold the port address. This
allows access to the full range of I/O ports from 0 to 65,535.
The advantage of the indirect form is that an I/O procedure can be setup and
shared between several peripherals by passing the port address ( in register DX) to the
procedure.
The address bus carries the port address on A0-A7 for direct I/O cycles, and A0 -
A15 for indirect I/O cycles. The D0-D7 data bus lines are used to transfer data form even-
addressed ports, and D8-D15 are used for odd-addressed ports. The BHE and A0 are used
to identify the type of transfer.
In the minimum mode, the condition M/I/O =0 is used to identify the current bus
cycle as an I/O operation. RD and WR then indicate the direction of data flow.
In the maximum mode the 8288 bus controller provides separate I/O read and write
commands.
Table 2 indicates the two forms of each instruction.

39
 Table 2 8086 I/O INSTRUCTIONS
Control busa
Type Instruction Address bus Data bus Min.mode Max.mode
Direct IN AL (or AX),port A0-A7=port addressb D0-D7=even byte M / IO =0 IORC=0
A8-A19=0 D8-D15=odd byte
D0-D15=even word RD=0

OUT port,AL(or AX) A0-A7=port addressb D0-D7=even byte M/IO=0 IOWC=0

A8-A19=0 D8-D15=odd byte AIOWC=0
D0-D15=even word WR=0
Indirect IN AL (or AX),DX A0-A15=port addressc as above as above as above
A16-A19=0
OUT DX,AL(or AX) A0-A15=port addressc as above as above as above
A16-A19=0
a
BHE and A0 are encoded as follows:
BHE A0
0 0 Word access
0 1 Even byte access
1 0 Odd byte access
1 1 No action
b
The port address is supplied within the instruction.
c
The port address is supplied in register DX.

Memory- Mapped I/O

The address space of the 8086 is divided into 1,048,576 bytes of memory space
and 65,536 bytes of I/O space. These two registers do not overlap because memory
addresses are selected with the memory commands (MEMR, MRDC, MEMW, MWTC),
while the I/O addresses are selected with the I/O commands (IOR, IORC, IOW, IOWC).
But consider designing a one byte read/write memory. we would use latches to
store the data during a memory write cycle, and tri-state gates to drive the bus during a
memory read cycle- exactly the same hardware that we would use for an output or input
port.
This is the essence of memory-mapped I/O. In hardware it appears to be a
conventional I/O port. But because it is mapped to a memory address, it is accessible in
software using any of the memory read or write instructions. For example, the instruction
MOV BH, MEMBDS becomes an input instruction ( input the data at "port" MEMBDS
to register BH). Indirect I/O is also possible. The instruction sequence.
LEA SI, MEMWDS : Point SI at the port
MOV (S.I), CX : output CX to port
allows CX to be output to the 16-bit port at address DS:MEMWDS.

40
 The advantage of memory- mapped I/O is the large number of instructions and
addressing modes available for refreshing memory. This is compared to the single input
and output commands available with an I/O mapped port.
Serial I/O
The two basic methods used for serial data transmission and reception are
Asynchronous and Synchronous serial communication.
Asynchronous serial communication
One of the most common applications for a serial I/O port is to interface the
keyboard on a Video display terminal(VDT). In this circuit each key stroke generates a 7-
bit ASCII code which is converted to a bit-by-bit serial and then transmitted to a
computer over a two-or three- conductor cable. Because, even the fastest typist cannot
exceed data rates of 60 to 100 words per minute, it is a good match for the slow
transmission rate of the serial port. At some times the serial port will be required to
transfer data at 10 to 20 characters/S, but at other times the data rate may be only 1 to 2
characters/S. Most of the time the key board is not in use and the data rate is zero.
Because of this erratic data rate, an asynchronous communications protocol must be
established.
The accepted technique for asynchronous serial communication is to hold the
serial output line to a logic 1 level until data is to be transmitted. Each character is
required to begin with a logic 0 for one bit time. The first bit is called the start bit and is
used to synchronize the transmitter and receiver. The data is sent least significant bit first
and framed between a start bit (always a 0) and one or two stop bits ( always a 1). The
start and stop bits carry no information but are required because of the asynchronous
nature of the data. Fig. 14 illustrates how the data byte 7BH would look when transmitted
in the asynchronous serial format.

41
Writing a program compatible with all the different asynchronous communication
protocols can be a difficult task. It is also an inefficient use of the microprocessor, as much
of its time will be spent in timing loops waiting to transmit or receive another character.
Because of this, the semiconductor companies have developed the universal,
Asynchronous Receiver/Transmitter (UART)
It is interesting to note that to the microprocessor a serial port (the UART)
appears as a conventional parallel port. When the transmitter buffer is empty, all the bits in
the word to be transmitted are output to the port at once ( in parallel) similarly, all bits of
the received word are input at once when the received data is ready.
The job of converting the data from serial to parallel, or parallel to serial, has been
transferred to the UART.
Synchronous Serial communication
The start and stop bits of asynchronous serial data represent wasted overhead
bytes that reduce the overall character rate. Even adding a parity bit can reduce the
transfer rate by 10%. But giving up the start and stop bits will require some means of
synchronizing the data. The two common synchronous serial protocols that are used for
Synchronizing the data are the Bisync Protocol and Serial Data Link Control (SDLC).

Bisync Protocol
Because there is no start bit, a special Sync, character is required to all
synchronous serial formats. This character tells the receives that data is about to follow.
The USART ( Universal Synchronous/Asynchronous Receiver/Transmitter), accordingly,
must have a special " hunt" or "search" mode so that the Sync. Character can be found.

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 In Bisync protocol several special characters are used to control the data transfer.
Fig 15 illustrates one frame of a Synchronous message.
In fig. 15 two sync. Characters are output followed by STX- start of text, ETX
signifies end of text BCC is a block check character used for error detector. Pad is the
character output when no data is being transmitted and corresponds to the "mark" output
in asynchronous serial.

Serial Data Link Control (SDLC)

This format was developed by IBM for use with their Systems Network
Architecture (SNA) communications package. Fig. 16 illustrates one frame of data using
this protocol. It is similar to bisync but it is not byte oriented.

The SDLC receiver searches for the beginning flag (01111110) as its sync
character. An 8-bit address field follows, allowing each frame to be addressed to a
particular station among a network of stations. Control characters are identified by a
sequence of six or more logic 1's. The information field may be of any format. The
transmitter will automatically insert 0's in this field if five or more log 1's should appear in
sequence. This will avoid inadvertent control characters appearing in the information
field. The receiver automatically deletes these 0's. The 16-bit frame check is used for error
detection. The frame ends with the ending flag.
Programmed I/O

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 Program instructions are controlling the transfer of data during the IN and OUT
operations. The software therefore initiates, as well as, controls the process of data
transfer. The hardware’s responsibilities are confined to merely performing the necessary
operations. The appropriate device is first checked in the device interface to determine
whether it is ready. Device readiness must be tested because the CPU is much faster than
peripheral devices. The test is followed by a conditional skip instruction. If the ready flag
is '1' (device ready), the program proceeds to the next step. If the Ready Flag is '0', the
program loops back to the test instruction. The CPU, therefore, waits for a slow device by
continually testing the readiness of the device, until it reports ready. When the I/O device
is ready, the data transfer operation takes place. Immediately after the transfer of one
character, the CPU reset the ready Flag to 0. The device then sets the Flag back to 1,
when it is again ready to receive the data.
Programmed data transfer has the advantage that it allows simple hardware
interfaces, because most of the management of the I/O operations is performed by
software. The disadvantage of this technique is that valuable CPU time is wasted while
the CPU waits for the peripheral device to get ready.
Interrupt Driven I/O
When interfacing a peripheral to a microprocessor, the microprocessor is not
knowing when the peripheral is ready. That is, the peripheral operates asynchronously with
respect to the microprocessor. One solution is to programme the CPU to repeatedly check
the peripheral's READY flag. However, this has a built-in disadvantage in that all the
resources of the processor are devoted to waiting for this flag. No other task can be
performed. If the peripheral is READY once in every 10,000 µsec, the CPU will spend
most of its time idling. A more logical approach would be to have the peripheral "tell the
CPU" when it is ready. This is the purpose of the microprocessor's interrupt input. An
interrupt is used to cause a temporary halt in the execution of a program. The
microprocessor responds to the interrupt with an Interrupt Service Sub-routine (ISS)
which is a short programme or a subroutine that instructs the microprocessor on how to
handle the interrupt.
Fig. 17 diagrams the CPU's response to an interrupt. During time 1 the processor
is assumed to be executing its main task. At time 2 the peripheral's READY flag causes an
interrupt to occur. After finishing the current instruction at time 3, the CS, IP and flag

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registers are pushed on to the stack at time 4. Control then transfers to the ISS at time 5.
During time 6, the ISS is executed, terminating with the instruction IRET (interrupt
return). The CS, IP and flag registers are recovered from the stack during time 7 and the
original task is resumed at time 8.

If we assume that 100µs is required to respond to the interrupt and supply the
peripheral with data, then in the case of a 10,000 µs per character printer, 9900 µs will be
available to the processor for its main task.
The 8086 has two interrupt pins labeled INTER and NM1. NM1 is a nonmaskable
interrupt, which means that it requires an immediate response from the processor and it
cannot be blocked. INTR is maskable via the IF flag. Only when this flag is set will
interrupts on this input be accepted. Interrupts can be generated by both hardware and
software. Interrupts are also prioritized to allow for the case when more than one interfere
Because the NMI input is nonmaskable, care must be taken when using this
interrupt. This is because there may be some programs which we do not want to interrupt-
reading or writing data to a disk drive, for example. For this reason, NMI input is
normally reserved for catastrophic events like memory error or impending power failure.
Direct Memory Access
DMA is a type of I/O technique in which data can be transferred between the
micro computer memory and an external device without utilising the microprocessor. The
DMA is typically used to transfer blocks of data between the memory Subsystem and an
external device . A DMA write operation transfers data from an external device to
memory.

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 Since the main purpose of DMA operation is to transfer data between external
devices and memory without involving the MPU, another device is required. This device is
called a DMA controller. The DMA controller must be capable of performing read and
write operations in the same manner as the MPU. Therefore, the DMA controller is
actually a special- purpose microprocessor whose only task is to perform high-speed data
transfer between memory and an external device. The major difference between an I/O
program controlled transfer and DMA is that data transfer does not employ the registers
of the CPU.
The primary advantage of the DMA data transfer technique is that it provides an
efficient transfer of large amount of data between storage devices and the main memory
without involving the CPU.
Several DMA transfer combinations are possible.
1. Memory to peripheral.
2. Peripheral to memory.
3. Memory to memory.
4. Peripheral to peripheral
DMA request takes precedence over all other bus activities, including interrupts. In
fact, no interrupt- maskable or non-maskable- will be recognised during a DMA operation.
***********

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