Design of Basic Computer

By: Ahmad Abdulghany

Faculty of Engineering Ain Shams University Egypt, Cairo

Design of Memory Control Logic :

READ Terminal : R' T1 : IR M [AR] D7' T1: AR M [AR] Do T4: DR M [AR] D1 T4 : DR M [AR] D2 T4 : DR M [AR] D6 T4 : DR M [AR] WRITE Terminal : R T1 : M [AR] TR D3 T4 : M [AR] AC D5 T4 : M [AR] PC D6 T6 : M [AR] DR BUS Control (7) :

R' T1 D7' T1 Do T4 D1 T4 D2 T4 D6 T4 R T1 D3 T4 D5 T4 D6 T6

Form BUS 16

Memory Unit 4096 x 16

READ ADDRESS WRITE

16

To BUS

12

AR

We'll use the instructions of READ , when use BUS ,as memory is source in this case.

Design of Accumulator (AC) Logic : LOAD Terminal : R' T0 : AR PC R' T2 : AR IR (0-11) D7' I T4 : AR M [AR] INCREMENT Terminal : R T1 : AR AR + 1 CLEAR Terminal : R T0 : AR 0 BUS Control (1) : D5 T5 : PC AR
* BUS control gates will be drown together each other when designing the BUS .

12 Form BUS

AR
LD INR CLR

12

R' T0 R' T2
D7' I T4

To BUS and Memory address

R T1 R T0

(1)

Design of Program Counter (PC) Logic :

Form BUS 12

PC
LD INR CLR

12

To BUS

r = D7 I' T3 p = D7 I T3 LOAD Terminal : D4 T4 : PC AR D5 T5 : PC AR INCREMENT Terminal : R' T1 : PC PC + 1 R T2 : PC PC + 1 r B4 : if (AC(15)=0) then (PC PC+ 1) r B3 : if (AC(15)=1) then (PC PC +1) r B2 : if (AC=0) then (PC PC + 1) AC 0 r B1 : if (E=0) then (PC PC + 1) p B9 : if (FGI=1) then (PC PC + 1) DR 0 p B8 : if (FGO=1) then (PC PC + 1) CLEAR Terminal : R T1 : PC 0 BUS Control (2) : R' T0 : AR PC R T0 : TR PC
* BUS control gates will be drown together each other when designing the BUS . ** The 16-bit Comparator can be set of XNOR gates contains one XNOR for each bit , i.e. it will contain 16-XNOR gates .( Or simply one NOR gate with 16 inputs in case of comparing with zerp ) *** Each XNOR gate acts as a bitwise comparator , since : A(XNOR)B = 1 if and only if A = B otherwise , it is = 0 .

16 16 16 16

D4 T4 D5 T5 R' T1 R T2 AC (15) 0 r B4 AC (15) r 1 B3 16 bit Comparator r B2

16 bit Comparator
E 0 FGI 1 FGO 1 T6
D6

D7 I' T3

r
B1

p B9
R T1

D7 I T3

p B8

Design of Instruction Register (IR) Logic :

LOAD Terminal : R' T1 : IR M [AR] BUS Control (5) :

R' T3 : D0,D1,,D7 Decode IR(12-14) AR IR(0-11) , I IR(15)

* BUS control gates will be drown together each other when designing the BUS .

Design of Temporary Register (TR) Logic :

Form BUS

16 LD

IR

16

To BUS

LOAD Terminal : R T0 : TR PC BUS Control (6) :

R T1 : M [AR] TR
* BUS control gates will be drown together each other when designing the BUS .

R' T1
Form BUS 16

TR
LD

16

To BUS

Design of Output Register (OUTR) Logic :

LOAD Terminal : p B10 : OUTR AC ( 0 7 )

R T0
Form AC

8 LD

OUTR

To o/p Device

From i/p device

INPR

To ALU

p B10

(2)

Design of Data Register (DR) Logic :

From BUS

16

DR
LD INR CLR

16

LOAD Terminal : D0 T4 : DR M [AR] D1 T4 : DR M [AR] D2 T4 : DR M [AR] D6 T4 : DR M [AR] INCREMENT Terminal : D6 T4 : DR DR + 1 BUS Control (3) : D6 T5 : M [AR] DR
* BUS control gates will be drown together each other when designing the BUS . ** Note that : to put the contents of DR in AC we don't use the bus , but we use the shift instruction to do so . then we didn't use the following instruction as BUS one :

To BUS And To ALU

D0 T4 D1 T4 D2 T4 D6 T4 D6 T4
From ALU

16
LD

AC
INR CLR

16

To BUS

D2 T5 : AC DR Design of Accumulator (AC) logic and one stage of ALU ( i : 0,1,2, ,15 ) : LOAD Terminal :
D0 T5 : AC AC DR D1 T5 : AC AC + DR D2 T5 : AC DR p B11 : AC (0-7) INPR r B9 : AC AC r B7 : AC shr AC , AC(15) E r B6 : AC shl AC , AC(0) E
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And ALU

D0 T5 D1 T5 D2 T5 p B11 r B9 r B7 r B6 r B11 p B11

AND ADD DR INPR COM SHR SHL INC CLR LD

AND Add Transfer DR Transfer INPR Complement Shift right Shift left Increment

INCREMENT Terminal : CLEAR Terminal : BUS Control (4) :

p B11 : OUTR (0-11) AC r B11 : AC 0 r B5 : AC AC + 1

Clear

* BUS control gates will be drown together each other when designing the BUS . ** INPR has only 8 bits . *** AND , ADD , DR , are connected between both figures shown .

Ci
AC(i)

AND
DR (i)

One stage of ALU

FA
DR (i)

ADD

One stage of AC
DR
LD

Ci+1 DR (i) INPR

From INPR bit (i)

J K

AC(i)

COM SHR SHL

DR' (i) AC (i+1) AC (i-1)

(3)

Design of Flip-Flops Design of ( I ) R' T2 : I IR (15) Design of ( S ) r B0 : S 0

D1 T3 r B7 r B6
B B

R' T2 IR (15)

Q Q

J
C
OUT

r
B

'

AC (0) AC (15)

B0
J

Design of ( E ) D1 T3 : E COUT r B10 : E 0

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r B8 r B10

T0' T1' T2' FGI FGO

Q Q

r B8

:EE

T2

r B7 : E AC (0) r B6 : E AC (15) Design of ( R )

T0'T1'T2'(IEN)(FGI+FGO) : R 1

p B7
B

IEN

B6 R T2
B

R T2 : R 0 Design of ( IEN ) p B7 : IEN 1 p B6 : IEN 0 R T2 : IEN 0 Design of ( FGI ) p B11 : FGI 0 Design of ( FGO ) p B10 : FGO 0
p B11
B

FGI

FGO

p B10
B

(4)

Design of the BUS : Encoder for BUS Selection lines x1 0 1 0 0 0 0 0 0 x2 0 1 0 0 0 0 0 0 x3 0 0 0 1 0 0 0 0

x1 x2 x3 x4 x5 x6 x7

Inputs x4 x5 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0

x6 0 0 0 0 0 0 1 0

x7 0 0 0 0 0 0 0 1

S2 0 0 0 0 1 1 1 1

Outputs S1 S0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1

Register selected for BUS

None AR PC DR AC IR TR Memory

8x3 Encoder

S0 MUX BUS S1 Selection Inputs S2

x1 = D4 T4 + D5 T5 x2 = R T0 + R' T0 + D5 T4 = (R + R') T0 D5 + T4 = To + D5 T4 x3 = D6 T6 x4 = p B11 x5 = R' T3 x6 = R T1 x7 = R' T1 +D7' T1+Do T4 +D1 T4 + D2 T4 + D6 T6 = R' T1 +D7' I T1+ ( D0+D1+D2+D6 ) T4
D4 T4 D5 T5 To D5 T4 D6 T6 p B11 R' T3 R T1 R' T1
D7' I T1

x1

x2 x3 x4 x5 x6 x7 8x3 Encoder S0 MUX BUS S1 Selection Inputs S2

D0 D1 D2 D6 T4

(5)

Design of the Sequence Counter ( SC ) R T0 : SC 0 D0 T5 : SC 0 D1 T5 : SC 0 D2 T5 : SC 0 D3 T4 : SC 0 D4 T4 : SC 0 D5 T5 : SC 0 D6 T6 : SC 0 r : SC 0 p : SC 0

Then , one can write that :

CLR (SC) = R T0 + D6 T6 + ( D0 + D1 + D2 + D5 ) T5 + ( D3 + D4 ) T4 + r + p

T0 , T1 , T2 , ,,, Through T15

4 X 16

Decoder

4- bit
Sequence Counter (S.C.)

.....
CLR INR Clock

0 1 2 3

15

R
T0 D6 T6 D0 D1 D2 D5 T5 D3 D4 T4

(6)