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CH.

1 MICROPROCESSOR ARCHITECTURE & SYSTEM

BASIC COMPUTER SYSTEM.


A BASIC COMPUTER SYSTEM IS SHOWN AS UNDER,

DATA BUS
INPUT DEVICE
CONTROL BUS CONTROL BUS

OUTPUT DEVICE

I/O PORTS

CPU

MEMORY

ADDRESS BUS

[FIG1.1 A BASIC COMPUTER SYSTEM] I/O DEVICE :THEY CONNECT THE SYSTEM WITH REAL WORLD. INPUTS ARE AS KEY BOARD, MOUSE ETC. OUTPUTS ARE AS LCD, PRINTER ETC.

CPU :HERE IT WORKS AS AN MPU. IT HAS MICROPROCESSOR CONTAINING REGISTERS, ALU & TIMING & CONTROL UNIT.

MEMORY :IT CONSISTS OF MIXTURE OF RAM & ROM. BUS :IT IS A GROUP OF CONNECTING WIRES. IT CARRIES DATA, ADDRESS &/OR SIGNALS.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM

BASIC STRUCTURE OF MICROPROCESSOR.


IN GENERAL EACH & EVERY MICROPROCESSOR CONTAINS BASIC BLOCKS ARE SHOWN IN FIGURE AS UNDER

REGISTERS DATA BUS ARITHMATIC & LOGICAL UNIT CONTROL & TIMING UNIT CONTROL BUS
[FIG. 1.2 BASIC STRUCTURE OF MICROPROCESSOR]

ADDRESS BUS

REGISTERS :USED TO STORE THE DATA. SIZE DEPENDS ON THE WIDTH OF DATA BUS. GIVEN UNIQUE NAME THAT CAN BE INSTRUCTION.

REFFERED

IN

ALU :IT IS RESPONSIBLE FOR ALL ARITHMATIC & LOGICAL OPERATIONS. ARITHMATIC LIKE ADDITION SUBTRACTION ETC. LOGICAL MEANS AND, OR, NOT, NOR, SHIFT ETC.

CONTROL & TIMING UNIT :PROVIDES NECESSARY TIMING & CONTROL SIGNALS TO PERFORM VARIOUS INTERANAL & EXTERNAL OPERATIONS. CONTROLS ALL THE ACTIVITIES OF MICROPROCESSOR.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


DATA BUS :-

BIDIRECTIONAL. RESPONSIBLE FOR DATA XFER BETWEEN PROCESSOR & MEMORY OR PERIPHERAL DEVICES.

ADDRESS BUS :UNIDIRACTIONAL. CARRY AN ADRRESS OF MEMORY LOCATION OR THE PORT NO. OF I/O DEVICES.

CONTROL BUS :CONSISTS OF VARIOUS SIGNAL LINES. LINE CARRIES SYNCHRONIZATION SIGNALS FOR APPROPRIATE TIMING. LINE CARRIES CONTROL SIGNALS TO HANDLE ALL THE OPERATIONS PERFACTLY.

MEMORY ORGANIZATION.
IT PROVIDES NECESSARY STOREGE FOR PROGRAM & DATA. IT CAN BE DIVIDED INTO TWO CATEGORIES :-

MEMORY

PRIMARY
PRIMARY MEMORY :-

SECONDARY

RAM & ROM FORM THE PRIMARY MEMORY.

SECONDARY MEMORY :HARD DISK, FLOPPY DISK FORM THE SECONDARY MEMORY.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


PRIMARY MEMORY :RAM :Random Access Memory. IT CAN BE READ &/OR WRITE BOTH.

ROM :Read Only Memory. IT CAN BE ONLY READ.

RAM
RANDOM ACCESS MEMORY CAN BE READ &/OR WRITE.

ROM
READ ONLY MEMORY CAN BE ONLY READ.

VOLATILE :- IF POWER IS NON VALATILE :- CONTENT OF SWITCHED OFF THE CONTENT ROM CAN BE RETAINED IF OF RAM IS LOST. POWER IS SWITCHED OFF. CAN BE USED AS A TEMPORARY USED AS STORAGE. STORAGE. A PERMANENT

NO. OF HOUSE PER STREET = M=8

0/A
NO. OF STREET IN A SOCIETY N =7

0 1 2 3 4 5 6 7

1/B 2/C 3/D 4/E 5/F 6/G 0 1 2 3 4 5 6 7

N-1

M -1

[FIG. 1.3 ORGANIZATION OF MEMORY]

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM

A TYPICAL ORGANIZATION OF MEMORY MAY BE VIEWED AS A HOUSING SOCIETY HAVING 7 STREETS (N-1=6, 0TO 6) & 8 HOUSES (M-1=7, 0 TO 7) IN EACH STREET. EACH HOUSE HAS A PARTICULAR ADDRESS.THERE ARE SO MANY WAYS TO BUILT UP THE ADDRESS. FOR EXAMPLE :

STREET NO 1 1 1 = 10 3 = 30 A F

HOUSE NO. 1 2 1 = 10 7 = 70 001 007

FINAL ADDRESS OF HOUSE 11 12 1010 3070 A001 F007

HOUSE NO. 1 IN 1ST STREET CAN BE ADDRESSED IN TWO DIGITS AS 11 BUT THE SAME HOUSE CAN BE ADDRESSED IN 4 DIGITS AS 1010; SAME AS 3RD STREET CAN BE SHOWN AS 30 & HOUSE NO. 7 CAN BE AS 70 SO FINAL ADDRESS IS 3070. THE ADDRESS PATERN DEPENDS ON THE BUILDER WHETHER HE WANTS TO KEEP 2 DIGIT OR 4 DIGIT IN A SINGLE ADDRESS. 11 & 1010 SHOWS THE SAME HOUSE ONLY DIFFERENCE IS OF NO. OF DIGIT.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM

ADDRESS ADDRESS RANGE.


RANGE MEANS UPPER BOUNDARY & LOWER BOUNDARY. LARGEST NUMBER MAKES THE UPPER BOUNDARY. SMALLEST NUMBER MAKES THE LOWER BOUNDARY. LARGEST & SMALLEST NO. DEPEND ON THE NUMBER SYSTEM.

SR NUMBER SYSTEM 1 2 3 4 BINARY OCTAL DECIMAL HEXADECIMAL

BASE 2 8 10 16

SMALLEST NO. LARGEST NO. 0 0 0 0 1 7 9 F(15)

FOR A SINGLE DIGIT, RANGE IN DEC. NUM. SYS. = 0 TO 9. FOR TWO DIGITS, RANGE IN DEC. NUM. SYS. = 00 TO 99. FOR TWO DIGITS, RANGE IN OCT. NUM. SYS. = 00 TO 77. FOR 4 DIGITS, RANGE IN BIN. NUM. SYS. = 0000 TO 1111. (0 TO F) FOR 16 DIGITS, RANGE IN BIN. NUM. SYS.

8
SMALLEST LARGEST

4 2 1 8

4 2 1 8 4 2 1

8 4 2 1

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000 HEX 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFF HEX

MICROPROCESSOR CONTAIN 16 BITS ADDRESS LINE. MEANS THESE 16 DIGITS MAKES THE ADDRESS. FOR A BINARY NUM. SYSTEM IF WE WANT TO FIND THE ADDRESS RANGE THEN PUT SMALLEST NO. OF BIN. NUM. SYS. (0) FOR LOWER RANGE & LARGEST NO. (1) FOR UPPER RANGE AT 16 DIGITS. WHICH IS SHOWN ABOVE.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM

READ/WRITE MEMORY READ/WRITE OPERATION.


WE WILL UNDERSTAND THIS TOPIC BY TAKING AN EXAMPLE OF MONEY TRANSFER..
CHHAGAN IS A MAGANS FRIEND KNOW

1. MAGAN GIVES ADDRESS OF CHHAGAN TO CHANDU. 2. MAGAN CALLS CHHAGAN THAT CHANDU IS COMING FOR MONEY. 3. CHHAGAN CHECK THE POCKET & PLACE THE MONEY IN A COVER. 4. THAT COVER IS THAEN REACHED TO MAGAN.

MAGAN LIMBDI KNOW DONT KNOW

CHHAGAN RAJKOT

CHANDU DONT KNOW WHO IS CHHAGAN

MAGAN IS A CHNDUS FRIEND

CHANDU RAJKOT

[FIG. 1.4 SCHEMATIC OF MONEY XFER TO UNDERSTAND MEMORY READ]

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM

[FIG. 1.5 MEMORY READ OPERATION]

HOW MEMORY READ OPERATION IS DONE BY PROCESSOR CAN BE UNDERSTAND AS FOLLOWING.. HERE 55H DATA IS STORED IN MEMORY AT 2010H LOCATION. MEMORY READ MEANS PROCESSOR READ THE CONTENT OF THAT LOCATION.i.e. THAT DATA GOES INTO THE PROCESSOR. THE OPERATION IS DONE IN 4 STEPS AS FOLLOWING. 1.) FIRST OF ALL WE HAVE TO KNOW THE PLACE WHERE THE DATA IS STORED.. ADDRESS OF LOCATION. 2.) THEN PROCESSOR HAS TO TELL TO MEMORY THAT I WANT TO READ YOU.GENERATE CONTROL SIGNAL. 3.) NOW MEMORY DEVICE CHECK THE ADDRESS & READ THE DATA & PLACE ON THE BUS.. READ ADDRESS & PLACE DATA. 4.)FINALLY PROCESSOR READS THE DATA FROM DATA BUS. .. READ THE DATA.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


M A R N*m RAM DATA.BUS M B R DATA.BUS M B R M A R N*m RAM

ADD.BUS

ADD.BUS

[FIG. 1.6 MEMORY READ OPERATION] [FIG. 1.7 MEMORY WRITE OPERATION]

STEPS IN MEMORY READ OPERATION :P SENDS ADRESS OF MEMORY LOCATION INTO MAR (FROM WHERE DATA IS TO BE READ). AT THE SAME TIME, P SENDS READ SIGNAL TO ACTIVATE MEMORY. MEMORY READ THE CONTENT WHOSE ADDRESS IN MAR(MEMORY ADDRESS REGISTER) & PLACE THE DATA INTO MBR.(MEMORY BUFFER REGISTER). P READS THE CONTENT OF MBR.

STEPS IN MEMORY READ OPERATION :P SENDS ADRESS OF MEMORY LOCATION INTO MAR (AT WHER DATA IS TO BE WRITE). P SENDS DATA (WHICH IS TO BE WRITTEN) INTO MBR. AT THE SAME TIME, P SENDS WRITE SIGNAL TO ACTIVATE MEMORY. MEMORY STORES THE DATA FROM MBR AT THE ADDRESS STORED IN MAR.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM

10

MEMORY CHIPS.

CS WR RD A0 A1
ADDRESS LINES
. . .

CS A0 A1

RD

RAM

ADDRESS LINES

. . .

ROM

AN-1
D0
-

AN-1
D7 D0
-

D7

DATA LINES [FIG. 1.8 RAM & ROM CHIPS]

DATA LINES

RAM IS A READ\WRITE MEMORY SO IT CONTAINS RD & WR TERMINALS. ROM IS A ONLY READ MEMORY SO IT CONTAINS ONLY RD TERMINALS. ADDRESS & DATA LINES ARE CONNECTED WITH THE MICROPROCESSOR. ALL THE 8 DATA LINES ARE CONNECTED WITH THE PROCESSOR. BUT ALL 16 ADDRESS LINES MAY OR MAY NOT BE CONNECTED. NO. OF ADDRESS LINES DEPEND ON THE GIVEN MEMORY CAPACITY. FINDING ADDRESS RANGE IS CALLED MEMORY MAPPING. CS TERMINAL IS A CHIP SELECTION ACTIVATES THE CHIP.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM

11

MEMORY MAP & ADDRESS LINE.


MEMORY MAPPING IS A PROCESS TO FIND THE ADDRESS RANGE USED BY PROCESSOR TO ACCESS TOTAL AMOUNT OF MEMORY. ADDRESS LINES ARE USED TO ACTIVATE CHIP. THE CRITICAL QUESTIONS ARISE THAT 1.)HOW MANY ADDRESS LINES ARE NEEDED IN CHIP SELECTION & 2.) HOW MANY LINES ARE USED IN ACCESSING MEMORY FOR A GIVEN MEMORY AMOUNT. THIS CALCULATION CAN BE EXPLAINED AS FOLLOWING.. STEP :- 1 FIND THE ADDRESS LINES FOR ACCESSING MEMORY. EX. 4K RAM. 4K = 1K X 4 =2 =2
10 2

x2

14

MEANS 14 ADDRESS LINES (A0 TO A13) NEEDED FOR ACCESSING MEMORY. ADDRESS LINES = FOR CHIP SELECTION TOTAL ADDRESS LINE ADD. LINES TO ACCESS MEMORY

=16 14 =2 MEANS 2 ADDRESS LINES(A14 TO A15) ARE NEEDED FOR CHIP SELECTION. THIS IS AS SHOWN BELOW :

CHIP SELECTION

FOR MEMORY ACCESS

A15 A14 A13 A12 A11 A10 A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM

12

A15 A14 A13 A12 A11 A10 A9 A8 8085 A7 A6 A5 A4 A3 A2 A1 A0 D0 D7 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

CS WR RD

RAM

D0

D7

DATA LINES

[FIG. 1.9 CHIP SELECTION USING ADDRESS LINES]

WE CAN SEE THAT ADDRESS LINES A0 TO A13 FROM PROCESSOR ARE USED TO ACCESS RAM. REMAINING LINES A14 & A15 ARE USED FOR CHIP SELECTION.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


THERE ARE THREE TOPICS CONNECTED WITH THIS ONE. A. FINDING AMOUNT OF MEMORY FROM GIVEN ADDRESS LINES. B. FINDING ADDRESS LINE FROM GIVEN AMOUNT OF MEMORY. C. FINDING ADDRESS RANGE. STARTING & ENDING ADDRESS.

13

A.) FINDING AMOUNT OF MEMORY FROM GIVEN ADDRESS LINES.


ADDRESS LINES CAN BE FOUND FROM AMOUNT OF MEMORY USING RELATION GIVEN AS : 2 = AMOUNT OF MEMORY (IN KILO bytes) WHERE N= NO. OF ADDRESS LINES EX.1 A PROCESSOR HAS 10 ADDRESS LINES. FIND THE AMOUNT OF MEMORY CAN BE ACCESSED. W.K.T. 2 = AMOUNT OF MEMORY (Kb) 2
10 N N

= 1024 Kb = 1Kb

EX.2 HOW MUCH MEMORY CAN BE ACCESSED BY A PROCESSOR HAVING 8 DATA LINES & 14 ADDRESS LINES ? HERE DATA BUS IS GIVEN BUT IT IS NOT IMPORTANT TO FIND AMOUNT OF MEMORY. W.K.T. 2N = AMOUNT OF MEMORY (Kb) 2
14

= 2 X 2 = 1 Kb X 16 = 16 Kb

10

NOTE :- REMEMBER THAT THERE ISNT ANY ROLE OF DATA BUS IN CALCULATING OF AMOUNT OF MEMORY CAN BE ACCESSED BY PROCESSOR

NOTE :-IT IS OBVIOUS THAT 210 = 1K & IS ALSO TRUE VICE VERSA.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


B.) FINDING ADDRESS LINE FROM GIVEN AMOUNT OF MEMORY.

14

HERE THE SAME EQUATION CAN BE USED TO FIND OUT ADDRESS LINES USED TO ACCESS MEMORY. 2 = AMOUNT OF MEMORY. WHERE N = NO. OF ADDRESS LINES. EX.1 IF 4K RAM IS INTERFACED WITH PROCESSOR THEN FIND THE NO. OF ADDRESS LINES OF PROCESSOR 1.) USED TO ACCESS THE MEMORY 2.) USED FOR CHIP SELECTION. W.K.T. 2
N N N

= AMOUNT OF MEMORY. = 4K = 1K X 4 =2
10 14

X2

=2 SO, N = 14, HENCE 14 ADDRESS LINES ARE REQUIRED TO ACCESS MEMORY. NOW REMEINING ADDRESS LINES ARE USED FOR CHIP SELECTION. MEANS [ TOTAL ADD. LINES ADD. LINES TO ACCESS MEMORY ] TOTAL ADD. LINES, 16 14, ADD. LINES TO ACCESS MEMORY. HENCE 2 ADDRESS LINES ARE REQUIRED FOR CHIP SELECTION.

EX.2. HOW MUCH ADDRESS LINES ARE USED TO ACCESS 32K ROM ? W.K.T. 2
N

= AMOUNT OF MEMORY.

2 = 32K = 1K X 32 =2
N 10

X2

2 =2

15

HENCE N = 15 ADDRESS LINES ARE REQUIRED.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


C.) FINDING ADDRESS RANGE FOR A GIVEN MEMORY AMOUNT .
EX.1. FIND ADDRESS RANGE FOR 4K RAM. STEP 1:- FIND ADD. LINES 1.) DIRECT CONNECTED, 2.) CHIP SELECTION ? 4K = 1K X 4 =2 =2
10 2

15

X 2

12

HENCE 12 ADD. LINES ARE USED TO ACCESS THE MEMORY. (A0 TO A11). IT MEANS 4 ADD. LINES ARE USED FOR CHIP SELECTION. (A12 TO A15). STEP 2 :- DIVIDE TOTAL ADD. LINES FROM ABOVE CALCULATION.

CHIP SELECTION

DIRECT CONNECTED

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

STEP 3 :- TO FIND THE RANGE WE HAVE TO FIND STARTING & ENDING ADD. FOR STARTING ADD. GIVE VALUE 0 AT ALL ADD. LINES. FOR ENDING ADD. GIVE VALUE 1 AT ALL ADD. LINES. CHIP SELECTION LINES REMAIN AS IT IS FOR STARTING & ENDING ADD.. A12 TO A15 REMAINS AT 0

CHIP SELECTION

DIRECT CONNECTED

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 START END 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0000H 1 0FFFH

SO. ADD. RANGE FOR 4K IS FROM 0000H TO 0FFFH.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


EX.2. FIND ADDRESS RANGE FOR 32K RAM. STEP 1:- FIND ADD. LINES 1.) DIRECT CONNECTED, 2.) CHIP SELECTION ? 32K = 1K X 32 =2 =2
10 5

16

X 2

15

HENCE 15 ADD. LINES ARE USED TO ACCESS THE MEMORY. (A0 TO A14). IT MEANS 1 ADD. LINES ARE USED FOR CHIP SELECTION. (A15). STEP 2 :- DIVIDE TOTAL ADD. LINES FROM ABOVE CALCULATION.

CS

DIRECT CONNECTED

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

STEP 3 :- TO FIND THE RANGE WE HAVE TO FIND STARTING & ENDING ADD. FOR STARTING ADD. GIVE VALUE 0 AT ALL ADD. LINES. FOR ENDING ADD. GIVE VALUE 1 AT ALL ADD. LINES. CHIP SELECTION LINES REMAIN AS IT IS FOR STARTING & ENDING ADD. ONLY A15 REMAINS AT 0

CHIP SELECTION

DIRECT CONNECTED

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 START END 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0000H 1 7FFFH

HENCE ADD. RANGE IS FROM 0000H TO 7FFFH.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


EX.3. FIND ADDRESS RANGE FOR 1K ROM. STEP 1:- FIND ADD. LINES 1.) DIRECT CONNECTED, 2.) CHIP SELECTION ? 1K = 1K X 1 =2 =2
10 0

17

X 2

10

HENCE 10 ADD. LINES ARE USED TO ACCESS THE MEMORY. (A0 TO A9). IT MEANS 1 ADD. LINES ARE USED FOR CHIP SELECTION. (A11 TOA15). STEP 2 :- DIVIDE TOTAL ADD. LINES FROM ABOVE CALCULATION.

CS

DIRECT CONNECTED

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

STEP 3 :- TO FIND THE RANGE WE HAVE TO FIND STARTING & ENDING ADD. FOR STARTING ADD. GIVE VALUE 0 AT ALL ADD. LINES. FOR ENDING ADD. GIVE VALUE 1 AT ALL ADD. LINES. CHIP SELECTION LINES REMAIN AS IT IS FOR STARTING & ENDING ADD. SO A10 TO A15 REMAINS AT 0

CHIP SELECTION

DIRECT CONNECTED

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 START END 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0000H 1 7FFFH

HENCE ADD. RANGE IS FROM 0000H TO 03FFH.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM

18

FIRST OF ALL WE WILL UNDERSTAND THAT WHY VALUE OF CHIP SELECTION BITS REMAIN AS IT IS ? CONSIDER A CASE OF 4K RAM FROM PAGE NO. 15, EX NO. 1. 0 0 0 0
A15 A14 A13 A12 A11 A10 A9 A8 8085 A7 A6 A5 A4 A3 A2 A1 A0 D0 D7

0 1
CS WR RD

0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

0 F
1 1 1 1 1 1 1 1 1 1 1 1
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D0 D7 RAM

[FIG. 1.10 LOW LOGIC REACHES AT CS TERMINAL OF MEMORY]

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 START 0 END 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0000H 0FFFH

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM

19

HERE RAM HAS A TERMINAL NAMED CHIP SELECTION AT WHICH THE ADDRESS LINES ARE CONNECTED WHICH ARE NOT USED TO ACCESS MEMORY. CS IS AN ACTIVE LOW TERMINAL SO IT IS ACTIVITED ONLY IF LOW LOGIC MEANS 0 IS APPLIED AT THAT TERMINAL. THE MEMORY CHIP CAN BE ACTIVATED BY APPLYING 0 LOGIC AT ADD. LINES, USED FOR CHIP SELECTION. ADD. LINES FOR CS ARE GIVEN AS AN INPUT AT BUBBLED NAND GATE & OUTPUT OF GATE IS GIVEN TO CS TERMINAL. HOW LOE LOGIC REACHED AT CS TERMINAL OF MEMORY IS SHOWN AS UNDER :-

0 0 0 0

1 1 1 1

0
TO THE CS

[FIG. 1.11 HOW LOW LOGIC 0 REACHES AT CS TERMINAL]

NOW COMING TO THE MAIN POINT THAT HOW THE START/END ADDRESS CAN BE FOUND FROM THE ANY ONE OF TWO. IF THE START ADDRESS IS GIVEN THEN END CAN BE FOUND & IF END IS GIVEN THEN START CAN BE FOUND. THIS CAN BE EXPLAINED AS FOLLOWING :

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


EX.1. IF END ADDRESS IS 7FFFh THEN FIND START ADDRESS FOR 4K RAM. STEP 1. WRITE GIVEN HEX ADDRESS IN 16 BIT BINARY FORM. A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 START END 0 1 1 7 1 1 1 F 1 1 1 1 F 1 1 1 1 F 1 1

20

STEP 2. FIND ADDRESS LINES USED FOR CHIP SELECTION. MEMORY = 4K = 1K X 4 =2 =2


10 12 2

X2

MEANS 12 ADDRESS LINES NEEDED TO ACCESS MEMORY & REMAINING 4 ARE NEEDE FOR CHIP SELECTION. A0 TO A11 TO ACCESS MEMORY & A12 TO A15 FOR CHIP SELECTION.

STEP 3. FING THE REQUIRED ADDRESS. PUT THE SAME BITS FOR CHIP SELECTION. IF START ADD. REQUIRED THEN PUT

0 AT REMAINING LINES.

IF END ADD. REQUIRED THEN PUT 1 AT REMAINING LINES.

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 START 0 END 0 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1

7000H 7FFFH

SO STARTING ADDRESS IS 7000H.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


EX.2. IF START ADDRESS IS A000h THEN FIND END ADDRESS FOR 8K ROM. STEP 1. WRITE GIVEN HEX ADDRESS IN 16 BIT BINARY FORM. A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 START END A 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0

21

STEP 2. FIND ADDRESS LINES USED FOR CHIP SELECTION. MEMORY = 8K = 1K X 8 =2 =2


10 13 3

X2

MEANS 13 ADDRESS LINES NEEDED TO ACCESS MEMORY & REMAINING 3 ARE NEEDE FOR CHIP SELECTION. A0 TO A12 TO ACCESS MEMORY & A13 TO A15 FOR CHIP SELECTION.

STEP 3. FING THE REQUIRED ADDRESS. PUT THE SAME BITS FOR CHIP SELECTION. IF START ADD. REQUIRED THEN PUT

0 AT REMAINING LINES.

IF END ADD. REQUIRED THEN PUT 1 AT REMAINING LINES.

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 START 1 END 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

A000H BFFFH

SO ENDING ADDRESS IS BFFFH.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


EX.3. IF END ADDRESS IS F3FFh THEN FIND START ADDRESS FOR 1K RAM. STEP 1. WRITE GIVEN HEX ADDRESS IN 16 BIT BINARY FORM. A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 START END 1 1 1 F 1 0 0 3 1 1 1 1 F 1 1 1 1 F 1 1

22

STEP 2. FIND ADDRESS LINES USED FOR CHIP SELECTION. MEMORY = 1K = 1K X 1 =2 =2


10 10 0

X2

MEANS 10 ADDRESS LINES NEEDED TO ACCESS MEMORY & REMAINING 6 ARE NEEDE FOR CHIP SELECTION. A0 TO A9 TO ACCESS MEMORY & A10 TO A15 FOR CHIP SELECTION.

STEP 3. FING THE REQUIRED ADDRESS. PUT THE SAME BITS FOR CHIP SELECTION. IF START ADD. REQUIRED THEN PUT

0 AT REMAINING LINES.

IF END ADD. REQUIRED THEN PUT 1 AT REMAINING LINES.

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 START 1 END 1 1 1 1 1 1 1 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1

F300H F3FFH

SO STARTING ADDRESS IS F300H.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM

23

EX.4. IF START ADDRESS IS 4000h THEN FIND END ADDRESS FOR 16K ROM. STEP 1. WRITE GIVEN HEX ADDRESS IN 16 BIT BINARY FORM. A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 START END 4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0

STEP 2. FIND ADDRESS LINES USED FOR CHIP SELECTION. MEMORY = 16K = 1K X 16 =2 =2
10 14 4

X2

MEANS 14 ADDRESS LINES NEEDED TO ACCESS MEMORY & REMAINING 2 ARE NEEDE FOR CHIP SELECTION. A0 TO A13 TO ACCESS MEMORY & A14 TO A15 FOR CHIP SELECTION.

STEP 3. FING THE REQUIRED ADDRESS. PUT THE SAME BITS FOR CHIP SELECTION. IF START ADD. REQUIRED THEN PUT

0 AT REMAINING LINES.

IF END ADD. REQUIRED THEN PUT 1 AT REMAINING LINES.

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 START 0 END 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

4000H 7FFFH

SO ENDING ADDRESS IS 7FFFH.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM

24

BUS ORGANISATION .
BUS MEANS A BASIC CONNECTING LINE. PROCESSOR HAS TO COMMUNICATE WITH THE MEMORY & INPUT/OUTPUT DEVICES. THIS CAN BE DONE BY MEANS OF CONNECTING LINES BETWEEN PROCESSOR & MEMROY/I/O DEVICES. THESE LINES JUST TRANSFER THEBITS FROM PROCESSOR TO MEMORY/IO DEVICES & VICE VERSA. THE 8085 IS INTERFACED WITH OTHER DEVICES USING THREE BUSES CALLED DATA, ADDRESS,CONTROL BUS.

[FIG. 1.12 BUS ORGANISATION OF 8085]

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


DATA BUS :IT IS A BIDIRECTONAL BUS. IT IS 8 BIT WIDE. RELATED WITH THE DATA XFER. DATA XFER IS DONE BETWEEN PROCESSOR & MEMORY/PERIPHERAL DEVICES. ADDRESS BUS :IT IS A UNIDIRECTIONAL BUS. IT IS 16 BIT WIDE. IT CARRIES ADDRESS OF MEMORY LOCATION. IT CARRIES ADDRESS OF THE I/O DEVICE OR MEMORY LOCATION TO THE PROCESSOR. CONTROL BUS :IT CONSISTS OF VARIOUS SIGNALS. THEY ARE SYNCHRONIZATION SIGNALS. THESE SIGNALS SYNCHRONIZ ALL OF THE OPERATIONS OF THE PROCESSOR. FOR EACH & EVERY OPERATIOS PROCESSOR GENERATES THE CONTROL SIGNALS.

25

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM

26

PIN OUT DIAGRAM OF 8085.


IT IS A 40 PIN (Dual In line Package) IC.

Vcc & Vss.


Vcc IS CONNECTED TO THE +5V. Vss IS CONNECTED TO THE GROUND.

CLOCK PINS.
A CRYSTAL IS CONNECTED BETWEEN X1 & X2 PINS TO GENERATE INTERNAL CLOCK. CLKOUT IS USED TO PROVIDE THE SYSTEM CLOCK TO OTHER DEVICES IN THE SYSTEM.

RESET PINS.
WHEN RESETIN IS LOW PROCESSOR RESETS ITSELF. THROUGH RESETOUT PROCESSOR INFORMS TO OTHER IO DEVICES THAT PROCESSOR IS BEING RESET.

SERIAL COMMUNICATION PINS.


SID IS USED FOR SERIAL INPUT DATA. SOD IS USED FOR SERIAL OUT DATA.

INTERRUPT PINS.
TRAP IS NON-MASKABLE & HAVING HIGHEST PRIORITY INTERRUPT. RST 7.5, RST 6.5, RST 5.5 ARE RESET & MASKABLE INTERRUPTS. THEY CAN BE CONTROLLED BY EI, DI, RIM & SIM INSTRUCTIONS. INTR IS GENERAL PURPOSE & MASKABLE INTERRUPTS. IT CAN BE CONTROLLED BY EI & DI INSTRUCTIONS. INTA IS ACKNOWLEDGE PIN & IS USED BY PROCESSOR TO REPLAY THE INTERRUPT REQUEST.

ADDRESS PINS.
8085 HAS 16 ADDRESS PINS. A0 TO A15. LOWER PINS, A0 TO A7, ARE MULTIPLEXED WITH THE DATA PINS MAKING AD0 TO AD7. HIGHER PINS, A8 TOA15, ARE INDIVIDUALS.

DATA PINS.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM

27

8085 HAS 8 DATA PINS. THEY ARE MULTIPLEXED WITH THE LOWER ADDRESS PINS MAKING AD0 TO AD7.

X1 X2 RESET OUT SOD SID TRAP RST7.5 RST6.5 RST5.5 INTR INTA AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Vss

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

Vcc HOLD HLDA CLK (OUT) RESET IN READY IO/M S1 RD WR ALE S0 A15 A14 A13 A12 A11 A10 A9 A8

[FIG. 1.13 PIN OUT DIAGRAM OF 8085] DMA CONTROLLER PINS.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM

28

HOLD IS A REQUEST TO GRANT THE CONTROL OF BUSES OF PROCESSOR. HLDA IS ACKNOWLEDGEMENT USED BY PROCESSOR TO GRANTING REQUEST. STATUS SIGNALS. S0 & S1, THESE ARE USED TOGETHER WITH IO/M TO REPRESENT THE DIFFERENT MACHINE CYCLE. FOR EX. IO/M S0 S1 MACHINE CYCLE MEMORY WRITE 0 1 0 0 1 1 OPCODE FETCH 0 0 1 MEMORY READ CONTROL SIGNALS. RD & WR ARE USED TO PERFORM READ & WRITE OPERATIONS. THEY ARE USED TOGETHER WITH THE IO/M & GENERATE THE MEMR, MEMW, IOW, IOR SIGNALS. IO/M. INPUT-OUTPUT/MEMORY. IT DIFFERENTIATE BETWEEN INPUT-OUTPUT & MEMORY OPERATONS. WHEN HIGH, PROCESSOR PERFORMS I/O OPERATONS. WHEN LOW, PROCRSSOR PERFORMS MEMORY OPERATIONS. READY. WHEN A PERIPHERAL DEVICE, INTERFACED WITH PROCESSOR, IS SLOWER IN SPEED THAN THE PROCESSOR AT THAT TIME THE READY SIGNAL PLAYS THE ROLE. WHEN IT IS HIGH, THE DEVICE IS READY TO PERFORM THE OPERATIONS. ALE. ADDRESS LATCH ENABLE. WHEN IT IS HIGH, THE LOWER ADDRESS IS PRESENT ON THE ADDRESS BUS. ALE GOES HIGH IN START OF EVERY MACHINE CYCLE.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM

29

ARCHITECTURE OF 8085.

[FIG. 1.14 ARCHITECTURE OF 8085]

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


INTERRUPT SECTION.
THERE ARE 5 INTERRUPTS IN 8085. INTERRUPT PRIORITY ADDRESS TRAP 1 0024H RST 7.5 2 003CH RST 6.5 3 0034H RST 5.5 4 002CH INTR 5 ------TRAP IS NON-MASKABLE WHILE OTHER ARE MASKABLE. WHEN INTERRUPT COMES ON ONE OF THE PIN, 8085 SUSPENDS CURRENT ACTIVITY, SAVES THE STATUS.

30

SERIAL CONTROL SECTION.


THIS SECTION OF 8085 PROVIDES SERIAL INTERFACE . THIS CAN BE ACHIEVED BY SID & SOD PINS. DATA ENTERS 8085 THROUGH Serial Input Data PIN. DATA COMES OUT FROM 8085 THROUGH Serial Output Data.

Acc.
IT IS AN 8 BIT REGISTER. IT IS USED IN ALL ARITHMATIC & LOGICAL OPERATIONS. IT STORES THE RESULT AFTER OPERATIONS. IT IS USED TO DEAL WITH MEMORY DIRECTLY.

ALU.
ARITHMATIC & LOGICAL UNIT. IT CONTAINS LOGIC CIRCUITS WHICH IS RESPONSIBLE FOR ALL TYPE OF ARITHMATIC & LOGICAL OPERATION. ALU RECEIVES DATA FROM Acc OR REGISTERS. THEN ALU PROCESSES ON THE DATA & STORES RESULT IN Acc. AT THAT TIME IT ALSO ACCESSES THE FLAG REGISTER.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


FLAG REGISTER.
IT IS AN 8-BIT REGISTER CONTAINING 5 1-BIT FLAGS. IT SHOWS THE CONDITIONS OF THE RESULTS.

31

-----

AC

-----

-----

CY

SIGN :- IF RESULT IS NEGATIVE THEN IT IS SET OTHERWISE RESET. ZERO :- IF RESULT IS ZERO THAN IT IS SET OTHERWISE RESET. Auxiliary Carry :- IN RESULT IF CARRY IS XFERED FROM BIT D3 TO D4 THAN AC FLAG IS SET OTHERWISE RESET. PARITY :- IN RESULT IF NO. OF 1S IS EVEN THEN IT IS SET OTHERWISE RESET. CARRY :- IF A CARRY IS OUT FROM D7 BIT THEN IT IS SET OTHERWISW RESET.

INSTRUCTION REGISTER & DECODER.


DURING THE OPCODE FETCH CYCLE, THE 8-BIT OPCODE OF AN INSTRUCTION IS XFERED FROM MEMORY TO THIS REGISTER. INSTRUCTION DECODER DECODES THIS OPCODE TO FIND THE MEANING OF THE INSTRUCTION.

GENERAL PURPOSE REGISTERS.


THEY ARE USED TO STORE THE DATA. GENERALLY THEY ARE OF 8-BIT IN SIZE. B,C,D,E,H, & L FOR 16-BIT OPERATION THEY ARE USED TOGETHER MAKE A PAIR LIKE BC,DE & HL.

PROGRAM COUNTER.
IT IS A 16-BIT REGISTER. IT STORES THE ADDRESS OF THE NEXT INSTRUCTION TO BE FETCHED.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


STACK POINTER.
IT IS A 16-BIT REGISTER. IT STORES THE ADDRESS OF TOP OF STACK.

32

TIMING & CONTROL UNIT.


IT CONTROLS ALL OF THE OPERATIONS OF PROCESSOR. IT GENERATES TIMING & CONTROLLING SIGNALS TO SYNCHRONIZE OPERATIONS.

DEMULTIPLEXING OF MULTIPLEXED ADD/DATA BUS .


THE LOWER ADDRESS & DATA BUS IS MULTIPLEXED MAKING AD0 AD7. IT IS REQUIRED TO DEMULTIPLEX THE LOWER ADDRESS BUS AT EVERY MACHINE CYCLE. THIS CAN BE ACHIEVED BY ALE SIGNAL MAKING IT HIGH AT EVERY START OF MACHINE CYCLE. SO WHEN ALE IS LOW DATA IS PRESENT AT THOSE PINS. A LATCH IS ALSO USED IN THIS OPERATION. THIS CAN BE SHOWN AS FOLLOWING :

A15 A8

A15 A8

ALE 8085 LATCH AD0 AD7 A0 D7 D0 A7

[FIG. 1.15 DEMULTIPLEXING OF MULTIPLEXED ADD./DATA BUS]

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM

33

WORD. PROGRAM STATUS WORD.


PSW IS A FLAG REGISTER CONTAINING 5 FLIPFLOPS. THE STSTUS OF EACH FLIPFLOP DEPENDS ON THE RESULT OF ARITHMATIC & LOGICAL OPERATIONS ONLY. THE FLAGS ARE NOT AFFECTED BY DATA XFER OPERATIONS. FORMATE OF PSW IS AS SHOWN BELOW : D7 D6 D5 D4 D3 D2 D1 D0

------

AC

-----

-----

CY

[FIG. 1.16 FLAG REGISTER OF 8085]

1.) SIGN FLAG.


IT INDICATES THE SIGN OF RESULT. SIGN CAN BE DECIDED FROM THE FIRST BIT OF THE RESULT. IF 1ST BIT = 1 THEN RESULT IS NEGATIVE, S BIT IS SET TO 1. IF 1ST BIT = 0 THEN RESULT IS POSITIVE, S BIT IS SET TO 0. 1 1 0 1 1 0 1 0 1 1 0 1 0 0 0 1 0 1) 0 1 0 1 0 1 1 1 S BIT = 0

THE BIT NO. D7 IS 0, INDICATING IN BOX, SO RESULT IS POSITIVE & SIGN FLAG IS RESET.

2.) ZERO FLAG.


IF RESULT AFTER OPERATION IS ZERO THEN Z FLAG IS SET TO 1. 1 1 0 1) 0 1 0 1 0 1 1 0 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 1 1 0 0

Z BIT = 1

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


3.) AUXILIARY CARRY FLAG.
THIS FLAG IS SET WHEN CARRY IS XFERED FROM BIT D3 TO D4. 1 1 0 1 0 1 1 1 0 1 0 0 0 1 0 0 0 1) 0 0 1 1 0 1 1 0

34

AC FLAG = 1

4.) PARITY FLAG.


PARITY MEANS NUMBER OF 1S. IN RESULT IF NO. OF 1S IS EVEN THEN FLAG IS SET TO 1. IF NO. OF 1S IS ODD THEN FLAG IS SET TO 0.

1 1 1 1 1 1 1 0 1 0 1 0 1 1 1 0 1 1 0 1 0 0 1 1 1 0 0 0 0 0 0 NO. OF 1 = 2, 2 IS EVEN NO. SO P FLAG = 1

1 0 1 1) 0

1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 0 1 0 0 1 1 0 0 0 0 0 0 NO. OF 1 = 1, 1 IS ODD NO. SO P FLAG = 0

5. CARRY FLAG.
IF CARRY IS OUT FROM D7 BIT THEN CARRY FLAG IS SET TO 1.

1 0 1 1) 0

1 1 1 1

1 0 1 0

1 1 0 0

1 0 1 0

1 1 0 0

1 1 1 0 1 0 0

CY FLAG = 1

HERE 1 IS OUT FROM D7 BIT, INDICATING IN A BOX, SO CARRY FLAG IS SET TO 1.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM

35

GENERATION OF CONTROL SIGNALS.


PROCESSOR DONE BASICALLY 4 OPERATIONS AS LISTED BELOW : MEMORY READ TO READ DATA FROM MEMORY. MEMORY WRITE TO WRITE DATA INTO MEMORY. I/O READ TO READ DATA FROM INPUT DEVICES. I/O WRITE TO WRITE DATA TO OUTPUT DEVICES. FOR MEMORY OPERATIONS I FOR EACH & EVERY OPERATIONS PROCESSOR GENERATES CONTROL SIGNALS AS FOLLOWING : FOR MEMORY READ MEMR. FOR MEMORY WRITE MEMW. FOR I/O READ IOR. FOR I/O WRITE IOW. PROCESSOR USES THREE PINS FOR THE PURPOSE : IO/M. RD. WR. WHETHER PROCESSOR DOES MEMORY OR I/O OPERATIONS CAN BE DECIDED FROM IO/M PIN. AS WELL AS READ OR WRITE OPERATION CAN BE SELECTED FROM THE INPUTS AT RD & WR PINS. HIGH LOGIC,1, AT IO/M PIN INITIATES I/O OPERATIONS. LOW LOGIC,0, AT IO/M PIN INITIATES MEMORY OPERATIONS. LOW LOGIC,0, AT RD PIN INITIATES READ OPERATIONS. LOW LOGIC,0, AT WR PIN INITIATES WRITE OPERATIONS.

THERE ARE TWO METHODS TO GENERATE THESE CONTROL SIGNALS. 1.) USING 3X8 DECODER. 2.) USING NAND GATE.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


1,) GENERATION OF CONTROL SIGNALS USING 3X8 DECODER.

36

[FIG. 1.17 GENERATION OF CONTROL SIGNALS USING 3X8 DECODER.]

IO/M
0 0 1 1

RD
0 1 0 1

WR
1 0 1 0

CONTROL SIGNAL
MEMR MEMW IOR IOW

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


2,) GENERATION OF CONTROL SIGNALS USING NAND GATE. IO/M RD WR

37

MEMR

MEMW

IOR

IOW

[FIG. 1.18 GENERATION OF CONTROL SIGNALS USING NAND GATES.] COMBINATION OF IO/M(LOW) & RD(LOW) GENERATES MEMR SIGNAL. COMBINATION OF IO/M(LOW) & WR(LOW) GENERATES MEMW SIGNAL. COMBINATION OF IO/M(HIGH) & RD(LOW) GENERATES IOR SIGNAL. COMBINATION OF IO/M(HIGH) & WR(LOW) GENERATES IOW SIGNAL.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM

38

GENERATE MEMR FROM IO/M & RD USING 2 TO 4 DECODER.

IO/M 2X4 DECODER RD MEMR

[FIG. 1.19 GENERATION OF MEMR FROM IO/M & RD USING 2X4 DECODER.]

GENERATE IOR FROM IO/M & RD USING 2 TO 4 DECODER.


IO/M 2X4 DECODER RD IOR

[FIG. 1.20 GENERATION OF IOR FROM IO/M & RD USING 2X4 DECODER.]

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM

39

GENERATE MEMW FROM IO/M & WR USING 2 TO 4 DECODER


IO/M 2X4 DECODER WR [FIG. 1.21 GENERATION OF MEMW FROM IO/M & WR USING 2X4 DECODER.] MEMW

GENERATE IOW FROM IO/M & WR USING 2 TO 4 DECODER.


IO/M 2X4 DECODER WR IOW

[FIG. 1.22 GENERATION OF IOW FROM IO/M & WR USING 2X4 DECODER.]

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM

40

MICROPROCESSOR THE MICROPROCESSOR OPERATIONS.


BASICALLY A PROCESSOR ACCEPTS DATA FROM INPUT DEVICES, PERFORMS TASKS BASED ON GIVEN INSTRUCTIONS, GIVE THE OUTPUT TO REAL WORLD. THE FUNCTIONS CAN BE CLASSIFIED INTO THREE CATEGORIES, 1.) MICROPROCESSOR INITIATED OPERATIONS. 2.) INTERNAL DATA MANIPULATION. 3.) PERIPHERAL INITIATED OPERATIONS. EACH OPERATION IS PERFORMED IN SYNCHRONIZATION WITH CLOCK PULSE CALLED T-STATE.

1.) MICROPROCESSOR INITIATED OPERATIONS.


IT PERFORMS 4 BASIC OPERATIONS AS : MEMORY READ, MEMORY WRITE, IO READ, IO WRITE. TO PERFORM THESE OPERATIONS, PROCESSOR PERFORMS THREE STEPS AS : TO IDENTIFY MEMORY LOCATION FOR MEMORY OPERATION & I/O DEVICES BY I/O PORT ADDRESS. XFER THE DATA. PROVIDE THE NECESSARY CONTROL SIGNALS. THIS CAN BE SHOWN BELOW IN THE FORM OF TIMING DIAGRAM. ALE GOES HIGH TO FETCH LOWER ADDRESS, AFTER THEN ALE GOES LOW & DATA IS PRESENT ON THE BUS, IT INITIATES CONTROL SIGNALS ACCORDING TO THE OPERATION, DATA IS XFERED TO THE DATA BUS.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


TIMING DIAGRAM OF MEMORY READ CYCLE
T1 CLK T2 T3

41

ALE

A15- A8

HIGH ORDER ADDRESS

AD7-AD0

LOW ORDER ADDRESS

DATA FROM MEMORY

IO/M M

RD

MEMR

[FIG. 1.23 TIMING DIAGRAM OF MEMORY READ CYCLE.]

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


3 TSTATES ARE REQUIRED TO COMPLETE A MEMORY READ CYCLE. DURING 1ST T-STATE: ALE GOES HIGH, 8085 PLACES THE HIGHER ADDRESS ON A8 TO A15, 8085 PLACES THE LOWER ADDRESS ON AD0 TO AD7, IO/M GETS LOW LOGIC TO INDICATE MEMORY OPERATION, DURING 2ND & 3RD T-STATE : RD GOES LOW FOR READ OPERATION 8085 GENERATES MEMR CONTROL SIGNAL.

42

THEREFORE MEMORY DEVICE PLACES THE CONTENT OF MEMORY ON DATA BUS. THIS IS THE WAY IN WHICH PROCESSOR READS THE MEMORY CONTENT.

TIMING DIAGRAM OF MEMORY WRITE CYCLE.


3 TSTATES ARE REQUIRED TO COMPLETE A MEMORY WRITE CYCLE. DURING 1ST T-STATE: ALE GOES HIGH, 8085 PLACES THE HIGHER ADDRESS ON A8 TO A15, 8085 PLACES THE LOWER ADDRESS ON AD0 TO AD7, IO/M GETS LOW LOGIC TO INDICATE MEMORY OPERATION, DURING 2ND & 3RD T-STATE : WR GOES LOW FOR WRITE OPERATION 8085 GENERATES MEMW CONTROL SIGNAL. THEREFORE MEMORY DEVICE READS THE CONTENT OF MEMORY FROM PROCESSOR. THIS IS THE WAY IN WHICH PROCESSOR WRITES INTO THE MEMORY.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


T1 T2 T3

43

CLK

ALE

A15- A8

HIGH ORDER ADDRESS

AD7-AD0

LOW ORDER ADDRESS

DATA FROM MPU

IO/M

WR

MEMW

[FIG. 1.24 TIMING DIAGRAM OF MEMORY WRITE CYCLE.]

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


2.) INTERNAL DATA MANIPULATION.

44

DATA IS XFERED TO THE PROCESSOR THROUGH MEMORY READ &/OR I/O READ OPERATIONS. THEN AFTER PROCESSOR PERFORMS OPERATIONS ON THIS DATA AS IN FOLLOWING SEQUENCE : IT STORES THE 8 BIT DATA, DECODE THE DATA, PERFORM THE ARITHMATIC & LOGICAL OPERATION ACCORDING TO THE INSTRUCTION, STORE THE RESULT.

3.) EXTERNALLY INITIATED OPERATIONS :


EXTERNAL DEVICES CAN INITIATE THE FOLLOWING OPERATIONS BY SENDING SIGNAL ON SPECIFIC PIN OF THE PROCESSOR : RESET. THIS OPERATION CAN BE INITIATED BY MAKING RESET IN SIGNAL LOW OF 8085. WHEN RESET IS ACTIVATED, THE 8085 SUSPENDS ALL THE CURRENT ACTIVITIES. IT STOPS ALL THE OPERATIONS & GOES AT THE STARTING OF THE PROGRAM & HENCE CLEAR THE PROGRAM COUNTER. IT MEANS THE VALUE OF PC AFTER RESET IS PC = 0000H. INTERRUPT. THE EXTERNAL DEVICES CAN DISTURB THE 8085S CURRENT OPERATIONS. THE INTERRUPTION CAN BE CREATED BY SENDING SIGNAL ON ONE OF THE INTERRUPT PINS.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


WHEN PERIPHERAL DEVICE SENDS INTERRUPT TO PROCESSOR :

45

PROCESSOR SAVES CURRENT STATUS OF PC ON STACK CONTROLS (PC) ARE X FERED TO THE DEVICE, DEVICE EXECUTES THE GROUP OF INSTRUCTUIONS CALLED INTERRUPT SERVICE ROUTINE (ISR), AFTER COMPLETING ISR, IT RESUMS NORMAL EXECUTION WHICH CONTENT IS SAVED ON STACK, READY. THIS IS USED TO SYNCHRONIZE THE OPERATION OF THE SLOWER DEVICE WITH THE PROCESSOR. HOLD. WHEN HOLD GOES HIGH, THE 8085 COMPLETES THE CURRENT CYCLE & LEAVES THE CONTROL OF BUSES IN ORDER TO ALLOW THE OTHER PERIPHERAL DEVICES.

8085 INTERRUPTS.
THERE ARE FIVE INTERRUPTS IN 8085 : TRAP RST 7.5 RST 6.5 RST 5.5 INTR - MASKABLE, - NON MASKABLE, - NON MASKABLE, - NON MASKABLE, - NON MASKABLE,

WHEN INTERRUPT COMES ON ONE OF THE 8085 PINS : 8085 SUSPENDS CURRENT ACTIVITY, SAVES THE STATUS ON THE STACK, JUMPS ON THE ADDRESS WHERE SPECIFIC ISR IS WRITTEN.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


PRIORITY : ALL THE INTERRUPTS WORK ON THEIR PRIORITY WHICH IS DEFAULT IN PROCESSOR. THEY ARE LISTED AS BELOW :

46

NAME OF INTERRUPT TRAP RST 7.5 RST 6.5 RST 5.5 INTR

PRIORITY 1 2 3 4 5

INTA :- INTERRUPT ACKNOWLEDGEMENT. THIS IS ACTIVE LOW SIGNAL & GENERATED BY PROCESSOR IN THE RESPONSE OF THE INTERRUPT REQUEST. VECTOR ADDRESS : WHEN INTERRUPT COMES ON ONE OF THE 8085 PIN, THE PC JUMPS TO SPECIFIC ADDRESS WHERE ISR (INTERRUPT SERVICE ROUTINE) IS WRITTEN. THAT ADDRESS IS CALLED VECTOR ADDRESS. THAT ADDRESS IS AS GIVEN BELOW : NAME OF INTERRUPT TRAP RST 7.5 RST 6.5 RST 5.5 INTR ADDRESS 0024H 003CH 0034H 002CH ADD. GIVEN BY EXT. INTERRUPT CONTROLLER

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM

47

QUESTIONS ASKED FOR 2 MARKS.


1.) GIVE THE MAJOR DIFFERENCE BETWEEN RAM & ROM. RAM CAN BE READ & WRITTEN WHILE ROM CAN ONLY BE READ NOT WRITTEN. RAM IS A TEMPORARY STORAGE WHERE AS ROM IS A PERMANENT STORAGE. 2.) WHAT HAPPENS WHEN INTERRUPT COMES ? PROCESSOR STOPS EXECUTION OF ALL CURRENT ACTIVITIES. PC GETS 0000H VALUE. PROCESSOR XFERS THE CONTROLS TO THE PERIPHERALS. 3.) WHY DO WE REQUIRE TO DEMULTIPLEX MULTIPLEXED ADD/DATA BUS ? OPCODES & DATAA ARE STORED IN MEMORY HAVING 16 BIT ADDRESS, A8 TO A15 HIGHER ADDRESS & AD0 TO AD7 LOWER ADDRESS. AT EACH MACHINE CYCLE WE NEED A COMPLETE 16 BIT ADDRESS. A8 TO A15, MEANS HIGHER ADDRESS IS AVAILABLE INDIVIDUALLY AT PIN NO. 20 TO 28. BUT LOWER ADDRESS LINES ARE MULTIPLEXED WITH THE DATA BUS SO WE NEED TO DEMULTIPLEX THEM. 4.) WHAT DO YOU MEAN BY FETCH-DECODE-EXECUTE CYCLE ? EACH & EVERY INSTRUCTION HAS AN OPCODE WHICH IS STORED IN MEMORY. THE TIME REQUIRED TO FETCH THE OPCODE FROM MEMORY IS CALLED FETCH CYCLE. THE TIME REQUIRED TO DECODE THAT FETCHED OPCODE IS CALLED DECODE CYCLE. THE TIME REQUIRED TO EXECUTE THE DECODED OPCODE IS CALLED EXECUTE CYCLE.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


5.) WHY ARE PC & SP 16 BIT IN 8085 ? PROGRAM COUNTER (PC) STORES THE ADDRESS OF THE NEXT INSTRUCTION TO BE FETCHED. STACK POINTER (SP) STORES THE ADDRESS OF THE TOP OF THE STACK.

48

MEANS BOTH THE REGISTERS STORE THE16 BITS ADDRESS SO SIZE OF THOSE REGISTERS IS 16 BIT. 6.) WHAT IS STACK ? WHAT IS THE USE OF STACK POINTER ? STACK IS THE PART OF RAM, USED TO STORE TEMPORARY DATA. STACK POINTER STORES THE ADDRESS OF TOP OF STACK. 7.) WHY DOES ROM CHIP HAS ONLY RD ? ROM MEANS READ ONLY MEMORY. IT CAN ONLY BE READ NOT WRITTEN SO IT HAS ONLY RD TERMINAL NOT WR. 8.) GIVE THE FORMATE OF FLAG REGISTER. D7 S D6 Z D5 ----D4 AC D3 ----D2 P D1 ----D0 CY

9.) WHAT HAPPENS WHEN 8085 RECIEVES THE RESET SIGNAL ? FIRST OF ALL, PROCESSOR SUSPENDS ALL THE CURRENT OPERATIONS. PROCESSOR CLEARS THE PROGRAM COUNTER i.e. PC STORES 0000H. 10.) GIVE THE IMPORTANCE OF READY SIGNAL. THIS SIGNAL IS USED TO SYNCHRONIZE THE OPERATION OF SLOWER DEVICES WITH THE PROCESSOR. WHEN READY GOES LOW, THE PROCESSOR GOES INTO WAIT STATE & REMAINS IDLE UNTIL READY GOES HIGH AGAIN.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


11.) LIST THE PERIPHERAL INITIATED OPERATIONS. RESET, INTERRUPT, READY, HOLD. 12.) GIVE THE FUNCTIONS OF CONTROL SIGNALS : IO/M, RD, & WR.

49

IO/M DECIDES WHETHER THE OPERATION IS IO TYPE OR MEMORY TYPE. RD SIGNAL ACTIVATES READ OPERATION. WR SIGNAL ACTIVATES WRITE PERATION. THE COMBINATION OF THESE THREE SIGNSLS GENERATES CONTROL SIGNSLS LIKE : MEMORY READ, MEMORY WRITE, IO READ & IO WRITE. 13.) LIST THE 8085 MACHINE CYCLES ALONG WITH STATUS SIGNAL VALUES.

MACHINE CYCLE MEMORY WRITE IO WRITE MEMORY READ IO READ OPCODE FETCH INTERRUPT ACKNOWLEDGE HALT HOLD RESET

IO/M 0 1 0 1 0 1 * * *

S1 0 0 1 1 1 1 0 X X

S0 1 1 0 0 1 1 0 X X

14.) GIVE THE FUNCTION OF PROGRAM COUNTER. PC STORES THE 16 BIT ADDRESS OF THE NEXT INSTRUCTION TO BE FETCHED. 15.) GIVE THE FUNCTION OF ALE PIN OF 8085. ALE IS USED TO FETCH THE LOWER 8-BIT ADDRESS FROM MULTIPLEXED ADDRESS & DATA BUS.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


16.) GIVE THE FUNCTIONS OF HOLD & HLDA PINS OF 8085. THESE SIGNALS ARE USED WITH DMA CONTROLLER.

50

DMA CONTROLLER USES HOLD TO SEND THE REQUEST FOR GRANTING THE CONTROL OF BUSES TO PROCESSOR. HLDA IS USED BY PROCESSOR TO ACKNOWLEDGE THE GRANTING OF REQUEST. 17.) HOW DO YOU DETERMINE THE MAXIMUM MEMORY THAT CAN BE ACCESSED BY A PROCESSOR ? AMOUNT OF MEMORY CAN BE FOUND BY TAKING THE ADDRESS LINES POWER OF THE 2. AMOUNT OF MEMORY = 2
ADDRESS LINES

(OCTOBER/NOVEMBER-2001)
18.) DIFFERENTIATE ACTIVE HIGH & ACTIVE LOW LOGIC. ACTIVE HIGH LOGIC MEANS PIN IS ACTIVATED WHEN 1 LOGIC IS APPLIED AT THAT PIN IS CALLED ACTIVE HIGH LOGIC. ACTIVE LOW LOGIC MEANS PIN IS ACTIVATED WHEN 0 LOGIC IS APPLIED AT THAT PIN IS CALLED ACTIVE LOW LOGIC. 19.) ENUMERATE INTERRUPT PINS OF 8085 PROCESSOR. NAME OF PIN TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA PIN NUMBER 6 7 8 9 10 11

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


20.) DRAW DIAGRAM TO GENERATE MEMR FROM IO/M & RD USING 2X4 DECODER. IO/M 2X4 MEMR RD DECODER

51

21.) DIFFERENTIATE LATCH & BUFFER. LATCH IS ONE TYPE OF MEMORY WHICH REMEMBERS THE LAST STATE. BUFFER IS USED TO INCREASE THE STRENGTH OF THE INPUT SIGNAL. 22.) WHAT IS TRI-STATE ? THE DEVICE HAVING THREE STATES NAMED 0, 1, & Z. Z MEANS HIGH IMPEDANCE.

I/P 0 1 0 1

CONTROL C 0 1 1

O/P

Z 0 1

I/P

O/P

23.) WHAT IS T-STATE ? T-STATE IS A SUB DIVISION OF A MACHINE CYCLE. A MACHINE CYCLE CONSISTS NUMBER OF T-STATES AS PER OPERATION.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


24.) STARTING ADDRESS OF MEMORY OF 1 Kb IS 7000H THEN WHAT IS ENDING ADDRESS OF THAT MEMORY ? CALCULATION OF ADDRESS LINES :ADDRESS LINES TO ACCESS MEMORY = 1KB = 1K X 1 =2 =2 CHIP SELECTION
A15 A14 A13 A12 A11 A10 0 0 1 1 1 1 1 1 0 0 0 0 A9 0 1 A8 0 1 0 1

52

10

X2

10

DIRECT CONNECTED
A7 A6 0 1 A5 0 1 A4 0 1 A3 0 1 A2 0 1 A1 0 1 A0 0 1 ADDRESS 7000H 73FFH

ENDING ADDRESS IS 73FFH. 25.)ONE PROCESSOR IS HAVING 8-BIT DATA BUS & 12-BIT ADDRESS BUS. CALCULATE MAXIMUM ADDRESSING CAPACITY OF THAT PROCESSOR. MAXIMUM ADDRESSING CAPACITY DEPENDS UPON NO. OF ADDRESS BUS NOT ON DATA BUS, SO IT IS NO MATTER THAT HOW MANY DATA BUS IS GIVEN. MAXIMUM ADDRESSING CAPACITY = 2
NO. OF ADDRESS BUS 12

=2 =210 X 22 =1K X 4 =4Kbyte MAXIMUM ADDRESSING CAPACITY OF THE PROCESSOR IS 4K. 26.) WHAT IS MULTIPLEXING ? WHY IT IS NEEDED IN PROCESSOR FOR ADDRESS DATA. MULTIPLEXING MEANS MORE THAN ONE QUANTITY CAN BE PRESENT ON A SINGLE WIRE. HERE ADDRESS & DATA ARE AVAILABLE AT PIN AD0 TO AD7 CALLED MULTIPLEXED ADDRESS DATA BUS. IT IS USED TO SAVE THE NUMBER OF PINS TO MAKE THE CHIP SMALLER IN AREA.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


27.) GIVE THE FUNCTION OF STACK. STACK IS THE AREA OF A RAM. IT IS USED TO STORE THE DATA TEMPORARY.

53

(OCTOBER/NOVEMBER 2003)
28.) DEFINE MACHINE CYCLE & INSTRUCTION CYCLE. THE TIME REQUIRED TO COMPLETE A SINGLE OPERATION IS CALLED A MACHINE CYCLE. THE TIME REQUIRED TO COMPLETE THE EXECUTION OF AN INSTRICTION IS CALLED INSTRUCTION CYCLE. 29.) DRAW FLAG REGISTER INDICATING ALL FLAGS SYMBOL & EXPLAIN FUNCTION OF AC. D7 S SIGN D6 Z ZERO D5 ----D4 AC D3 ----D2 P PARITY D1 ----D0 CY CARRY

AUXILIARY CARRY

AC FLAG IS SET WHEN CARRY IS XFFERED ROM BIT D3 TO D4. 30.) WHAT IS THE FUNCTION OF READY PIN. SEE THE ANSWER OF QUESTION NO. 10. 31.) IF ANY ARBITRARY PROCESSOR HAS 12-BIT ADDRESS LINE & 8-BIT DATA LINE. FIND OUT ADDRESSING CAPABILITY OF THAT PROCESSOR. SEE THE ANSWER OF QUESTION NO. 25. 32.) DIFFERENTIATE ACTIVE HIGH & ACTIVE LOW LOGIC. SEE THE ANSWER OF QUESTION NO. 18.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


MAY/JUNE 2004
33.) WHAT IS PROGRAM COUNTER ? WHAT IS SIZE OF PC IN 8085 PROCESSOR ? PC STORES THE 16 BIT ADDRESS OF THE NEXT INSTRUCTION TO BE FETCHED. THE SIZE OF THE PC IS 16 BIT. 34.) WHAT IS THE FUNCTION OF ALE SIGNAL IN 8085 PROCESSOR.

54

ALE IS USED TO FETCH THE LOWER 8-BIT ADDRESS FROM MULTIPLEXED ADDRESS & DATA BUS, WHEN IT IS HIGH.

APRIL/MAY 2005
35.) WHAT IS ALE ? GIVE ITS FUNCTIONALITY. SEE THE ANSWER OF QUESTION NO. 34. 36.) GIVE IMPORTANCE OF AC FLAG IN 8085. SEE THE ANSWER OF QUESTION NO. 29. 37.) GIVE THE FUNCTION OF SP & PC. SP STORES THE 16-BIT ADDRESS OF TOP OF THE STACK. PC STORES THE 16-BIT ADDRESS OF THE NEXT INSTRUCTION TO BE FETCHED. 38.) DRAW THE CIRCUIT TO GENERATE IOR, IOW, MEMR & MEMW FROM RD, WR & IO/M USING 3X8 DECODER. 8085 IO/M RD WR DECODER A B C IOW IOR MEMW MEMR

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM

55

39.) WHAT IS THE DIFFERENCE BETWEEN OPCODE FETCH & MEMORY READ CYCLE ? IN OPCODE FETCH CYCLE OPCODE OF AN INSTRUCTION IS FETCHED FROM MEMORY. IT IS A CODE OF AN INSTRUCTION STORED IN MEMORY. IT COCSISTS OF 4 T-STATES. DURING MEMORY READ CYCLE DATA IS BEING FETCHED FROM THE MEMORY. IT CONSISTS OF 3 T-STATES. 40.) WHAT IS THE FUNCTION OF READY PIN OF 8085. SEE THE ANSWER OF QUESTION NO. 10.

APRIL/MAY 2006
41.) THE VECTOR ADDRESS OF TRAP IS 0024H. 42.) SID & SOD PINS OF 8085 ARE USED FOR SERIAL I/O. 43.) IF STARTING ADDRESS OF 8K RAM IS 8000H, THEN ENDING ADDRESS IS 9FFFH. 44.) THE REGISTER ALWAYES POINTING TO THE LOCATION OF NEXT INSTRUCTION TO BE FETCHED IS PROGRAM COUNTER.

JUNE/JULY 2008
45.) GIVE SIGNIFICANCE OF ALE. SEE THE ANSWER OF Q.15. 46.) WHAT IS STACK? WHAT IS FUNCTION OF SP? SEE THE ANSWER OF Q.27. & Q.37. 48.) GIVE THE FULL FORM OF PSW. DRAW STRUCTURE OF IT. Program Status World. FOR STRUCTURE, SEE THE ANSWER OF Q.29. 49.) LIST THE FUNCTION OF CONTROL SIGNALS IO/M, RD, & WR. THEY ARE USED TO GENERATE THE CONTROL SIGNALS AS : MEMR FROM IO/M & RD. MEMW FROM IO/M & WR. IOR FROM IO/M & RD. IOW FROM IO/M & WR.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM

56

50.) LIST THE INTERRUPT PINS. TRAP, RST 7.5, RST 6.5, RST 5.5, INTR, & INTA. 51.) GIVE THE FUNCTION OF HOLD & HLDA PINS OF 8085. SEE THE ANSWER OF Q.16. 52.) DIFFERENTIATE BETWEEN MASKABLE & NON MASKABLE INTERRUPTS. THE EXECUTION OF MASKABLE INTERRUPTS CAN BE STOPPED BY MEANS OF EITHER BY SOFTWARE OF BY HARDWARE. BUT THE EXECUTION OF NON MASKABLE INTERRUPTS CAN NOT BE STOPPED BY ANY HOW.

(OCTOBER/NOVEMBER-2008)
53.) DRAW FLAG REGISTRY OF 8085. EXPLAIN ANY ONE. SEE THE ANSWER OF Q.29. 54.) EXPLAIN FUNCTION OF ALE PIN IN BRIEF. SEE THE ANSWER OF Q.15. & Q.34. 55.) WHAT IS THE VALUE OF PROGRAM COUNTER AT THE TOME OF RESET? 0000H. 56.) DRAW THE CIRCUIT TO GENERATE IOR & IOW FROM RD, WR & IO/M. SEE THE ANSWER OF Q.38.

QUESTION ASKED FOR 5 MARKS.


OCTOBER/NOVEMBER - 2001
1.) DRAW & EXPLAIN BLOCK DIAGRAM OF ARCHITECTURE OF 8085 MICROPROCESSOR WITH NEAT SKETCH. 2.) DRAW DIAGRAM FOR DEMULTIPLEXING OF ADDRESS & DATA BUS. EXPLAIN IT.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


MAY/JUNE - 2002
3.) Q.1. 4.) DRAW STRUCTURE OF FLAG REGISTER & EXPLAIN EACH FLAG. 5.) Q.2. 6.) TABULATE ALL TYPES OF M/C ALONG WITH RD, WR, IO/M, S1 & S0. EXPALIN IMPORTANCE OF STATUS SIGNALS. 7.) DRAW & EXPLAIN REGISTER FILE IN 8085. ENUMARATE GENERAL PURPOSE REGISTERS & SPECIAL PURPOSE REGISTERS & GIVE ITS SPECIALITY. 8.) MEMORY MAPPING IN 8085 BASED SYSTEM.

57

OCTOBER/NOVEMBER - 2002
9.) Q.1. 10.) EXPLAIN INTERRUPT SYSTEM OF 8085 IN DETAIL. 11.) DRAW THE CIRCUIT TO GENERATE IOR, IOW, MEMR & MEMW FROM RD, WR & IO/M USING 3X8 DECODER. 12.) Q.4. 13.) FUNCTION OF PROGRAM COUNTER & STACK POINTER.

MAY/JUNE - 2003
14.) Q.1. 15.) Q.4. 16.) Q.7.

OCTOBER/NOVEMBER - 2003
17.) Q.1. 18.) Q.11. 19.) Q.13.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


MAY/JUNE - 2004
20.) Q.1. 21.) Q.11. 22.) Q.10.

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OCTOBER/NOVEMBER - 2004
23.) EXPLIAN 8 BIT & 16 BIT REGISTERS IN 8085 PROCESSOR. 24.) Q.2.

MAY/JUNE - 2005
25.) Q.1. 26.) Q.4. 27.) Q.2.

OCTOBER/NOVEMBER - 2005
28.) Q.1. 29.) Q.10. 30.) Q.4. 31.) Q.11.

APRIL/MAY - 2006
32.) Q.4. 33.) WHAT IS BUS ? EXPLIAN BUS ORGANIZATION IN 8085 WITH DIAGRAM. 34.) WHAT IS DMA ? EXPLAIN DMA IN 8085 USING PINS HOLD & HLDA. 35.) Q.2.

NOVEMBER 2006
36.) Q.1. 37.) Q.10. 38.) Q.4.

KUNAL S. THAKER

CH. 1 MICROPROCESSOR ARCHITECTURE & SYSTEM


39.) EXPLAIN MEMORY WRITE OPERATION WITH THE HELP OF TIMING DIAGRAM. 40.) Q.11.

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MAY/JUNE - 2007
41.) Q.1. 42.) EXPLAIN BASIC MICROCPMPUTER SYSTEM. 43.) EXPLAIN IN BRIEF, ALL PINS OF 8085 PROCESSOR, WHICH ARE RELATED TO INTERRUPT OPERATION. 44.) EXPLAIN REGISTER STRUCTURE OF 8085. (SAME AS Q.23.)

OCTOBER/NOVEMBER - 2007
45.) Q.1. & Q.4. 46.) Q.2. 47.) Q.11. (USING NAND GATE)

JUNE/JULY - 2008
48.) Q.23. 49.) Q.4.

NOVEMBER/DECEMBER - 2008
50.) Q.1.

KUNAL S. THAKER