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Standard cell methodology is an example of design abstracton, whereby a low-evel YLS I-layout is encapsulated into an abstract hgic representation. Standard cell methodology was responsible for allowing designers to scae ASICs from comparatively simple single-function [Cs (of several thousand gates) to cornpex multi-million gate devices (SoCs)
Standard cell methodology is an example of design abstracton, whereby a low-evel YLS I-layout is encapsulated into an abstract hgic representation. Standard cell methodology was responsible for allowing designers to scae ASICs from comparatively simple single-function [Cs (of several thousand gates) to cornpex multi-million gate devices (SoCs)
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Standard cell methodology is an example of design abstracton, whereby a low-evel YLS I-layout is encapsulated into an abstract hgic representation. Standard cell methodology was responsible for allowing designers to scae ASICs from comparatively simple single-function [Cs (of several thousand gates) to cornpex multi-million gate devices (SoCs)
Droits d'auteur :
Attribution Non-Commercial (BY-NC)
Formats disponibles
Téléchargez comme PDF, TXT ou lisez en ligne sur Scribd