Decoupling Capacitor Stacked Chip (DCSC) in TSVbased 3D-ICs

Eunseok Song, Kyoungchoul Koo, Myunghoi Kim, Jun So Pak and Joungho Kim
Department of Electrical Engineering KAIST Daejeon, South Korea essonguy@kaist.ac.kr
AbstractIn this paper, we introduce a new decoupling capacitor stacked chip (DCSC) with discrete capacitors and throughsilicon-vias (TSVs) that can overcome the limitations of the conventional decoupling capacitor solutions such as expensive onchip NMOS capacitor and package-level discrete decoupling capacitor with narrow-band. The key idea of the proposed TSVbased DCSC is mounting the decoupling capacitors such as silicon-based NMOS capacitor and discrete capacitor on the backside of a chip and connecting the capacitors to the on-chip PDN through TSVs. Therefore, the TSV-based DCSC provides the lowest parasitic inductance (ESL: under several tens pH) through a short interconnections between the on-chip PDN and decoupling capacitors as well as the largest capacitance (up to several uF) by stacking the additional decoupling capacitors to 3D-IC systems. Keywords- decoupling capacitor, through-silicon-via (TSV), three-dimensional integrated circuit (3D IC), power integrity, power distribution network (PDN), simultaneous switching noise (SSN)

as timing jitter and skew in high-speed digital channels, electromagnetic interference (EMI) in mobile systems, and noise coupling in digital/RF mixed-mode systems, especially, as 3D integration poses grander power delivery challenges for increased power density. As TSV-based 3D-ICs include highspeed and high-current integrated circuits (ICs), distribution of stable power supply voltages and suppression of SSN noise have become critical design issues. The way to keep a clean power supply in 3D-IC is to mainly focus on the PDN design for the lowest impedance. 3D-IC technologies make floorplanning a much more difficult problem because the multi-tier structures dramatically enlarge the solution space and the increased power density accentuates the thermal issue. Therefore, moving to 3D designs increases the issue of complexity greatly.

I.

INTRODUCTION

Through-silicon-via (TSV) has emerged as a promising solution to achieve 3-D integration technologies at the future electronics market such as mobile processors, high-end computers, flat-panel high-definition TVs (HDTVs) and health care. The main drivers for 3D stacking are size reduction, solving the interconnect bottleneck, heterogeneous integration of different technologies, and higher electrical performance. TSV has been identified as one of the major technologies to accomplish the goals above by 3D integration [1]. TSVs technology can be developed in an area array format thereby increasing the vertical interconnection density such as heterogeneous integration of different ICs. Therefore, TSVbased 3D integration provides many benefits of high density, high band-width, low-power, low-slew 3D clock delivery network (CDN) and small form-factors [2], [3]. Moreover, TSV interconnects can provide vertical connections between various layers of chips and thereby largely reduce the interconnect length between a microprocessor chip and decoupling capacitors. Accordingly, the TSV interconnect parasitics, such as the resistance and inductance, will be reduced, which can enable better power delivery network design. In general, when a switching device pulls large amounts of current simultaneously, power and ground fluctuations occur which can result in functional failures such

Figure 1. Basic conceptual structure of a face-down TSV-based DCSC and application and implementation of proposed TSV-based DCSC (decoupling capacitor stacked chip) face-down structures in the 3D integration system.

In 3D systems, a power-integrity problem arises from the third dimension, and we can also push the solutions into the third dimension. In the following sections, new design methodologies will be presented in a "3D" way to tackle the 3D problem. The basic decoupling capacitor technologies for suppressing simultaneous switching noise (SSN) in a 3D stacked system can mainly be classified in two broad categories: package-level decoupling capacitors and on-chip

978-1-4244-9401-9/11/$26.002011 IEEE 978-1-4244-9399-9/11/$26.002011

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NMOS capacitors. The package-level decoupling capacitor scheme has a disadvantage of higher PDN loop inductance (up to several nH) compared to on-chip decoupling capacitor method. On the other hand, the on-chip NMOS decoupling capacitors has the limitation of the capacitance (0.1 uF) due to a lack of the area of a chip. In this study, a new TSV-based decoupling capacitor stacked chip (DCSC) stacked on the backside of a chip is proposed which overcomes the limits of conventional decoupling capacitor solutions for SSN noise mitigation in PDNs. The proposed structure has a large capacitance by stacking an additional decoupling capacitor such as a siliconbased NMOS capacitor chip and a discrete decoupling capacitor with low ESL of 90 pH as well as lower PDN loop inductance due to the use of TSV technology compared to package level decoupling capacitor solution. The proposed TSV-based DCSC can be used as a promising way in order to improve the power and ground noise by placing the NMOS capacitor chip between mobile application processor (AP) and memory DDR3 DRAM chip in 3D-ICs [4]. Fig. 1 schematically depicts the structure of the proposed TSV-based DCSC and its implementation in 3D-ICs. As indicated in Fig. 1, TSV-based DCSCs can be used in various 3D stacked structures, and the decoupling capacitors are a face-down type that can be either silicon-based NMOS capacitors or discrete decoupling capacitors. This study suggests, using a new TSVbased DCSC mounted on the backside of a chip to overcome the limitations of conventional decoupling capacitor solutions for SSN noise mitigation in PDNs. This approach using TSVs satisfies the target impedance for a wide range of frequencies in 3D-IC. While the TSV-based DCSC shows an advantage of on-chip NMOS capacitors in the inductive PDN impedance region and represents a strong point of on-package decoupling capacitors with high capacitance in the capacitive PDN impedance region. II. PROPOSED TSV-BASED DECOUPLING CAPACITOR STACKED CHIP (DCSC)

As depicted in Fig. 2, TSV-based DCSC uses decoupling capacitors such as silicon-based NMOS capacitor, with discrete capacitor mounted on the backside of a chip that connects them to the on-chip PDN through TSV technology. Thus, The TSVbased DCSC can provide the lowest equivalent series inductance (ESL) by using TSVs between the on-chip PDN and decoupling capacitors and the largest capacitance by using additional decoupling capacitors in 3D-IC systems. Moreover, in order to guarantee the routability of signal I/Os in the 3D integration system, TSV-based DCSC stacked as a type of face-down (flip-chip) is suggested. Fig. 2 represents the facedown TSV-based DCSC structure and its detailed parameters, respectively. The on-chip PDN metal consists of six layers (meshed type) and is fully located in the IMD (inter-metal dielectric) layer of a 5mm5mm chip. The TSV used a viamiddle process in which the diameter and the height of the TSV were determined to be 6 um and 50 um, respectively. A metal pad was formed for stacking the decoupling capacitors on the backside of the DCSC chip that employs an RDL (redistribution layer) process.

(a)

As on-chip decoupling capacitor generally has low inductance, it is effective in improving power noise such as SSN, but it has disadvantages in increasing the capacitance value to a specific level due to the limitation of the chip area, which embeds the NMOS transistors. On the other hand, an off-chip decoupling capacitor provides a very high capacitance by using extra ceramic capacitors. However, relatively large loop inductance of PDN makes the off-chip decoupling capacitor vulnerable to high frequency noise. In this paper, we introduce the TSV-based DCSC that indicates the advantages of low on-chip level ESL and high off-chip level capacitance. While the TSV-based DCSC shows an advantage of on-chip NMOS capacitors such as low ESL of below several tens pH, a disadvantage of on-package decoupling capacitors with high inductance of several nH, and represents a strength of onpackage decoupling capacitors like high capacitance of up to several uF, a weak point of on-chip NMOS capacitors with low capacitance of below a several hundred nF. In this section, the basic ideas of the proposed TSV-based DCSC are presented. Fig. 2 shows the basic conceptual structure of the TSV-based DCSC with a type of face-down.

(b) Figure 2. Configuration of the proposed TSV-based decoupling capacitor stacked chip (DCSC): (a) Perspective view of the proposed TSV-based DCSC (face-down type); (b) Detailed structures, dimension variables, and materials of the TSV-based DCSC with a face-down design. Discrete decoupling capacitors with low ESL are stacked on a chip that has six P/G metal layers with a 5.0 mm5.0 mm area, and a chip thickness of 50 um.

As described in Fig. 2, the DCSC uses an on-chip power/ground metal with multi-layers, through-silicon-vias (TSV), and discrete decoupling capacitors stacked on the

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backside of a chip. The proposed DCSC structure can directly supply power to stacked decoupling capacitors during the operation of the chip by connecting the chip-PDN and decoupling capacitors with the TSVs. By ensuring low PDN impedance via the TSV and decoupling capacitors stacked on the backside of the chip, it is possible to ensure a stable SSN noise margin. In general, this restricts the number of P/G TSVs that can be used in the 3D PDN with which exceeding the area budget of a chip and routing congestion can be avoided. This complex optimization usually results in a large area, more power consumption, and lower performance, thereby diminishing the benefit of TSV-based 3D-IC technology. Thus, one suggestion is to use various types of chips stacked as a type of face-down in order to ensure the routability of signal I/Os through the 3D stacked structure. Therefore, the TSV-based DCSC in this study presumes a type of face-down structure that stacks decoupling capacitors on the backside of a chip, thereby presenting a plethora of possible application to 3D-IC systems. III. ANALYSIS FOR THE TSV-BASED DECOUPLING CAPACITOR STACKED CHIP (DCSC)

was determined as 3.0 nH, and the ESL for each discrete decoupling capacitor was configured as 90 pH. As indicated in Fig. 3, in the case of the wirebond-type SiP package, the level of the inductive impedance curve is high, and the parallel resonance occurs at a frequency band of 180 MHz due to the interaction between the wirebond inductance and the on-chip PDN. In addition, the more the inductance of a wirebond-type SiP package is increased, the more the peak of parallel resonance generated by the interaction between the inductance of wire bonding and the capacitance of the chipPDN would increase. Due to the increase in the impedance of anti-resonance, the power noise margin like SSN decreases and that leads to generate operational failures in a 3D-IC system. Eventually, if off-chip decoupling capacitors are used in a high-speed 3D integration system, it will cause an anti-parallel resonance peak by a large scale of unwanted ESL, a level of few nH in ESL, even though it may increase the capacitance of the capacitors significantly.

In this section, we carefully verify the advantages of a TSV-based DCSC interconnection in decreasing the inductive and capacitive impedance of a PDN and suppressing the simultaneous switching noise in a 3-D stacked chip. For verifying the enhanced performance of the proposed TSVbased DCSC, conventional decoupling capacitor solutions, such as a wirebond SiP package with decoupling capacitors and on-chip NMOS decoupling capacitors, and the PDN impedance were compared using the segmentation method [5].

Figure 4. Comparison of the simulated PDN self-impedances (Z11) between the on-chip decoupling capacitors and the proposed TSV-based DCSC.

Figure 3. Comparison of the simulated PDN self-impedance (Z11) between the wirebond-type SiP package (dotted line) with off-chip decoupling capacitors (0.47 uF4ea) and the proposed TSV-based DCSC (solid line). The PDN inductance of the wirebond-type package is assumed to be 3.0 nH.

In Fig. 3, a wirebond SiP package that has four 0.47 uF offchip capacitors is presented. In the case of the wirebond SiP package, because the impedance of the wirebond in the PDN path from the on-chip metal to the decoupling capacitor is large, there is an increase in the inductive impedance curve at frequency bands occurring at several tens of MHz. In the simulation, the PDN inductance of the wirebond-type package

In order to demonstrate the performance of the proposed structure, the comparison of the conventional on-chip NMOS decoupling capacitor solution and the TSV-based DCSC was also carried out. For the chip-level NMOS capacitor, the PDN simulation was applied by using two different arrangements: one with the NMOS capacitors embedded in only 10% of the entire chip area, and the other with the NMOS capacitors arranged over the entire chip (100%) using a 5mm5mm chip. The on-chip metal PDN was configured into six layers with the same design as the one that was used in the DCSC structure. In addition, this structure contained an arrangement of on-chip NMOS capacitors. As described in Fig. 4, in the case where the NMOS capacitors utilized only 10% of the chip area (10% area is occupied by NMOS decaps), the resulting series resonance (C_NMOS cap + C_chip PDN) // (L_PDN loop L + L_TSV + L_decap ESL) moved to a high frequency range due to the decrease in the NMOS capacitance. When utilizing an on-chip NMOS capacitor, although a parallel resonance at a frequency band of 1 GHz was not observed because of the small ESL of the NMOS capacitor, an interaction between the TSV inductance and the PDN loop inductance was observed in the TSV-based DCSC structure. However, the parallel resonant

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peak is very small because the inductance of the TSV is as small as several tens of pH, compared to that of the loop inductance of the PDN. The first series resonances for three cases were 2.1 MHz (TSV-based DCSC), 7.0 MHz (100% of chip area) and 20 MHz (10% of chip area) respectively. Also, in the case of utilizing an on-chip NMOS capacitor, a parallel resonance at a frequency band of 1 GHz was not observed because of the small ESL of the NMOS capacitor, whereas the inductive impedance curve of the TSV-based DCSC represents a similar level compared with that of the on-chip NMOS capacitor. This is due to the fact that the inductance level of TSV (under 30 pH) is considerably smaller than that of the loop inductance of the chip-PDN (a level of 2~3 nH). If the TSV-based DCSC is properly used in a 3D-IC system, it will be possible to present a chip NMOS capacitor level of inductance and a ceramic capacitor level of capacitance at the same time. In a 3D-IC system, according to the decrease in the capacitance of on-chip NMOS capacitors the impedance below several tens of MHz will be increased. In addition, there is a disadvantage in increasing the overall chip cost because the area of the chip capacitor increases in order to increase the capacitance of onchip decoupling capacitors. The PDN impedance performance of the TSV-based DCSC is comparatively equal to that obtained when the NMOS capacitors are arranged over the entire chip area. Thus, the proposed DCSC structure can provide a low inductive PDN, suppress power and ground noises in 3D-IC systems. In addition, it is important to consider the arrangement of the TSV as well as to design a chip-PDN exhibiting a low inductive level in order to achieve a 3D PDN of low inductive impedance.
TABLE I. SUMMARY OF THE ADVANTAGES AND THE DISADVANTAGES OF THE WIREBOND-TYPES WITH ON-PACKAGE DECOUPLING CAPACITORS, ONCHIP DECOUPLING CAPACITORS EMBEDDED IN THE CHIP, AND THE PROPOSED DCSC USING TSV TECHNOLOGY. On-chip NMOS decoupling capacitor Capacitance Limited (below 0.1 [uF]) Very Good (several [pH]) Difficult High On-package decoupling capacitor (SiP) Good (up to several tens [uF]) Poor (several [nH]) Easy Low Proposed TSV-based DCSC Good (up to several tens [uF]) Good (20~50 [pH]) Medium Medium

decoupling solution methods. The most important merit of the proposed structure is its use as a 3D PDN enhancing technology for 3D-IC systems. IV. CONCLUSION

A new TSV-based DCSC structure that can remarkably overcome the limitations in a conventional decoupling capacitor solutions has been introduced. In this paper, we have carefully demonstrated the advantages of a TSV-based DCSC interconnection of decreasing the inductive and capacitive impedance of a PDN and suppressing SSN noise in a 3-D stacked chip. For demonstrating the performance of the proposed DCSC structure, a segmentation method was applied to compare the PDN impedance (Z11) property of the TSVbased DCSC with well-known conventional decoupling capacitor methods such as the on-chip NMOS capacitor and package-level decoupling capacitor. Based on the TSV technology, it was possible to implement not only low inductive impedance of 3D PDN but also high capacitance through stacking extra decoupling capacitors on the backside of a chip. Consequently, the TSV-based DCSC represents both the advantage of on-chip NMOS capacitors that have low ESL and the merit of off-chip decoupling capacitors that have high capacitance. Finally, the TSV-based DCSC is expected to be a promising power integrity (PI) solution for 3D-IC systems in which heterogeneous chips are stacked using a 3D TSV technology. ACKNOWLEDGMENT This work was supported by the IT R&D program of MKE/KEIT. [KI002134, Wafer Level 3D IC Design and Integration]. REFERENCES
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[2]

ESL Manufacturing Cost

[3]

Table compares the capacitances, ESLs, manufacturing challenges, and costs of the proposed TSV-based DCSC and two types of well-known conventional solutions. While the TSV-based DCSC shows an advantage of on-chip NMOS capacitors like low ESL (50 pH) that is a disadvantage of onpackage decoupling capacitors (>several nH), and represents a strength of on-package decoupling capacitors like high capacitance (up to several uF), which is a weak point of onchip NMOS capacitors (0.1 uF). Although there are currently some challenges regarding manufacturing and cost, this design represents an adaptable competitiveness compared to other

[4]

[5]

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