VLSI Technology Overview

Jeff Davis ECE6130 Reading (IEDM 2002 Paper plus Begin Chapter 3)

Outline
Introduction/Motivation Physical Technology Trends Clock Frequency and Power Trends Intels 90nm Logic Process Future Opportunities Questions

10000

Moores Law
1 billion transistors @ 2008 Pentium 4

1000

Number of Transistors (Millions)

100

10

Pentium II

Pentium III

1 million transistors @ 1989

486 DX

Pentium

286 0.1

386

8086 0.01 4004 0.001 1965 1970 1975 1980 1985 1990 Year 1995 2000 2005 2010 2015 8080 8008

Number of transistors doubles every 18 months!!

Cost-per-function
Historically 25% reduction every year.
1971to 2004 --- approximately 4 orders of magnitude decrease in cost in cost-per-function. Question where does this come from? Smaller Transistor size reduces the Cost-Per-Function! 1.58 x increase in transistors per die ?=? 38% reduction in cost?

ITRS Future Trends/Projections

(public.itrs.net)
# of transistors per chip (M/chip)

ITRS partially uses historical trends to PROJECT the FUTURE of the Semiconductor Industry FYI: Intel recently announced that they will reach 1 billion transistors by 2007 with 65nm technology

10000

1000

100

10

1 1995 2000 2005 Year 2010 2015

Gigascale Integration (GSI) = 1 billion transistors per chip

Technology Generation Definition

Traditionally this has been every three years (1994 Roadmap)
(Intel has new technology generation every two years)

Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com

Intel on Schedule?
The company has attained yields suitable for volume production of 90nm-based processors at Fab D1C, according to Burns. Incorporating CDO (carbon-doped oxide, a low-k dielectric material) technology, seven copper interconnect layers and flip chip packaging, the processors performance was outstanding, he added. Fabs 11X is slated to begin volume production next quarter and Fab 24 will start wafer input in 2004. Further, Intel has begun 65nm test production at its Fab D1D and Fabs 24 and 12C will follow in 2005. When Intel enters 32 and 22nm processing in 2009 and 2011, respectively, the transistors will be smaller than a chromosome, Burns noted.

DigiTimes (Sept. 22, 2003)

Zeroth Level MOSFET Model

Parallel Plate Charge Approximation electron mobility Cox Definition

Q = CV
Moving all charge out of Channel

<v>=mE
Lateral Electric Field Approx

Cox = eox/tox
Gate Stack Capacitance

Q<v>/L = I
Current Expression

E = V/L
Rough average carrier velocity

C = CoxWL

IDS= C(VGS-VT)<v>/L

<v>=m(VDS/L)

IDS= m Cox (W/L)(VGS-VT)VDS kn = process transconductance = m Cox

VLSI designer does not control

bn= device transconductance = (W/L) kn

Zeroth Order nFET Model

Drain Drain Gate Source Source IDS
Normally open switch -- assert high switch (i.e. VG = high then switch is on ) Rn= VDS/IDS= 1/[mnCox (W/L)n(VGS-VTn)]

Zeroth Order pFET Model

Drain Drain Gate
Normally closed switch -- assert low switch (i.e. VG = low then switch is on )

IDS Source

=
Source

Rp= VDS/IDS= 1/[mpCox (W/L)p(VGS-|VTp|)]

Zeroth Level MOSFET Model

Drain Gate IDS IDS
Drive Current when VGS=VDS=VDD

VGS=VDD VT <VGS<VDD

Source

VDS

Vdd

VGS< VT

Isaturation
Not include:

1 = bn (VGS - VTn )(VDS ) VDS=VGS -Vt 2

1) Channel Length Modulation 2) Mobility degradation 3) Drain Induced Barrier Lowering (DIBL) 4) etc

Drive Current Metric

Gate Length Vdd tox Source p n+ L Channel Length n+ Drain

Idrive

m n e oe r W m n e oe r W 2 = (Vdd - VTn ) (Vdd )2 2 tox L 2 tox L

Constant-Field Scaling
MOSFET device parameters Gate Oxide Thickness (tox) Channel Length (L) Transistor Width (W) Junction Depth (xj) Doping concentration (Na, Nd) Voltage (V) Scaling factor (s>1) 1/s 1/s 1/s 1/s s 1/s

I drive

m e oe r W m e oe r W 2 2 = (Vdd - Vt ) (Vdd ) 2 tox L 2 tox L

MOSFET device parameters Electric Field (E) Carrier Velocity (v = mE) Depletion Layer Width

Constant-Field Scaling Device Behavior

1 1 1/s 1/s 1 1/s 1

Scaling factor (s>1)

Gate Capacitance (C=eA/tox) Inversion layer charge density (Qi) Current (drift) Channel Resistance (R)

Constant-Field Scaling Circuit Behavior

MOSFET device parameters Circuit Delay Time(t ~ CV/I) Power Dissipation per circuit (~VI) Power-Delay Product per circuit (P x t) Circuit Density ( 1/A ) Power Density (P/A) Scaling factor (s>1) 1/s 1/s2 1/s3 s2 1

Transistor Performance Metric

dVds I ds = C g dt
t =t

CV I drive

1 dt = C g I ds t =0

Vds =Vdd

Vds =0
2

dVds

Vdd CoxWLVdd L t =C = 2 I drive C m W (V - V ) 2 m (Vdd ) ox dd t 2L

A Different View of CV/I?

Rn= VDS/IDS= 1/[mnCox (W/L)n(VGS-VTn)]

CGn= CoxWL

t = 2.3RnCGn

Cox WL L2 = 2.3 2 W m (Vdd ) Cox m (Vdd - Vt ) L

Dont forget the wires!

IBM microprocessor micrograph

Interconnections between transistors are stacked on top!! M4 M3 M2 M1

silicon wafer surface

Wires Classification: Local and Global

local wires = intra macrocell wiring

global wires = inter macrocell wiring

Impact Extra Wire Capacitance??

Cw

CV I drive

Cg

Vdd CoxWLVdd + CwVdd t = C g + Cw = I ds C m W (V - V ) 2 ox dd t 2L LC w L2 2 m (V ) + 2 C mWV dd ox dd

Global Wire Performance Metric

Wr Hr He

Rwire

r = Lwire Wr H r
Cwire =

e r e o Wr
He

Lwire

t = RwireC wire = e re o r

2 Lwire

H r He

Transistor and Interconnect Performance Metrics

Transistor only Transistor plus local wire Global long wire

L2 2 m (Vdd )

LC w L2 2 +2 m (V ) Cox mWVdd dd

er 2 Lwire H r He

Smaller = Faster!

Smaller = No Improvement!
.Or slower!!

MinimumLithographic Feature Size Projections Feature Size Projections Minimum

200

Drawn and Effective Channel Length

180 160 140 120 100 80 60 40 20 0 1999 2002

LC w L2 2 +2 m (V ) Cox mWVdd dd

DRAM 1/2 Pitch MPU ProjectGate Length Drawn Channel Length (nm) Effective Channel Length (nm)

2005

2008

2011

2014

Year

Minimum Feature Size Decreases 30% every technology generation!

Intel is ahead!

Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com

Equivalent Gate Oxide Thickness Projections

3

Effective Oxide Thickness [nm]

2.5 2 1.5 1

Ltox Cw L2 2 m (V ) + 2 e mWV dd ox dd

No known solutions Quantum Effects!

0.5 0 1999 2002 2005 2008 Year 2011 2014

Intel is ahead!

Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com

Gate Leakage on the RISE!

Intel Technology Journal Q3 1998 Thompson, Packan and Bohr

Supply Voltage Scaling

2 1.8

Supply Voltage [Volts]

1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1999 2002 2005

LC w L2 2 +2 m (V ) Cox mWVdd dd

2008 Year

2011

2014

WHY SCALE THIS?

Intel?

Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com

Drive Current per unit width (Idrive/W) (microA/micron)

ITRS Drive Current per Transistor Width Stays constant!

2500 2000 1500 1000 500 0 1999 2002 2005 2008 2011 2014 Year Drive Current Projections (microA/micron) ITRS Projections

Idrive m e oe r 1 m e oe r 1 2 = (Vdd - Vt ) (Vdd )2 W 2 tox L 2 tox L

Intel?

Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com

Why?

Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com

CV/I Metric Projections

1.2E-11 1E-11

LC w L2 2 +2 m (V ) Cox mWVdd dd

CV/I metric [secs]

8E-12 6E-12 4E-12 2E-12 0 1999 2002 2005 2008 Year 2011 2014 Transistor Only Transistor plus Local Interconnect ITRS Values

Assume Lwire = 30F!!

Global Interconnect Delay Trends for Lwire=1mm

Global RC Charging Time/ CV/I gate delay metric
160.00 140.00 120.00 100.00 80.00 60.00 40.00 20.00
Global Interconnect 1mm : W=F : Aluminum

e re o r Lwire 2 F2

0.00 1999 2002 2005 Year 2008 2011 2014

What are we going to do! Interconnects dont scale!

Material Changes will help!

Global RC Charging Time/ (CV/I) gate delay metric
160.00 140.00 120.00 100.00 80.00 60.00 40.00 20.00 0.00 1999 2002 2005 2008 2011 2014 Year
Global Interconnect 1mm : W=F: Aluminum Global Interconnect 1mm: W=F : Copper Global Interconnect 1mm: W=F : Copper Low k dielectric

Reverse-Scaling Methodology
90.00

Global RC Charging Time/ CV/I gate delay metric

Global Interconnect 1mm : W=F : Copper

80.00 70.00 60.00 50.00 40.00 30.00 20.00 10.00 0.00

Global Interconnect 1mm : W=2F : Copper Global Interconnect 1mm : W=3F : Copper

2F

3F

er 2 Lwire H r He
1999 2002 2005 Year 2008 2011 2014

Reverse Scaling works --- but at a price!! DENSITY

Repeater Insertion
L L/k
90.00

L/k

L/k

Global RC Charging Time/ CV/I gate delay metric

Global Interconnect: L= 1mm : W=F : Copper

80.00 70.00 60.00 50.00 40.00 30.00 20.00 10.00 0.00 1999 2002 2005 Year 2008 2011 2014
Global Interconnects With Repeaters: L=1mm: W=F: Cu

Current Solution: Metal Wire Stacks

12 10 8 6 4 2 0 1999 2002 2005 2008 2011 2014 Year

Number of Metal Levels

Silicon Transistors

Outline
Introduction/Motivation Physical Technology Trends Clock Frequency and Power Trends Intels 90nm Logic Process Future Opportunities Questions

Trends in Clock Frequency

Doubles every technology generation

Intel Technology Journal Q3 1998 Thompson, Packan and Bohr

What is driving Increase in Clock Frequency?

Circuit Delay Time(t ~ CV/I) 1/s

1.42x performance increase every generation with device performance ???? 2.0x increase in clock frequency

Where is extra performance coming from?

Average # of gate delays per clock cycle

60 50

Reduction in number gates in Critical Path

Intel
To maintain 2x increase in frequency 1) reduced number of gates in one clock period (more pipelined) 2) employing advance circuit techniques

40 30 20 10 0
1985 1990 1995

Alpha

2000

2005

2010

Year
*Vivek De and Shekhar Borkar (INTEL), "Technology and Design Challenges for Low Power and High Performance," 1999 International Symposium on Low Power Electronics and Design, San Diego, CA, Aug. 16-17 1999, pp. 163-168. *Paul Gronowski, et al (Compact Digital), "High Performance Microprocessor Design," IEEE Journal of Solid-State Circuits, Vol. 33, No. 5, May 1998, pp. 676-686.

Trends in Power Dissipation

~ 1.8x increase per generation

Intel Technology Journal Q3 1998 Thompson, Packan, and Bohr

Dynamic vs. Static Power Trends

Intel Technology Journal Q3 1998 Thompson, Packan, and Bohr

Why is Static Power Increasing?

Intel Technology Journal Q3 1998 Thompson and Bohr

Why is Static Power Increasing?

Intel Technology Journal Q3 1998 Thompson, Packan, and Bohr

Outline
Introduction/Motivation Physical Technology Trends Clock Frequency and Power Trends Intels 90nm Logic Process Future Opportunities Question

Intel State of the Art

90nm Technology with 50nm gate lengths 1.2nm gate oxides Strained silicon used to increase mobility

Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com

Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com

After K, Rim, et al (IBM),Mobility Enhancement in Strained Si NMOSFETs with Hf02 Gate Dielectrics, 2002 Symposium on VLSI Technology Digest of Technical Papers, Kyoto, Japan, pp. 12-13.

Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com

Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com

Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com

Mark Bohr, Intel Fellow, 2002 Press Release www.intel.com

Outline
Introduction/Motivation Physical Technology Trends Clock Frequency and Power Trends Intels 90nm Logic Process Future Opportunities Questions

INTELs TRANSISTOR OF THE FUTURE!!!!

THE TERAHERTZ TRANSISTOR!! AKA Fully-Depleted SOI Device!

Kevin Teixeira, Online Intel Technological Background Report, Intels Terahertz Transistor Architecture, www.intel.com/research/silicon.

Kevin Teixeira, Online Intel Technological Background Report, Intels Terahertz Transistor Architecture, www.intel.com/research/silicon.

Other Choices???

James Hutchby, et al, Extending the Road Beyond CMOS, IEEE Circuits and Devices Magazine, March 2002, pp. 28-41.

Exotic Choices??

James Hutchby, et al, Extending the Road Beyond CMOS, IEEE Circuits and Devices Magazine, March 2002, pp. 28-41.

Outline
Introduction/Motivation Physical Technology Trends Clock Frequency and Power Trends Intels 90nm Logic Process Future Opportunities Questions