Itrs 2008

ORTC INDEX
2007 ITRS Chapters
2008 FOCUS ITWG TABLES: System Drivers, Design, Test & Test Equipment, RF and AMS for Wireless, and Process Integration (PIDS)
Link to file for Emerging Research Devices (ERD), Emerging Research Materials (ERM), Front-end Proc Lithography, Interconnect, Factory Integration, and Assembly & Packaging
Link to file for Environment, Safety, & Health (ESH), Yield Enhancement, Metrology, Modeling & Simulat Link to the 2008 Update Overview Link to the 2007 ITRS chapters
System Drivers
TEXT
Table SYSD1
UPDATED Table SYSD2
Table SYSD3 Table SYSD4
Design
TEXT TEXT TEXT TEXT TEXT
TEXT TEXT TEXT
Table DESN1 ADDED Table DESN X UPDATED Table DESN2 UPDATED Table DESN3 Table DESN4 Table DESN5 Table DESN6 Table DESN7 Table DESN8 Table DESN9 Table DESN10 Table DESN11 Table DESN12
Test and Test Equipment

TEXT
Table TST1
UPDATED Table TST2
TEXT
Table TST3 Table TST4 Table TST5 UPDATED Table TST6 UPDATED Table TST7 UPDATED Table TST8 Table TST9 Table TST10 Table TST11 Table TST12
TEXT
Table TST13 Table TST14 Table TST15
RF and AMS for Wireless

UPDATED Table RFAMS1 UPDATED Table RFAMS2 UPDATED Table RFAMS3 UPDATED Table RFAMS4 UPDATED Table RFAMS5
Table RFAMS6 Table RFAMS7 Table RFAMS8
Process Integration, Devices, and Structures (PIDS)

TEXT
Table PIDS1
UPDATED Table PIDS2 UPDATED Table PIDS3a and b UPDATED Table PIDS3c and d
TEXT
Table PIDS4 UPDATED Table PIDS5 Table PIDS6 Table PIDS7
TO ACCESS THESE TABLES LISTED BELOW, USE THE LINKS AT THE TOP OF THIS PAGE Emerging Research Devices Please refer to the ERD summary in the 2008 Update Overview Emerging Research Materials Please refer to the ERM summary in the 2008 Update Overview Front End Processes
TEXT UPDATED UPDATED UPDATED UPDATED UPDATED UPDATED UPDATED UPDATED
TEXT
TEXT
Table FEP1 Table FEP2 Table FEP3 Table FEP4a Table FEP4b Table FEP5 Table FEP6 Table FEP7 Table FEP8 Table FEP9
Lithography
TEXT TEXT UPDATED UPDATED UPDATED UPDATED UPDATED
Table LITH1 Table LITH2 Table LITH3 Table LITH4AB Table LITH4C Table LITH5AB Table LITH5CD Table LITH5EF Table LITH6
Interconnect
TEXT
Table INTC1
UPDATED Table INTC2 UPDATED Table INTC3
TEXT
Table INTC4 Table INTC5 UPDATED Table INTC6 Table INTC7
Factory Integration
TEXT TEXT
TEXT TEXT
Table FAC1 Table FAC2 Table FAC3 UPDATED Table FAC4 Table FAC5 UPDATED Table FAC6 Table FAC7 Table FAC8 Table FAC9
Assembly and Packaging

TEXT UPDATED UPDATED ADD UPDATED UPDATED UPDATED
TEXT UPDATED
Table AP1 Table AP2 Table AP3 Table AP4 Table AP4B Table AP5A Table AP5B Table AP5C Table AP6 Table AP7 Table AP8 Table AP9
TEXT
UPDATED Table AP10 UPDATED Table AP11
TEXT TEXT TEXT TEXT TEXT TEXT TEXT TEXT UPDATED UPDATED UPDATED UPDATED
Table AP12a and b Table AP12c Table AP13 Table AP14 Table AP15 Table AP16 Table AP17 Table AP18 Table AP19 Table AP20 Table AP21
TO ACCESS THESE TABLES LISTED BELOW, USE THE LINKS AT THE TOP OF THIS PAGE CROSSCUT WORKING GROUP TABLES Environment, Safety, and Health
TEXT
Table ESH1
UPDATED Table ESH2a UPDATED Table ESH2b
Table ESH3 Table ESH4a Table ESH4b UPDATED Table ESH5 Table ESH6
Yield Enhancement
TEXT TEXT UPDATED UPDATED UPDATED UPDATED
Table YE1 Table YE2 Table YE3 Table YE4 Table YE5 Table YE6
UPDATED Table YE7 UPDATED Table YE8 UPDATED Table YE9
Metrology
TEXT
Table MET1 Table MET2 Table MET3
Table MET4a and b Table MET4c and d UPDATED Table MET5a Table MET5b Table MET6
Modeling and Simulation

TEXT UPDATED Table MS1 UPDATED Table MS2a UPDATED Table MS2b UPDATED Table MS3
S ITWG TABLES: rs, Design, Test & Test Equipment, RF and AMS for Wireless, and Process Integration, Devices, & Structures
Emerging Research Devices (ERD), Emerging Research Materials (ERM), Front-end Processes (FEP), nterconnect, Factory Integration, and Assembly & Packaging
Environment, Safety, & Health (ESH), Yield Enhancement, Metrology, Modeling & Simulation 08 Update Overview 07 ITRS chapters
Major Product Market Segments and Impact on System Drivers SOC Consumer Driver Design Productivity Trends Projected Mixed-Signal Figures of Merit for Four Circuit Types Embedded Memory Requirements
Overall Design Technology Challenges Description of Improvement System-Level Design Requirements Correspondence Between System-Level Design Requirements and Solutions Logical/Circuit/Physical Design Technology Requirements Correspondence Between Logical/Circuit/Physical Requirements and Solutions Design Verification Requirements Correspondence Between Design Verification Requirements and Solutions Design for Test Technology Requirements Design for Manufacturability Technology Requirements Correspondence Between Design for Manufacturability Requirements and Solutions Near-term Breakthroughs in Design Technology for AMS Design Technology Improvements and Impact on Designer Productivity
t Equipment Summary of Key Test Drivers, Challenges, and Opportunities Multi-site Test for Product Segments System on Chip Test Requirements Logic Test Requirements Vector Multipliers Memory Test Requirements Mixed-signal Test Requirements RF Test Requirements Burn-in Requirements Test Handler and Prober Difficult Challenges Prober Requirements Handler Requirements
Probing Difficult Challenges Wafer Probe Technology Requirements Test Socket Technology Requirements
S for Wireless RF and Analog Mixed-Signal CMOS Technology Requirements RF and Analog Mixed-Signal Bipolar Technology Requirements On-Chip Passives Technology Requirements Embedded Passives Technology Requirements Power Amplifier Technology Requirements Base Station Devices Technology Requirements Millimeter Wave 10 GHz100 GHz Technology Requirements RF and Analog Mixed-Signal RFMEMS
gration, Devices, and Structures (PIDS) Process Integration Difficult Challenges High-performance Logic Technology Requirements Low Standby Power Technology Requirements Low Operating Power Technology Requirements DRAM Technology Requirements Non-volatile Memory Technology Requirements Reliability Difficult Challenges Reliability Technology Requirements
THESE TABLES LISTED BELOW, USE THE LINKS AT THE TOP OF THIS PAGE
esearch Devices o the ERD summary in the 2008 Update Overview
esearch Materials o the ERM summary in the 2008 Update Overview
Front End Processes Difficult Challenges Starting Materials Technology RequirementsNear and Long-term Years Front End Surface Preparation Technology RequirementsNear and Long-term Years Thermal, Thin Film, Doping and Etching Technology RequirementsNear-term Years Thermal, Thin Film, Doping and Etching Technology RequirementsLong-term Years DRAM Stacked Capacitor Technology RequirementsNear and Long-term Years DRAM Trench Capacitor Technology RequirementsNear and Long-term Years FLASH Non-volatile Memory Technology Requirements Phase Change Memory (PCM) Technology RequirementsNear and Long-term Years FeRAM Technology RequirementsNear and Long-term Years
Various Techniques for Achieving Desired CD Control and Overlay with Optical Projection Lithography Lithography Difficult Challenges Lithography Technology RequirementsNear and Long-term Years Resist RequirementsNear and Long-term Years Resist Sensitivities Optical Mask RequirementsNear and Long-term Years EUVL Mask RequirementsNear and Long-term Years Imprint Template RequirementsNear and Long-term Years Maskless Technology RequirementsNear and Long-term Years
Interconnect Difficult Challenges MPU Interconnect Technology RequirementsNear and Long-term Years DRAM Interconnect Technology RequirementsNear and Long-term Years Interconnect Surface Preparation Technology RequirementsNear and Long-term Years Options for Interconnects Beyond the Metal/Dielectric System High Density Through Silicon via Draft Specification M inimum Density of Metallic SWCNTs Needed to Exceed Minimum Cu Wire Conductivity
Factory Integration Difficult ChallengesNear and Long-term Years Key Focus Areas and Issues for FI Functional Areas Beyond 2007 Factory Operations Technology RequirementsNear and Long-term Years Production Equipment Technology RequirementsNear and Long-term Years Material Handling Systems Technology RequirementsNear and Long-term Years Factory Information and Control Systems Technology RequirementsNear and Long-term Years Facilities Technology RequirementsNear and Long-term Years Crosscut Issues Relating to Factory Integration List of Next Wafer Size Challenges
d Packaging Assembly and Packaging Difficult Challenges Single-chip Packages Technology RequirementsNear and Long-term Years Chip-to-package Substrate Technology RequirementsNear and Long-term Years Substrate to Board PitchNear and Long-term Years Warpage at Peak Temperature Package SubstratesNear and Long-term Years Polymer Package Substrate Design ParametersNear and Long-term Years Cost Performance Glass-ceramic Substrates (high end FCBGA) Wafer Level PackagingNear and Long-term Years Key Technical Parameters for Stacked Architectures Using TSV Comparison of SoC and SiP Architecture Package Level System Integration
Processes for SiP System in Package RequirementsNear and Long-term Years Thinned Silicon Wafer Thickness 200 mm/300 mmNear and Long-term Years Challenges and Potential Solutions in Thinning Si Wafers SiP Failure Modes Some Common Optoelectronic Packages and Their Applications Optical Communications and Interconnect Optoelectronic Packaging Challenges and Potential Solutions MEMS Packaging Methods MEMS Packaging Examples Materials Challenges Package Substrate Physical Properties Automotive Operating Environment Specifications THESE TABLES LISTED BELOW, USE THE LINKS AT THE TOP OF THIS PAGE
WORKING GROUP TABLES
, Safety, and Health ESH Difficult Challenges ESH Intrinsic RequirementsNear-term Years ESH Intrinsic RequirementsLong-term Years Chemicals and Materials Management Technology Requirements Process and Equipment Management Technology RequirementsNear-term Years Process and Equipment Management Technology RequirementsLong-term Years Facilities Energy and Water Optimization Technology Requirements Sustainability and Product Stewardship Technology Requirements
Definitions for the Different Interface Points Yield Enhancement Difficult Challenges Defect Budget Technology Requirement Assumptions Yield Model and Defect Budget MPU Technology Requirements Yield Model and Defect Budget DRAM/Flash Technology Requirements Defect Inspection on Patterned Wafer Technology Requirements Defect Inspection on Unpatterned Wafers: Macro, and Bevel Inspection Technology Requirements Defect Review and Automated Defect Classification Technology Requirements Technology Requirements for Wafer Environmental Contamination Control
Metrology Difficult Challenges Metrology Technology Requirements Lithography Metrology (Wafer) Technology Requirements
Lithography Metrology (Mask) Technology Requirements: Optical Lithography Metrology (Mask) Technology Requirements: EUV Front End Processes Metrology Technology RequirementsNear-term Years Front End Processes Metrology Technology RequirementsLong-term Years Interconnect Metrology Technology RequirementsNear and Long-term Years
d Simulation Modeling and Simulation Difficult Challenges Modeling and Simulation Technology Requirements: CapabilitiesNear-term Years Modeling and Simulation Technology Requirements: CapabilitiesLong-term Years Modeling and Simulation Technology Requirements: AccuracyNear-term Years
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n Lithography
2008 INDEX 2007 ITRS Chapters
Overall Roadmap Technology Characteristics [ORTC]

UPDATED UPDATED UPDATED UPDATED UPDATED UPDATED UPDATED UPDATED UPDATED UPDATED UPDATED UPDATED UPDATED
Trends Graphic Table 1a&b Table 1c&d Table 1e&f Table 1g&h Table 1i&j Table 2a&b Table 3a&b Table 4a&b Table 4c&d Table 5a&b Table 6a&b Table 7a&b
Roadmap Technology Characteristics [ORTC]

Product Generations and Chip Size Model Technology Trend Targets DRAM and Flash Production Product Generations and Chip Size Model DRAM Introduction Product Generations and Chip Size Model MPU (High-volume Microprocessor) Cost-Performance Product Generations and Chip Size Model High-Performance MPU and ASIC Product Generations and Chip Size Model Lithographic-Field and Wafer Size Trends Performance of Packaged Chips: Number of Pads and Pins Performance and Package Chips: Pads, Cost Performance and Package Chips: Frequency On-chip Wiring Levels Electrical Defects [**] Power Supply and Power Dissipation Cost
2008 Update Trend Graphic, including ITRS 7/15 meetings Final Litho Printed Ga
ngs Final Litho Printed Gate Length Proposal
Table 1a&bProduct Generations and Chip Size Model Technology Trend Targets
Year of Production Flash Pitch (nm) (un-contacted Poly)(f) DRAM Pitch (nm) (contacted) DRAM Pitch (nm) (contacted) MPU/ASIC Metal 1 (M1) Pitch (nm) MPU Printed Gate Length (nm) MPU Printed Gate Length (GLpr) (nm) MPU Physical Gate Length (GLph) (nm) MPU Physical Gate Length (GLph) (nm) ASIC/Low Operating Power Printed Gate Length (nm) ASIC/Low Operating Power Printed Gate Length (nm) ASIC/Low Operating Power Physical Gate Length (nm) ASIC/Low Operating Power Physical Gate Length (nm) 2007 54 65 68 68 42 54 25 32 54 64 32 38 2008 45 57 59 59 38 47 23 29 48 54 28 32 2009 40 50 52 52 34 41 20 27 42 47 25 29 2010 36 45 45 45 30 35 18 24 38 41 23 27 2011 32 40 40 40 27 31 16 22 34 35 20 24 2012 28 36 36 36 24 28 14 20 30 31 18 22 2013 25 32 32 32 21 25 13 18 27 25 16 18 2014 23 28 28 28 19 22 11 17 24 22 14 17
2015 20 25 25 25 17 20 10 15 21 20 13 15
2016 17.9 23 22.5 22.5 15 17.7 8.9 14.0 19 17.7 11 14.0
2017 15.9 20 20.0 20.0 13 15.7 8.0 12.8 17 15.7 10 12.8
2018 14.2 18 17.9 17.9 12 14.0 7.1 11.7 15 14.0 8.9 11.7
2019 12.6 16 15.9 15.9 11 12.5 6.3 10.7 13 12.5 8.0 10.7
2020 11.3 14 14.2 14.2 9.5 11.1 5.6 9.7 12 11.1 7.1 9.7
2021 10.0 13 12.6 12.6 8.4 9.9 5.0 8.9 11 9.9 6.3 8.9
2022 8.9 11 11.3 11.3 7.5 8.8 4.5 8.1 9.5 8.8 5.6 8.1
Table 1c&d DRAM and Flash Production Product Generations and Chip Size Model
Year of Production DRAM Pitch (nm) (contacted) MPU/ASIC Metal 1 (M1) Pitch (nm) MPU Physical Gate Length (nm) 2007 68 68 32 6
2
2008 59 59 29 6 0.021 56.08% 2G 2.15 81 2.65
2009 52 52 27 6 0.016 56.08% 2G 2.15 61 3.50
2010 45 45 24 6 0.012 56.08% 4G 4.29 93 4.62
2011 40 40 22 6 0.0096 56.08% 4G 4.29 74 5.82
2012 36 36 20 6 0.0077 56.08% 4G 4.29 59 7.33
2013 32 32 18 6 0.0061 56.08% 8G 8.59 93 9.23
2014 28 28 17 6 0.0048 56.08% 8G 8.59 74 11.63
2015 25 25 15 6 0.0038 56.08% 8G 8.59 59 14.65
DRAM Product Table

Cell area factor [a] Cell area [Ca = af2] (um ) Cell array area at production (% of chip size) Generation at production Functions per chip (Gbits) Chip size at production (mm ) Gbits/cm2 at production
2
0.028 56.08% 2G 2.15 107 2.01
Flash Product Table

Flash Pitch (nm) (un-contacted Poly)(f) Cell area factor [a] Cell area [Ca = af ] (um ) Cell array area at production (% of chip size) Generation at production SLC Generation at production MLC [2 bits/cell] Generation at production MLC [4 bits/cell] Functions per chip (Gbits) SLC Functions per chip (Gbits) MLC [2 bits/cell] Functions per chip (Gbits) MLC [4 bits/cell] Chip size at production (mm ) SLC Chip size at production (mm2) MLC [2 bits/cell & 4 bits/cell] Bits /cm
2 2 2 2
53.5 4 0.0115 68.35% 8G 16G 32G 8.59 17.18 34.36 143.96 143.96 5.97E+09 1.19E+10
45.0 4 0.0081 68.35% 8G 16G 32G 8.59 17.18 34.36 101.80 101.80 8.44E+09 1.69E+10
40.1 4 0.0064 68.35% 8G 16G 32G 8.59 17.18 34.36 80.80 80.80 1.06E+10 2.13E+10
35.7 4 0.0051 68.35% 16G 32G 64G 17.18 34.36 68.72 128.26 128.26 1.34E+10 2.68E+10
31.8 4 0.0041 68.35% 16G 32G 64G 17.18 34.36 68.72 101.80 101.80 1.69E+10 3.38E+10
28.3 4 0.0032 68.35% 16G 32G 64G 17.18 34.36 68.72 80.80 80.80 2.13E+10 4.25E+10
25.3 4 0.0026 68.35% 32G 64G 128G 34.36 68.72 137.44 128.26 128.26 2.68E+10 5.36E+10
22.5 4 0.0020 68.35% 32G 64G 128G 34.36 68.72 137.44 101.80 101.80 3.38E+10 6.75E+10
20.0 4 0.0016 68.35% 32G 64G 128G 34.36 68.72 137.44 80.80 80.80 4.25E+10 8.51E+10
at production SLC
Bits/cm2 at production MLC [2 bits/cell]
2016 22.5 22.5 14.0 6 0.0030 56.08% 16G 17.18 93 18.46
2017 20.0 20.0 12.8 6 0.0024 56.08% 16G 17.18 74 23.26
2018 17.9 17.9 11.7 6 0.0019 56.08% 16G 17.18 59 29.31
2019 15.9 15.9 10.7 6 0.0015 56.08% 32G 34.36 93 36.93
2020 14.2 14.2 9.7 6 0.0012 56.08% 32G 34.36 74 46.52
2021 12.6 12.6 8.9 6 0.00096 56.08% 32G 34.36 59 58.61
2022 11.3 11.3 8.1 6 0.00076 56.08% 64G 68.72 93 73.85
17.9 4 0.0013 68.35% 64G 128G 256G 68.72 137.44 274.88 128.26 128.26 5.36E+10 1.07E+11
15.9 4 0.0010 68.35% 64G 128G 256G 68.72 137.44 274.88 101.80 101.80 6.75E+10 1.35E+11
14.2 4 0.00080 68.35% 64G 128G 256G 68.72 137.44 274.88 80.80 80.80 8.51E+10 1.70E+11
12.6 4 0.00064 68.35% 128G 256G 512G 137.44 274.88 549.76 128.26 128.26 1.07E+11 2.14E+11
11.3 4 0.00051 68.35% 128G 256G 512G 137.44 274.88 549.76 101.80 101.80 1.35E+11 2.70E+11
10.0 4 0.00040 68.35% 128G 256G 512G 137.44 274.88 549.76 80.80 80.80 1.70E+11 3.40E+11
8.9 4 0.00032 68.35% 256G 512G 1024G 274.88 549.76 1099.51 128.26 128.26 2.14E+11 4.29E+11
Table 1e&f DRAM Introduction Product Generations and Chip Size Model
Year of Production DRAM Pitch (nm) (contacted) MPU/ASIC Metal 1 (M1) Pitch (nm) MPU Physical Gate Length (nm) Cell area factor [a] Cell area [Ca = af ] (um ) Cell array area at introduction (% of chip size) Generation at introduction Functions per chip (Gbits) Chip size at introduction (mm )
2 2 2
2007 68 68 32 6 0.028 73.52% 16G 17.18 652
2008 59 59 29 6 0.021 73.76% 16G 17.18 493
2009 52 52 27 6 0.016 73.97% 16G 34.36 745
2010 45 45 24 6 0.012 74.16% 32G 34.36 563
2011 40 40 22 6 0.0096 74.30% 32G 34.36 446
2012 36 36 20 6 0.0077 74.47% 32G 68.72 706
2013 32 32 18 6 0.0061 74.61% 64G 68.72 560
2014 28 28 17 6 0.0048 74.70% 64G 68.72 444
2015 25 25 15 6 0.0038 74.83% 64G 68.72 351
2016 22.5 22.5 14.0 6 0.0030 74.93% 128G 137.44 557
2017 20.0 20.0 12.8 6 0.0024 75.00% 128G 137.44 442
2018 17.9 17.9 11.7 6 0.0019 75.09% 128G 137.44 350
2019 15.9 15.9 10.7 6 0.0015 75.18% 256G 274.88 555
2020 14.2 14.2 9.7 6 0.0012 75.27% 256G 274.88 440
2021 12.6 12.6 8.9 6 0.00096 75.36% 256G 274.88 349
2022 11.3 11.3 8.1 6 0.00076 75.45% 512G 549.76 553
Table 1g&h MPU (High-volume Microprocessor) Cost-Performance Product Generations and Chip Size Model
Year of Production DRAM Pitch (nm) (contacted) MPU/ASIC Metal 1 (M1) Pitch (nm) MPU Physical Gate Length (nm) SRAM Cell (6-transistor) Area factor ++ Logic Gate (4-transistor) Area factor ++ SRAM Cell (6-transistor) Area efficiency ++ Logic Gate (4-transistor) Area efficiency ++ SRAM Cell (6-transistor) Area (um2)++ SRAM Cell (6-transistor) Area w/overhead (um2)++ Logic Gate (4-transistor) Area (um2) ++ Logic Gate (4-transistor) Area w/overhead (um2) ++ Transistor density SRAM (Mtransistors/cm ) Transistor density logic (Mtransistors/cm ) Generation at introduction * Functions per chip at introduction (million transistors [Mtransistors]) Chip size at introduction (mm ) Cost performance MPU (Mtransistors/cm (including on-chip SRAM)
2 2 2 2
2007 68 68 32 97.5 279 0.63 0.5 0.45 0.73 1.3 2.6 827 154 p10c 773 280 at introduction) 276 p07c 386 140
2
2008 59 59 29 100.7 292 0.63 0.5 0.35 0.57 1.0 2.1 1,057 194 p10c 773 222 348 p07c 386 111 348
2009 52 52 27 104.1 306 0.63 0.5 0.28 0.45 0.82 1.6 1,348 245 p13c 1546 353 438 p07c 386 88 438
2010 45 45 24 107.8 320 0.63 0.5 0.22 0.35 0.65 1.3 1,718 309 p13c 1546 280 552 p10c 773 140 552
2011 40 40 22 106.7 320 0.63 0.5 0.17 0.27 0.51 1.0 2,187 389 p13c 1546 222 696 p10c 773 111 696
2012 36 36 20 105.7 320 0.63 0.5 0.13 0.22 0.41 0.82 2,781 490 p16c 3092 353 876 p10c 773 88 876
2013 32 32 18 104.8 320 0.63 0.5 0.11 0.17 0.32 0.65 3,532 617 p16c 3092 280 1104 p13c 1546 140 1104
2014 28 28 17 104.1 320 0.63 0.5 0.084 0.13 0.26 0.51 4,484 778 p16c 3092 222 1391 p13c 1546 111 1391
2015 25 25 15 103.4 320 0.63 0.5 0.066 0.11 0.20 0.41 5,687 980 p19c 6184 353 1753 p13c 1546 88 1753
Generation at production * Functions per chip at production (million transistors [Mtransistors]) Chip size at production (mm ) Cost performance MPU (Mtransistors/cm including on-chip SRAM) at production,
2
276
2016 22.5 22.5 14.0 102.8 320 0.63 0.5 0.052 0.083 0.16 0.32 7,208 1,235 p19c 6184 280 2209 p16c 3092 140 2209
2017 20.0 20.0 12.8 102.2 320 0.63 0.5 0.041 0.066 0.13 0.26 9,130 1,555 p19c 6184 222 2783 p16c 3092 111 2783
2018 17.9 17.9 11.7 101.7 320 0.63 0.5 0.032 0.052 0.10 0.20 11,558 1,960 p22c 12368 353 3506 p16c 3092 88 3506
2019 15.9 15.9 10.7 101.3 320 0.63 0.5 0.026 0.041 0.081 0.16 14,625 2,469 p22c 12368 280 4417 p19c 6184 140 4417
2020 14.2 14.2 9.7 100.9 320 0.63 0.5 0.020 0.032 0.064 0.13 18,497 3,111 p22c 12368 222 5565 p19c 6184 111 5565
2021 12.6 12.6 8.9 100.5 320 0.63 0.5 0.016 0.026 0.051 0.10 23,394 3,920 p25c 24736 353 7012 p19c 6184 88 7012
2022 11.3 11.3 8.1 100.1 320 0.63 0.5 0.01 0.020 0.040 0.08 29,588 4,938 p25c 24736 280 8834 p22c 12368 140 8834
Table 1i&j High-Performance MPU and ASIC Product Generations and Chip Size Model
Year of Production DRAM Pitch (nm) (contacted) MPU/ASIC Metal 1 (M1) Pitch (nm) MPU Physical Gate Length (nm) Logic (Low-volume Microprocessor) High-performance Generation at Introduction Functions per chip at introduction (million transistors) Chip size at introduction (mm ) Generation at production ** Functions per chip at production (million transistors) Chip size at production (mm ) High-performance MPU Mtransistors/cm production (including on-chip SRAM) ASIC ASIC usable Mtransistors/cm
2 2 2 2
2007 68 68 32
2008 59 59 29
2009 52 52 27
2010 45 45 24
2011 40 40 22
2012 36 36 20
2013 32 32 18
2014 28 28 17
2015 25 25 15
p10h 2212 620 p07h 1106 310 at introduction and 357 357 858 3,061
p10h 2212 492 p07h 1106 246 449 449 858 3,857
p13h 4424 391 p07h 1106 195 566 566 858 4,859
p13h 4424 620 p10h 2212 310 714 714 858 6,122
p13h 4424 492 p10h 2212 246 899 899 858 7,713
p16h 8848 391 p10h 2212 195 1133 1133 858 9,718
p16h 8848 620 p13h 4424 310 1427 1427 858 12,244
p16h 8848 492 p13h 4424 246 1798 1798 858 15,427
p19h 17696 391 p13h 4424 195 2265 2265 858 19,436
(auto layout)
2
ASIC max chip size at production (mm ) (maximum lithographic field size) ASIC maximum functions per chip at production (Mtransistors/chip) (fit in maximum lithographic field size)
2016 22.5 22.5 14.0
2017 20.0 20.0 12.8
2018 17.9 17.9 11.7
2019 15.9 15.9 10.7
2020 14.2 14.2 9.7
2021 12.6 12.6 8.9
2022 11.3 11.3 8.1
p19h 17696 620 p16h 8848 310 2854 2854 858 24,488
p19h 17696 492 p16h 8848 246 3596 3596 858 30,853
p22h 35391 391 p16h 8848 195 4531 4531 858 38,873
p22h 35391 620 p19h 17696 310 5708 5708 858 48,977
p22h 35391 492 p19h 17696 246 7192 7192 858 61,707
p25h 70782 391 p19h 17696 195 9061 9061 858 77,746
p25h 70782 620 p22h 35391 310 11416 11416 1716 195,906
Table 2a&b Lithographic-Field and Wafer Size Trends

Year of Production DRAM Pitch (nm) (contacted) Flash Pitch (nm) (un-contacted Poly)(f) MPU/ASIC Metal 1 (M1) Pitch (nm) MPU Physical Gate Length (nm) Lithography Field Size Maximum Lithography Field Sizearea (mm ) Maximum Lithography Field Sizelength (mm) Maximum Lithography Field Sizewidth (mm) Maximum Substrate Diameter (mm)High-volume Production (>20K parts wafer starts per month) Bulk or epitaxial or SOI wafer
2
2007 68 54 68 32
2008 59 45 59 29
2009 52 40 52 27
2010 45 36 45 24
2011 40 32 40 22
2012 36 28 36 20
2013 32 25 32 18
2014 28 22 28 17
2015 25 20 25 15
858 33 26
858 33 26
858 33 26
858 33 26
858 33 26
858 33 26
858 33 26
858 33 26
858 33 26
300
300
300
300
300
450
450
450
450
2016 22.5 18 22.5 14.0
2017 20.0 16 20.0 12.8
2018 17.9 14 17.9 11.7
2019 15.9 13 15.9 10.7
2020 14.2 11 14.2 9.7
2021 12.6 10 12.6 8.9
2022 11.3 9 11.3 8.1
858 33 26
858 33 26
858 33 26
858 33 26
858 33 26
858 33 26
858 33 26
450
450
450
450
450
450
450
Table 3a&bPerformance of Packaged Chips: Number of Pads and Pins

Year of Production DRAM Pitch (nm) (contacted) Flash Pitch (nm) (un-contacted Poly)(f) MPU/ASIC Metal 1 (M1) Pitch (nm) MPU Physical Gate Length (nm) Number of Chip I/Os (Number of Total Chip Pads)Maximum Total padsMPU unchanged Signal I/OMPU (% of total pads) Power and ground padsMPU (% of total pads) Total padsASIC High Performance unchanged Signal I/O padsASIC high-performance (% of total pads) Power and ground padsASIC high-performance (% of total pads) Number of Total Package PinsMaximum [1] Microprocessor/controller, cost-performance Microprocessor/controller, high-performance ASIC (high-performance) 6002140 4000 4000 6002400 4400 4400 6602801 4620 4620 6602783 4851 4851 720- 3061 5094 5094 7203367 5348 5348 8003704 5616 5616 800-4075 5896 5896 8804482 6191 6191 3,072 33.3% 66.7% 4,400 50.0% 50.0% 3,072 33.3% 66.7% 4,400 50.0% 50.0% 3,072 33.3% 66.7% 4,600 50.0% 50.0% 3,072 33.3% 66.7% 4,800 50.0% 50.0% 3,072 33.3% 66.7% 4,800 50.0% 50.0% 3,072 33.3% 66.7% 5,000 50.0% 50.0% 3,072 33.3% 66.7% 5,400 50.0% 50.0% 3,072 33.3% 66.7% 5,400 50.0% 50.0% 3,072 33.3% 66.7% 5,600 50.0% 50.0% 2007 68 54 68 32 2008 59 45 59 29 2009 52 40 52 27 2010 45 36 45 24 2011 40 32 40 22 2012 36 28 36 20 2013 32 25 32 18 2014 28 22 28 17 2015 25 20 25 15
2016 22.5 18 22.5 14.0
2017 20.0 16 20.0 12.8
2018 17.9 14 17.9 11.7
2019 15.9 13 15.9 10.7
2020 14.2 11 14.2 9.7
2021 12.6 10 12.6 8.9
2022 11.3 9 11.3 8.1
3,072 33.3% 66.7% 6,000 50.0% 50.0%
3,072 33.3% 66.7% 6,000 50.0% 50.0%
3,072 33.3% 66.7% 6,200 50.0% 50.0%
3,072 33.3% 66.7% 6,200 50.0% 50.0%
3,072 33.3% 66.7% 6,200 50.0% 50.0%
3,072 33.3% 66.7% 6,840 50.0% 50.0%
3,072 33.3% 66.7% 6,840 50.0% 50.0%
8804930 6501 6501
960-5423 6826 6826
9605966 7167 7167
1050-6562 7525 7525
1050 - 7218 7902 7902
1155-7940 8297 8297
1155-8337 8712 8712
Table 4a&b Performance and Package Chips: Pads, Cost

Year of Production DRAM Pitch (nm) (contacted) Flash Pitch (nm) (un-contacted Poly)(f) MPU/ASIC Metal 1 (M1) Pitch (nm) MPU Physical Gate Length (nm) Chip Pad Pitch (micron) Pad pitchball bond Pad pitch Wedge bond Pad Pitch Area array flip-chip (cost-performance, highperformance) Pad Pitch 2-row staggered-pitch (micron) Pad Pitch Three-tier-pitch pitch (micron) Cost-Per-Pin Package cost (cents/pin) (Cost per Pin Minimum for Contract Assembly Cost-performance) minimummaximum Package cost (cents/pin) (Low-cost, hand-held and memory) minimummaximum 30 25 130 55 60 30 25 130 50 60 25 20 130 45 60 25 20 130 45 55 25 20 120 45 55 20 20 110 40 50 20 20 110 40 45 20 20 100 40 45 20 20 100 40 45 2007 68 54 68 32 2008 59 45 59 29 2009 52 40 52 27 2010 45 36 45 24 2011 40 32 40 22 2012 36 28 36 20 2013 32 25 32 18 2014 28 22 28 17 2015 25 20 25 15
.69-1.19 .27-.50
.66-1.13 .25-.48
.63-1.70 .24-.46
.60-1.20 .23-.44
.57-.97 .22-.42
.54-.92 .21-.40
.51-.87 .20-.38
.48 - .83 .20-.36
.46 - .79 .20 -.34
2016 22.5 18 22.5 14.0 20 20 95 35 45
2017 20.0 16 20.0 12.8 20 20 95 35 45
2018 17.9 14 17.9 11.7 20 20 90 35 45
2019 15.9 13 15.9 10.7 20 20 90 35 45
2020 14.2 11 14.2 9.7 20 20 85 35 45
2021 12.6 10 12.6 8.9 20 20 85 35 45
2022 11.3 9 11.3 8.1 20 20 80 35 45
.44 - .75 .20-.32
.42 - .71 .20-.30
.39 - .68 .20-.29
.37 - .64 .20-.27
.35 - .61 .20-.26
.33-.58 .19-.25
0.32-0.55 .19-.25
Table 4c&d Performance and Package Chips: Frequency On-chip Wiring Levels
Year of Production DRAM Pitch (nm) (contacted) Flash Pitch (nm) (un-contacted Poly)(f) MPU/ASIC Metal 1 (M1) Pitch (nm) MPU Physical Gate Length (nm) Chip Frequency (MHz) On-chip local clock [1] Maximum number wiring levels [3] [**] 4.700 11 5.063 12 5.454 12 5.875 12 6.329 12 6.817 12 7.344 13 7.911 13 8.522 13 2007 68 54 68 32 2008 59 45 59 29 2009 52 40 52 27 2010 45 36 45 24 2011 40 32 40 22 2012 36 28 36 20 2013 32 25 32 18 2014 28 22 28 17 2015 25 20 25 15
[**] [Note ** : The Interconnect TWG has deleted their "optional levels" from table 80a&b, therefore the ORTC "Maximum number wiring levels - maximum" line is deleted; also the "Maximum nu
2016 22.5 18 22.5 14.0 9.180 13
2017 20.0 16 20.0 12.8 9.889 14
2018 17.9 14 17.9 11.7 10.652 14
2019 15.9 13 15.9 10.7 11.475 14
2020 14.2 11 14.2 9.7 12.361 14
2021 12.6 10 12.6 8.9 13.315 15
2022 11.3 9 11.3 8.1 14.343 15
" line is deleted; also the "Maximum number wiring levels - minimum" is now just "Maximum number of wiring levels."
Table 5a&b Electrical Defects [**]

Year of Production DRAM Pitch (nm) (contacted) Flash Pitch (nm) (un-contacted Poly)(f) MPU/ASIC Metal 1 (M1) Pitch (nm) MPU Physical Gate Length (nm) Flash Random Defect D 0 at production chip size and 89.5% yield (faults/m ) Flash Random Defect D 0 at production chip size and 89.5% yield (faults/m ) DRAM Random Defect D 0 at production chip size and 89.5% yield (faults/m ) DRAM Random Defect D 0 at production chip size and 89.5% yield (faults/m ) MPU Random Defect D 0 at production chip size and 83% yield (faults/ m ) # Mask LevelsMPU # Mask LevelsDRAM # Mask LevelsFlash [to be added in 2009]
2 2 2 2 2
2007 68 54 68 32
2008 59 45 59 29
2009 52 40 52 27
2010 45 36 45 24
2011 40 32 40 22
2012 36 28 36 20
2013 32 25 32 18
2014 28 22 28 17
2015 25 20 25 15
2503
2503
2503
2503
2503
2503
2503
2503
2503
2503 3517
2503 2957
2503 2957
2503 2957
2503 2957
2503 2957
2503 2957
2503 2957
2503 2957
2430
2430
2430
2430
2430
2430
2430
2430
2430
1395 33 24 ??
1395 35 24 ??
1395 35 24 ??
1395 35 26 ??
1395 35 26 ??
1395 35 26 ??
1395 37 26 ??
1395 37 26 ??
1395 37 26 ??
2016 22.5 18 22.5 14.0
2017 20.0 16 20.0 12.8
2018 17.9 14 17.9 11.7
2019 15.9 13 15.9 10.7
2020 14.2 11 14.2 9.7
2021 12.6 10 12.6 8.9
2022 11.3 9 11.3 8.1
2503
2503
2503
2503
2503
2503
2503
2503 2957
2503 2957
2503 2957
2503 2957
2503 2957
2503 2957
2503 2957
2430
2430
2430
2430
2430
2430
2430
1395 37 26 ??
1395 39 26 ??
1395 39 26 ??
1395 39 26 ??
1395 39 26 ??
1395 39 26 ??
1395 39 26 ??
Table 6a&b Power Supply and Power Dissipation

Year of Production DRAM Pitch (nm) (contacted) Flash Pitch (nm) (un-contacted Poly)(f) MPU/ASIC Metal 1 (M1) Pitch (nm) MPU Physical Gate Length (nm) Power Supply Voltage (V) Vdd (high-performance) Vdd (high-performance) 2007 68 54 68 32 1.1 1.1 0.80 0.90 2008 59 45 59 29 1.0 1.1 0.80 0.80 2009 52 40 52 27 1.0 1.1 0.80 0.80 2010 45 36 45 24 1.0 1.1 0.70 0.80 2011 40 32 40 22 0.95 1.0 0.70 0.77 2012 36 28 36 20 0.90 1.0 0.70 0.70 2013 32 25 32 18 0.90 1.0 0.60 0.70 2014 28 22 28 17 0.90 1.0 0.60 0.65 2015 25 20 25 15 0.80 1.0 0.60 0.60
V dd (Low Operating Power, high V dd transistors)[WAS] V dd (Low Operating Power, high V dd transistors) Allowable Maximum Power [1] High-performance with heatsink (W) Maximum Affordable Chip Size Target for Highperformance MPU Maximum Power Calculation Maximum High-performance MPU Maximum Power Density for Maximum Power Calculation Cost-performance (W) Maximum Affordable Chip Size Target for Costperformance MPU Maximum Power Calculation Maximum Cost-performance MPU Maximum Power Density for Maximum Power Calculation Battery (W)(low-cost/hand-held)
102 310 0.33 102 140 0,57 3
146 310 0.47 146 140 0.86 3
143 310 0.46 143 140 0.9 3
146 310 0.47 146 140 0.96 3
161 310 0.52 161 140 1.13 3
158 310 0.51 158 140 1.11 3
149 310 0.48 149 140 1.1 3
152 310 0.49 152 140 1.17 3
143 310 0.46 143 140 1.19 3
2016 22.5 18 22.5 14.0 0.80 0.90 0.50 0.60
2017 20.0 16 20.0 12.8 0.70 0.90 0.50 0.60
2018 17.9 14 17.9 11.7 0.70 0.90 0.50 0.60
2019 15.9 13 15.9 10.7 0.70 0.90 0.50 0.57
2020 14.2 11 14.2 9.7 0.65 0.80 0.50 0.50
2021 12.6 10 12.6 8.9 0.65 0.80 0.45 0.50
2022 11.3 9 11.3 8.1 0.65 0.80 0.45 0.50
130 310 0.42 130 140 1.07 3
130 310 0.42 130 140 1.12 3
136 310 0.44 136 140 1.19 3
133 310 0.43 133 140 1.27 3
130 310 0.42 130 140 1.24 3
130 310 0.42 130 140 1.63 3
130 310 0.42 130 140 1.73 3
Table 7a&b Cost

Year of Production DRAM Pitch (nm) (contacted) Flash Pitch (nm) (un-contacted Poly)(f) MPU/ASIC Metal 1 (M1) Pitch (nm) MPU Physical Gate Length (nm) Affordable Cost per Function ++ DRAM cost/bit at (packaged microcents) at samples/introduction DRAM cost/bit at (packaged microcents) at production Cost-performance MPU (microcents/transistor) (including on-chip SRAM) at introduction Cost-performance MPU (microcents/transistor) (including on-chip SRAM) at production High-performance MPU (microcents/transistor) (including on-chip SRAM) at production 2.6 0.96 22.0 13.3 12.2 1.9 0.68 15.6 9.4 8.6 1.3 0.48 11.0 6.7 6.1 0.9 0.34 7.8 4.7 4.3 0.7 0.24 5.5 3.3 3.0 0.5 0.17 3.9 2.4 2.2 0.3 0.12 2.8 1.7 1.5 0.2 0.08 1.9 1.2 1.1 0.2 0.06 1.4 0.83 0.76 2007 68 54 68 32 2008 59 45 59 29 2009 52 40 52 27 2010 45 36 45 24 2011 40 32 40 22 2012 36 28 36 20 2013 32 25 32 18 2014 28 22 28 17 2015 25 20 25 15
2016 22.5 18 22.5 14.0
2017 20.0 16 20.0 12.8
2018 17.9 14 17.9 11.7
2019 15.9 13 15.9 10.7
2020 14.2 11 14.2 9.7
2021 12.6 10 12.6 8.9
2022 11.3 9 11.3 8.1
0.1 0.04 0.97 0.59 0.54
0.1 0.03 0.69 0.42 0.38
0.1 0.02 0.49 0.29 0.27
0.0 0.01 0.34 0.21 0.19
0.0 0.01 0.24 0.15 0.13
0.0 0.01 0.17 0.10 0.10
0.0 0.01 0.12 0.07 0.07
Table SYSD1
Market Drivers I. Portable/consumer 1. Size/weight ratio: peak in 2004
Major Product Market Segments and Impact on System Drivers

SOC Low power paramount Analog/MS Migrating on-chip for voice processing, A/D sampling, and even for some RF transceiver function MPU
Specialized cores to optim per microwatt
2. Battery life: peak in 2004 3. Function: 2/2 years 4. Time-to-market: ASAP II. Medical 1. Cost: slight downward pressure Need SOC integration (DSP, MPU, I/O cores, etc.)
High-end products only. Absolutely necessary for physical Often used for programm Reprogrammability possible. Mainly measurement and response but may not be when real-time performan ASSP, especially for patient data storage integrated on chip important and telemedicine; more SOC for high-end digital with cores for imaging, real-time diagnostics, etc.
(~1/2 every 5 years) 2. Time-to-market: >12 months
Recent advances in multi have made programmabil performance possible
3. Function: new on-chip functions 4. Form factor often not important 5. Durability/safety 6. Conservation/ ecology III. Networking and communications 1. Bandwidth: 4/34 years 2. Reliability 3. Time-to-market: ASAP 4. Power: W/m of system IV. Defense 1. Cost: not prime concern
3
Large gate counts High reliability
Migrating on-chip for MUX/DEMUX circuitry
MPU cores, FPGA cores specialized functions
More reprogrammability to accommodate MEMS for optical switching. custom functions
Most case leverage existing processors but Absolutely necessary for physical Often used for programm some requirements may drive towards measurement and response but may not be when real-time performan single-chip designs with programmability integrated on chip important
2. Time-to-market: >12 months 3. Function: mostly on SW to ride
Recent advances in multi have made programmabil performance possible
technology curve 4. Form factor may be important 5. High durability/safety V. Office 1. Speed: 2/2 years 2. Memory density: 2/2 years 3. Power: flat to decreasing, Large gate counts; high speed
Minimal on-chip analog; simple A/D and MPU cores and some spe D/A functions Video i/f for automated camera monitoring, video conferencing
Drives demand for digital functionality
Increased industry partne common designs to reduc costs (requires data sharin across multiple design sy
driven by cost and W/m 4. Form factor: shrinking size
Primarily SOC integration of custom off- Integrated high-speed A/D, D/A for the-shelf MPU and I/O cores monitoring, instrumentation, and rangespeed-position resolution
5. Reliability VI. Automotive
1. Speed: 2/2 years 2. Memory density: 2/2 years 3. Power: flat to decreasing,
Large gate counts; high speed
Minimal on-chip analog; simple A/D and MPU cores and some spe D/A functions Video i/f for automated camera monitoring, video conferencing
Drives demand for digital functionality
Increased industry partne common designs to reduc costs (requires data sharin across multiple design sy
driven by cost and W/m 4. Form factor: shrinking size
Primarily SOC integration of custom off- Integrated high-speed A/D, D/A for the-shelf MPU and I/O cores monitoring, instrumentation, and rangespeed-position resolution
5. Reliability VI. Automotive 1. Functionality 2. Ruggedness (external environment, noise) Mainly ASSP, but increasing SOC for high end using standard HW platforms with RTOS kernel, embedded software Signal processing shifting to DSP for voice, visual Mainly entertainment systems Cost-driven on-chip A/D and D/A for sensor and actuators
3. Reliability and safety 4. Cost Physical measurement (communicating sensors for proximity, motion, positioning); MEMS for sensors ASSPapplication-specific standard product FPGAfield programmable gate array MUXmultiplexer D/Adigital to analog DEMUXdemultiplexer HWhardware
A/Danalog to digital
DSPdigital signal processing
i/finterface I/Oinput/output
MEMSmicroelectromechanical systems
RTOSreal-time operating system
System Drivers
MPU Specialized cores to optimize processing per microwatt
MS
oice processing, for some RF
r physical Often used for programmability especially nse but may not be when real-time performance is not important
Recent advances in multicore processors have made programmability and real-time performance possible
MUX/DEMUX
MPU cores, FPGA cores and some specialized functions
hing.
r physical Often used for programmability especially nse but may not be when real-time performance is not important
Recent advances in multicore processors have made programmability and real-time performance possible
; simple A/D and MPU cores and some specialized functions Increased industry partnerships on common designs to reduce development costs (requires data sharing and reuse across multiple design systems)
camera rencing
/D, D/A for tion, and rangen
; simple A/D and MPU cores and some specialized functions Increased industry partnerships on common designs to reduce development costs (requires data sharing and reuse across multiple design systems)
camera rencing
/D, D/A for tion, and rangen
D and D/A for
ng to DSP for
communicating motion, r sensors
demultiplexer HWhardware
Table SYSD2
SOC Consumer Driver Design Productivity T

2007 2008 1.29 1.24 42% 1.25 1.21 2.51 2.42 2009 1.62 1.52 46% 1.54 1.45 3.08 2.89
WAS IS
Trend: SoC total Logic Size (Normalized to 2007) Requirement: % of reused design Requirement: Productivity for new designs (Normalized to 2007) Requirement: Productivity for reused designs (Normalized to productivity for new designs at 2008)
1 1 38% 1 1 2 2
WAS IS WAS IS
umer Driver Design Productivity Trends

2010 2.12 1.93 50% 1.96 1.79 3.92 3.58 2011 2.64 2.41 54% 2.38 2.17 4.76 4.35 2012 3.24 2.98 58% 2.84 2.61 5.68 5.22 2013 4.07 3.74 62% 3.47 3.19 6.94 6.37 2014 5.29 4.74 66% 4.37 3.92 8.74 7.84 2015 6.62 5.96 70% 5.31 4.78 10.62 9.56 2016 8.52 7.54 74% 6.63 5.87 13.26 11.73 2017 10.33 9.41 78% 7.78 7.09 15.56 14.18 2018 12.76 11.78 82% 9.3 8.58 18.59 17.16 2019 16.17 14.87 86% 11.38 10.46 22.75 20.93 2020 21.14 18.91 90% 14.36 12.84 28.71 25.68 2021 24.6 23.35 92% 16.4 15.57 32.79 31.13 2022 34.4 30.26 94% 22.51 19.8 45.02 39.6
Table SYSD3
Year of Production RF-CMOS Pitch
Projected Mixed-Signal Figures of Merit for Four Circuit Types

2007 65 20 1.4
4
2010 45 2832 1.51.7 30 22.5
2013 32 4050 1.82 5070 2.53.5
2016 22 5080 22.4 90100 35
2019 18 6090 2.43 110130 46
FoM LNA (GHz) FoM VCO (1/J) 10 22 FoM PA (WGHz ) 10

2
15 1.5
FoM ADC (GHz/W) 10 3 [1]
[1] Lower bound is for "high-resolution/thermal noise limited" A/D converters; upper bound is for "low-resolution/speed limited" A/D converters.
2022 13 70-100 2.73.5 120-140 610
Driver Refer to the RF and AMS Technologies for Wireless chapter
n/speed limited" A/D converters.
Table SYSD4a
Year of Production DRAM Pitch (nm) CMOS SRAM High-performance, low standby power (HP/LSTP) DRAM pitch (nm), Feature Size F 6T bit cell size (F ) [1] Array efficiency [2] Process overhead versus standard CMOS #added mask layers Operating voltage Vdd (V) [4] Static power dissipation (mW/Cell) [5] Dynamic power consumption per cell (mW/MHz) [6] Read cycle time (ns) [7] Write cycle time (ns) [7] Percentage of MBU on total SER Soft error rate (FIT/Mb) [8] Embedded Non-Volatile Memory (code/data), DRAM pitch (nm) Cell size (F ) NOR FLOTOX / NAND FLOTOX [9] Array efficiency NOR FLOTOX/ NAND FLOTOX [10] Process overhead versus standard CMOS #added mask layers [3] Read operating voltage (V) Write (program/erase) on chip maximum voltage (V) NOR/NAND [11] Static power dissipation (mW/cell) [5] Dynamic power consumption per cell (mW/MHz) [6] Read cycle time (ns) NOR FLOTOX / NAND FLOTOX [7] Program time per cell (s) NOR FLOTOX / NAND FLOTOX [12] Erase time per cell (ms) NOR FLOTOX / NAND FLOTOX [12] Data retention requirement (years) [12] Endurance requirement [12] Embedded DRAM, pitch (nm) 1T1C bit cell size (F ) [13] Array efficiency [2] Process overhead versus standard CMOS #added mask layers [3] Read operating voltage (V) Static power dissipation (mW/Cell) [5] Dynamic power consumption per cell (mW/MHz) [6] DRAM retention time (ms) [12] Read/Write cycle time (ns) [7] Soft error rate (FIT/Mb) [8] FITfailures in time FLOTOXfloating gate tunnel oxide NORnot OR logic operation
2 2 2
Embedded Memory Requirements

2007 65 65 140F 0.7 2 1.1 3E-4/1E-6 4.5E-7/7E-7 0.3/1.5 0.3/1.5 16% 1150 90 10F /5F 0.6/0.8 68 2V 12V/15V 1.00E-06 6.00E-09 Oct-50 1.0/1000.0 10.0/0.1 10 100000 90 1230 0.6 35 2 1.00E-11 1.00E-07 64 0.7 60 MBUmultiple bit upsets
2 2
2008 55 65 140F 0.7 2 1/1.1 3E-4/1E-6 4E-7/6.5E-7 0.3/1.5 0.3/1.5 16% 1150 90 10F /5F 0.6/0.8 68 2V 12V/15V 1.00E-06 6.00E-09 Oct-50 1.0/1000.0 10.0/0.1 10 100000 90 1230 0.6 35 2 1.00E-11 1.00E-07 64 0.7 60
2 2
2009 50 65 140F 0.7 2 1/1.1 3E-4/1E-6 4E-7/6E-7 0.3/1.5 0.3/1.5 16% 1150 90 10F /5F 0.6/0.8 68 2V 12V/15V 1.00E-06 6.00E-09 Oct-50 1.0/1000.0 10.0/0.1 10 100000 65 1230 0.6 35 1.8 1.00E-11 1.00E-07 64 0.5 60
2 2
NANDnot AND logic operation
Definitions of Terms for Tables SYSD4a and SYSD4b: [1] Size of the standard 6T CMOS SRAM cell as a function of minimum feature size. [2] Typical array efficiency defined as (core area / memory instance area).
[3] Typical number of extra masks needed over standard CMOS logic process in equivalent technology. This is typically zero; however for some high-perfo immune) SRAMs special process options are sometimes applied like additional highV th pMOS cell transistors and using higher V dd for better noise mar transistors for fast read-out. [4] Nominal operating voltage refers to the HP and LSTP devices in the logic device requirements table in the PIDS chapter.
[5] Static power dissipation per cell in standby mode. This is measured at I_standby V dd . (off-current and V dd are taken from the HP and LSTP devices table in the PIDS Chapter.
[6] This parameter is a strong function of array architecture. However, a parameter for technology can be determined per cell level. Assume full V dd swin V dd swing on the Bitline (BL). Determine the WL capacitance per cell (CWL) and BL capacitance per cell (CBL). Then: dynamic power consumption per M cell) (V dd ) + V dd CBL (per cell) (V dd ) 10 6 .
[7] Read cycle time is the typical time it takes to complete a READ operation from an address. Write cycle time is the typical time it takes to complete a WR Both cycle times depend on memory size and architecture. [8] A FIT is a failure in 1 billion hours. This data is presented as FIT per megabit.
[9] Size of the standard 1T FLOTOX cell/size of the standard 2T select gate (SG) cell/size of the standard NAND cell. Cell size is somewhat enhanced comp integration issues.
[10] Array efficiency of the standard stacked gate NOR architecture/standard split gate NOR architecture/standard NAND architecture. Data refer to the N in the PIDS chapter. [11] Maximum voltage required for operation, typically used in WRITE operation. Data refer to the NVM device requirements table in the PIDS chapter.
[12] Program time per cell is typically the time needed to program data to a cell. Erase time per cell is typically the time needed to erase a cell. Data reten for which the data must remain non-volatile even under worst-case conditions. Endurance requirement specifies the number of times the cell can be progra
[13] Size of the standard cell for embedded trench DRAM cell. Data refers to the DRAM requirements table in the PIDS chapter.
2010 45 45 140F 0.7 2 1 5E-4/1.2E-6 3E-7/5E-7 0.2/1.2 0.2/1.2 32% 1200 65 10F /5F 0.6/0.8 68 1.8V 12V/15V 1.00E-06 6.00E-09 Jul-35 1.0/1000.0 10.0/0.1 10 100000 65 1230 0.6 35 1.7 1.00E-11 1.50E-07 64 0.4 60
2 2
2013 35 35 140F 0.7 2 0.9/1 1E-3/1.5E-6 2.5E-7/4.5E-7 0.15/0.8 0.15/0.8 64% 1250 45 10F /5F
2 2 2
2016 25 25 140F 0.7 2 0.8/0.9 2E-3/2E-6 2E-7/4E-7 0.1/0.5 0.1/0.5 100% 1300 35 10F /5F
2 2 2
2019 18 18 140F 0.7 2 0.7/0.8 3E-3/2.5E-6 1.5E-7/3E-7 0.07/0.3 0.07/0.3 100% 1350 25 10F /5F
2 2 2
2022 13 13 140F 0.7 2 0.7/0.8 5E-3/3E-6 1E-7/2E-7 0.07/0.3 0.07/0.3 100% 1400 18 10F /5F
2 2 2
0.6/0.8 68 1.5V 12V/15V 1.00E-06 4.00E-09 25-May 1.0/1000.0 10.0/0.1 10 100000 45 1230 0.6 36 1.6 1.00E-11 1.60E-07 64 0.3 60
0.6/0.8 68 1.3V 12V/15V 1.00E-06 3.50E-09 3.5/18 1.0/1000.0 10.0/0.1 10 100000 35 1230 0.6 36 1.5 1.00E-11 1.70E-07 64 0.25 60
0.6/0.8 68 1.2V 12V/15V 1.00E-06 3.00E-09 2.5/12 1.0/1000.0 10.0/0.1 10 100000 25 1230 0.6 36 1.5 1.00E-11 1.70E-07 64 0.2 60
0.6/0.8 68 1.1V 12V/15V 1.00E-06 3.00E-09 10-Feb 1.0/1000.0 10.0/0.1 10 100000 25 1230 0.6 36 1.5 1.00E-11 1.70E-07 64 0.2 60
ogic operation
ically zero; however for some high-performance or highly reliable (noise nd using higher V dd for better noise margin or zero-V th access
DS chapter.
re taken from the HP and LSTP devices in the logic device requirements
ned per cell level. Assume full V dd swing on the Wordline (WL) and 0.8 Then: dynamic power consumption per MHz per cell = V dd CWL (per
he typical time it takes to complete a WRITE operation to an address.
ell. Cell size is somewhat enhanced compared to stand-alone NVM due to
d NAND architecture. Data refer to the NVM device requirements table
equirements table in the PIDS chapter.
e time needed to erase a cell. Data retention requirement is the duration e number of times the cell can be programmed and erased.
PIDS chapter.
Table DESN1
Challenges 32 nm Design productivity
Overall Design Technology Challenges

Summary of Issues System level: high level of abstraction (HW/SW) functionality spec, platform based design, multiprocessor programmability, system integration, AMS co-design and automation Verification: executable specification, ESL formal verification, intelligent test bench, coverage-based verification Logic/circuit/layout: analog circuit synthesis, multi-objective optimization
Power consumption Manufacturability
Logic/circuit/layout: dynamic and static (leakage), system and circuit, power optimization Performance/power variability, device parameter variability, lithography limitations impact on design, mask cost, quality of (process) models ATE interface test (multi-Gb/s), mixed-signal test, delay BIST, test-volume-reducing DFT Logic/circuit/layout: MTTF-aware design, BISR, soft-error correction Logic/circuit/layout: signal integrity analysis, EMI analysis, thermal analysis Summary of Issues Complete formal verification of designs, complete verification code reuse, complete deployment of functional coverage Tools specific for SOI and non-static logic, and emerging devices Cost-driven design flow Heterogeneous component integration (optical, mechanical, chemical, bio, etc.)
Reliability Interference Challenges <32 nm Design productivity
Power consumption Manufacturability
SOI power management Uncontrollable threshold voltage variability Advanced analog/mixed signal DFT (digital, structural, radio), statistical and yield-improvement DFT Thermal BIST, system-level BIST
Reliability Interference
Autonomic computing, robust design, SW reliability Interactions between heterogeneous components (optical, mechanical, chemical, bio, etc.)
ATEautomatic test equipment
BISRbuilt-in self repair
BISTbuilt-in self test
DFTdesign for test MTTFmean time to failure
EMIelectromagnetic interference SOIsilicon on insulator
ESLElectronic System-Level
HW/SWhardware/software
Overall Design Technology Challenges

Summary of Issues System level: high level of abstraction (HW/SW) functionality spec, platform based design, multiprocessor programmability, system integration, AMS co-design and automation Verification: executable specification, ESL formal verification, intelligent test bench, coverage-based verification Logic/circuit/layout: analog circuit synthesis, multi-objective optimization Logic/circuit/layout: dynamic and static (leakage), system and circuit, power optimization Performance/power variability, device parameter variability, lithography limitations impact on design, mask cost, quality of (process) models ATE interface test (multi-Gb/s), mixed-signal test, delay BIST, test-volume-reducing DFT Logic/circuit/layout: MTTF-aware design, BISR, soft-error correction Logic/circuit/layout: signal integrity analysis, EMI analysis, thermal analysis Summary of Issues Complete formal verification of designs, complete verification code reuse, complete deployment of functional coverage Tools specific for SOI and non-static logic, and emerging devices Cost-driven design flow Heterogeneous component integration (optical, mechanical, chemical, bio, etc.) SOI power management Uncontrollable threshold voltage variability Advanced analog/mixed signal DFT (digital, structural, radio), statistical and yield-improvement DFT Thermal BIST, system-level BIST Autonomic computing, robust design, SW reliability Interactions between heterogeneous components (optical, mechanical, chemical, bio, etc.)
quipment
BISRbuilt-in self repair
BISTbuilt-in self test
DFTdesign for test MTTFmean time to failure
c interference ator
ESLElectronic System-Level
HW/SWhardware/software
Description of Improvement In-House place and Route
The transfer of the IC Place and Route function from the semiconductor to the design team. T The presence in the Design Team of at least one senior engineer who had aexperience in all phases of the design process. R Blocks from 2,500 74,999 gates e R Blocks from 75.000 1M gates e IC Implementation Tool Suite Tightly integrated tool set that goes from RTL Synthesis to GDS II through IC Place and Route. RTL Functional verification Tightly integrated RTL Verification tool suite including all simulators and formal tool suite tools needed to complete the verification process. Transactional Modeling The development of standard SystemC models at the Transaction Level of abstraction. Very Large Block reuse Blocks that exceed 1M gates Homogeneous Parallel Many identical processor cores which allows for performance, power efficiency Processing and high reuse. (SMP) IA verification tool (cockpit) that takes in an ES-Level description and partitions it ninto verification blocks, then executes the proper verification tools on the blocks; Concurrent Software A set of tools that allow concurrent software development and debug. Infrastructure Heterogeneous parallel Parallel Processing using different application specific processors for each of the processing separate functions in the system. Transactional Memory A concurrency control mechanism analogous to database transactions for controlling access to shared memory in concurrent computing . It functions as an alternative to lock-based synchroniza tion. System Design Automation True System Level design including Electronic hardware and software, Mechanical, Bio, Opto, Chemical and fluids domains. Executable Specification A design flow that has no manual processes from the specification to completed system and that can be completely validated at each step.
mprovement nd Route
The transfer of the IC Place and Route function from the semiconductor to the design team. T The presence in the Design Team of at least one senior engineer who had aexperience in all phases of the design process. R Blocks from 2,500 74,999 gates e R Blocks from 75.000 1M gates e on Tool Suite Tightly integrated tool set that goes from RTL Synthesis to GDS II through IC Place and Route. verification Tightly integrated RTL Verification tool suite including all simulators and formal tools needed to complete the verification process. odeling The development of standard SystemC models at the Transaction Level of abstraction. k reuse Blocks that exceed 1M gates arallel Many identical processor cores which allows for performance, power efficiency and high reuse. (SMP) IA verification tool (cockpit) that takes in an ES-Level description and partitions it ninto verification blocks, then executes the proper verification tools on the blocks; ware A set of tools that allow concurrent software development and debug. Parallel Processing using different application specific processors for each of the separate functions in the system. A concurrency control mechanism analogous to database transactions for controlling access to shared memory in concurrent computing . It functions as an alternative to lock-based synchroniza tion. True System Level design including Electronic hardware and software, Mechanical, Bio, Opto, Chemical and fluids domains. A design flow that has no manual processes from the specification to completed system and that can be completely validated at each step.
arallel
emory
Automation
ification
Table DESN2
Year of Production
System-Level Design Requirements

2007 2008 2009
Design Reuse Design block reuse [1] % of all logic Platform Based Design Available platforms [2] Normalized to 100% in the start year [3] Platforms supported [4] % of platforms fully supported by tools [5] High Level Synthesis Accuracy of high level estimates (performance, area, power, costs) [6] % versus measurements Reconfigurability SOC reconfigurability [7] % of SOC functionality that is reconfigurable Analog/Mixed Signal Analog automation [8] % versus digital automation [9] Modeling methodology, description languages, simulation environments [10] % vs. digital methodology
35% 87% 10%
36% 83% 25%
38% 75% 35%
60%
63%
66%
28%
28%
30%
17% 58%
17% 60%
24% 62%
ADD ADD ADD ADD
Embedded Software Hardware productivity Software productivity SW productivity needed according to forecast from figure DESN3: (2x every year), normalized to 2007 100% 100% 100% 200.0% 100.0% 200% 200.0% 100.0% 400%
2010
2011
2012
2013
2014
2015
2016
2017
2018
40% 70% 50%
41% 60% 57%
42% 55% 64%
44% 52% 75%
46% 48% 80%
48% 45% 85%
49% 43% 90%
51% 40% 92%
52% 37% 94%
70%
73%
76%
80%
83%
86%
90%
92%
94%
35%
38%
40%
42%
45%
48%
50%
53%
56%
24% 65%
27% 67%
30% 70%
32% 73%
35% 76%
38% 78%
40% 80%
43% 83%
46% 86%
275.0% 100.0% 800%
275.0% 100.0% 1600%
275.0% 100% 3200%
275.0% 100% 6400%
550% 100% 12800%
550% 100% 25600%
1100% 100% 51200%
1100% 100% 102400%
1760% 100% 204800%
2019
2020
2021
2022
54% 35% 95%
55% 32% 97%
57% 29% 99%
58% 27% 100%
95%
97%
99%
100%
60%
62%
65%
68%
50% 90%
52% 92%
55% 95%
58% 98%
1760% 100% 409600%
5280% 100% 819200%
5280% 100% 1638400%
5280% 100% 3276800%
Table DESN3
Correspondence Between System-Level Design Requirements and Solutions

Requirement Design block reuse Solution System-level component reuse
Explanation of the Cor
Available platforms Platforms supported
The larger and more co reuse On-chip network design methods Standardized communi be easily integrated and Multi-fabric implementation planning (AMS, Enables integration of d RF, MEMS, ) number of platforms Automated interface synthesis Automated interface sy Automated HW-SW co-design and verification Improved system-level power estimation techniques Chip-package co-design methods On-chip network design methods
Required for integrated
Accuracy of high level estimates
System-level power est
Packaging effects, e.g.,
SOC reconfigurability Analog automation Modeling methodology, description languages, simulation environments HW offers multi-cores that have to be exploited by SW Reduce SW verification effort Productivity increase required for SW since SW cost >> 50% of total system cost Increase SW execution performance SW Productivity increase required
To provide flexible, rec
Multi-fabric implementation planning (AMS, Multi-fabric implemen RF, MEMS, ) automation Mixed-Signal/RF verification As in digital design, ve Parallel Processing Intelligent Testbench Concurrent Software Infrastructure
ADD ADD ADD
Due to thermal and pow systems.
SW simulation, formal embedded software and
A set of tools that allow
ADD ADD
Heterogeneous Parallel Processing Transactional Memory
Parallel Processing usin system A concurrency control memory in concurrent
ADD ADD
Productivity increase required for HW/SW co-design Reduce verification effort
System Design Automation (SDA) Executable Specification
True System Level desi and fluids domains
Specifications written i process and at high abs enables a design flow t be completely validated
Requirements and Solutions

Explanation of the Correspondence
The larger and more complex the components that can be reused, the greater the expected overall design reuse esign methods Standardized communication structures and interfaces support reuse: IPs with standardized interfaces can be easily integrated and exchanged, and communication structures reused mentation planning (AMS, Enables integration of different fabrics on same die or in same package (SIP); hence, enables reduced number of platforms ce synthesis Automated interface synthesis is one building block to an integrated synthesis flow for whole platforms. Required for integrated, platform-based system development System-level power estimation needs to match progress in high-level area and performance estimation Packaging effects, e.g., on timing, must be accounted for in higher-level estimations To provide flexible, reconfigurable communication structures
onent reuse
W co-design and
evel power estimation
esign methods
esign methods
mentation planning (AMS, Multi-fabric implementation planning for AMS and RF components are a building block to analog automation verification As in digital design, verification is an increasingly critical and time-consuming activity in the design flow Due to thermal and power limitations further performance increases have to be realized with multi-core systems. SW simulation, formal verification and automated testbenches for SW will reduce the verification effort for embedded software and enhance quality. A set of tools that allow concurrent software development and debug
ch
re Infrastructure
allel Processing
Parallel Processing using different application specific processors for each of the separate functions in the system A concurrency control mechanism analogous to database transactions for controlling access to shared memory in concurrent computing. It functions as an alternative to lock-based synchronization True System Level design including Electronic hardware and software, Mechanical, Bio, Opto, Chemical and fluids domains Specifications written in a formal language allow automated verification process starting early in the design process and at high abstraction levels without the need to code several new verification models. This enables a design flow that has no manual processes from the specification to completed system and that can be completely validated at each step.
mory
tomation (SDA)
cation
Table DESN4 Logical/Circuit/Physical Design Technology Requirements

Year of Production Asynchronous global signaling: % of a design driven by handshake clocking Parameter uncertainty:%-effect (on signoff delay) Simultaneous analysis objectives: # of objectives during optimization Circuit families: # of families in a single design Synthesized analog content: % of total design analog content Full-chip leakage (normalized to full-chip leakage power dissipation in 2007) 2007 7% 6% 4 3 15% 1 2008 11% 8% 5 3 16% 1.5 2009 15% 10% 6 4 17% 2 2010 17% 11% 6 4 18% 2.5
2011 19% 11% 6 4 19% 2.75
2012 20% 12% 6 4 20% 3
2013 22% 14% 7 4 23% 3.5
2014 23% 15% 8 4 25% 4
2015 25% 18% 8 4 28% 6
2016 30% 20% 8 4 30% 8
2017 30% 20% 8 4 35% 8
2018 30% 20% 8 4 40% 8
2019 35% 22% 8 4 45% 8
2020 40% 25% 8 4 50% 8
2021 43% 26% 8 4 55% 8
2022 45% 28% 8 4 60% 8
Table DESN5
Requirement Asynchronous global signaling % of a design (SOC) Parameter uncertainty
Correspondence Between Logical/Circuit/Physica

Solution Automated handshake logic/circuit tools
Ex
De red
Synthesis and timing analysis accounting for variability
To un
%-effect (on signoff delay) Simultaneous analysis objectives Simultaneous analysis objectives Simultaneous analysis objectives Circuit/layout enhancement accounting for variability Power management analysis and logic insertion SOI SOC tools Cost-driven implementation flow
Op
Re
Co no ad
Circuit families # of circuit families in a single design Synthesized analog content Full-chip leakage
Non-static logic implementation
No
Analog synthesis (circuit/layout) Macro block/chip leakage analysis
Al
En
ween Logical/Circuit/Physical Requirements and Solutions

Explanation of the Correspondence Departure from fully synchronous design paradigm needed for power reduction, latency insensitivity, variation-tolerance Tools that account for process uncertainty, and resulting parametric uncertainty, will reduce guardbanding and increase chip yields
rcuit tools
accounting for variability
counting for variability
Optimizations which consider parametric uncertainty Requires budgeting of area/power/timing constraints Cost is an engineering parameter that affects turnaround times. Silicon cost no longer dominant; test and manufacturing costs increase emphasis on adaptive, self-repairing circuits Non-static implementations help improving different chip parameters
nd logic insertion SOI SOC tools
ow
on
ut)
Allows for larger portions of a chip to be analog Enables accurate leakage predictions
ysis
Table DESN6 Design Verification Requirements

Year of Production Productivity Design size verifiable by 1 engineer-year (in millions of transistors based on an SOC design and a 10-person engineering team) [1] Methodology Design errors exposed using formal or semi-formal verification (%, versus simulation) Effort spent on system-level verification: software, hardware and electrical effects (%) Portion of the design specification formalized for verifiability (%) Bugs Escape rate: bugs found after first tapeout (per each 100K lines of design code) Bugs found after system integration until tapeout (per each 100K lines of design code) Reuse Portion of the verification infrastructure (e.g., test beds, coverage, checkers) which is newly developed (versus reused components and acquired IP) (%) [2] Portion of the verification infrastructure which is acquired from third parties (i.e., verification IP) (%) [2] Functional coverage Portion of design for which verification quality is evaluated through functional coverage (%) Coverage goal density (expressed as number of coverage goals for each million transistors of the design) [3] 2007 2008 2009 2010
7.9
10.3
13.5
17.6
4.7 11.6 13.8
7.1 13.1 17.5
9.4 14.7 21.3
11.8 16.3 25
8 62
7 68
7 74
7 79
73.9
70.8
67.8
64.7
15.5
18.3
21.1
23.8
46.5 1294
49.7 1608
52.9 1922
56.2 2235
2011
2012
2013
2014
2015
2016
2017
2018
2019
23.1
30.3
39.8
52.3
69.6
91.8
121
159.7
210.9
14.1 17.8 28.8
16.5 19.4 32.5
18.8 20.9 36.3
21.2 22.5 40
23.5 24.1 43.8
25.9 25.6 47.5
28.2 27.2 51.3
30.6 28.8 55
32.9 30.3 58.8
6 85
6 91
6 97
6 103
5 109
5 115
5 121
4 126
4 132
61.6
58.6
55.5
52.5
49.4
46.4
43.3
40.2
37.2
26.6
29.4
32.1
34.9
37.6
40.4
43.2
45.9
48.7
59.4 2549
62.6 2863
65.9 3176
69.1 3490
72.4 3804
75.6 4118
78.8 4431
82.1 4745
85.3 5059
2020
2021
2022
278.6
368.5
487.6
35.3 31.9 62.5
37.6 33.4 66.25
40 35 70
4 138
3 144
3 150
34.1
31.1
28
51.5
54.2
57
88.5 5373
91.8 5686
95 6000
TableCorrespondence Between Design Verification Requirements and Solutions DESN7

Requirement Productivity of verification tasks Solution Verification methodology centered on verification IPs and reuse Hierarchical hardware verification Reusable methodologies for functional coverage development
Explanation of the Corresponden
Verification IPs and reuse reduce verification development required
Structured methodologies improv productivity Functional coverage is time-cons specific for each distinct design; reusability techniques is critical t productivity
Concurrent verification of hardware and software components during development
Advancing the verification of har with that of software components shorten time-to-market of a produ methodologies that begin softwar after the first hardware prototype
Formal and semi-formal verification centered methodology
Hierarchical hardware verification methodology
Enables the decomposition of the smaller blocks which are suitable verification
Design development and structure taking into account verifiability
Design for verifiability organizes simplify verification; additional specific hardware structures furth time verification tasks
Methodologies for system-level verification
Verification methodology centered on verification IPs and reuse
Verification IP components enab system-level verification
Integrated verification of hardware and embedded software and their interface Portion of design specification formalized Design specification formalized for verifiability for verifiability Escape rate after tapeout Design structure taking into account verifiability
Directly provides solutions for ef level verification Formal languages and methodolo formal specification of a design
Development of hardware structu which can be used to detect and c entering an escaped erroneous co customer shipment
System integration bug rate
Analog and mixed-signal verification Simulation and verification solutions for the detection and correction of soft failures and manufacturing faults
Limits the bug rate due to analog
Manufacturing faults occurring in detected at system-level integratio detect and correct electrical and t reduce the effort required to expo these problems.
Hierarchical verification methodology Functional coverage Reusable methodologies for functional coverage development
Supports management of comple decomposition Reusable functional coverage sol coverage development effort and results
Verification Requirements and Solutions

Explanation of the Correspondence Verification IPs and reuse reduce the amount of new verification development required in a project Structured methodologies improve design team productivity Functional coverage is time-consuming, and specific for each distinct design; development of reusability techniques is critical to boosting productivity Advancing the verification of hardware in parallel with that of software components can significantly shorten time-to-market of a product, in contrast to methodologies that begin software verification only after the first hardware prototype Enables the decomposition of the system into smaller blocks which are suitable for formal verification Design for verifiability organizes a design so as to simplify verification; additional verificationspecific hardware structures further simplify designtime verification tasks Verification IP components enable an early start on system-level verification Directly provides solutions for effective systemlevel verification Formal languages and methodologies to support the formal specification of a design Development of hardware structures (checker-like) which can be used to detect and correct a system entering an escaped erroneous configuration after customer shipment Limits the bug rate due to analog effects Manufacturing faults occurring in post-silicon are detected at system-level integration; techniques to detect and correct electrical and transient defects reduce the effort required to expose and correct these problems. Supports management of complexity through decomposition Reusable functional coverage solutions leverage the coverage development effort and boost quality of results
ogy centered on verification
verification
es for functional coverage
n of hardware and software velopment
verification methodology
nd structure taking into
ogy centered on verification
of hardware and embedded rface ormalized for verifiability
g into account verifiability
nal verification
ation solutions for the on of soft failures and
on methodology
es for functional coverage
Table DESN8 Design for Test Technology Requirements

Year of Production System Driver: Analog/Mixed-signal/RF All-digital DFT for analog/mixed-signal/RF circuits and systems. % digital circuits in DFT implementations Correlation of DFT results with existing specification-based test methods. % results correlated Availability of fault/defect models for DFT-oriented test methods. % AMS/RF blocks with accepted fault models System Drivers: MPU/PE/DSP DFT coverage of digital blocks or subsystems. % blocks with DFT DFT for delay test of critical paths. % paths covered DFT for fault tolerance in logic blocks. % blocks with fault tolerance System Drivers: Memories DFT for yield improvement. General SOC/SIP requirements DFT support for logic and other non-memory circuit repair. % blocks with repair DFT reuse for performance calibration, and measurement purposes. % DFT circuits reused DFT impact on system performance (noise, power, sensitivity, bandwidth, etc.). % performance impact (aggregate figure of merit) DFT efficacy in test volume reduction. Reduction factor DFT / ATE interface standard, including DFT control via standard test access protocols. % of test interface standardized 2007 2008 2009 2010
40 40 25
45 45 30
50 50 35
55 55 40
70 55 40
70 55 40
70 60 45
75 60 45
85 50 35 15 5 45
90 60 35 15 5 45
90 60 40 10 5 50
90 60 40 10 10 50
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
60 60 45
60 60 50
60 60 55
60 60 60
80 80 65
85 85 70
90 90 75
90 90 80
100 100 85
100 100 90
100 100 95
100 100 100
75 60 50
75 60 50
80 70 55
80 70 55
85 70 60
85 80 65 98 80 60
90 80 70 98 90 60
90 90 80 98 90 70
95 90 90 100 100 70
95 100 100 100 100 70
97.5 100 100 100 105 72.5
100 100 100 100 110 75
90 70 40 10 10 60
95 70 45 10 10 60
95 70 45 10 20 70
95 80 50 10 20 70
95 80 50 10 20 75
5 20 90
5 50 80
5 50 90
5 50 100
5 50 100
5 50 100
5 50 100
Table DESN9 Design for Manufacturability Technology Requirements

Year of Production Normalized mask cost from public and IDM data % Vdd variability: % variability seen in on-chip circuits % Vth variability: doping variability impact on Vth, (minimum size devices, memory) % Vth variability: includes all sources % Vth variability: typical size logic devices, all sources % CD variability % circuit performance variability circuit comprising gates and wires % circuit total power variability circuit comprising gates and wires % circuit leakage power variability circuit comprising gates and wires 2007 1 10% 31% 33% 16% 12% 46% 56% 124% 2008 1.3 10% 35% 37% 18% 12% 48% 57% 143% 2009 1.7 10% 40% 42% 20% 12% 49% 63% 186%
2010 2.3 10% 40% 42% 20% 12% 51% 68% 229%
2011 3 10% 40% 42% 20% 12% 60% 72% 255%
2012 3.9 10% 58% 58% 26% 12% 63% 76% 281%
2013 5.1 10% 58% 58% 26% 12% 63% 80% 287%
2014 6.6 10% 81% 81% 36% 12% 63% 84% 294%
2015 8.7 10% 81% 81% 36% 12% 63% 88% 331%
2016 11.4 10% 81% 81% 36% 12% 63% 92% 368%
2017 14.9 10% 81% 81% 36% 12% 65% 96% 381%
2018 19.6 10% 112% 112% 50% 12% 66% 102% 395%
2019 25.6 10% 112% 112% 50% 12% 69% 110% 360%
2020 33.6 10% 112% 112% 50% 12% 69% 121% 325%
2021 44.2 10% 112% 112% 50% 12% 71% 130% 477%
2022 57.7 10% 112% 112% 50% 12% 73% 140% 628%
Table DESN10
Requirement Mask cost
Correspondence Between Design for Manufacturability Requirements an

Solution Tools that account for mask cost in their algorithms RDRs (grid-like layouts, no diagonals, etc.) RET tools aware of circuit metrics (timing, power) Statistical leakage analysis and optimization tools Post-tapeout RET interacting with synthesis, timing, P&R Model-based physical verification Model-based physical synthesis Manufacturing-friendly design rules (hard rules) Explanation of the Correspondence Obvious
Better manufacturability and yield, less mask
More effective optimization, fewer design iter
Estimation and control of soaring leakage vari
By interacting with earlier-in-the-flow EDA to more effectively address litho issues
Can address litho issues with precision Explicit litho model-based approach moves in physical synthesis toolset Reduces mask, manufacturing cost; addresses Obvious
% Vdd variability seen at onchip circuits
Tools that account for mask cost in their algorithms RDRs (grid-like layouts, no diagonals, etc.) RET tools aware of circuit metrics (timing, power) Statistical leakage analysis and optimization tools Post-tapeout RET interacting with synthesis, timing, P&R Model-based physical verification Model-based physical synthesis Manufacturing-friendly design rules (hard rules)
By interacting with earlier-in-the-flow EDA to more effectively address litho issues
Can address litho issues with precision Explicit litho model-based approach moves in physical synthesis toolset Reduces mask, manufacturing cost; addresses
% Vth variability (doping variability impact) % Vth variability Includes all sources
Statistical analysis, opt tools and flows (Vdd, T, Vth) Statistical analysis, opt tools and flows (Vdd, T, Vth) Adaptable and redundant circuits Statistical leakage analysis and optimization tools
Better estimate of variability impact reduces o
Better estimate of variability impact reduces o Inherent circuit robustness to variability
% CD variability
RET tools aware of circuit metrics (timing, power) RDRs (grid-like layouts, no diagonals, etc.) Adaptable and redundant circuits Statistical leakage analysis and optimization tools Post-tapeout RET interacting with synthesis, timing, P&R Model-based physical verification Model-based physical synthesis Manufacturing-friendly design rules (hard rules)
Inherent circuit robustness to variability Leakage power variability will soar. Statistica tools are critical to estimate and control it. By interacting with earlier-in-the-flow EDA to more effectively address litho issues
Can address litho issues with precision Explicit litho model-based approach moves in physical synthesis toolset Reduces mask, manufacturing cost; addresses
Circuit performance variability (gates and wires) Circuit power variability (gates and wires)
Router-friendly standard cells Adaptable and redundant circuits Adaptable and redundant circuits Statistical leakage analysis and optimization tools Post-tapeout RET interacting with synthesis, timing, P&R Model-based physical verification Model-based physical synthesis Manufacturing-friendly design rules (hard rules) Router-friendly standard cells
Routing-friendly rules reduce design, mask, an manufacturing complexity Inherent circuit robustness to variability
Inherent circuit robustness to variability Estimation and control of soaring leakage vari By interacting with earlier-in-the-flow EDA to more effectively address litho issues
Can address litho issues with precision Explicit litho model-based approach moves in physical synthesis toolset
Reduces mask, manufacturing cost; addresses Routing-friendly rules reduce design, mask, an manufacturing complexity
Circuit power variability (gates and wires)
Adaptable and redundant circuits Statistical leakage analysis and optimization tools Post-tapeout RET interacting with synthesis, timing, P&R Model-based physical verification Model-based physical synthesis Manufacturing-friendly design rules (hard rules) Router-friendly standard cells
Inherent circuit robustness to variability Estimation and control of soaring leakage vari By interacting with earlier-in-the-flow EDA to more effectively address litho issues
Can address litho issues with precision Explicit litho model-based approach moves in physical synthesis toolset
Reduces mask, manufacturing cost; addresses Routing-friendly rules reduce design, mask, an manufacturing complexity
nufacturability Requirements and Solutions
planation of the Correspondence
bvious
tter manufacturability and yield, less mask complexity
ore effective optimization, fewer design iterations
timation and control of soaring leakage variability
y interacting with earlier-in-the-flow EDA tools, can ore effectively address litho issues
n address litho issues with precision plicit litho model-based approach moves into the ysical synthesis toolset
duces mask, manufacturing cost; addresses printability
bvious
timation and control of soaring leakage variability
y interacting with earlier-in-the-flow EDA tools, can ore effectively address litho issues
duces mask, manufacturing cost; addresses printability
tter estimate of variability impact reduces overdesign
tter estimate of variability impact reduces overdesign
herent circuit robustness to variability
timation and control of soaring leakage variability.
herent circuit robustness to variability akage power variability will soar. Statistical leakage ols are critical to estimate and control it. y interacting with earlier-in-the-flow EDA tools, can ore effectively address litho issues
n address litho issues with precision plicit litho model-based approach moves into the ysical synthesis toolset duces mask, manufacturing cost; addresses printability
outing-friendly rules reduce design, mask, and anufacturing complexity
herent circuit robustness to variability
herent circuit robustness to variability timation and control of soaring leakage variability. y interacting with earlier-in-the-flow EDA tools, can ore effectively address litho issues
duces mask, manufacturing cost; addresses printability outing-friendly rules reduce design, mask, and anufacturing complexity
herent circuit robustness to variability timation and control of soaring leakage variability. y interacting with earlier-in-the-flow EDA tools, can ore effectively address litho issues
duces mask, manufacturing cost; addresses printability outing-friendly rules reduce design, mask, and anufacturing complexity
Table DESN11
Field of Breakthrough Specification, validation, verification Architectural design
Near-term Breakthroughs in Design Technology for

2008/09 Multi-language support, AMS extension of HW/SW description languages for full system simulation Language-based performance evaluation; closer coupling of architectural, block, and circuit level Module generators for often re-used blocks, design centering, performance estimation
2007 State-of-the-Art Established AMS Hardware Description Languages Algorithm-oriented design (e.g., with Matlab/Simulink) Procedural layout generation, module generators for a few block types
Complete spec flow; so verificat
Synthesizeable aware H extende
Physical mixed A/D and RF design
Synthesis: beh the mos blocks)
Parasitics extraction, automated modeling, accelerated simulation
Electromagnetic immunity 2D/3D model-based simulation works but order reduction for is too complicated for interconnect systems and broad usage substrate effects on chip, thermal package modeling
New fault-tole robustne paramet reductio and ante
ghs in Design Technology for AMS

2010/11 Complete specification-driven design flow; some specialized formal verification methods Synthesizeable AMS description; poweraware HW/SW partitioning extended to AMS systems Synthesis: behavior to layout (at least for the most important building blocks) New fault-tolerant circuit architectures, robustness against technology parameter variations; order reduction for all kinds of parasitics and antennas
2008/09 age support, extension of HW/SW iption languages for ystem simulation
ased performance ation; closer coupling hitectural, block, and t level
erators for often ed blocks, n centering, rmance estimation
el-based reduction for onnect systems and rate effects on chip, mal package modeling
Table DESN12
DT Improvement None In-house place and route Engineer Reusesmall blocks Reuselarge blocks Year 1990 1993 1995 1997 1999
Design Technology Improvements and Impact on Designer Produ

Productivity Delta Productivity (Gates/DesignYear) 4K 5.55K 9.09K 40K 56K Cost of Component Affected PD Integration Chip/circuit/PD Verification Circuit/PD Verification Chip/circuit/PD Integration Verification Chip/circuit/PD Integration EDA support SW development Verification
Description of Imp
+38.9% +63.6% +340% +38.9%
Automated block placement
Engineer can pursue all requ complete a design blo GDSII
Blocks from 2,50074,999 g
Blocks from 75,0001M gate
IC implementation suite
2001
+63.6%
91K
RTL functional verification tool suite
2003
+37.5%
125K
Transactional Modeling
2005
+60%
200K
SW development Verification
Tightly integrated tool set th synthesis to GDSII thr route RTL verification tool (cock ES-level description a verifiable blocks, then verification tools on th tracking and reporting Level above RTL, including design; it consists of a the system function ha partitioned) and an arc (where HW and SW a handed off to design t
Very large block reuse Homogeneous parallel processing
2007
+200% +100% HW +100% SW
600K
Chip/circuit/PD Verification Chip/circuit/PD Design and Verification Chip/circuit/PD Verification Chip and Electronic System Design and Verification System Electronic Design and Verification System Electronic Design and Verification System Electronic Design and Verification System Electronic Design and Verification
Blocks >1M gates; intellectu
2009
1200K
Intelligent test bench
2011
37.5%
1650K
Many identical cores provide processing around a m which allows for perfo efficiency, and high re Like RTL verification tool su automation of the Ver Partitioning step
Concurrent software compiler
2013
200% SW
1650K
Enables compilation and SW highly parallel process
Heterogeneous massive parallel processing
2015
+100% HW +100% SW +100% HW +100% SW 60% HW 38% SW 200% HW +200% SW
3300K
Transactional Memory
2017
6600K
System-level DA
2019
10557K
Executable specification
2021
31671K
Each of the specialized cores processor is not identi programming and imp standpoint Automates true electronic sy and off-chip for the fir heterogeneous techno Automates true electronic sy and off-chip for the fir heterogeneous techno Automates true electronic sy and off-chip for the fir heterogeneous techno
Total
+264,000%
System-level DA
2019
60% HW 38% SW 200% HW +200% SW
10557K
Executable specification
2021
31671K
System Electronic Design and Verification System Electronic Design and Verification
Automates true electronic sy and off-chip for the fir heterogeneous techno Automates true electronic sy and off-chip for the fir heterogeneous techno
Total
+264,000%
and Impact on Designer Productivity

Description of Improvement
of onent ted
D ation
Automated block placement and routing Engineer can pursue all required tasks to complete a design block, from RTL to GDSII Blocks from 2,50074,999 gates Blocks from 75,0001M gates Tightly integrated tool set that goes from RTL synthesis to GDSII through IC place and route RTL verification tool (cockpit) that takes an ES-level description and partitions it into verifiable blocks, then executes verification tools on the blocks, while tracking and reporting code coverage Level above RTL, including both HW and SW design; it consists of a behavioral (where the system function has not been partitioned) and an architectural level (where HW and SW are identified and handed off to design teams) Blocks >1M gates; intellectual-property cores Many identical cores provide specialized processing around a main processor, which allows for performance, power efficiency, and high reuse Like RTL verification tool suite, but also with automation of the Verification Partitioning step Enables compilation and SW development in highly parallel processing SOCs Each of the specialized cores around the main processor is not identical from the programming and implementation standpoint Automates true electronic system design onand off-chip for the first time, including heterogeneous technologies (Phase 1) Automates true electronic system design onand off-chip for the first time, including heterogeneous technologies (Phase 2) Automates true electronic system design onand off-chip for the first time, including heterogeneous technologies (Phase 3)
cuit/PD ation
t/PD ation cuit/PD ation ation cuit/PD ation pport
opment ation
opment ation
cuit/PD ation
cuit/PD n and ation
cuit/PD ation
and System n and ation
ectronic n and ation
ectronic n and ation ectronic n and ation ectronic n and ation
ectronic n and ation ectronic n and ation
Automates true electronic system design onand off-chip for the first time, including heterogeneous technologies (Phase 2) Automates true electronic system design onand off-chip for the first time, including heterogeneous technologies (Phase 3)
Table TST1
Key Drivers (not in any particular order)
Summary of Key Test Drivers, Challenges, and Opportunities

Increasing device interface bandwidth (# of signals and data rates) Increasing device integration (SoC, SiP, MCP, 3D packaging) Integration of emerging and non-digital CMOS technologies Complex package electrical and mechanical characteristics Device characteristics beyond one sided stimulus/response model Multiple I/O types and power supplies on same device Multiple digital I/O types on same device Device customization during the test process Distributed test to maintain cost scaling Feedback data for tuning manufacturing Dynamic test flows via Adaptive Test Higher order dimensionality of test conditions
Device trends
Increasing test process complexity
Continued economic scaling of test
Physical limits of test parallelism Managing (logic) test data and feedback data volume Defining an effective limit for performance difference for HVM ATE versus DUT Managing interface hardware and (test) socket costs Trade-off between the cost of test and the cost of quality Multiple insertions due to system test and BIST
Difficult Challenges (in order of priority) Test for yield learning Detecting Systemic Defects
Critically essential for fab process and device learning below optical device dimen
Testing for local non-uniformities, not just hard defects Detecting symptoms and effects of line width variations, finite dopant distribution defects Implementation challenges and efficacies of burn-in, IDDQ, and Vstress Erratic, non deterministic, and intermittent device behavior
Screening for reliability
Potential yield losses
Tester inaccuracies (timing, voltage, current, temperature control, etc) Over testing (e.g., delay faults on non-functional paths) Mechanical damage during the testing process Defects in test-only circuitry or spec failures in a test mode e.g., BIST, power, no Some IDDQ-only failures Faulty repairs of normally repairable circuits Decisions made on overly aggressive statistical post-processing
Future Opportunities (not in any order) Test program automation (not ATPG) Simulation and modeling Convergence of test and system reliability solutions Automation of generation of entire test programs for ATE
Seamless Integration of simulation and modeling of test interface hardware and in device design process
Re-use and fungibility of solutions between test (DFT), device, and system reliabi reporting, correction) BISTbuilt-in self test
ATEautomatic test equipment ATPGautomatic test pattern generation MCPmulti-chip packaging MEMsmicro-electromechanical systems
HVMhigh volume man
Challenges, and Opportunities
of signals and data rates) MCP, 3D packaging) CMOS technologies cal characteristics stimulus/response model n same device e
cess g
itions
data volume ce difference for HVM ATE versus DUT ocket costs e cost of quality d BIST
evice learning below optical device dimensions
st hard defects width variations, finite dopant distributions, systemic process
s of burn-in, IDDQ, and Vstress nt device behavior
ent, temperature control, etc) nctional paths) ocess ures in a test mode e.g., BIST, power, noise
uits tistical post-processing
rograms for ATE
modeling of test interface hardware and instrumentation into the
een test (DFT), device, and system reliability (error detection,
uilt-in self test
HVMhigh volume manufacturing
104442563.xls.ms_office
2007 High Performance MPU, ASIC Wafer test Wafer test Package test Package test SoC Wafer test Package test Low Performance - MCU, MPU, ASIC Wafer test Wafer test Package test Package test Mixed-signal & Communications Wafer test wafer test Package test Packaged Test Commodity DRAM Memory Wafer test Wafer test Package test Package test Commodity Flash Memory Wafer test Wafer test Package test Package test RF Wafer test Wafer test Package test Number of sites Number of sites Number of sites 4 4 8 Number of sites Number of sites Number of sites Number of sites 256 768 512 700 Number of sites Number of sites Number of sites Number of sites 256 384 256 256 Number of sites Number of sites Number of sites Number of sites 4 8 8 4 Number of sites Number of sites Number of sites Number of sites 32 16 32 8 Number of sites Number of sites Number of sites Number of sites 8 1 4 1
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
16 1 8 2
16 1 8 2
16 1 8 2
16 1 8 2
32 2 16 4
32 2 16 4
32 2 16 4
64 4 32 4
64 4 32 4
64 4 32 4
64 4 32 8
64 8 32 8
64 8 32 8
64 8 32 16
64 8 32 16
Number of sites Number of sites
4 4
4 4
4 4
4 4
4 4
8 8
8 8
8 8
16 16
16 16
16 32
16 32
16 32
16 32
16 32
16 32
64 32 64 16
64 32 64 16
64 32 64 16
64 32 64 16
64 64 64 32
64 64 64 32
64 64 64 32
128 128 128 64
128 128 128 64
128 128 128 64
128 128 128 64
128 128 128 64
128 128 128 64
128 128 128 64
128 128 128 64
8 16 16 8
8 16 16 8
16 32 16 16
16 32 16 16
16 32 16 16
16 32 64 16
16 32 64 16
32 64 128 32
32 64 128 32
64 64 256 32
128 64 256 32
128 64 256 32
256 128 512 32
256 128 512 32
256 128 512 32
512 384 512 256
512 384 512 256
1000 512 512 512
1000 512 512 512
1000 512 512 512
1000 768 512 1024
1000 768 512 1024
1000 768 1024 1024
1000 1536 1024 1024
1000 1536 1024 1024
1000 1536 1024 1024
1000 2048 1024 1024
1000 2048 1024 1024
1000 2048 1024 1024
1000 2048 1024 1024
512 768 512 700
1000 768 512 700
1000 1024 1024 700
1000 1024 1024 1024
1000 1024 1024 1024
1000 1536 1024 1024
1000 1536 1024 1024
1000 1536 2048 1024
1000 2048 2048 2048
1000 2048 2048 2048
1000 2048 2048 2048
1000 2048 2048 2048
1000 2048 2048 2048
1000 2048 2048 2048
1000 2048 2048 2048
4 4 16
8 8 32
8 16 48
16 16 64
16 16 64
16 32 64
32 32 128
32 32 128
32 32 128
64 64 256
128 64 256
128 64 256
256 128 512
256 128 512
256 128 512
2008_TST2
Table TST3
Year of Production
System on Chip Test Requirements

2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022
Embedded Cores: Logic Random Pattern Logic BIST Area Investment beyond Scan (%) [1] Compressed Deterministic Pattern Test Area Investment beyond Scan (%) [2] Supported Fault Models by ATPG for Overall Test (SA+T: Stuck-at & Transition, SD: Small Delay, SDX: Extended Small Delay, NDF: New Defect-based Fault Model) Ratio of Overall Pattern Count per Gate to Stuck-at Fault Pattern [3] Estimation & Requirements for SoC Test Pattern (without Core-Parallel Test) SAF Pattern Count per Chip (k) Overall Pattern Count per Chip (k) Ratio of Test Application Time per Chip to 2007's [4] Ratio of Test Application Time per Gate to 2007's = Required Reduction Ratio [5] Required Test Data Volume Compression Ratio [6] DFT Methodology for SoC Level Design DFT method in High Level Design Phase (DRC: DFT Design Rule Check, TA: Testability Analysis and Fault Coverage Estimation, SYN: Test Synthesis) Application of BISR for Logic Cores (AH: Ad hoc Method, PA: Partially Automated Method, LA: Limited Use of Automated Method, GA: General Use of Automated Method) DFT/ATPG Approach to Reduce Yield-Loss (PA: Power-Aware DFT/ATPG, NA: Noise Aware DFT/ATPG, NAX: Extended NoiseAware DFT/ATPG) Embedded cores: Memory (SRAM) Repairing Mechanism of Memory Cells to improve Yield [7] ( RC: BISR/BISD for a few Row & Col R/D, RCM: for more Row & Col R/D, M: for More Sophisticated R/D) Area Investment of BIST/BISR/BISD [8] (Kgates/Mbits) Standardized High-Speed Memory Test I/F [9] (S: Some, P: Partially, F: Fully) Core Integration Standardization of I/F for Reusable IP Cores [10] (P: Partial Use, F: Full Use) Standardization of DFT-ATE I/F [11] (LP: Limited Use of Partial Information, LF: Limited Use of Full Information, F: General Use of Full Information) SoC Level Fault Coverage [12] (AH: Adhoc, L: Logic, M: Memory, IO: I/O, A: Analog) Inter-Core/Core-Interface Test (F: Complemental Functional Test; PA: Partially Automated ; FA: Fully Automated) SoC Manufacturing Systematic Hierarchical Diagnosis (L: Logic, M: Memory, I: Interface) Supported Defect Type for Fault Diagnosis (C: Conventional (SAF, TF, BF), D: Delay Fault Model Considering Defective Delay Size, CT: Cross-talk, TRF: Transient Response Fault) Standardized Diagnosis Interface/Data in the diagnosis flow (ATE: Tester Log, DFT: DFT Method, PFA: Physical Failure Analysis) Volume Diagnosis Data Base (SI: Collection and Storing Defect Information (B: Bad sample, G: Good sample), AD: Automated SoC Diagnosis) P P P P P P F F F F F F F F F F 11 53 1.00 1.00 30 14 68 1.29 0.96 51 17 85 1.62 0.93 84 22 334 4.24 2.00 202 28 416 5.29 2.00 314 34 510 6.48 1.90 496 43 1,283 10.81 2.65 746 56 1,665 14.03 2.65 1,257 70 2,085 17.57 2.65 1,972 90 5,370 30.26 3.55 3,269 109 6,510 36.69 3.55 4,805 134 8,040 45.31 3.55 7,329 170 20,370 76.68 4.74 11,761 222 26,640 100.28 4.74 20,116 258 30,990 116.66 3.67 35,180 361 86,700 217.29 5.04 66,721 3.1 1.1 SA+T X5 3.1 1.1 SA+T X5 3.1 1.2 SA+T X5 3.1 1.3 +SD X 15 3.1 1.4 +SD X 15 3.1 1.5 +SD X 15 3.1 1.6 +SDX X 30 3.1 1.6 +SDX X 30 3.1 1.7 +SDX X 30 3.1 1.8 +NDF X 60 3.1 1.9 +NDF X 60 3.1 2 +NDF X 60 3.1 2.1 +NDF X 120 3.1 2.1 +NDF X 120 3.1 2.1 +NDF X 120 3.1 2.1 +NDF X 240
DRC
DRC
DRC
+TA
+TA
+TA
+TA
+TA
+TA
+SYN
+SYN
+SYN
+SYN
+SYN
+SYN
+SYN
AH
AH
AH
PA
PA
PA
LA
LA
LA
GA
GA
GA
GA
GA
GA
GA
PA
PA
PA
+NA
+NA
+NA
+NAX
+NAX
+NAX
+NAX
+NAX
+NAX
+NAX
+NAX
+NAX
+NAX
RC u35 S
RC u35 S
RC u35 S
RCM 35 P
RCM 35 P
RCM 35 P
M 35 P
M 35 P
M 35 P
M 35 F
M 35 F
M 35 F
M 35 F
M 35 F
M 35 F
M 35 F
LP
LP
LP
LF
LF
LF
AH
AH
AH
L+M
L+M
L+M
+IO
+IO
+IO
+A
+A
+A
+A
+A
+A
+A
PA
PA
PA
PA
PA
PA
FA
FA
FA
FA
FA
FA
FA
L C
L C
L C
+M +D
+M +D
+M +D
+I +CT
+I +CT
+I +CT
+I +CT
+I +TRF
+I +TRF
+I +TRF
+I +TRF
+I +TRF
+I +TRF
ATE
ATE
ATE
+DFT
+DFT
+DFT
+PFA
+PFA
+PFA
+PFA
+PFA
+PFA
+PFA
+PFA
+PFA
+PFA
SI(B)
SI(B)
SI(B)
+SI(G)
+SI(G)
+SI(G)
+SI(G)
+SI(G)
+SI(G)
+AD
+AD
+AD
+AD
+AD
+AD
+AD
Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known
Definitions for System on Chip Test Requirements Table: [1] Area investment of random pattern logic BIST consists of BIST controller and test points. [2] Area investment of compressed deterministic pattern test consists of controller and test points. [3] This shows the number of pattern count (number of captures), which corresponds to various fault models. [4] This is proportional to the overall pattern count and inversely proportional to internal scan data rate. [5] We set the requirement that test application time per gate should be stable. [6] The size of ATE vector memory is assumed to increase as fast as DRAM bit size increases. [7] Growing number of row & column spares, and both divided and shared spares for segments in the future. [8] The current BISR for two dimensional repair is limited to a few row and column spares. [9] Common interface of test logic embedded in memory hard macro for high-speed testing. [10] IEEE1500 is an example. Standardization of I/F for re-usable IP Cores. [11] STIL (Test Interface Language, IEEE1450.x) is an example. I/F should include not only test vectors, but also parametric factors. [12] A method to obtain overall test quality measure of SoC considering all cores; logic, memory and analog.
2007_TST3
2007 Device Characteristics # of Transistors (M) - CPU # of Transistors (M) - Consumer Chip size at production mm^2 - CPU Chip size at production mm^2 - Consumer non differential data rate (GT/s) Internal Scan data rate (MHz) Single ended External Scan Data rate (Mb/s) Differential External Scan Data rate (Gb/s) Vdd CPU CPU total cores CPU Unique cores Percentage of Memory transistors Percentage of random logic transistors Percentage of core transistors Transistors per Flip Flop Supplies per DUT Number of patterns for high coverage SAF only Total # of bits scanned in (same as scan out) Gb Maximum power consumption at test (W) Maximum power consumption at test (W) - Server Number of logic gates (M) Consumer Consumer total cores Consumer Unique cores Percentage of Memory transistors Percentage of random logic transistors Percentage of core transistors Transistors per Flip Flop Supplies per DUT Number of patterns for high coverage SAF only Total # of bits scanned in (same as scan out) Gb Number of logic gates (M) 386 254 140 64 2 50 400 3 0.81.1 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 3,893 3,205 140 64 3.2 169 1200 5 0.50.7 2018 4,905 3,973 140 64 3.2 169 1200 5 0.50.7 2019 6,181 5,049 140 64 3.2 253 1200 5 0.40.7 2020 7,788 6,623 140 64 3.2 253 1200 5 0.40.6 2021 9,812 7,714 140 64 3.2 253 1200 5 0.40.6 2022 12,364 10,816 140 64 3.2 380 1200 5 0.40.6
486 613 772 973 1,226 1,545 1,946 2,452 3,090 344 450 608 773 926 1,225 1,609 2,031 2,633 140 140 140 140 140 140 140 140 140 64 64 64 64 64 64 64 64 64 2 2 2 3.2 3.2 3.2 3.2 3.2 3.2 50 50 75 75 75 113 113 113 169 400 800 800 800 800 1200 1200 1200 1200 3 3 3 3 5 5 5 5 5 0.81.0 0.81.0 0.71.0 0.71.0 0.70.9 0.60.9 0.60.9 0.60.8 0.50.8
4 1 65% 5% 30% 26 16 6572 4 200 300 34
4 1 65% 5% 30% 26 16 7003 6 200 300 43
5 2 70% 5% 25% 26 16 8744 11 300 300 46
6 2 70% 5% 25% 26 14 9524 14 300 300 58
6 2 70% 5% 25% 26 14 10456 19 300 300 73
7 2 70% 5% 25% 26 13 11571 24 300 300 92
8 2 70% 5% 25% 26 13 12911 32 300 300 116
9 4 75% 5% 20% 26 13 17828 69 300 400 122
10 4 75% 5% 20% 26 13 20193 92 300 400 153
11 4 75% 5% 20% 26 13 23025 123 300 400 193
12 4 75% 5% 20% 26 13 26426 167 300 400 243
14 4 75% 5% 20% 26 13 30524 228 300 400 307
16 6 80% 5% 15% 26 13 37458 353 300 400 309
17 6 80% 5% 15% 26 13 43706 490 300 400 389
20 6 80% 5% 15% 26 13 51278 685 300 400 491
22 6 80% 5% 15% 26 13 60479 965 300 400 618
32 4 83% 2% 15% 26 16 10,795 2 11
44 6 84% 2% 14% 26 16 13,760 3 14
58 7 85% 1% 14% 26 16 16,875 3 17
79 10 85% 1% 14% 26 14 22,800 5 23
101 13 86% 1% 13% 26 14 27,055 8 27
126 16 86% 0% 14% 26 13 32,410 7 32
161 20 86% 0% 14% 26 13 42,875 13 43
212 27 86% 0% 14% 26 13 56,315 22 56
268 34 86% 0% 14% 26 13 71,085 36 71
348 44 86% 0% 14% 26 13 92,155 60 92
424 526 669 878 1023 1435 53 66 84 110 128 179 86% 87% 87% 87% 87% 87% 0% 0% 0% 0% 0% 0% 14% 13% 13% 13% 13% 13% 26 26 26 26 26 26 13 13 13 13 13 13 112,175 129,123 164,093 215,248 250,705 351,520 89 118 191 328 445 875 112 129 164 215 251 352
2007_TST4
Table TST5 Vector Multipliers

Vector Fault Type BF (Bridging Fault) TF (Transition Fault) SD (Small Delay) Min 1.3 3 2 Multiplier Max 1.3 5 40
2007 DRAM Characteristics Capacity (Gbits) R&D Mass production Mass production I/O data rate (Gb/s) Performance I/O data rate (Gb/s) Mass production I/O width Mass Production CLK rate (GHz) NAND Characteristics Capacity (Gbits) R&D Mass production Maximum I/O data rate (Gb/s) Maximum I/O data rate (Gb/s) Data width (bits) Power supply voltage range Power supplies per device Maximum current (MA) Tester channels per device NOR Characteristics Capacity (Gbits) R&D Mass production Maximum I/O data rate (Gb/s) Data width (bits) Power supply voltage range Power supplies per device Maximum current (MA) Tester channels per test site Embedded DRAM Capacity (Mbits) DFT Embedded Flash Capacity (Mbits) DFT Embedded SRAM Capacity (Mbits) DFT 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022
8 2 1.1 1.9 16 0.5
8 2 1.3 2.4 16 0.7
16 4 1.3 2.4 16 0.7
16 4 1.6 2.9 16 0.8
16 4 1.6 2.9 16 0.8
32 8 2.1 3.8 16 1.1
32 8 2.7 4.8 16 1.3
32 8 2.7 4.8 16 1.3
64 16 3.2 5.8 16 1.6
64 16 3.2 5.8 16 1.6
64 16 4.3 7.7 16 2.1
128 32 5.3 9.6 16 2.7
128 32 5.4 9.6 16 2.7
128 32 6.4 11.5 16 3.2
256 64 6.4 11.5 16 3.2
256 64 8.5 15.4 16 4.3
64 16 0.05 0.05
64 16 0.05 0.1
128 32 0.05 0.133
128 32 0.066 0.2
128 32 0.066 0.2
256 64 0.1 0.266
256 64 0.1 0.266
256 64 0.1 0.333
512 128 0.1 0.333
512 128 0.133 0.4
512 128 0.133 0.4
1024 256 0.133 0.4
1024 256 0.133 0.533
1024 256 0.266 0.533
2048 512 0.266 0.533
2048 512 0.266 0.533
16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 1.55.5 1.53.5 1.53.5 1.53.5 1.53.5 1.53.5 1.53.5 1.03.5 1.03.5 1.03.5 1.03.5 1.03.5 1.03.5 1.03.5 1.03.5 1.03.5 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 35 35 35 35 35 35 35 35 50 50 50 50 50 50 50 50 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24
4 4 8 8 8 16 16 16 32 32 32 64 64 64 128 128 1 1 2 2 4 4 8 8 16 16 16 32 32 2 4 8 0.2 0.2 0.266 0.266 0.266 0.333 0.333 0.333 0.4 0.4 0.4 0.533 0.533 0.533 0.533 0.533 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 1.05.5 1.05.5 0.93.5 0.93.5 0.93.5 0.93.5 0.93.5 0.93.5 0.93.5 0.93.5 0.93.5 0.93.5 0.93.5 0.93.5 0.93.5 0.93.5 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 150 72 72 72 72 72 72 72 72 72 72 72 72 72 72
256
512
512
512
1024
1024
1024
2048 2048 BIST/BISR 512 512
2048
4096
4096
4096
4096
4096
8192
64
128
128
128
256
256
256
512
1023
1024
1024
1024
2048
2048
BIST/BIST/DAT 0.5 1 1 1 2 2 2 4 4 BIST/BISR 4 8 8 8 16 16 16
2008_TST6
2007 Low Frequency Waveform [Note 1] BW (MHz) BW-max (MHz) BW-center (MHz) [Note 2] Sample rate (MS/s) Sample rate (MS/s) Resolution (bits) Noise floor (dB/RT Hz) Noise floor-Max (dB/RT Hz) [Note 3] Noise floor-mid (dB/RT Hz) [Note 4] Very High Frequency Waveform Source [Note 5] Level V (pkpk) Accuracy () BW (GHz) BW (GHz) Sample rate (GS/s) Sample rate (GS/s) Resolution (bits) AWG/Sine Resolution (bits) AWG/Sine Noise floor (dB/RT Hz) -155 -160 -145 4 0.50% 1.6 2 6.4 6.4 8-10 8-10 -140 -160 -160 -145 -160 -160 -155 50 120 45 2008 75 120 45 2009 75 120 45 2010 75 320 80 2011 100 320 80 2012 100 320 80 2013 100 320 80 2014 100 320 80 2015 100 320 80 2016 100 320 80 2017 100 320 80 2018 100 320 80 2019 100 320 80 2020 100 320 80 2021 100 320 80 2022 100 320 80
Moving from Nyquist sample rates to over/under sampling sources/digitizers Nyquist sample rates or higher for sources/digitizers DSP computation to 24 bits, effective number of bits limited by noise floor -160 -165 -165 -165 -165 -165 -165 -165 -165 -165 -160 -155 -165 -155 -165 -155 -165 -155 -165 -155 -165 -155 -165 -155 -165 -155 -165 -155 -165 -155 -165 -165 -155 -165 -165 -155 -165 -165 -155
4 <4 <4 <4 <4 <4 <4 <4 <4 <4 <4 <4 <4 <4 <4 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 1.9 2.25 2.7 2.7 3 3 3.75 3.75 3.75 3.75 3.75 3.75 3.75 3.75 3.75 2 7.6 6.6 8-10 8-10 -140 4 9 10 8-10 8-10 -140 4 10.8 10 8-10 8-10 -140 4 11 10 8-10 8-10 -140 4 12 10 10-12 8-10 -145 5 12 12 10-12 8-10 -145 5 15 12 10-12 8-10 -145 5 15 12 10-12 8-10 -145 5 15 12 10-12 8-10 -145 5 15 12 10-12 8-10 -145 5 15 12 10-12 8-10 -145 5 15 12 10-12 8-10 -145 5 15 12 10-12 8-10 -145 5 15 12 10-12 8-10 -145 5 15 12 10-12 8-10 -145
Very High Frequency Waveform Digitizer [Note 6] Level V (pkpk) 4 Accuracy () 0.50% BW (GHz) (under sampled) 9.2 Sample rate (GS/s) 0.4 Min resolution (bits) 12 Noise floor (dB/RT Hz) -145 Time Measurement Jitter measurement (ps RMS) Frequency measurement (MHz) Single shot time capability (ps)
4 <4 <4 <4 <4 <4 <4 <4 <4 <4 <4 <4 <4 <4 <4 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 0.50% 10.8 10.8 12.5 12.5 15 15 15 15 15 15 15 15 15 15 15 0.4 0.4 0.4 0.4 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 0.6 12 12 12 12 14 14 14 14 14 14 14 14 14 14 14 -145 -145 -145 -145 -150 -150 -150 -150 -150 -150 -150 -150 -150 -150 -150 Will be driven by high-speed serial communication ports Will be driven by high-performance ASIC clock rates Will be driven by high-speed serial communication ports
2008_TST7
Year of Production Leading Edge Carrier Frequency (GHz) [1] Modulation RF BW (MHz) [2] High Volume Carrier Frequency (GHz) Carrier Frequency (GHz) [1] Modulation RF BW (MHz) Amplitude Accuracy (dB) Amplitude Accuracy (dB) ACLR (dB) Number of RF Ports per Device Phase Noise (dBc/Hz @ 100k offset) Phase Noise (dBc/Hz @ 100k offset) Error Vector Magnitude 3G/4G [3] OIP3 (dBm) [4] IIP3 (dBm) [4] 2007 18 80 6 6 20 <0.8 <0.8 65 <9 -125 -125 1-2% 30 40 2008 18 528 8 8 40 <0.6 <0.6 65 <12 -130 -130 1-2% 30 50 2009 22 528 12 12 80 <0.5 <0.5 70 <16 -135 -135 0.5% 30 60 2010 22 528 12 12 528 <0.5 <0.5 72 <20 -140 -140 0.5% 30 60 2011 60 528 22 22 528 <0.5 <0.5 72 <24 -142 -142 0.5% 30 60 2012 77 528 22 22 2013 77 528 36 36 2014 95 528 36 36 2015 95 528 36 36 2016 95 528 36 36 2017 95 528 36 36 2018 95 528 36 36 2019 95 1000 36 36 2020 95 1000 36 36 2021 95 1000 36 36 2022 95 1000 36 36
1000 1000 528 528 528 528 528 528 528 528 528 <0.25 <0.25 <0.25 <0.25 <0.25 <0.25 <0.25 <0.125 <0.125 <0.125 <0.125 <0.25 <0.25 <0.25 <0.25 <0.25 <0.25 <0.25 <0.125 <0.125 <0.125 <0.125 72 <20 -145 -145 0.5% 30 60 75 <18 -148 -148 0.5% 30 60 75 <16 -150 -150 0.5% 30 60 80 <16 -150 -150 0.5% 30 60 80 <16 -150 -150 0.5% 30 60 80 <16 -152 -152 0.5% 30 60 85 <16 -152 -152 0.5% 30 60 85 <16 -152 -152 0.5% 30 60 85 <16 -152 -152 0.5% 30 60 85 <16 -152 -152 0.5% 30 60 85 <16 -152 -152 0.5% 30 60
Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known u Manufacturable solutions are NOT known
2008_TST8
Year of Production Clock input frequency (MHz) Off-chip data frequency (MHz) Power dissipation (W per DUT) Power Supply Voltage Range (V) High-performance ASIC / microprocessor / graphics processor Low-end microcontroller Mixed-signal Maximum Number of Signal I/O High-performance ASIC High-performance microprocessor / graphics processor / mixed-signal Commodity memory Maximum Current (A) High-performance microprocessor High-performance graphics processor Mixed-signal Burn-in Socket Pin count Pitch (mm) Power consumption (A/Pin) Wafer Level Burn-In Maximum burn-in temperature (C) Pad Layout Linear Minimum pad pitch (m) Minimum pad size (m) Maximum number of probes Pad Layout Periphery, Area Array Minimum pad pitch (m) *1 Minimum pad size (m) Maximum number of probes Power consumption (W/DUT Low-end microcontroller, DFT/BIST SOC *2) Vector memory depth (M vectors DFT/BIST SOC *2)
2007 400 75 600
2008 400 75 600
2009 400 75 600
2010 400 75 600
2011 400 75 600
2012 400 75 600
2013 400 75 600
2014 400 75 600
2015 400 75 600
2016 400 75 600
2017 400 75 600
2018 400 75 600
2019 400 75 600
2020 400 75 600
2021 400 75 600
2022 400 75 600
0.52.5 0.52.5 0.52.5 0.710.0 0.710.0 0.710.0 0.5500 384 128 72 450 100 20 3000 0.3 3 1753 65 50 70k 100 40 150k 10 32 0.5500 384 128 72 450 150 20 3000 0.3 4 1753 65 50 70k 80 35 150k 10 64 0.5500 384 128 72 450 200 20 3000 0.3 4 1753 65 50 70k 80 35 150k 10 64
0.52.5 0.510
0.5-2.5 0.510
0.52.5 0.510
0.52.5 0.510
0.52.5 0.510
0.52.5 0.510
0.52.5 0.510
0.52.5 0.510
0.42.5 0.510
0.42.5 0.510
0.42.5 0.510
0.42.5 0.510
0.42.5 0.510
0.5500 0.5500 0.5500 0.5500 0.5500 0.51000 0.51000 0.51000 0.51000 0.51000 0.51000 0.51000 0.51000 384 128 72 450 200 30 3000 0.2 5 1753 65 50 70k 80 35 150k 20 64 384 128 72 450 200 30 3000 0.2 5 1753 65 50 70k 80 35 150k 20 64 384 128 72 450 200 30 3000 0.2 5 1753 65 50 70k 80 30 150k 20 64 384 128 72 450 200 30 3000 0.2 5 1753 65 50 70k 80 30 150k 20 64 384 128 72 450 200 30 3000 0.2 5 1753 65 50 70k 80 30 150k 20 64 384 128 72 450 200 30 3000 0.1 5 1753 50 40 140k 60 25 300k 20 128 384 128 72 450 200 30 3000 0.1 6 1753 50 40 140k 60 25 300k 20 128 384 128 72 450 200 30 3000 0.1 6 1753 50 40 140k 60 25 300k 20 128 384 128 72 450 200 30 3000 0.08 6 1753 50 40 140k 60 25 300k 20 256 384 128 72 450 200 30 3000 0.08 6 1753 50 40 140k 60 25 300k 20 256 384 128 72 450 200 30 3000 0.08 6 1753 50 40 140k 60 25 300k 20 256 384 128 72 450 200 30 3000 0.08 6 1753 50 40 140k 60 25 300k 20 256 384 128 72 450 200 30 3000 0.08 6 1753 50 40 140k 60 25 300k 20 256
2007_TST9
Table TST10
Test Handler and Prober Difficult Challenges
High Power Handler
Temperature control and temperature rise control due to high power densities during test Continuous lot processing (lot cascading), auto-retest, asynchronous device socketing with low-con Better ESD control as products are more sensitive to ESD and on-die protection circuitry increases Lower stress socketing, low-cost change kits, higher I/O count for new package technologies Package heat lids change thermal characteristics of device and hander Multi-site handling capability for short test time devices (17 seconds)
Medium Power Hander
Support for stacked die packaging and thin die packaging Wide range tri-temperature soak requirements (-45C to 150C) increases system complexity Continuous lot processing (lot cascading), auto-retest, low conversion times, asynchronous operatio Shielding issues associated with high frequency testing (>10 GHz)
Low Power Handler
A wide variety of package sizes, thicknesses, and ball pitches requires kitless handlers with thin-die Package ball-to-package edge gap decreases from 0.6 mm to 0 mm require new handling and socke Parallelism at greater than x128 drives thermal control and alignment challenges
Prober
Consistent and low thermal resistance across chuck is required to improve temperature control of d Heat dissipation of >100 Watts at > 85C is a configuration gap in the prober industry Advances in probe card technology require a new optical alignment methodology
er Difficult Challenges
gh power densities during test nchronous device socketing with low-conversion times and on-die protection circuitry increases cost. ount for new package technologies and hander 17 seconds)
50C) increases system complexity conversion times, asynchronous operation 10 GHz)
hes requires kitless handlers with thin-die handling capability to 0 mm require new handling and socketing methods d alignment challenges
uired to improve temperature control of device under test n gap in the prober industry alignment methodology
Year of Production Wafer diameter (mm) Wafer thickness (um) Maximum I/O pads Chuck X & Y positioning accuracy (um) Chuck Z positioning accuracy (um) Probe-to-pad alignment (m) Maximum chuck force (kg) Set point range (C) Total power (Watts) Power density (Watt/cm )
2
2007 300 80775 3000 2 1 4.5 100
2008 300 80775 4000 2 1 4.5 100
2009 300 80775 4000 1 0.5 4.5 100
2010 300 5300 1 0.5 3.5 100 -45 to +125 250 120
2011 300 5300 1 0.5 3.5 100 -45 to +125 250 120
2012 300 5300 1 0.5 3.5 100 -45 to +125 250 120
2013 300 5300 1 0.5 3.5 100 -45 to +125 250 120
2014 450 5300 1 0.5 3.5 100 -45 to +125 250 120
2015 450 5300 1 0.5 3.5 100 -45 to +125 250 120
2016 450 5300 1 0.5 3.5 100 -45 to +125 250 120
2017 450 5300 1 0.5 3.5 100 -45 to +125 250 120
2018 450 5300 1 0.5 3.5 100 -45 to +125 250 120
2019 450 5300 1 0.5 3.5 100 -45 to +125 250 120
2020 450 5300 1 0.5 3.5 100 -45 to +125 250 120
2021 450 5300 1 0.5 3.5 100 -45 to +125 250 120
2022 450 5300 1 0.5 3.5 100 -45 to +125 250 120
80775 80775 80775 80775 501000 501000 501000 501000 501000 501000 501000 501000 501000
-30 to +85 -30 to +85 -30 to +85 130 60 130 60 250 120
2007_TST11
Year of Production High, Medium and Low Power Temperature set point range (C) High Power - >10W per DUT Temperature accuracy at DUT (C) Number of pins/device Parallel testing: Throughput (devices per hour) Index time (S) Sorting Categories Allowable device temperature rise (C) Maximum socket load per unit (kg) Asynchronous capability Pin/land pitch (mm) Medium Power - 0.5 to 10W per DUT Temperature accuracy at DUT (C) Number of pins/device Parallel testing: Throughput (devices per hour) Index time (S) Sorting Categories Allowable device temperature rise (C) Maximum socket load per unit (kg) Asynchronous capability Pin/land pitch (mm) Low Power - < 0.5W per DUT Temperature accuracy at DUT (C) Number of pins/device Parallel testing: Throughput (devices per hour) Index time (S) Sorting Categories Min. Pkg. Size(mm ) Pin pitch (mm) Ball edge to package edge clearance (mm) Minimum package thickness (mm)
2
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
-55 to 175 -55 to 175 -55 to 175 -55 to 175 -55 to 175 -55 to 175 -55 to 175 -55 to 175 -55 to 175 -55 to 175 -55 to 175 -55 to 175 -55 to 175 -55 to 175 -55 to 175 -55 to 175 2 750 1-2 1.52K 0.3 36 20 24 Yes 1.1 2 800 8-16 46K 0.3 36 5 50 Yes 0.3 2 6250 128-512 810K 25 59 4x6 0.41.0 0.25 0.41.8 2 750 1-2 1.52K 0.3 36 20 27 Yes 1.1 2 800 8-16 46K 0.3 36 5 50 Yes 0.3 2 6250 128-1024 1220K 25 59 3x5 0.251.0 0.25 0.31.8 2 800 1-2 1.52K 0.25 36 20 30 Yes 1 2 850 8-16 46K 0.3 36 5 35 Yes 0.3 1.5 6250 128-1024 1220K 24 59 3x5 0.21.0 0.25 0.21.8 2 800 1-2 23.5K 0.25 36 20 30 Yes 1 2 850 8-16 610K 0.3 36 5 60 Yes 0.3 1.5 6250 128-1024 1220K 24 59 3x5 0.21.0 0.25 0.21.8 2 850 1-2 23.5K 0.25 36 20 35 Yes 0.8 2 850 8-16 610K 0.25 36 5 35 Yes 0.3 1.5 6250 128-1024 1220K 24 59 3x5 0.21.0 0.25 0.21.8 2 850 1-2 23.5K 0.25 36 20 35 Yes 0.6 2 850 8-16 610K 0.25 36 5 60 Yes 0.3 1.5 6250 128-1024 1220K 24 59 3x5 0.21.0 0 0.21.8 2 850 1-2 23.5K 0.25 36 20 35 Yes 0.6 2 850 8-16 610K 0.25 36 5 60 Yes 0.2 1.5 6250 128-1024 1220K 24 59 3x5 0.21.0 0 0.21.8 2 850 1-2 23.5K 0.25 36 20 35 Yes 0.6 2 850 8-16 610K 0.25 36 5 60 Yes 0.2 1.5 6250 128-1024 1220K 24 59 2x3 0.21.0 0 0.21.8 2 850 1-2 23.5K 0.25 36 20 35 Yes 0.6 2 900 8-16 610K 0.25 36 5 65 Yes 0.2 1.5 6250 128-2048 1220K 24 59 2x3 0.21.0 0 0.21.8 2 850 1-2 23.5K 0.25 36 20 35 Yes 0.6 2 900 8-16 610K 0.25 36 5 65 Yes 0.2 1.5 6250 128-2048 1220K 24 59 2x3 0.21.0 0 0.21.8 2 900 1-2 23.5K 0.25 36 20 35 Yes 0.4 2 900 8-16 610K 0.25 36 5 65 Yes 0.2 1.5 6250 128-2048 1220K 24 59 2x3 0.21.0 0 0.21.8 2 900 1-2 23.5K 0.25 36 20 35 Yes 0.4 2 1000 8-16 610K 0.25 36 5 75 Yes 0.2 1.5 6250 128-2048 1220K 24 59 2x3 0.21.0 0 0.21.8 2 900 1-2 23.5K 0.25 36 20 35 Yes 0.4 2 1000 8-16 610K 0.25 3-6 5 75 Yes 0.2 1.5 6250 128-2048 1220K 24 59 2x3 0.21.0 0 0.21.8 2 1000 1-2 23.5K 0.25 36 20 35 Yes 0.4 2 1000 8-16 610K 0.25 36 5 75 Yes 0.2 1.5 6250 128-2048 1220K 24 59 2x3 0.21.0 0 0.21.8 2 1000 1-2 23.5K 0.25 36 20 35 Yes 0.4 2 1000 8-16 610K 0.25 36 5 75 Yes 0.2 1.5 6250 128-2048 1220K 24 59 2x3 0.21.0 0 0.21.8 2 1000 1-2 23.5K 0.25 36 20 35 Yes 0.4 2 1000 8-16 610K 0.25 36 5 75 Yes 0.2 1.5 6250 128-2048 1220K 24 59 2x3 0.21.0 0 0.21.8
2007_TST12
Table TST13
Probing Difficult Challenges
Geometry
Probe technologies to support peripheral fine pitch probe of 23 m peripheral staggered pad probe at effective pitches of 20/40, and fine pitch (45 m) for dual row, non-staggered probing on a four die sides. Fine pitch vertical probe technologies to support 130 m pitch area array solder bump and 50 m pitch staggered pad devices. Multi-site pad probing technologies with corner pitch capability below 125 m. Reduction of pad damage at probe commensurate with pad size reductions (or better). Alternative probe technology for 75 m on 150 m pitch dense array (vertical probe; bumped device). Increasing probe array planarity requirements in combination with increasing array size. Need a probe technology to handle the complexity of SoC devices while probing more than one device. Current probe technologies have I/O limitations for bumped device probes.
Parallel test
Probing at temperature Product
Reduce effects on probes for non-ambient testing -50C to 150C; especially for fine-pitch device For effects on Handlers and Probers, see that section.
Probe technologies to direct probe on copper bond pads including various oxidation consideration Probe technologies for probing over active circuitry (including flip-chip).
Probe force
Reduce per pin force required for good contact resistance to lower total load for high pin count an multi DUT probe applications. Evaluation and reduction of probe force requirements to eliminate die damage, including interlayer dielectric damage with lo A chuck motion model is required to minimize probe damage
Probe cleaning
Development of high temperature (85C150C) in situ cleaning mediums/methods, particularly f fine pitch, multi-DUT, and non-traditional probes. Reduction of cleaning requirements while maintaining electrical performance to increase lifetime. A self cleaning probe card is required for fine pitch bumped pad devices
Cost and delivery
Fine pitch or high pin count probe cards are too expensive and take too long to build. Time and cost to repair fine pitch or high pin count probe cards is very high. The time between chip design completion (tape-out) and the availability of wafers to be probed less than the time required to design and build a probe card in almost every probe technology except traditional cantilever. Space transformer lead times are too long, thus causing some vertical probe technologies to have lengthy lead-times. Tools are required that support fine pitch probe characterization and pad damage measurements. Metrology correlation is needed for post repair test versus on-floor usage.
Probe metrology
High power devices
Probe technologies will need to incorporate thermal management features capable of handling device power dissipations approaching 1000 Watts and the higher currents ( 1.5 amp) flowin through individual probe points.
Contact resistance
Probe technologies that achieve contact resistance <.5 Ohms initially and throughout use are need A method to measure contact resistance is needed. The traditional continuity test is insufficient to monitor contact resistance.
High frequency probing
Traditional probe technologies do not have the necessary electrical bandwidth for higher frequenc devices. At the top end are RF devices, requiring up to 40 GHz.
llenges
e of 23 m peripheral staggered pad probes ) for dual row, non-staggered probing on all
m pitch area array solder bump and 50 m
apability below 125 m. pad size reductions (or better). h dense array (vertical probe; bumped
nation with increasing array size.
oC devices while probing more than one
mped device probes. to 150C; especially for fine-pitch devices.
including various oxidation considerations. cluding flip-chip).
ce to lower total load for high pin count and ction of probe force requirements to c damage with lo amage cleaning mediums/methods, particularly for
electrical performance to increase lifetime. mped pad devices
ve and take too long to build. be cards is very high. and the availability of wafers to be probed is obe card in almost every probe technology
some vertical probe technologies to have
erization and pad damage measurements. us on-floor usage.
nagement features capable of handling and the higher currents ( 1.5 amp) flowing
Ohms initially and throughout use are needed. traditional continuity test is insufficient to
y electrical bandwidth for higher frequency p to 40 GHz.
Year of Production DRAM Pitch (nm) (contacted) MPU and ASIC Products Wirebond - inline pad pitch Bump - array pad pitch I/O Pad Size (m) Wirebond Bump Scrub (% of pad) Wirebond Bump Size of Probed Area (mm ) Number of Probe Points /Touchdown - Asics Number of Probe Points / Touchdown - MPU Maximum Current (mA) ASIC MPU Maximum Resistance (Ohm) Memory Products Wirebond - inline pad pitch I/O Pad Size (m) Wirebond Scrub (% of pad) Wirebond Size of Probed Area (mm ) Number of Probe Points / Touchdown - Memory Maximum Current (mA) Maximum Resistance (Ohm) RF and Mixed Signal Products Wirebond - inline pad pitch Bump - array pad pitch I/O Pad Size (m) Wirebond Bump Scrub (% of pad) Wirebond Bump Size of Probed Area (mm ) Number of Probe Points /Touchdown Maximum Resistance (Ohm)
2 2 2
2007 65 40 130 X 30 65 AREA 25 30 Y 55 65 DEPTH 50 30 2050 5000 20000 Probe Tip 400 1000 Contact <0.5 75 X 65 AREA 25 Y 80 DEPTH 50 X 65 AREA 25 DC Leakage <.001 <.001 Series <3 X 30 65 AREA 25 30
2008 57 35 130 Y 55 65 DEPTH 50 30 2400 6000 20000 Probe Tip 500 1000 Contact <0.5 75 Y 80 DEPTH 50 X 60 AREA 25 DC Leakage <.001 <.001 Series <3 X 30 60 AREA 25 30
2013 32 25 110 Y 35 55 DEPTH 40 30 2400 9000 30000 Probe Tip 1000 1500 Contact <0.5 60 Y 80 DEPTH 50 X 55 AREA 25 DC Leakage <.001 <.001 Series <3 X 20 50 Offline 20 30
2020 14 25 85 Y 25 40 DEPTH 40 30 2400 9000 30000 Probe Tip 1000 1500 Contact <0.5 50 Y 80 DEPTH 50 DC Leakage <.001 <.001 Series <3
100% of wafer 20000 Probe Tip 200 Contact <0.5 DC Leakage <.001 Series <3
100% of wafer 30000 Probe Tip 250 Contact <0.5 DC Leakage <.001 Series <3 25 95
40 130 X 30 65 AREA 25 30 Y 55 65 DEPTH 50 30 1600 680 Contact <0.5 Series <3 X 30 65 AREA 25 30
35 130 Y 55 65 DEPTH 50 30 1600 680 Contact <0.5 Series <3 X 30 60 AREA 25 30
25 110 Y 35 55 DEPTH 40 30 1600 680 Contact <0.4 Series <3 X 20 50 Offline 20 30
25 100 Y 35 50 DEPTH 40 30 1600 680 Series <3 X 15 50 AREA 20 30
25 100 Y 25 50 DEPTH 40 30 1600 680 Series <3 X 15 45 AREA 20 30
Y 25 45 DEPTH 40 30 1600 680 Series <3
X 15 45 AREA 20 30
Y 25 45 DEPTH 40 30 1600 680 Series <3
X 15 45 AREA 20 30
Y 25 45 DEPTH 40 30 1600 680 Series <3
X 15 45 AREA 20 30
Y 25 45 DEPTH 40 30 1600 680
X 15 40 AREA 20 30
Y 25 40 DEPTH 40 30 1600 680
Contact <0.4
Contact <0.4
Contact <0.4
Contact <0.4
Contact <0.4
Contact <0.4
Series <3
Contact <0.4
Series <3
2007_TST14
2007 TSOP Flash (NAND) Contact blade [1] Commodity NAND Memory Lead Pitch (mm) Data rate (MT/s) Contact blade Inductance (nH) Contact Stroke (mm) Contact force (N) Contact resistance (m ohm) Slit width (mm) BGA DRAM Spring Probe [2] Commodity DRAM (Mass production) Lead Pitch (mm) DRAM RM GT/S Spring Probe Inductance (nH) Contact Stroke (mm) Contact force (N) Contact resistance (m ohm) BGA SoC Spring Probe (50 ohm) [3] Logic (High volume microprocessor) Lead Pitch (mm) I/O data (GT/s) Spring Probe (50 ohm) Impedance (ohm) Contact Stroke (mm) Contact force (N) Contact resistance (m ohm) BGA SoC Conductive Rubber [4] [5] Logic (High volume microprocessor) Lead Pitch (mm) I/O data (GT/s) Spring Probe (50 ohm) Inductance (nH) Contact Stroke (mm) Contact force (N) Contact resistance (m ohm) Thickness (mm) 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022
0.4 50
0.3 50
0.3 50
0.3 66
0.3 66
0.3 100
0.3 100
0.3 100
0.3 100
0.3 133
0.3 133
0.3 133
0.3 133
0.3 266
0.3 266
0.3 266
10-15 5-10 5-10 5-10 5-10 5-10 5-10 5-10 5-10 5-10 5-10 5-10 5-10 5-10 5-10 5-10 0.3-0.5 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.4 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 0.2-0.3 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 30 0.22 0.17 0.17 0.17 0.17 0.17 0.17 0.17 0.17 0.17 0.17 0.17 0.17 0.17 0.17 0.17
0.65 1.1 1.5 0.3 <0.4 100
0.65 1.3 1.5 0.3 <0.4 100
0.65 1.3 1.5 0.3 <0.4 100
0.5 1.6 1 0.3 <0.3 100
0.5 1.6 1 0.3 <0.3 100
0.5 2.1 1 0.3 <0.3 100
0.5 2.7 0.5 0.2 <0.2 100
0.5 2.7 0.5 0.2 <0.2 100
0.5 3.2 0.3 0.2 <0.2 100
0.5 3.2 0.3 0.2 <0.2 100
0.5 4.3 0.3 0.2 <0.2 100
0.5 5.3 0.2 0.2 <0.2 100
0.5 5.4 0.2 0.2 <0.2 100
0.5 6.4 0.15 0.2 <0.2 100
0.5 6.4 0.15 0.2 <0.2 100
0.5 8.5 0.15 0.2 <0.2 100
0.8 6 50 0.3 <0.4 100
0.8 6 50 0.3 <0.4 70
0.8 12 50 0.3 <0.4 70
0.65 12 50 0.3 <0.3 50
0.65 12 50 0.3 <0.3 50
0.65 12 50 0.3 <0.3 50
0.65 15 50 0.3 <0.3 50
0.65 15 50 0.3 <0.3 50
0.65 15 50 0.3 <0.3 50
0.5 20 50 0.3 <0.2 50
0.5 20 50 0.3 <0.2 50
0.5 20 50 0.3 <0.2 50
0.5 40 50 0.3 <0.2 50
0.5 40 50 0.3 <0.2 50
0.5 40 50 0.3 <0.2 50
0.5 40 50 0.3 <0.2 50
0.8 6 0.15 0.15 0.2 50 0.5
0.8 6 0.15 0.15 0.2 50 0.5
0.8 12 0.15 0.15 0.2 50 0.5
0.65 12 0.15 0.15 0.15 50 0.5
0.65 12 0.15 0.15 0.15 50 0.5
0.65 12 0.15 0.15 0.5 50 0.5
0.65 15 0.15 0.15 0.15 50 0.5
0.65 15 0.15 0.15 0.15 50 0.5
0.65 15 0.15 0.15 0.15 50 0.5
0.5 20 0.15 0.15 0.1 50 0.5
0.5 20 0.15 0.15 0.1 50 0.5
0.5 20 0.15 0.15 0.1 50 0.5
0.5 40 <0.1 0.15 0.1 50 0.5
0.5 40 <0.1 0.15 0.1 50 0.5
0.5 40 <0.1 0.15 0.1 50 0.5
0.5 40 <0.1 0.15 0.1 50 0.5
Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known u Manufacturable solutions are NOT known Notes: [1] For pitches less than 0.3mm contactor molding becomes difficult due to the thin wall thickness between pins. [2] For higher performance, a shorter probe spring is required which shortens the contact stroke. In 2019, the contact stroke will be 0.2mm so the contact resistance will be unstable. [3] The spring probe must be coaxial for high-speed test. 20GT/s cannot be supported with finer pitches. [4] Ball height is expected to change over the roadmap but amount of change is not known. [5] A contact stroke of 0.15mm was assumed with a 0.5mm rubber thickness. For high ball count devices the contact pressure has been lowered.
2007_TST15
Table RFAMS1 RF and Analog Mixed-Signal CMOS Technology Requirements

Year of Production Performance RF/Analog [1] Supply voltage (V) [2] Tox (nm) [2] Gate Length (nm) [2] gm/gds at 5Lmin-digital [3] 1/f-noise (Vm/Hz) [4] s Vth matching (mVm) [5] Ids (A/m) [6] Peak Ft (GHz) [7] Peak Fmax (GHz) [8] NFmin (dB) [9] Precision Analog/RF Driver [1] Supply voltage (V) Tox (nm) [10] Gate Length (nm) [10] gm/gds at 10Lmin-digital [11] 2007 1.2 2 53 32 160 6 13 170 200 0.25 2.5 5 250 220 1000 9 40 70 2008 1.1 1.9 45 30 140 6 11 200 240 0.22 2.5 5 250 220 1000 9 40 70 2009 1.1 1.6 37 30 100 5 9 240 290 0.2 2.5 5 250 220 1000 9 40 70 2010 1 1.5 32 30 90 5 8 280 340 <0.2 1.8 3 180 160 360 6 50 90
IS
1/f Noise (Vm/Hz) [4] s Vth matching (mVm) [5] Peak Ft (GHz) [7] Peak Fmax (GHz) [8]
CMOS NFET [1 HP CMOS lag 2 yrs] V dd : Power Supply Voltage (V) [13] EOT: Equivalent Oxide Thickness () [13] 1.1 12 53 170 200 2.1 4.0 5.3 1.1 11 37 240 290 1.8 3.5 4.7 1.1 11 32 280 340 1.7 3.4 4.5 1 9 29 310 380 1.6 3.3 4.4
IS IS IS IS IS ADD
Lg: Physical Lgate for High Performance logic (nm) [13] Peak Ft (GHz) [7] Peak Fmax (GHz) [8] NFmin (dB) at 24GHz[14] NFmin (dB) at 60GHz[14] NFmin (dB) at 94GHz[14]
Notes for Table RFAMS1a and b:
[1] Year of first digital product for a given technology generation as given in overall roadmap technology characteristics (ORTC) tables. Lithographic d are indicated. Year of first RF and mixed-signal product at the same technology lag the low-standby power roadmap by one year. Beyond Planar CMO CMOS reflect DG CMOS, Precision Analog/RF driver device color change to yellow reflecting uncertainty on device integration. The supply voltage, To Fmax color codes reflected the low-standby power roadmap. Any discrepancies, please refer to those of low-standby power roadmap.
[2] Nominal supply voltage, V dd , SiO 2 equivalent physical CMOS gate dielectric thickness, T ox , and minimum nominal gate length from low-standby p simplicity, only the Extended planar and DG technology options were used and the value was interpolated in the transition years.
[3] Measure for the low frequency amplification of a 5X minimum length, low-standby power CMOS transistor. Using different lengths is an extra degree designs. Long devices have better G ds amplification (at low frequencies). Operation point taken at 200 mV above the threshold voltage, V th , and at V value of 30 exceeds the projected technology capability with continued scaling for the standard logic device. When this occurs, the standard logic device s unique device designed for specifically for superior gain.
[4] Gate-referred 1/f noise spectral density, at a frequency of 1 Hz, normalized to an active gate area of 1 m 2 . Operation point taken at 200 mV above and at Vds = Vdd/2.
[5] Matching specification for the NMOS transistors threshold voltage, assuming near neighbor devices at minimum practical separation. Careful lay uniformity, e.g. by using dummy structures, are required. Statistical dopant fluctuations start limiting further improvement with SiO 2 . Matching behavior very may be problematic. This parameter determines the lower boundary for the size of transistor in a mixed-signal circuit for a given accuracy a performance, and DC power consumption.
[6] I ds for F t of 50 GHz for a minimum transistor length. F t of 50 GHz is chosen for being 10X the application frequency for 5 GHz. An application fre as a mid-point for the frequency range of interest (110 GHz). [7] Peak Ft measured from H21 extrapolated from 40 GHz with a 20 dB/dec slope. [8] Peak F max measured from unilateral gain extrapolated from 40 GHz with a 20 dB/dec slope. [9] This is the minimum transistor noise figure at 5GHz. 0.2dB represents the limitation of commercially available measurement equipment.
[10] This device is required to achieve direct modulation of the PA for applications from 2 to5 GHz and to support precision analog applications. D tolerance are typically integrated with logic devices to support input-output interfaces. With continued scaling of logic devices alternate device stru support the required specifications.
[11] Measure for the low frequency amplification of a 10 minimum length, low-standby power CMOS transistor. Using different lengths is an extra d signal designs. Long devices have better G ds amplification (at low frequencies). Operation point taken at 200 mV above the threshold voltage, V th , and at
[12] Nominal supply voltage, V dd , SiO 2 equivalent electrical CMOS gate dielectric thickness, EOTelec and minimum nominal gate length from high-per For simplicity, only the Extended planar and DG technology options were used and the value was interpolated in the transition years.
[13] Nominal supply voltage, V dd , SiO 2 equivalent physical CMOS gate dielectric thickness, T ox , and minimum nominal gate length from high perform simplicity, only the Extended planar and DG technology options were used and the value was interpolated in the transition years. [14] This is the minimum transistor noise figure at 24 and 60GHz.
2011 1 1.4 28 30 80 5 7 320 390 <0.2 1.8 3 180 160 360 6 50 90
2012 1 1.3 25 30 70 5 6 360 440 <0.2 1.8 3 180 160 360 6 50 90
2013 1 1.2 22 30 60 5 6 400 510 <0.2 1.8 3 180 160 360 6 50 90
2014 0.95 1.1 20 30 50 5 5 440 560 <0.2 1.8 3 180 160 360 6 50 90
2015 0.85 1.2 18 30 60 5 4 490 630 <0.2 1.8 3 180 160 360 6 50 90
switch to DG device
2016 0.8 1.1 16 30 50 4 4 550 710 <0.2 1.8 3 180 160 360 6 50 90
2017 0.8 1.1 14 30 50 4 3 630 820 <0.2 1.8 3 180 160 360 6 50 90
2018 0.8 1 13 30 40 4 3 670 880 <0.2 1.8 3 180 160 360 6 50 90
2019 0.8 1 12 30 40 4 3 730 960 <0.2 1.5 2.6 130 110 270 5 70 120
switch to DG device 0.9 6 17 520 670 1.3 2.7 3.7 0.8 6 15 590 760 1.2 2.6 3.5 0.8 5.5 14 630 820 1.2 2.5 3.5 0.7 5.5 12.8 680 900 1.1 2.4 3.4
1 7.5 27 330 410 1.6 3.2 4.3
1 6.5 24 370 460 1.5 3.0 4.1
0.95 5.5 22 400 510 1.4 3.0 4.0
0.9 5 20 440 560 1.4 2.9 3.9
0.9 6 18 490 630 1.3 2.7 3.8
stics (ORTC) tables. Lithographic drivers for key technologies by one year. Beyond Planar CMOS, performance RF/Analog integration. The supply voltage, Tox, Gate Length and Ids, Ft, ower roadmap.
nal gate length from low-standby power digital roadmap. For tion years.
different lengths is an extra degree of freedom in mixed signal he threshold voltage, V th , and at V ds = V dd /2. The minimum s occurs, the standard logic device should be replaced with an
ration point taken at 200 mV above the threshold voltage, Vth,
um practical separation. Careful layout and photolithographic ment with SiO 2 . Matching behavior of high- k gate dielectrics nal circuit for a given accuracy and will limit dimensional,
uency for 5 GHz. An application frequency of 5 GHz is chosen
asurement equipment.
rt precision analog applications. Device with higher voltage logic devices alternate device structures may be required to
Using different lengths is an extra degree of freedom in mixed ve the threshold voltage, V th , and at V ds = V dd /2.
m nominal gate length from high-performance digital roadmap. ransition years.
minal gate length from high performance digital roadmap. For tion years.
2020 0.75 0.9 11 30 30 3 2 790 1050 <0.2 1.5 2.6 130 110 270 5 70 120
2021 0.75 0.9 10 30 30 4 2 870 1160 <0.2 1.5 2.6 130 110 270 5 70 120
2022 0.7 0.8 10 30 30 5 2 870 1160 <0.2 1.5 2.6 130 110 270 5 70 120
fixed error in scaling relationship
witch to DG device 0.7 5.5 11.7 740 990 1.1 2.3 3.2 0.7 5 10.7 810 1080 1.0 2.3 3.1 0.65 5 9.7 890 1200 1.0 2.2 3.0
following FEP, PIDS changes
matched published data and used more-physical scaling model matched published data and used more-physical scaling model added 94GH Nfmin starting in 2013
Table RFAMS2 RF and Analog Mixed-Signal Bipolar Technology Requirements

Year of Production General Analog NPN Parameters Emitter width (nm) (HS and HV NPN) 1/f-noise (Vm/Hz) s current matching (%m) High Speed (HS) NPN (Common to mmWave Table) 2007 130 2 2 250 280 3 1.8 13 90 170 3.1 0.26 28 30 80 7 17 2008 120 2 2 275 305 2.5 1.7 15 90 180 3.1 0.24 22 30 80 7 17 2009 100 2 2 300 330 2.2 1.65 17 100 190 2.9 0.2 16 30 80 7 17 2010 100 1.5 2 320 350 1.9 1.6 18 100 200 2.9 <0.2 15 35 80 7 17
IS IS
Peak Ft (GHz) Peak Fmax (GHz) Nfmin (dB) at 60GHz BVceo (V) Jc at Peak Ft (mA/m2) High Voltage (HV) NPN Peak Ft (GHz) [Vcb=1V] Peak Fmax (GHz) BVceo NFmin (dB) at 5GHz Ic (A/m) at 50GHz Ft Power Amplifier (PA) NPN (Common to PA Table)
IS IS IS IS
Peak Ft (GHz) [Vcb=1V] Peak Fmax (GHz) Bvceo (V) BVcbo (V) Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known

Year of Production General Analog NPN Parameters Emitter width (nm) (HS and HV NPN) 1/f-noise (Vm/Hz) s current matching (%m) High Speed (HS) NPN (Common to mmWave Table) Peak Ft (GHz) Peak Fmax (GHz) Nfmin (dB) at 60GHz BVceo (V) Jc at Peak Ft (mA/m2) High Voltage (HV) NPN Peak Ft (GHz) [Vcb=1V] Peak Fmax (GHz) BVceo NFmin (dB) at 5GHz Ic (A/m) at 50GHz Ft Power Amplifier (PA) NPN (Common to PA Table) Peak Ft (GHz) [Vcb=1V] Peak Fmax (GHz) Bvceo (V) BVcbo (V) Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known 35 80 7 17 35 80 7 17 40 80 7 17 40 80 7 17 40 80 7 17 110 210 2.8 <0.2 14 110 220 2.8 <0.2 13 120 230 2.6 <0.2 12 120 240 2.6 <0.2 11 130 250 2.5 <0.2 10 2011 100 1.5 2 340 370 1.7 1.55 19 2012 90 1.5 2 360 390 1.5 1.5 21 2013 90 1 2 380 410 1.4 1.45 22 2014 90 1 2 395 425 1.3 1.4 23 2015 80 1 2 415 445 1.2 1.35 24

Year of Production General Analog NPN Parameters Emitter width (nm) (HS and HV NPN) 1/f-noise (Vm/Hz) s current matching (%m) High Speed (HS) NPN (Common to mmWave Table) Peak Ft (GHz) Peak Fmax (GHz) Nfmin (dB) at 60GHz BVceo (V) Jc at Peak Ft (mA/m2) High Voltage (HV) NPN Peak Ft (GHz) [Vcb=1V] Peak Fmax (GHz) BVceo NFmin (dB) at 5GHz Ic (A/m) at 50GHz Ft Power Amplifier (PA) NPN (Common to PA Table) Peak Ft (GHz) [Vcb=1V] Peak Fmax (GHz) Bvceo (V) BVcbo (V) Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known 40 80 7 17 40 80 7 17 40 80 7 17 40 80 7 17 40 80 7 17 130 260 2.5 <0.2 9 140 270 2.4 <0.2 8 140 280 2.4 <0.2 7 150 290 2.4 <0.2 6 150 300 2.4 <0.2 5 2016 80 1 2 430 460 1.1 1.35 25 2017 80 1 2 445 475 1 1.3 26 2018 70 1 2 455 485 1 1.3 27 2019 70 1 2 470 500 0.9 1.3 28 2020 70 1 2 480 510 0.9 1.3 29

Year of Production General Analog NPN Parameters Emitter width (nm) (HS and HV NPN) 1/f-noise (Vm/Hz) s current matching (%m) High Speed (HS) NPN (Common to mmWave Table) Peak Ft (GHz) Peak Fmax (GHz) Nfmin (dB) at 60GHz BVceo (V) Jc at Peak Ft (mA/m2) High Voltage (HV) NPN Peak Ft (GHz) [Vcb=1V] Peak Fmax (GHz) BVceo NFmin (dB) at 5GHz Ic (A/m) at 50GHz Ft Power Amplifier (PA) NPN (Common to PA Table) Peak Ft (GHz) [Vcb=1V] Peak Fmax (GHz) Bvceo (V) BVcbo (V) Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known 40 80 7 17 40 80 7 17 160 310 2.3 <0.2 5 160 320 2.3 <0.2 5 2021 70 1 2 490 520 0.9 1.25 29 2022 70 1 2 500 530 0.8 1.25 30
updated numbers, drop vcb defintion updated numbers and colors
updated numbers updated numbers updated numbers updated numbers

Year of Production General Analog NPN Parameters Emitter width (nm) (HS and HV NPN) 1/f-noise (Vm/Hz) s current matching (%m) High Speed (HS) NPN (Common to mmWave Table) Peak Ft (GHz) Peak Fmax (GHz) Nfmin (dB) at 60GHz BVceo (V) Jc at Peak Ft (mA/m2) High Voltage (HV) NPN Peak Ft (GHz) [Vcb=1V] Peak Fmax (GHz) BVceo NFmin (dB) at 5GHz Ic (A/m) at 50GHz Ft Power Amplifier (PA) NPN (Common to PA Table) Peak Ft (GHz) [Vcb=1V] Peak Fmax (GHz) Bvceo (V) BVcbo (V) Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known
updated numbers, drop vcb defintion
Table RFAMS3 On-Chip Passives Technology Requirements

Year of Production Analog MOS Capacitor Density (fF/m) [1] Leakage (A/cm) [8] Resistor Thin Film BEOL Parasitic capacitance (fF/m) Temp. linearity (ppm/C) 1s Matching (% m) Sheet resistance, Rs (Ohm/sq) P+ Polysilicon Parasitic capacitance (fF/m) Temp. linearity (ppm/C) 1s Matching (% m) Sheet resistance, Rs (Ohm/sq) RF Metal-Insulator-Metal Capacitor 2007 2008 2009 2010
7 <1e-9
7 <1e-9
7 <1e-9
11 <2e-6
0.03 <100 0.2 50 0.1 <100 1.7 200300
0.03 <100 0.2 50 0.1 <100 1.7 200300
0.05 40-80 0.15 50 0.1 40-80 1.7 200300
0.05 40-80 0.15 50 0.1 40-80 1.7 200300
IS IS IS IS IS
Density (fF/m ) [2] Voltage linearity (ppm/V) Leakage (A/cm) [9] s Matching (%m) Q (5 GHz for 1pF) MOM Capacitor Density (fF/m) Voltage linearity (ppm/V) s Matching (% for 1pF) Inductor Q (5 GHz, 1nH) [3] MOS Varactor Tuning Range [4]
5 <100 <1e-8 0.5 >50 3.7 <100 <0.15 29 >5.5 35
5 <100 <1e-8 0.5 >50 5 <100 <0.15 30 >5.5 40
5 <100 <1e-8 0.5 >50 5.3 <100 <0.15 32 >5.5 40
5 < 100 <1e-8 0.5 >50 6.2 <100 <0.15 34 >5.5 45
IS
Q (5 GHz, 0 V) PA PA III-V Passives
IS
Inductors Q (1GHz, 5nH) [5] Capacitor Q [6] RF capacitor density (fF/m ) [7] PA Silicon/SiGe Passives
2
15 >100 1.2 10 >100 2
25 >100 1.2 14 >100 2
25 >100 1.2 14 >100 2
25 >100 2 14 >100 2
IS IS
Inductors Q (1GHz, 5nH) [5] Capacitor Q [6] 2 RF capacitor density (fF/m ) [7] Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known
Notes for Table RFAMS3a and b: [1] This capacitance density corresponds to the highest end of the gate oxide thickness for precision analog device in the CMOS table.
[2] No stacking (two capacitors on top of each other) is included. Coloring reflected MIM capacitor meeting all requirements including density, voltage linearity on copper metallization. [3] Q at 5 GHz for a single-ended 1nH inductor with a dedicated thick metal (analog metal).
[4] Defined as Cmax/Cmin in C-V curve of the varactor. Varactor align with performance RF device in the CMOS table.
[5] Inductor Q-quality factor of a 5nH inductor at 1 GHz achievable with the technology with a metallization suitable for handling the power requirements of the
[6] Capacitor Q-quality factor of a 10 pF capacitor at 1 GHz achievable with the technology. Capacitor breakdown voltage must be rated for appropriate power
[7] RF capacitor density-capacitor used for all other functions (matching, harmonic filtering, coupling, etc.). Capacitor must have adequate breakdown for the stacking.
[8] Leakage current is defined at room temperature and for the highest end of the supply voltage range and thickness end of the gate oxide thickness for precisi CMOS table. [9] Leakage current is defined at room temperature and for the highest end of the supply voltage range for precision analog device in the CMOS table.
2011
2012
2013
2014
2015
2016
2017
2018
2019
11 <2e-6
11 <2e-6
11 <2e-6
11 <2e-6
11 <2e-6
11 <2e-6
11 <2e-6
11 <2e-6
13 <2e-5
0.05 40-80 0.15 50 0.1 40-80 1.7 200300
0.05 40-80 0.15 50 0.1 40-80 1.7 200300
0.08 30 0.1 50 0.1 30 1 200300
0.08 30 0.1 50 0.1 30 1 200300
0.08 30 0.1 50 0.1 30 1 200300
0.08 30 0.1 50 0.1 30 1 200300
0.08 30 0.1 50 0.1 30 1 200300
0.08 30 0.1 50 0.1 30 1 200300
0.08 20 0.08 50 0.1 30 0.08 200300
5 < 100 <1e-8 0.5 >50 7 <100 <0.15 36 >5.5 45
5 < 100 <1e-8 0.5 >50 6.5 <100 <0.15 38 >5.5 50
7 < 100 <1e-8 0.3 >50 7.5 <100 <0.1 40 >5.5 50
7 < 100 <1e-8 0.3 >50 8.6 <100 <0.1 42 >5.5 50
7 < 100 <1e-8 0.3 >50 9.9 <100 <0.1 44 >5.5 55
10 < 100 <1e-8 0.2 >50 11.4 <100 <0.1 46 >5.5 55
10 < 100 <1e-8 0.2 >50 13.1 <100 <0.1 48 >5.5 60
10 < 100 <1e-8 0.2 >50 15.1 <100 <0.1 50 >5.5 60
12 < 100 <1e-8 0.2 >50 17.4 <100 <0.08 52 >5.5 65
25 >100 2 14 >100 2
30 >100 2 18 >100 2
30 >100 2 18 >100 2
30 >100 2 18 >100 2
30 >100 2 18 >100 2
30 >100 2 18 >100 2
30 >100 2 18 >100 2
30 >100 2 18 >100 2
30 >100 2 18 >100 2
cision analog device in the CMOS table.
acitor meeting all requirements including density, voltage linearity, leakage and matching
device in the CMOS table.
a metallization suitable for handling the power requirements of the PA.
Capacitor breakdown voltage must be rated for appropriate power amplification function.
, coupling, etc.). Capacitor must have adequate breakdown for the given application. No
age range and thickness end of the gate oxide thickness for precision analog device in the
ge range for precision analog device in the CMOS table.
2020
2021
2022
13 <2e-5
13 <2e-5
13 <2e-5
0.08 20 0.08 50 0.1 30 0.08 200300
0.08 20 0.08 50 0.1 20 0.08 200300
0.08 20 0.08 50 0.1 20 0.08 200300
12 < 100 <1e-8 0.2 >50 20 <100 <0.08 54 >5.5 65
12 < 100 <1e-8 0.2 >50 23 <100 <0.08 56 >5.5 70
12 < 100 <1e-8 0.2 >50 26.4 <100 <0.08 58 >5.5 70
updated numbers and colors updated numbers and colors updated numbers and colors updated numbers and colors updated numbers and colors
updated numbers and colors
30 >100 2 18 >100 2
30 >100 2 18 >100 2
30 >100 2 18 >100 2
updated colors
updated colors updated numbers and colors, applications do not require the higher cap
ot require the higher cap
Table RFAMS4 Embedded Passives Technology Requirements

Year of Production Resistor [1] Max Sheet resistance, Rs (Ohm/sq) Tolerance (%) [2] Temp. linearity (ppm/C) Min Sheet resistance, Rs (Ohm/sq) Tolerance (%) [2] Temp. linearity (ppm/C) Capacitor [3] Density (nF/cm) Tolerance (%) [2] TCC (ppm) Breakdown Voltage (V) max Q [4] Self Resonance Freq (GHz) [5] Inductor [3] Density (nH/mm2) Tolerance (%) [2] max Q [6] Self Resonance Freq (GHz) [7] 2007 1K <10% <500 100 <10% <300 >1 <10% <500 >500V >25 >0.5 0.4 <5% >40 >10 2008 1K <10% <300 100 <5% <200 >1 <7% <300 >1KV >30 >0.5 0.4 <5% >40 >10 2009 1K <5% <300 100 <3% <200 >5 <10% <500 >300V >25 >0.1 0.8 <5% >40 >10 2010 10K <10% <500 100 <1% <200 >5 <7% <400 >500V >30 >0.1 0.8 <5% >40 >10
IS IS IS IS IS IS IS
Notes for Table RFAMS4a and b: [1] For both thick and thin film process [2] Untrimmed total tolerance including material and process [3] For all material and process (lamination, buried, etc.) [4] Maximum Q for 1cm [5] SRF for 1cm
2 2
capacitor
capacitor
[6] Maximum Q for 10nH inductor [7] SRF for 25mm

2
inductor
2011 100K <10% <300 10 <10% <300 >5 <7% <400 >700V >30 >0.2 0.8 <5% >40 >10
2012 100K <5% <300 10 <5% <200 >5 <5% <300 >1KV >30 >0.2 0.8 <5% >40 >10
2013 500K <10% <500 10 <3% <200 >10 <10% <500 >500V >25 >0.05 2 <5% >40 >10
2014 500K <10% <300 10 <1% <200 >10 <7% <300 >700V >25 >0.1 2 <5% >40 >10
2015 500K <5% <300 5 <10% <300 >10 <5% <300 >1KV >30 >0.1 2 <3% >40 >10
2016 500K <5% <300 5 <5% <200 >100 <10% <300 >500V >15 >0.001 2 <3% >45 >10
2017 500K <5% <300 5 <3% <200 >100 <7% <300 >500V >20 >0.005 4 <3% >45 >10
2018 500K <5% <300 5 <1% <200 >100 <5% <200 >700V >25 >0.01 4 <3% >45 >10
2019 500K <5% <300 1 <10% <300 >1000 <10% <300 >500V >10 >0.001 4 <3% >45 >10
2020 500K <5% <300 1 <5% <200 >1000 <10% <200 >500V >15 >0.001 4 <3% >45 >10
2021 500K <3% <200 1 <3% <200 >1000 <7% <200 >700V >20 >0.001 8 <3% >45 >10
2022 500K <1% <200 1 <1% <200 >1000 <5% <200 >1KV >25 >0.001 8 <3% >45 >10
Table RFAMS5 Power Amplifier Technology Requirements

Year of Production Nominal battery voltage 2007 3.2 2.85 2008 3.2 2.85 2009 3.2 2.4 2010 3.2 2.4 Radio/Baseband SIP [2] 0.8-6 45 25 52 2.5 0.32 45 25 52 2.5 0.3 55 18 55 2.2 0.28 55 18 55 2.2 0.28 MESFET N/A HEMT N/A 45 20 55 4 0.28
2
IS
End-of-life battery voltage PA product solutions PA frequency (GHz) III-V HBT transistor F max (at V cc ) (GHz) BV CBO (V) Linear efficiency (%) [1] Area (mm ) [2] Cost/mm (US$) [3] III-V HBT integration Bias Control Power management [4] Switch [5] (by-pass) Filter [6] III-V PHEMT transistor F max (at V dd ) (GHz) BV DGO (V) Linear efficiency (%) [1] PA Area (mm ) [2] Cost/mm (US$) [3] III-V PHEMT integration Power management [4] Switch [7] logic integration Filter [6] Silicon MOSFET transistor T ox (PA) () [8] F max (at V dd ) BV DSS (V) Linear efficiency (%) [1] PA Area (mm 2 ) [2] Cost/mm (US$) [3] Silicon MOSFET integration Power management [4] MEMS switch [5] MEMS filter [6] SiGe HBT transistor [9] F max (GHz)
2 2 2 2
45 20 55 4 0.25
75 16 58 3.5 0.24
75 16 58 3.5 0.24 N/A E/D pHEMT N/A
60 45 12 45 6 0.08
60 45 12 45 6 0.08
35 60 10 45 4.5 0.06
35 60 10 45 4.5 0.06 Yes
NO Stack 60 17 50 2.5 0.12 60 17 50 2.5 0.12
Stack
Above IC WLP 80 17 52 2.2 0.11 Yes
80 17 52 2.2 0.11
IS
BV CBO (V) Linear efficiency (%) [1] PA Area (mm ) [2] Cost/mm (US$) [3] SiGe integration Power management MEMS switch [5]
2 2
NO
Stack
Above IC
MEMS filter [6] Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known
Stack
WLP
Notes for Table RFAMS5a and b: [1] Linear efficiencypower added efficiency of the final PA stage under personal communication service (PCS) CDMA (IS-95) modulation.
[2] Areatotal semiconductor area necessary for the implementation of the quad-band GSM/general packet radio service (GPRS)/ Enhanced Data rates fo function, including matching/filtering. [3] Cost/mm 2 approximate commercial foundry cost of the area mentioned in [4]. [4] Power managementcapability of the technology to provide RF power detection/DC power management for the PA. [5] Switchcapability of the technology to integrate cost-effectively a stage by-pass switch into the PA active die.
[6] Filtercapability of the technology to integrate high-quality band selection filters needed for the assumed PA solution; currently performed with surfa technology. [7] Switch Logic Integrationcapability of the technology to integrate cost-effectively a control circuitry with the Tx/Rx antenna switch. [8] T ox (PA)thickness of the MOSFET transistor in the RF power amplifier function.
[9] Ideally, the Si requirements and GaAs requirements would be the same, but we use different values to account for the state-of-the-art performance diffe
2011 2.4 1.6
2012 2.4 1.6
2013 2.4 1.6
2014 2.4 1.6
2015 2.4 1.6
2016 2.4 1.6
2017 2.4 1.6
2018 2.4 1.6
2019 2.4 1.6
Radio/Baseband SIP [2] 0.8-6 55 18 55 2.2 0.28 MESFET N/A HEMT N/A 75 16 58 3.5 0.24 N/A E/D pHEMT N/A 35 60 10 45 4.5 0.06 Yes Above IC WLP 80 17 52 2.2 0.11 Yes Above IC Integrated 80 17 52 2.2 0.11 80 17 52 2.2 0.11 Integrated Above IC 80 17 52 2.2 0.11 80 17 52 2.2 0.11 80 17 52 2.2 0.11 80 17 52 2 35 60 10 45 4.5 0.05 35 60 10 45 4.5 0.05 35 60 10 45 4.5 0.05 35 60 10 45 4.5 0.05 35 60 10 45 4.5 0.05 35 60 10 75 16 58 3.5 0.22 75 16 58 3.5 0.22 75 16 58 3.5 0.22 75 16 58 3.5 0.15 75 16 58 3.5 0.15 75 16 58 65 18 55 2.2 0.25 65 18 55 2.2 0.25 65 18 55 2.2 0.25 65 18 55 2.2 0.25 65 18 55 2.2 0.25 65 18 55 2
Radio/Baseband SIP [2]
65 18 55 2 0.25
65 18 55 2 0.25 MESFET N/A HEMT N/A
0.25
75 16 58 3.5 0.15
75 16 58 3.5 0.15 N/A E/D pHEMT N/A
3.5 0.15
35 60 10 45 4.5 0.05
35 60 10 45 4.5 0.05 Yes Integrated Above IC
45 4.5 0.05
80 17 52 2 0.11
80 17 52 2 0.11 Yes Integrated
0.11
WLP
Above IC
Above IC
S) CDMA (IS-95) modulation.
dio service (GPRS)/ Enhanced Data rates for GSM Evolution (EDGE) PA
or the PA.
ie.
PA solution; currently performed with surface acoustic wave (SAW) filter
he Tx/Rx antenna switch.
nt for the state-of-the-art performance differences between the technologies.
2020 2.4 1.6
2021 2.4 1.6
2022 2.4 1.6
Delay 2.4V intro
SIP [2]
65 18 55 2 0.25 MESFET N/A HEMT N/A 75 16 58 3.5 0.15 N/A E/D pHEMT N/A 35 60 10 45 4.5 0.05 Yes Integrated Above IC 80 17 52 2 0.11 Yes Integrated
65 18 55 2 0.25
65 18 55 2 0.25
75 16 58 3.5 0.15
75 16 58 3.5 0.15
35 60 10 45 4.5 0.05
35 60 10 45 4.5 0.05
80 17 52 2 0.11
80 17 52 2 0.11
updated numbers
Above IC
Table RFAMS6 Base Station Devices Technology Requirements

Year of Production Application frequency (GHz) [1] Cost ($$/Watt) Packaging (C-Ceramic, P-Plastic) Si LDMOS Operating voltage (V) Saturated power (Watt) Saturated power density (W/mm) Saturated PAE (%) Linear power (Watt) Linear PAE (%) GaAs FET Operating voltage (V) Saturated power (Watt) Saturated power density (W/mm) Saturated PAE (%) Linear power (Watt) Linear PAE (%) GaN FET Operating voltage (V) Saturated power (Watt) Saturated power density (W/mm) Saturated PAE (%) Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known Note for Table RFAMS6a and b: [1] Application frequencies affected device saturated PAE scaling. 2007 0.83.5 0.3 C, P 32, 48 240 1.8 55 120 39 57 150 40 28 240 1.5 67 120 47 48 200 4 60 62 65 300 2008 0.83.5 0.2 C, P 2009 0.83.5 0.2 C, P 32, 48 400 1.8 60 200 42 2010 0.85 0.15 Plastic
55 39 28 240 1.8
65 46
70 50
65 120 46 48 300 5 60
2011 0.85 0.15 Plastic
2012 0.85 0.15 Plastic 32, 48 500 1.8
2013 0.85 0.1 Plastic
2014 0.88 0.1 Plastic
2015 0.88 0.1 Plastic
2016
2017
2018
2019 0.88 0.1 Plastic 32, 48 500 1.8 60 250 42
57 250 40 28 240 1.8 67 120 47 48 400 5 62 65 500 50 70
60 42 28 240 1.8 70 120 50 48 500 5 65
28 240 1.8 70 120 50 48 500 5 65 51 72
2020 0.88 0.1 Plastic 32, 48 500 1.8 60 250 42 28 240 1.8 72 120 51 48 500 5 65
2021
2022
Table RFAMS7 Millimeter Wave 10 GHz100 GHz Technology Requirements

Year of Production Device TechnologyFET GaAs PHEMT (low noise) 2007 2008 2009 2010
IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS
Gate length (nm) Ft (GHz) Breakdown (volts) Imax (mA/mm) Gm (S/mm) NFmin (dB) at 26 GHz Associated Gain at 26 GHz NFmin (dB) at 94 GHz Associated Gain at 94 GHz GaAs PHEMT (power) Gate length (nm) Fmax (GHz) Breakdown (volts) Imax (ma/mm) Gm (S/mm) Pout at 24 GHz and peak efficiency (mW/mm) Peak efficiency at 24 GHz (%) Gain at 24 GHz, at P1dB (dB) GaAs PHEMT (power) Gate length (nm) Fmax (GHz) Breakdown (volts) Imax (ma/mm) Gm (S/mm) Pout at 60 GHz and peak efficiency (mW/mm) Peak efficiency at 60 GHz (%) Gain at 60 GHz, at P1dB (dB) Pout at 94 GHz and peak efficiency (mW/mm) Peak efficiency at 94 GHz (%) Gain at 94 GHz, at P1dB (dB) InP HEMT (low noise) Gate length (nm)
150 110 12 650 0.5 1 8.5 2.8 3 150 150 12 700 0.5 650 45 11 100 200 8 800 0.65 550 30 7 350 20 5 100 200 4 500 1.1 0.5 15 1 11
150 110 12 650 0.5 1 8.5 2.8 3 150 150 12 700 0.5 650 45 11 100 200 8 800 0.65 550 30 7 350 20 5 100 200 4 500 1.1 0.5 15 1 11
150 110 12 650 0.5 1 8.5 2.8 3 150 150 12 700 0.5 650 45 11 100 200 8 800 0.65 550 30 7 350 20 5 100 200 4 500 1.1 0.5 15 1 11
100 150 12 700 0.55 0.8 10.8 2.5 4 150 150 12 700 0.5 650 45 11 100 200 8 800 0.65 550 30 7 350 20 5 70 250 3 600 1.5 0.4 16 0.8 12
IS IS IS IS IS IS IS IS
Ft (GHz) Breakdown (volts) Imax (ma/mm) Gm (S/mm) Fmin (dB) at 24 GHz Associated Gain (dB) at 24 GHz Fmin (dB) at 60 GHz Associated Gain (dB) at 60 GHz
IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS
Fmin (dB) at 94 GHz Associated Gain (dB) at 94 GHz InP HEMT (power) Gate length (nm) Fmax (GHz) Breakdown (volts) Imax (ma/mm) Gm (S/mm) Pout at 24 GHz and peak efficiency (mW/mm) Peak efficiency at 24 GHz (%) Gain at 24 GHz, at P1dB (dB) Pout at 60 GHz and peak efficiency (mW/mm) Peak efficiency at 60 GHz (%) Gain at 60 GHz, at P1dB (dB) Pout at 94 GHz and peak efficiency (mW/mm) Peak efficiency at 94 GHz (%) Gain at 94 GHz, at P1dB (dB) GaAs MHEMT (low noise)Ka through W-Band Gate length (nm) Ft (GHz) Channel In content (%) Offstate Breakdown (volts) Imax (ma/mm) Gm (S/mm) Fmin (dB) at 24 GHz Associated Gain (dB) @ 24GHz Fmin (dB) at 60 GHz Associated Gain (dB) @ 60GHz Fmin (dB) at 94 GHz Associated Gain (dB) @ 94GHz GaAs MHEMT (Power) -Ka band Gate length (nm) Channel In content (%) Fmax (GHz) Offstate Breakdown (volts) Imax (ma/mm) Gm (S/mm) Pout at 24 GHz and peak efficiency (mW/mm) Peak efficiency at 24 GHz (%) Gain at 24 GHz, at P1dB (dB) GaAs MHEMT (Power) Gate length (nm) Channel In content (%) Fmax (GHz) Offstate Breakdown (volts) Imax (ma/mm) Gm (S/mm)
1.5 8 100 250 4 500 1.1 450 50 14 300 40 10 150 30 7 100 200 60 6 900 1.2 0.5 15 1 10 1.5 8 150 35 200 8 760 0.85 800 45 12 100 53 300 7 900 1.2
1.5 8 100 250 4 500 1.1 450 50 14 300 40 10 150 30 7 100 200 60 6 900 1.2 0.5 15 1 10 1.5 8 150 35 200 8 760 0.85 800 45 12 100 53 300 7 900 1.2
1.5 8 100 250 4 500 1.1 450 50 14 300 45 10 160 30 7 100 200 60 6 900 1.2 0.5 15 1 10 1.5 8 150 35 200 8 760 0.85 800 45 12 100 53 300 7 900 1.2
1.3 9 70 400 3 600 1.5
400 50 14 200 40 10 70 250 70 4 900 1.4 0.4 16 0.7 12 1.2 10 100 35 250 10 850 1 850 50 14 70 43 300 9 900 1.4
IS IS IS IS IS IS
Pout at 60 GHz and peak efficiency (mW/mm) Peak efficiency at 60 GHz (%) Gain at 60 GHz, at P1dB (dB) Pout at 94 GHz and peak efficiency (mW/mm) Peak efficiency at 94 GHz (%) Gain at 94 GHz, at P1dB (dB) GaN HEMT (low noise) Gate Length (nm) Ft (GHz) Breakdown (volts) Imax (ma/mm) Gm (S/mm) Fmin (dB) at 24 GHz Associated Gain at 24 GHz GaN HEMT (power) Gate Length (nm) Fmax (GHz) Breakdown (volts) Imax (ma/mm) Gm (S/mm) Pout at 24 GHz and peak efficiency (mW/mm)
500 40 8 225 30 6
500 40 8 225 30 6
500 40 8 225 30 6 150 120 40 1000 0.4 1.2 10
550 45 9 300 35 7 100 160 35 1200 0.5 1 12 150 150 60 1200 0.5 5000 50 10 100 200 40 1200 0.55 4000 30 8 2500 20 6
IS
Peak efficiency at 24 GHz (%) Gain at 24 GHz, at P1dB (dB) GaN HEMT (power) Gate length (nm) Fmax (GHz) Breakdown (volts) Imax (ma/mm) Gm (S/mm) Pout at 60 GHz and peak efficiency (mW/mm) Peak efficiency at 60 GHz (%) Gain at 60 GHz, at P1dB (dB) Pout at 94 GHz and peak efficiency (mW/mm) Peak efficiency at 94 GHz (%) Gain at 94 GHz, at P1dB (dB) Device TechnologyRF CMOS CMOS NFET [1 HP CMOS lag 2 yrs] V dd : Power Supply Voltage (V) [13] EOT: Equivalent Oxide Thickness () [13] 1.1 12 53 170 200 2.1 4.0 5.3 1.1 11 37 240 290 1.8 3.5 4.7 1.1 11 32 280 340 1.7 3.4 4.5
1 9 29 310 380 1.6 3.3 4.4
IS IS IS IS IS ADD
Lg: Physical Lgate for High Performance logic (nm) [13] Peak Ft (GHz) [7] Peak Fmax (GHz) [8] NFmin (dB) at 24GHz[14] NFmin (dB) at 60GHz[14] NFmin (dB) at 94GHz[14] Device TechnologyHBT InP HBT
IS
Emitter width (nm)
1000
1000
500
500
IS IS IS IS
Peak Ft (GHz) Peak Fmax (GHz) BVceo Jc at Peak Ft (mA/m ) SiGe HBT Emitter width (nm) Peak Ft (GHz) Peak Fmax (GHz) Nfmin (dB) at 60GHz
2
150 200 8
150 200 8
320 320 5 5 100 300 330 2.2 3.2 1.65 17
320 320 5 5 100 320 350 1.9 2.9 1.6 18
1
130 250 280 3 4.4 1.8
1
120 275 305 2.5 3.8 1.7 15
ADD
Nfmin (dB) at 94GHz BVceo Jc at Peak Ft (mA/m ) Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known
2
13
2011
2012
2013
2014
2015
2016
100 150 12 700 0.55 0.8 10.8 2.5 4 150 150 12 700 0.5 650 45 11 70 250 8 850 0.75 550 35 8 350 25 6 70 250 3 600 1.5 0.4 16 0.8 12
100 150 12 700 0.55 0.8 10.8 2.5 4 150 150 12 700 0.5 650 45 11
100 150 12 700 0.55 0.8 10.8 2.5 4 150 150 12 700 0.5 650 45 11 150 150 12 700 0.5 650 45 11 150 150 12 700 0.5 650 45 11 150 150 12 700 0.5 650 45 11
delayed start of 100 nm until 2010 delayed start of 100 nm until 2010 delayed start of 100 nm until 2010 delayed start of 100 nm until 2010 delayed start of 100 nm until 2010 delayed start of 100 nm until 2010 delayed start of 100 nm until 2010 delayed start of 100 nm until 2010 delayed start of 100 nm until 2010 deleted 100 nm data; extended 150 through 2016 deleted 100 nm data; extended 150 through 2016 deleted 100 nm data; extended 150 through 2016 deleted 100 nm data; extended 150 through 2016 deleted 100 nm data; extended 150 through 2016 deleted 100 nm data; extended 150 through 2016 deleted 100 nm data; extended 150 through 2016 deleted 100 nm data; extended 150 through 2016 70 nm data shifted 2 years out 70 nm data shifted 2 years out 70 nm data shifted 2 years out 70 nm data shifted 2 years out 70 nm data shifted 2 years out 70 nm data shifted 2 years out 70 nm data shifted 2 years out 70 nm data shifted 2 years out 70 nm data shifted 2 years out 70 nm data shifted 2 years out 70 nm data shifted 2 years out
35 420 2 500 2 0.3 18 0.6 14 35 420 2 500 2 0.3 18 0.6 14 25 500 1.5 500 2.2 0.25 20 0.5 16
70 250 8 850 0.8 550 40 9 350 30 7 50 350 2.5 550 1.8 0.3 17 0.6 13
70 250 8 850 0.8 550 40 9 350 30 7 50 350 2.5 550 1.8 0.3 17 0.6 13
shift 2 yrs. right; color changed for 35 nm data shift 2 yrs. rigth shift 2 yrs. right; color changed for 35 nm data shift 2 yrs. rigth shift 2 yrs. right; color changed for 35 nm data shift 2 yrs. right; color changed for 35 nm data shift 2 yrs. right; color changed for 35 nm data shift 2 yrs. right; color changed for 35 nm data shift 2 yrs. right; color changed for 35 nm data
1.3 9 70 400 3 600 1.5
1.1 11 70 400 3 600 1.5
1.1 11 50 450 2.5 600 1.7
1 12 50 450 2.5 600 1.7
1 12 50 450 2.5 600 1.7
0.9 14 50 450 2.5 600 1.7
shift 2 yrs. right; color changed for 35 nm data shift 2 yrs. right; color changed for 35 nm data shifted right 1 yr. and color changed for first 2 years @ 50 nm shifted right 1 yr. and color changed for first 2 years @ 50 nm shifted right 1 yr. and color changed for first 2 years @ 50 nm shifted right 1 yr. and color changed for first 2 years @ 50 nm shifted right 1 yr. and color changed for first 2 years @ 50 nm shifted right one year shifted right one year shifted right one year
400 50 14 200 40 10 70 250 70 4 900 1.4 0.4 16 0.7 12 1.2 10 100 35 250 10 850 1 850 50 14 70 43 300 9 900 1.4
400 50 14 200 40 10 70 250 70 4 900 1.4 0.4 16 0.7 12 1.2 10 100 35 250 10 850 1 850 50 14 200 40 11 50 350 70 3 950 1.5 0.3 17 0.6 14 1 12 70 35 300 9 900 1.2 900 55 15 200 40 11 50 350 70 3 950 1.5 0.3 17 0.6 14 1 12 70 35 300 9 900 1.2 900 55 15 50 35 325 9 950 1.5 200 40 11 50 350 70 3 950 1.5 0.3 17 0.6 14 1 12 70 35 300 9 900 1.2 900 55 15 50 35 325 9 950 1.5 200 40 11 35 420 70 2.5 950 1.8 0.2 18 0.4 15 0.8 13 70 35 300 9 900 1.2 900 55 15 50 35 325 9 950 1.5
shifted right one year shifted right one year shifted right one year shifted right one year shifted right one year shifted right one year no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right
70 43 300 9 900 1.4
50 35 325 9 950 1.5
550 45 9 300 35 7 100 160 35 1300 0.55 1 12 150 150 80 1200 0.5 6000 50 10 100 200 60 1200 0.55 4500 30 8.5 3000 25 6.5
550 45 9 300 35 7 70 200 30 1400 0.6 0.8 13 150 150 80 1400 0.6 7000 50 12 70 240 40 1500 0.65 5000 35 9 3500 30 7
600 55 10 350 45 8 70 200 30 1400 0.6 0.8 13 150 150 80 1400 0.6 8000 50 12 70 240 60 1500 0.65 5000 35 9.5 4000 30 7.5
600 55 10 350 45 8 50 240 25 1400 0.65 0.6 14 150 150 80 1400 0.6 8000 50 12 70 240 60 1500 0.65 5000 35 9.5 4000 30 7.5
600 55 10 350 50 9 50 240 25 1400 0.65 0.6 14 150 150 80 1400 0.6 8000 50 12 50 280 40 1500 0.65 4500 40 10 3500 35 8
600 55 10 350 50 9 50 240 25 1400 0.65 0.6 14 150 150 80 1400 0.6 8000 50 12 50 280 40 1500 0.65 4500 40 10 3500 35 8
no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right
data changed
1 7.5 27 330 410 1.6 3.2 4.3
1 6.5 24 370 460 1.5 3.0 4.1
0.95 5.5 22 400 510 1.4 3.0 4.0
0.9 5 20 440 560 1.4 2.9 3.9
0.9 6 18 490 630 1.3 2.7 3.8
0.9 6 17 520 670 1.3 2.7 3.7
following FEP, PIDS changes
matched published data and used more-physical scaling model added 94GH Nfmin starting in 2013
matched published data and used more-physical scaling model
250
250
250
130
130
130
no change in data but shifted one year to the right
400 560 4
400 560 4 10 90 360 390 1.5 2.3 1.5 21
400 560 4 10 90 380 410 1.4 2.1 1.45 22
560 800 3 20 90 395 425 1.3 2.0 1.4 23
560 800 3 20 80 415 445 1.2 1.8 1.35 24
560 800 3 20 80 430 460 1.1 1.7 1.35 25
no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right no change in data but shifted one year to the right
10
100 340 370 1.7 2.6 1.55 19
xtended 150 through 2016
hanged for 35 nm data
hanged for 35 nm data hanged for 35 nm data hanged for 35 nm data hanged for 35 nm data
hanged for 35 nm data hanged for 35 nm data
olor changed for first 2 years @ 50 nm
hifted one year to the right
hifted one year to the right hifted one year to the right
hifted one year to the right hifted one year to the right hifted one year to the right hifted one year to the right hifted one year to the right hifted one year to the right
a and used more-physical scaling model
a and used more-physical scaling model
Table RFAMS8 RF and Analog Mixed-Signal RFMEMS

Year of Production Design Tools BAW Resonator Switchcapacitive contact Switchmetal contact All MEMS devices 2007 2008 2009
(0) Separate tools (0) Separate tools
(1) IRFM, (2) CM (1) IRFM, (2) CM (1) IRFM (1) IRFM (4) MEMS TCAD (4) MEMS TCAD
(3) DF (3) DF
(0) Separate tools, (2) CM (0) Separate tools, (2) CM
Packaging BAW Resonator Switchcapacitive contact Switchmetal contact
Die stacking.
Wafer level package. Micro cavity package (CWS). Stacked die Above IC integration with CWS Above IC integration with CWS
Performance Driver BAW
F= 900MHz to 2.5GHz. size and cost ; TCF=-20 ppm/K; K2*Q=100
F= 900MHz to 5GHz. Testability improved. TCF= -5ppm; K2*Q=150
Resonator Switchcapacitive contact t Switchmetal contact
Real Time Clock (32 kHz)
Clock oscillator (10-100MHz) multi-frequency per die.
Cellular Frontend (Tuning): 20:1 tuning ratio, 40V actuation Cellular Frontend (Tuning, T/R): Insertion loss <0.3dB, lifetime >1e10 cycles
Cost Driver BAW Resonator Switchcapacitive contact Switchmetal contact
Die size / package MEMS processing cost

Packaging
Processing cost. Die size / microcavity package. Test. Process cost. Reliability / size / microcavity package. Test.
NOTES: Design Tools (0) Separate Tools - Mechanical and RF simulation tools not integrated. Manual integration with package and IC. Design Tools (1) IRFM - integrated RF and mechanical 3D simulation tools Design Tools (2) CM - physically based compact models i.e. simplified versions of IRFM Design Tools (3) DF - Design flow e.g. circuit level simulation, that includes IRFM Design Tools (4) MEMS TCAD-like 3D process sequence simulation tool to simulate deposition, roughness, thermal, underetch, etc Packaging CWS = cap wafer seal (die to wafer, or wafer to wafer) Packaging TFS = thin film seal (e.g. a thin film "pinch-off" technique)
2010
2011
2012
2013
(3) DF (3) DF (3) DF (3) DF
DF + MEMS TCAD
Micro cavity package (CWS).
Above IC integration and TFS
egration with CWS
egration with CWS
Integration into IC and TFS Embedded integration into IC and TFS Embedded integration into IC and TFS
Coupled Resonator Filter (CRF) increase functionality (e.g., impedance match).
F= 900MHz to 10GHz. Built In Self Test (BIST) structure. Tunable filter? TCF= -1ppm; K2*Q=200
cillator (10-100MHz) multi-frequency per die.
Nano resonator for filter function (800MHz2.5GHz) Cellular Frontend (Tuning): 30:1 tuning ratio, low-voltage actuation Cellular Frontend (Tuning, T/R): Insertion loss <0.2dB, lifetime >1e11 cycles
: 20:1 tuning ratio, 40V actuation
Insertion loss <0.3dB, lifetime >1e10 cycles
ze / package
Integration with semiconductor die Integration with semiconductor die Integration with semiconductor die Integration with semiconductor die
e / microcavity package. Test.
size / microcavity package. Test.
integration with package and IC.
, roughness, thermal, underetch, etc
Table PIDS1
Difficult Challenges 22 nm 1. Scaling of MOSFETs to the 22 nm technology generation
Process Integration Difficult ChallengesNear-term Y

Summary of Issues
Scaling planar bulk CMOS will face significant challenges due to the high chann required, band-to-band tunneling across the junction and gate-induced drain leak random doping variations, and difficulty in adequately controlling short channel e Also, keeping parasitics, such as series source/drain resistance with very shallow and fringing capacitance, within tolerable limits will be significant issues.
Implementation into manufacturing of new structures such as ultra-thin body full silicon-on-insulator (SOI) and multiple-gate (e.g., FinFET) MOSFETs is expected point. This implementation will be challenging, with numerous new and difficult particularly challenging issue is the control of the thickness and its variability for thin MOSFETs, as well as control of parasitic series source/drain resistance for v regions. 2. With scaling, difficulties in inducing adequate strain for enhanced mobility.
With scaling, it is critically important to maintain (or even increase) the current s enhanced CMOS channel mobility attained by applying strain to the channel. Ho strain due to current process-induced strain techniques tends to decrease with sca Multiple major changes are projected over the next seven years, such as.: Material: high- gate dielectric, metal gate electrodes, lead-free solder
3. Timely assurance for the reliability of multiple and rapid material, process, and structural changes
Process: elevated S/D (selective epi) and advanced annealing and doping techniq
Structure: ultra-thin body (UTB) fully depleted (FD) SOI, multiple-gate MOSFET chip package modules
4. Scaling of DRAM and SRAM to the 22 nm technology generation
It will be an important challenge to ensure the reliability of all these new mater processes, and structures in a timely manner. DRAM main issues with scalingadequate storage capacitance for devices with feature size, including difficulties in implementing high- storage dielectrics; acc design; holding the overall leakage to acceptably low levels; and deploying low sh resistance materials for bit and word lines to ensure desired speed for scaled DRA
SRAMDifficulties with maintaining adequate noise margin and controlling key instabilities and soft error rate with scaling. Also, difficult lithography and etch is scaling. 5. Scaling high-density non-volatile memory to the 22 nm technology generation
FlashNon-scalability of tunnel dielectric and interpoly dielectric. Dielectric ma properties and dimensional control are key issues. FeRAMContinued scaling of stack capacitor is quite challenging. Eventually, c scaling in 1T1C configuration. Sensitivity to IC processing temperatures and con
Difficult Challenges<22 nm 6. Implementation of advanced, non-classical CMOS with enhanced drive current and acceptable control of short channel effects for highly scaled MOSFETs
MRAMMagnetic material properties and dimensional control. Sensitivity to IC temperatures and conditions Summary of Issues
Advanced non-classical CMOS (e.g., multiple-gate MOSFETs) with ultra-thin, li body will be needed to scale MOSFETs to 10 nm gate length and below effective of parasitic resistance and capacitance will be critical.
To attain adequate drive current for the highly scaled MOSFETs, quasi-ballistic o with enhanced thermal velocity and injection at the source end appears to be need Eventually, nanowires, carbon nanotubes, or other high transport channel materia germanium or III-V thin channels on silicon) may be needed.
Difficult Challenges<22 nm 6. Implementation of advanced, non-classical CMOS with enhanced drive current and acceptable control of short channel effects for highly scaled MOSFETs
MRAMMagnetic material properties and dimensional control. Sensitivity to IC temperatures and conditions Summary of Issues
Advanced non-classical CMOS (e.g., multiple-gate MOSFETs) with ultra-thin, li body will be needed to scale MOSFETs to 10 nm gate length and below effective of parasitic resistance and capacitance will be critical.
To attain adequate drive current for the highly scaled MOSFETs, quasi-ballistic o with enhanced thermal velocity and injection at the source end appears to be need Eventually, nanowires, carbon nanotubes, or other high transport channel materia germanium or III-V thin channels on silicon) may be needed. 7. Dealing with fluctuations and statistical process variations in sub-11 nm gate length MOSFETs 8. Identifying, selecting, and implementing new memory structures
Fundamental issues of statistical fluctuations for sub-10 nm gate length MOSFET completely understood, including the impact of quantum effects, line edge roughn width variation.
Dense, fast, low operating voltage non-volatile memory will become highly desira
Increasing difficulty is expected in scaling DRAMs, especially scaling down the d equivalent oxide thickness and attaining the very low leakage currents and power that will be required. All of the existing forms of nonvolatile memory face limitations based on materia Success will hinge on finding and developing alternative materials and/or develop alternative emerging technologies. See Emerging Research Devices section for more detail. 9. Identifying, selecting, and implementing novel interconnect schemes
Eventually, it is projected that the performance of copper/low- interconnect wil inadequate to meet the speed and power dissipation goals of highly scaled ICs. Solutions (optical, microwave/RF, etc.) are currently unclear. For detail, refer to ITRS Interconnect chapter.
10. Eventually, identification, selection, and implementation of advanced, non-CMOS devices and architectures for advanced information processing
Will drive major changes in process, materials, device physics, design, etc.
Performance, power dissipation, etc., of non-CMOS devices need to extend well b CMOS limits. Non-CMOS devices need to integrate physically or functionally into a CMOS pla integration may be difficult. See Emerging Research Devices sections for more discussion and detail.
cult ChallengesNear-term Years
mary of Issues
nificant challenges due to the high channel doping the junction and gate-induced drain leakage (GIDL), in adequately controlling short channel effects. ource/drain resistance with very shallow extensions e limits will be significant issues.
ew structures such as ultra-thin body fully depleted gate (e.g., FinFET) MOSFETs is expected at some enging, with numerous new and difficult issues. A rol of the thickness and its variability for these ultraasitic series source/drain resistance for very thin
maintain (or even increase) the current significantly ned by applying strain to the channel. However, the ain techniques tends to decrease with scaling.
over the next seven years, such as.:
ate electrodes, lead-free solder advanced annealing and doping techniques
epleted (FD) SOI, multiple-gate MOSFETs, multi-
sure the reliability of all these new materials, manner. uate storage capacitance for devices with reduced lementing high- storage dielectrics; access device ceptably low levels; and deploying low sheet es to ensure desired speed for scaled DRAMs.
dequate noise margin and controlling key ng. Also, difficult lithography and etch issues with
ric and interpoly dielectric. Dielectric material ey issues. pacitor is quite challenging. Eventually, continued ty to IC processing temperatures and conditions.
and dimensional control. Sensitivity to IC processing
mary of Issues
ultiple-gate MOSFETs) with ultra-thin, lightly doped to 10 nm gate length and below effectively. Control will be critical.
highly scaled MOSFETs, quasi-ballistic operation ction at the source end appears to be needed. s, or other high transport channel materials (e.g., con) may be needed.
and dimensional control. Sensitivity to IC processing
mary of Issues
ultiple-gate MOSFETs) with ultra-thin, lightly doped to 10 nm gate length and below effectively. Control will be critical.
highly scaled MOSFETs, quasi-ballistic operation ction at the source end appears to be needed. s, or other high transport channel materials (e.g., con) may be needed.
ions for sub-10 nm gate length MOSFETs are not pact of quantum effects, line edge roughness, and
olatile memory will become highly desirable
ng DRAMs, especially scaling down the dielectric the very low leakage currents and power dissipation
memory face limitations based on material properties. oping alternative materials and/or development of
for more detail.
mance of copper/low- interconnect will become dissipation goals of highly scaled ICs.
are currently unclear.
apter.
terials, device physics, design, etc.
non-CMOS devices need to extend well beyond
ysically or functionally into a CMOS platform. Such
s for more discussion and detail.
Table PIDS2 High-performance Logic Technology Requirements

Grey cells delineate one of two time periods: either before initial production ramp has started for ultra-thin body fully depleted (UTB FD) SOI or double-gate (DG) MOSFETs, or beyond when planar bulk or UTB FD MOSFETs have reached the limits of practical scaling (see the text and the table notes for further discussion). Year of Production MPU/ASIC Metal 1 (M1) Pitch (nm) (contacted) WAS IS L g : Physical Lgate for High Performance logic (nm) [1] L g : Physical Lgate for High Performance logic (nm) [1] EOT: Equivalent Oxide Thickness [2] Extended planar bulk () UTB FD () DG () Gate Poly Depletion and Inversion-Layer Equivalent Thickness [3] IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS Extended Planar Bulk () UTB FD () DG () EOT elec : Electrical Equivalent Oxide Thickness in inversion [4] Extended Planar Bulk () UTB FD () DG () J g,limit : Maximum gate leakage current density [5] Extended Planar Bulk (A/cm2) UTB FD (A/cm2) DG (A/cm2) V dd : Power Supply Voltage (V) [6] Extended Planar Bulk (V) UTB FD and DG (V) V t,sat : Saturation Threshold Voltage [7] Extended Planar Bulk (mV) UTB FD (mV) DG (mV) I sd,leak : Source/Drain Subthreshold Off-State Leakage Current [8] Extended Planar Bulk (A/m) UTB FD (A/m) DG (A/m) I d,sat : NMOS Drive Current [9] Extended Planar Bulk (A/m) UTB FD (A/m) DG (A/m) Mobility enhancement factor due to strain [10] I d,sat enhancement factor due to strain [11] IS IS IS Extended Planar Bulk UTB FD DG 1.07 1.11 1.1 1.09 1.08 1.08 1.07 1.09 1.07 1.09 1.06 1.04 1.08 1.06 1.04 1.06 1.04 1.05 1.03 1.05 1.03 1.03 1.03 1.03 1006 1317 1370 1333 1639 1807 1948 1816 1970 1793 1970 1930 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1762 1944 1943 1.8 2123 2220 1.8 2197 2309 1.8 2181 2344 1.8 2395 1.8 2627 1.8 2533 1.8 0.13 0.17 0.46 0.71 0.7 0.64 0.33 0.69 0.43 0.71 0.57 0.27 0.68 0.62 0.34 0.56 0.37 0.55 0.38 0.57 0.38 0.4 0.44 0.48 225 196 175 168 94 103 103 102 96 107 88 110 112 87 105 94 104 97 106 99 109 111 110 109 1.1 1.1 1.07 1 1 1 1 0.975 1 0.925 0.95 0.9 0.9 0.9 0.9 0.9 0.8 0.8 0.7 450 650 830 900 1000 1100 1100 1200 1200 1300 1300 1300 1400 1400 1400 1500 1500 1700 1700 1900 1900 2100 2200 2500 19.4 13.3 12.7 11.9 10.4 9.3 11 8.75 10.5 7.95 9.8 11.5 7.6 9.5 11 9 10 9 10 9 10 9.9 9.5 9.5 7.4 3.3 3.2 3.1 2.9 2.8 4 2.75 4 2.65 4 4 2.6 4 4 4 4 4 4 4 4 4 4 4 2008 59 22 29 2009 52 20 27 2010 45 18 24 2011 40 16 22 2012 36 14 20 2013 32 13 18 2014 28 11 17 2015 25 10 15 2016 22 9 14 2017 20 8 12.8 2018 18 7 11.7 2019 16 6 10.7 2020 14 5.5 9.7 2021 13 5 8.9 2022 11 4.5 8.1
IS IS IS
12
10
9.5
8.8
7.5
6.5 7
6 6.5
5.3 6.8 7.7
5 5.5 7 5 6 5 6 5 6 5.9 5.5 5.5
Effective Ballistic Enhancement Factor, Kbal [12] IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS Extended Planar Bulk UTB FD DG R sd : Effective Parasitic series source/drain resistance [13] Extended Planar Bulk (-m) UTB FD (-m) DG (-m) C g,ideal : Ideal NMOS Device Gate Capacitance [14] Extended Planar Bulk (fF/m) UTB FD (F/m) DG (F/m) C g,total : Total gate capacitance for calculation of CV/I [15] Extended Planar Bulk (fF/m) UTB FD (F/m) DG (F/m) =CV/I: NMOSFET intrinsic delay (ps) [16] Extended Planar Bulk (ps) UTB FD (ps) DG (ps) 1/: NMOSFET intrinsic switching speed (GHz) [17] Extended Planar Bulk (GHz) UTB FD (GHz) DG (GHz) Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known 1268 1368 1565 1679 1961 2174 2439 2250 2610 2413 3002 3195 2500 3226 3448 3649 3938 4076 4441 4472 5000 5890 6667 7692 0.79 0.73 0.64 0.60 0.51 0.46 0.41 0.45 0.39 0.42 0.34 0.32 0.4 0.31 0.29 0.28 0.26 0.25 0.23 0.22 0.2 0.17 0.15 0.13 0.721 0.875 0.818 0.794 0.843 0.840 0.808 0.838 0.765 0.814 0.700 0.640 0.793 0.678 0.629 0.650 0.621 0.609 0.583 0.570 0.550 0.520 0.507 0.481 0.515 0.700 0.652 0.637 0.663 0.670 0.565 0.671 0.559 0.652 0.530 0.450 0.633 0.508 0.439 0.490 0.441 0.449 0.404 0.410 0.370 0.340 0.327 0.291 200 200 200 200 200 180 180 180 180 180 180 180 180 180 180 170 170 160 160 160 160 160 160 150 1 1 1 1 1 1 1.05 1 1.08 1 1.13 1.21 1 1.16 1.25 1.2 1.32 1.23 1.35 1.25 1.42 1.57 1.67 1.87
Table PIDS3a and b Low Standby Power Technology Requirements

Grey cells delineate one of two time periods: either before initial production ramp has started for ultra-thin body fully depleted (UTB FD) SOI or double-gate (DG) MOSFETs, or beyond when planar bulk or UTB FD MOSFETs have reached the limits of practical scaling (see the text and the table notes for further discussion). Year in Production MPU/ASIC Metal 1 (M1) Pitch (nm) (contacted) L g : Physical Lgate for High Performance logic (nm) [1] L g : Physical gate length for LSTP [1] IS IS Extended Planar Bulk and DG (nm) 38 32 UTB FD (nm) EOT: Equivalent Oxide Thickness [2] Extended planar bulk () 16 15 UTB FD () DG () Gate Poly Depletion and Inversion-Layer Equivalent Thickness [3] Extended planar bulk () 6.0 3.4 UTB FD () DG () EOT elec : Electrical Equivalent Oxide Thickness in inversion [4] IS IS IS Extended planar bulk () UTB FD () DG () Extended Planar Bulk (mA/cm2) UTB FD (A/cm2) DG (A/cm2) V dd : Power Supply Voltage (V) [6] IS IS Extended Planar Bulk (V) UTB FD (V) DG (V) V t,sat : Saturation Threshold Voltage [7] IS IS Extended Planar Bulk (mV) UTB FD (mV) DG (mV) Extended Planar Bulk (pA/m) UTB FD (A/m) DG (A/m) I d,sat : NMOS Drive Current [9] IS IS IS Extended Planar Bulk (A/m) UTB FD (A/m) DG (A/m) Mobility enhancement factor due to strain [10] Extended Planar Bulk UTB FD and DG I d,sat enhancement factor due to strain [11] IS IS Extended Planar Bulk UTB FD DG 1.17 1.16 1.17 1.17 1.16 1.17 1.07 1.07 1.07 1.05 1.08 1.04 1.07 1.04 499 501 528 542 560 519 669 744 786 702 771 738 838 839 567 535 535 544 552 547 399 401 404 366 404 366 405 371 1.1 1 1 1 1 0.95 0.9 0.9 0.85 0.8 0.8 0.8 0.8 0.8 22 18.4 17.3 16.2 15.1 14.1 16 15 14 15 13 15 12 14 29 27 22 18 20 11 12 17 18 15 17 14.0 16 12.8 15 11.7 10.7 9.7 8.9 8.1 2008 59 29 2009 52 27 2010 45 24 2011 40 22 2012 36 20 2013 32 18 2014 28 17 2015 25 15 2016 22 14 2017 20 12.8 2018 18 11.7 2019 16 10.7 2020 14 9.7 2021 13 8.9 2022 11 8.1
14
13
12
IS IS IS IS IS
11
10 11
9 11
8 10
10
3.3
3.2
3.1
3.1 4
4 4
4 4
4 4
14
13
13
12
12
J g,limit : Maximum gate leakage current density [5] 81 94 110 120 140 IS IS 150 150 170 180 190 190 210 200 230
250
270
300
330
380
0.8
0.75
0.75
0.7
0.7
365
374
378
369
376
I sd,leak : Source/Drain Subthreshold Off-State Leakage Current [8] 30.3 30.5 30.7 30.2 30.2 IS IS 30.3 30.9 31.7 30.2 26.5 31.0 29.7 32.7 25.5
33.8
26.2
23.9
33.8
28.9
889
895
935
934
946
1.8
1.8
1.8
1.8
1.8
IS
1.8 1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.04
1.04
1.04
1.04
1.04
IS IS
Effective Ballistic Enhancement Factor [12] Extended Planar Bulk UTB FD DG Extended Planar Bulk (-m) UTB FD (-m) DG (-m) Extended Planar Bulk (fF/m) UTB FD (F/m) DG (F/m)
1 1
1.1 1.1
1.15 1.15
1.18 1.22
1.27
1.4
1.45
1.5
1.55
R sd : Effective Parasitic series source/drain resistance [13] 180 180 180 180 180 IS IS IS IS IS IS IS IS 180 200 180 160 200 150 200 150 180
180
170
160
140
140
C g,ideal : Ideal NMOS Device Gate Capacitance [14] 0.581 0.601 0.558 0.532 0.502 0.490 0.431 0.414 0.419 0.368 0.425 0.322 0.431 0.320
0.296
0.292
0.265
0.259
0.230
C g,total : Total gate capacitance for calculation of CV/I [15] Extended Planar Bulk (fF/m) 0.791 UTB FD (F/m) DG (F/m) =CV/I: NMOSFET intrinsic delay (ps) [16] Extended Planar Bulk (ps) 1.74 UTB FD (ps) DG (ps) 1/: NMOSFET intrinsic switching speed (GHz) [17] Extended Planar Bulk (GHz) 575 UTB FD (GHz) DG (GHz) 0.821 0.768 0.732 0.692 0.670 0.671 0.654 0.639 0.608 0.625 0.562 0.631 0.560
0.526
0.502
0.465
0.449
0.420
1.64
1.46
1.35
1.24
IS IS
1.23 0.9
0.79
0.69 0.69
0.65 0.61
0.6 0.53
0.47
0.42
0.37
0.34
0.31
610
685
741
806
IS IS
813 1111
1266
1449 1449
1538 1639
1667 1887
2128
2381
2703
2941
3226
Table PIDS3c and d Low Operating Power Technology Requirements

Grey cells delineate one of two time periods: either before initial production ramp has started for ultra-thin body fully depleted (UTB FD) SOI or double-gate (DG) MOSFETs, or beyond when planar bulk or UTB FD MOSFETs have reached the limits of practical scaling (see the text and the table notes for further discussion). Year in Production MPU/ASIC Metal 1 (M1) Pitch (nm) (contacted) Lg: Physical Lgate for High Performance logic (nm) [1] L g : Physical gate length for LOP (nm) [1] L g : Physical gate length for LOP (nm) [1] 2008 59 29 28 32 2009 52 27 25 29 2010 45 24 22 27 2011 40 22 20 24 2012 36 20 18 22 2013 32 18 16 18 2014 28 17 14 17 2015 25 15 13 15 2016 22 14 11 14 2017 20 12.8 10 12.8 2018 18 11.7 9 11.7 2019 16 10.7 8 10.7 2020 14 9.7 7 9.7 2021 13 8.9 6.5 8.9 2022 11 8.1 6 8.1
IS
WAS
IS
IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS
EOT: Equivalent Oxide Thickness [2] Extended planar bulk () 12 11 UTB FD () DG () Gate Poly Depletion and Inversion-Layer Equivalent Thickness [3] Extended planar bulk () 6.4 3.4 UTB FD () DG () EOT elec : Electrical Equivalent Oxide Thickness in inversion [4] Extended planar bulk () UTB FD () DG () Extended Planar Bulk (A/ cm2) UTB FD (A/ cm2) DG (A/ cm2) V dd : Power Supply Voltage (V) [6] Extended Planar Bulk (V) UTB FD (V) DG (V) V t,sat : Saturation Threshold Voltage [7] Extended Planar Bulk (mV) UTB FD (mV) DG (mV) Extended Planar Bulk (nA/m) UTB FD (A/m) DG (A/m) I d,sat : NMOS Drive Current [9] Extended Planar Bulk (A/m) UTB FD (A/m) DG (A/m) Mobility enhancement factor due to strain [10] I d,sat enhancement factor due to strain [11] 541 634 310 313 0.8 0.8 18.4 14.4
10
10
8 9
8.5
8 8.5
8 8
8 8
7.3 8
7.5
3.4
3.3
3.3
3.2 4
4 4
4 4
4 4
4 4
13.4
13.3
12.3
11.2 13
12.5
12 12.5
12 12
11.9 12
11.4 12
11.7
11
11
11
J g,limit : Maximum gate leakage current density [5] 78 86 95 100 110 140 140 150 170 170 180 180 200 200 220 220 230 260 280 310
0.8
0.77
0.7
0.7 0.7
0.65
0.6 0.6
0.6 0.6
0.59 0.6
0.54 0.6
0.57
0.5
0.5
0.5
322
336
259
249 209
202
199 202
202 201
201 202
193 202
198
190
194
190
I sd,leak : Source/Drain Subthreshold Off-State Leakage Current [8] 9.08 7.78 7.89 12.1 18.3 35.7 11.9 16.1 19.4 9.66 18.6 10.7 21.5 11.2 31.0 12.4
15.9
21.4
20.0
24.9
651
600
682
760 788
768
755 790 1.8
763 826 1.8
801 895 1.8
749 908 1.8
884 1.8
821 1.8
855 1.8
895 1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS IS
Extended Planar Bulk UTB FD DG Effective Ballistic Enhancement Factor [12] Extended Planar Bulk UTB FD DG Extended Planar Bulk (-m) UTB FD (-m) DG (-m) Extended Planar Bulk (fF/m) UTB FD (F/m) DG (F/m)
1.15
1.15
1.15
1.15
1.11
1.09 1.07
1.07
1.07 1.05
1.06 1.05
1.06 1.04
1.06 1.04
1.04
1.04
1.04
1.04
1 1
1.05
1.1 1.17
1.1 1.18
1.16 1.25
1.21 1.26
1.29
1.37
1.43
1.45
R sd : Effective Parasitic series source/drain resistance [13] 190 190 190 190 190 190 190 185 175 180 170 180 165 170 162 170
166
154
149
141
C g,ideal : Ideal NMOS Device Gate Capacitance [14] 0.601 0.653 0.663 0.636 0.613 0.554 0.478 0.469 0.431 0.414 0.402 0.402 0.368 0.368 0.335 0.336
0.315
0.304
0.279
0.254
C g,total : Total gate capacitance for calculation of CV/I [15] Extended Planar Bulk (fF/m) 0.789 UTB FD (F/m) DG (F/m) = CV/I: NMOSFET intrinsic delay (ps) [16] Extended Planar Bulk (ps) 1.17 UTB FD (ps) DG (ps) 1/: NMOSFET intrinsic switching speed (GHz) [17] Extended Planar Bulk (GHz) 857 UTB FD (GHz) DG (GHz) 0.869 0.867 0.789 0.813 0.754 0.688 0.674 0.631 0.654 0.602 0.643 0.550 0.608 0.529 0.576
0.546
0.511
0.478
0.445
1.10
1.07
1.01
0.83
0.69 0.61
0.57
0.5 0.5
0.47 0.47
0.41 0.41
0.38 0.38
0.35
0.31
0.28
0.24
912
939
988
1205
1449 1639
1763
2008 2008
2128 2128
2473 2473
2660 2660
2882
3259
3631
4107
Table PIDS4
Year in Production
DRAM Technology Requirements

2007 68 0.0277 1.2 0.65 5.7 RCAT 5 3 yes 6 6 0.56 64 1000 1.3 3.2 P+Poly/W SiON 100 500 0.4 220 -0.45
2
2008 58 0.0202 0.9 0.65 7.2 RCAT 5 2.8 yes 5.6 6 0.56 64 1000 1.2 3 P+Poly/W SiON 90 465 0.4 210 -0.4
2009 50 0.015 0.8 0.6 7.5 RCAT 4.5 2.7 yes 6 6 0.56 64 1000 1.1 2.6 P+Poly/W SiON 75 470 0.38 220 -0.38
2010 45 0.0122 0.6 0.6 10 FinFET 4 2.7 yes 6.75 6 0.56 64 1000 1.1 2.6 P+Poly/W SiON 75 450 0.37 210 -0.38
DRAM Pitch (nm) [1] DRAM cell size (m ) [2] DRAM storage node cell capacitor dielectric: equivalent oxide thickness EOT (nm) [3] DRAM storage node cell capacitor voltage (V) [4] Equivalent Electric field of capacitor dielectric, (MV/cm) [5] DRAM cell FET structure [6] DRAM cell FET dielectric: equivalent oxide thickness, EOT (nm) [7] Maximum Wordline (WL) level (V) [8] Negative Wordline (WL) use [9] Equivalent Electric field of cell FET device dielectric (MV/cm) [10] Cell Size Factor: a [11] Array Area Efficiency [12] Minimum DRAM retention time (ms) [13] DRAM soft error rate (fits) [14] V int (support FET voltage) [V] [15] Support nMOS EOT [nm] [16] Support PMOS Gate Electrode [17] Support Gate Oxide [18] Support min. L gate for NMOS FET, physical [nm] [19] Support I sat-n [A/m] (25C, V g =V d =V int ) [20] Support min. V tn (25C, G m,max , V d =55mV) [21] Support I sat-p [A/m] (25C, Vg=V d =-V int ) [22] Support min. V tp (25C, G m,max , V d =55mV) [23]
Notes for Table PIDS4a and b:
[1] From ORTC (Overall Roadmap Technology Characteristics) Table 1a and b. These DRAM half pitch numbers are the same as those in the 2006 ITRS d pace of DRAM half pitch scaling during 2006.
[2] The DRAM cell size is driven by the values for DRAM capacity (bits per chip) and chip size, as discussed in more detail in the Front End Process chap numbers are based on the ORTC Tables 1a and 1b. Since the DRAM capacity and chip size numbers are quite aggressive, the cell size must also be scaled
in reducing the value of the cell size factor a, where a equals (cell size /F 2 ) and F is the DRAM half pitch. The required values of a are 6 for 68 nm
[3] Storage node cell dielectric EOT is defined as (dielectric physical thickness / [/3.9]), where is the relative dielectric constant of the storage node cel dielectric constant of thermal SiO 2 . The value of EOT is driven by the values for DRAM capacity (bits per chip) and chip size, as discussed in more detail The capacity and the chip size numbers used by FEP are from the ORTC Tables 1a and 1b. Since the values of DRAM capacity and chip size from FEP are also be scaled very aggressively. Up to 2009, the dielectric material is based on Al 2 O 3 or HfO 2 , and hence the color is white. Beyond 2009, breakthroug higher insulator material of epsilon more than 40 and physical thickness of less than 9nm are needed, so the color is yellow. Finally, for 2012 and beyo with demonstrated credibility, and hence the color is red. The actual EOT required for each year also depends on other factors such as cell height and/or 3 and contact formation.
[4] The DRAM storage node capacitor voltage must be low enough that the resulting electric field in the dielectric (see Note [5]) is within acceptable limit
[5] The equivalent electric field in the capacitor dielectric is (DRAM storage node capacitor voltage / DRAM storage node dielectric equivalent oxide thic the electric field if the dielectric is silicon dioxide; if the dielectric is high- k, the actual electric field is [equivalent field]/[ k /3.9]. Note the sharp increase The color turns yellow in 2009, when the field is 7.5 MV/cm, and red in 2012, when the field becomes 13.75 MV/cm..
[6] DRAM cell MOSFET structure migrates from RCAT (recessed channel array transistor) to FinFET. RCAT is a technology to improve retention time ch recessed channel structure. FinFET is used to increase the drive current in the limited cell FET area and also to improve retention time characteristics.
[7] DRAM cell FET dielectric EOT is defined as (dielectric physical thickness / [/3.9]), where is the relative dielectric constant of the DRAM cell FET d dielectric constant of thermal SiO 2 . The EOT values here are large, mainly because of the high word line voltage levels (see Note 8) and the need to keep within tolerable limits (see Note 9)
[8] Maximum word line level is the (highly boosted) gate voltage for cell FET devices. The high gate voltage is required to get enough device drive current back gate voltage at the operating condition.
[9] Negative word line is used to suppress sub-threshold leakage current of cell transistor even in the case of lower level of V t value of cell FET. The low current of cell FET.
[10] The equivalent electric field in the cell FET device dielectric is (maximum word line level / DRAM cell FET dielectric equivalent oxide thickness, EOT electric field if the dielectric is silicon dioxide; if the dielectric is high- k , the actual field is [equivalent field]/[ k /3.9]. [11] Cell size factor = a = (DRAM cell size/F 2 ), where F is the DRAM pitch. The required values of a are 6 for 2007 and beyond. In contrast, the 2005 8 in 2005, 2006 and 2007.
2
[12] Array area efficiency is the ratio of cell array area to total chip area. Hence, array area efficiency = 1 / (1 + [peripheral circuit area]/NaF ), where of bits per chip), F is the DRAM pitch, and a is the cell size factor (see Note 9). For a = 8, array area efficiency is estimated to be 0.63, so when a is dec area efficiency of 0.56 is made in conjunction with a = 6, assuming the same relative peripheral circuit area.
[13] Retention time is defined at 85C, and is the minimum time during which the data from memory can still be sensed correctly without refreshing a row the value needed for PC applications. The retention time depends on the combined interaction of device leakage current, signal strength, and signal sensin depends on operational frequency and temperature. [14] This is a typical FIT rate and depends on cycle time and the quality of cell capacitor and sensing circuits.
[15] V int is the nominal power supply voltage for DRAM support FET in peripheral circuit area. It has been chosen to maintain sufficient voltage over-dr saturation current drive values while still maintaining reasonable vertical gate dielectric electric field strengths.
[16] DRAM support MOS FET dielectric EOT is defined as (dielectric physical thickness / [/3.9]), where is the relative dielectric constant of the DRAM relative dielectric constant of thermal SiO 2 . [17] Support PMOS FET Gate electrode material migrates from P+Poly/W to TiN.
[18] DRAM support MOS FET dielectric material migrates from SiON to HfSiON in order to leakage current to meet.
[19] Physical support min. L gate for NMOS FET is the final, as-etched length of the bottom of the gate electrode.
[20] Support I sat-n (the saturation drive current for support NMOS FET) is defined as the NMOSFET drain current per micron device width with the gate V int (see Note [15]) and the source and substrate biases set to zero at 25C, namely V g =V d =V int ).
[21] Support min V tn is the saturation threshold voltage measured at 25 C, G m max ,V d =55mV. [22] Support Isat-p (the saturation drive current for support PMOS FET) is defined as the PMOSFET drain current per micron device width with the gate V int (see Note [15]) and the source and substrate biases set to zero at 25C ,namely, V g =V d =-V int ). [23] Support min V tp is the saturation threshold voltage measured at 25 C, G m max ,V d =55mV.
2011 40 0.0096 0.5 0.55 11 FinFET 4 2.7 yes 6.75 6 0.56 64 1000 1.1 2.5 P+Poly/W SiON 65 410 0.37 165 -0.38
2012 36 0.0078 0.4 0.55 13.8 FinFET 4 2.7 yes 6.75 6 0.56 64 1000 1.1 2.2 P+Poly/W SiON 60 430 0.33 170 -0.34
2013 32 0.0061 0.3 0.5 16.7 FinFET 4 2.6 yes 6.5 6 0.56 64 1000 1.1 2 P+Poly/W HfSiON 50 450 0.33 175 -0.34
2014 30 0.0054 0.3 0.5 16.7 FinFET 4 2.6 yes 6.5 6 0.56 64 1000 1 1.8 TiN HfSiON 48 445 0.31 170 -0.32
2015 25 0.0038 0.3 0.45 15 FinFET 4 2.4 yes 6 6 0.56 64 1000 0.9 1.6 TiN HfSiON 40 440 0.31 190 -0.32
2016 22 0.0029 0.3 0.45 15 FinFET 3.5 2.3 yes 6.57 6 0.56 64 1000 0.9 1.5 TiN HfSiON 35 480 0.31 215 -0.32
2017 20 0.0024 0.3 0.4 13.3 FinFET 3.5 2.3 yes 6.57 6 0.56 64 1000 0.9 1.4 TiN HfSiON 31 550 0.31 215 -0.32
2018 18 0.0019 0.3 0.4 13.3 FinFET 3.5 2.3 yes 6.57 6 0.56 64 1000 0.9 1.4 TiN HfSiON 28 550 0.31 215 -0.32
2019 16 0.00154 0.25 0.35 14 FinFET 3.5 2 yes 5.71 6 0.56 64 1000 0.9 1.3 TiN HfSiON 25 550 0.31 215 -0.32
s are the same as those in the 2006 ITRS due to no further speed up in the
more detail in the Front End Process chapter. The capacity and chip size gressive, the cell size must also be scaled aggressively. The difficulty will lie
The required values of a are 6 for 68 nm and beyond.
dielectric constant of the storage node cell dielectric and 3.9 is the relative and chip size, as discussed in more detail in the Front End Process chapter. RAM capacity and chip size from FEP are quite aggressive, the EOT must color is white. Beyond 2009, breakthroughs such as MIM structure with color is yellow. Finally, for 2012 and beyond, there are no known solutions n other factors such as cell height and/or 3D structure, film leakage current
ic (see Note [5]) is within acceptable limits.
rage node dielectric equivalent oxide thickness, EOT). The equivalent field is ent field]/[ k /3.9]. Note the sharp increase in the equivalent field with scaling. cm..
a technology to improve retention time characteristics by introducing improve retention time characteristics.
ielectric constant of the DRAM cell FET dielectric and 3.9 is the relative e levels (see Note 8) and the need to keep the electric field in the dielectric
equired to get enough device drive current with high threshold voltage due to
wer level of V t value of cell FET. The low V t is preferable to get higher drive
dielectric equivalent oxide thickness, EOT). The equivalent field is the
k /3.9].
or 2007 and beyond. In contrast, the 2005 version of the DRAM table has a =
+ [peripheral circuit area]/NaF ), where N is the DRAM capacity (number y is estimated to be 0.63, so when a is decreased to 6 from 2007, the array
sensed correctly without refreshing a row bit line. The 64 ms specified here is current, signal strength, and signal sensing circuit sensitivity, and also
sen to maintain sufficient voltage over-drive in order to meet the required
e relative dielectric constant of the DRAM cell FET dielectric and 3.9 is the
meet.
e.
rent per micron device width with the gate bias and the drain bias set equal to
ent per micron device width with the gate bias and the drain bias set equal to -
2020 14 0.00118 0.2 0.35 17.5 FinFET 3.5 2 yes 5.71 6 0.56 64 1000 0.9 1.3 TiN HfSiON 23 550 0.31 215 -0.32
Table PIDS5 Non-Volatile Memory Technology Requirements Near-term

Year of Production DRAM Pitch (nm) (contacted) MPU/ASIC Metal 1 (M1) Pitch (nm)(contacted) NAND Flash poly 1/2 Pitch (nm) NAND Flash NAND Flash technology node F (nm) [1] Number of word lines in one NAND string [2] Cell type (FG, CT, 3D, etc.) [3] 3D NAND number of memory layers A. Floating Gate NAND Flash Cell size area factor a in multiples of F2 SLC/MLC [4] Tunnel oxide thickness (nm) [5] Interpoly dielectric material [6] Interpoly dielectric thickness (nm) Gate coupling ratio (GCR) [7] Control gate material [8] Highest W/E voltage (V) [9] Endurance (erase/write cycles) [10] Nonvolatile data retention (years) [11] Maximum number of bits per cell (MLC) [12] B. Charge trapping NAND Flash (MANOS or Barrier Engineering) [13] Cell size area factor a in multiples of F2 SLC/MLC Tunnel dielectric material [14] Tunnel dielectric thickness EOT (nm) Blocking dielectric material [15] Blocking dielectric thickness EOT (nm) Charge trapping layer material [16] Charge trapping layer thickness (nm) [17] 4.0/1.0 SiO2 or ONO 3-4 SiO2 or Al2O3 68 SiN 57 4.0/2.0 6-7 ONO 10-13 0.60.7 n-Poly 17-19 1.E+05 10-20 2 4.0/2.0 6-7 ONO 10-13 0.60.7 n-Poly 17-19 1.E+05 10-20 2 4.0/1.3 6-7 ONO 10-13 0.60.7 n-Poly 15-17 1.E+05 10-20 3 4.0/1.0 6-7 ONO 10-13 0.60.7 n-Poly 15-17 1.E+05 10-20 4 51 32 FG 1 45 32 FG 1 40 64 FG 1 36 64 FG/CT 1 2007 65 67 2008 57 60 2009 50 54 2010 45 48
51
45
40
36
Gate material [18]
p-Poly/ Metal 15-17 1.E+05
Highest W/E voltage (V) Endurance (erase/write cycles) [19]
Nonvolatile data retention (years) [20] Maximum number of bits per cell (MLC) NOR Flash NOR Flash technology node F (nm) [21] A. Floating gate NOR Flash Cell size area factor a in multiples of F2 [22], [23], [24], [25] Gate length Lg, physical (nm) [26] Tunnel oxide thickness (nm) [27] Interpoly dielectric material [28] Interpoly dielectric thickness EOT (nm) Gate coupling ratio [29] Highest W/E voltage (V) [30] Iread (A) [31] Endurance (erase/write cycles) [32] Nonvolatile data retention (years) [33] Maximum number of bits per cell (MLC) [34] Array architecture (with cell contact (CC) or virtual ground (VG))[ 35] B. Charge trapping NOR Flash (SONOS/NROM) [36] SONOS/NROM technology node, F (nm) SONOS/NROM cell size - area factor a in multiples of F2 Cell size (per bit) area factor a in multiples of F2 (SLC/MLC) [37] Gate length Lg, physical (nm) [38] Tunnel oxide thickness (nm) [39] Charge trapping layer thickness (nm) [40] Blocking (top) dielectric thickness EOT (nm) [41] Highest W/E voltage (V) Iread (A) [31] Endurance (erase/write cycles) [32] Nonvolatile data retention (years) [33] Maximum number of bits per cell (physical 2-bit/cell + MLC) [37] Non-charge-storage NVM A. FeRAM (Ferroelectric RAM) 65 6-7 3.3/1.6 0.14 5 5-7 79 7-9 25-34 1.00E+05 1020 4 57 6-7 3.3/1.6 0.13 5 5-7 79 7-9 23-31 1.00E+05 1020 4 50 6-7 3.3/1.6 0.12 5 5-7 79 7-9 21-27 1.00E+05 1020 4 9-11 130 89 ONO 13-15 0.60.7 7-9 25-34 1.00E+05 1020 2 9-11 120 89 ONO 13-15 0.60.7 7-9 23-31 1.00E+05 1020 2 9-11 100 89 ONO 13-15 0.60.7 7-9 21-27 1.00E+05 1020 2 65 57 50
10-20 4
45
9-11 90 8 ONO 13-15 0.60.7 7-9 20-26 1.00E+06 1020 2
CC
CC
CC
CC
45 6-7 3.3/1.6 0.11 4.5 4-6 68 6-8 20-26 1.00E+06 1020 4
WAS
FeRAM technology node F (nm) [42]
180
180
180
130
IS
FeRAM technology node F (nm) [42] FeRAM cell size area factor a in multiples of F2 [43] FeRAM cell size ( m2) FeRAM cell structure [44] FeRAM capacitor structure [45]
180 22 0.713 2T2C stack 0.330 0.330 0.330 1.00 1.50 13.5 1.0E+14 10 Years
180 22 0.713 1T1C stack 0.330 0.330 0.330 1.00 1.50 13.5 1E+14 10 Years
180 22 0.713 1T1C stack 0.330 0.330 0.330 1.00 1.50 13.5 1E+14 10 Years
150 20 0.450 1T1C stack 0.200 0.20 0.20 1.00 1.20 20 1E+14 10 Years
WAS IS
FeRAM capacitor footprint (m2) [46] FeRAM capacitor footprint (m2) [46] FeRAM capacitor active area (m2) [47] FeRAM cap active area/footprint ratio [48] Ferro capacitor voltage (V) [49] FeRAM minimum switching charge density (C/cm2) [50] FeRAM endurance (read/write cycles) [51] FeRAM nonvolatile data retention (years) B. MRAM (Magnetic RAM) MRAM technology node F (nm) [52] MRAM cell size area factor a in multiples of F2 MRAM typical cell size (m2) MRAM switching field (Oe) [53] MRAM write energy (pJ/bit) [54] MRAM active area per cell (m2) [55] MRAM resistance-area product (Kohm(m2) [56] MRAM magnetoresistance ratio(%) [57] MRAM nonvolatile data retention (years) MRAM write endurance (read/write cycles) MRAM endurance tunnel junction reliability (years at bias) [58] C. PCRAM (Phase-Change RAM) PCRAM technology node F (nm) [58] PCRAM cell size area factor a in multiples of F2 (BJT access device) [59] PCRAM cell size area factor a in multiples of F2 (nMOSFET access device) [60] PCRAM typical cell size (nm2) (BJT access device) [61] PCRAM typical cell size (nm2) (nMOSFET access device) [62] PCRAM number of bits per cell (MLC) [63]
90 20 0.16 35 70 0.05 2 70 >10 >3e16 >10
65 22 0.09 35 35 0.025 1.1 70 >10 >3e16 >10
65 19 0.08 35 35 0.025 1 70 >10 >3e16 >10
45 20 0.041 35 25 0.013 0.8 70 >10 >3e16 >10
72 4.8
58 4.0
46 4.0
40 4.0
15.0 24883 77760 1
14.0 13456 47096 1
12.0 8464 25392 2
11.0 6400 17600 2
PCRAM typical cell area per bit size (m2) (BJT access device) [64] PCRAM typical cell area per bit size (m2) (nMOSFET access device) [65] PCRAM storage element CD (nm) [66] PCRAM phase change volume (nm3) [67] PCRAM reset current (A) [68] PCRAM set resistance (Kohm) [69] PCRAM BJT current density (A/cm2) [70] PCRAM BJT emitter area (nm2) [71] PCRAM nMOSFET apparent current density for reset (A/nm) [72] PCRAM nMOSFET apparent device width (nm) [73] PCRAM nonvolatile data retention (years) [74] PCRAM write endurance (read/write cycles) [75]
24883
13456
4232
3200
77760 45 373,000 235 3.54 1.50E+07 4072
47096 36 195,000 170 4.57 1.50E+07 2642
12696 30 112,000 130 5.68 1.50E+07 1662
8800 25 64,000 100 7.08 1.50E+07 1257
1.5
1.5
1.8
1.8
239 >10 1.0E+08
171 >10 1.0E+08
108 >10 1.0E+10
82 >10 1.0E+10
Notes for Table PIDS5a and b: [1] NAND Flash has surpassed CMOS and DRAM technology since 2005. This entry provides the F value for designs in the indicated time period.
[2] NAND Flash architecture consists of bit line strings of a number of storage devices. Long bit line strings reduce the overhead for bit line transistors and incr current. The number of word lines in a bit line string has increased from 16 to 32 nm.
[3] Because of the difficulty in maintaining high gate coupling ratio and preventing cross talk between neighboring cells, NAND technology is forecasted to migr for sub 50nm DRAM and NAND Flash manufacturing, in Tech. Digest International Electron Devices Meeting, pp. 539-543, 2005.) The statistical fluctuation li few electron phenomena on floating gate memory reliability, Tech. Digest 2004 International Electron Devices Meeting, pp. 877-880, 2004.) and 3D integra dimensionally stacked NAND Flash memory technology using stacking single crystal Si layers on ILD and TANOS structure for beyond 30nm node, Tech. Dige thin-film transistor (TFT) NAND-type Flash memory, Tech. Digest 2006 International Electron Devices Meeting, pp. 41-44, 2006.)
[4] The area factor a = cell area per bit/F 2 , so this entry presents the expected range for Flash cell area in multiples of the implementation technology F 2 . It to (11, 10, 00, 01), etc. by using multi-level cell (MLC). Therefore, the area factor includes both single-level cell (SLC) and multi-level cell (MLC) devices.
[5] The scaling of tunnel oxide for NAND Flash faces the same challenge as that for NOR Flash. However, the use of error code correction (ECC) in NAND Currently there are no known solutions to scale tunnel oxide significantly below 6 nm.
[6] ONO has been used as the interpoly dielectric (IPD) up to now and will continue in the near future. However, below 40 nm the spacing between floating gates gate to floating gate coupling will severely degrade the gate coupling ratio (GCR) and the device becomes inoperable. Since it is impossible to create additio migrating to high- IPD is shown. It is shown in red color since engineering solutions have not been demonstrated yet.
[7] Gate coupling ratio (GCR) is defined as (control gate to floating gate capacitance)/(total floating gate capacitance). GCR represents the fraction of voltage operations. High GCR is normally achieved by wrapping the control gate around the sidewalls of the floating gate. This requires tall floating gate and the cross the spacing between floating gates may become too narrow for the IPD and control gate to wrap around and maintaining sufficiently high GCR is a difficult chall
[8] n-type polysilicon (and polycide) gate has been used for the control gate so far and will continue in the near future. The introduction of high- IPD, with a material such as p-type polysilicon or metal gate may have to be adopted. [9] Low write and erase voltage is desirable but EOT for tunnel oxide and IPD must be decreased to allow lower W/E voltage without compromising W/E speed.
[10] Write and erase cycling endurance reflects the tunnel oxide damage caused by repeated passing of charges under high electric field. Scaling does not worse reduced. High- IPD may also trap charge and cause degradation. Current projection is gradually reduced cycling endurance for future technology. Note t endurance.
[11] Data retention is controlled by both tunnel oxide integrity and statistical distribution of the number of stored electrons. Both thinner tunnel oxide and fewer n
[12] Multi-level cell (MLC) with 4 logic levels (2-bit/cell) is commonly used for NAND Flash today and devices with 8 logic levels (3-bit/cell) and 16 logic level reach of current technology, thus no forecast is made for 8-bit/cell MLC even in the long-term years.
[13] MANOS (Metal-Al2O3-Nitride-Oxide-Si) devices use a relatively thin tunnel oxide, a SiN trapping layer for charge storage, Al 2O 3 to increase voltage drop novel SONOS structure of SiO 2/SiN/Al 2O 3 with TaN metal gate for multi-giga bit Flash memories, Tech. Digest 2003 International Electron Devices Meeting, p substrate hole tunneling, yet prevents low field hole direct tunneling during retention. (Ref: H.T. Lue, et al., "BE-SONOS: a bandgap engineered SONOS with ex 558, 2005.) Without floating gate GCR and cross talk issues, these two CT approaches promise to help NAND scaling below 30 nm.
[14] Tunnel dielectric for MANOS type device is a relatively thin silicon oxide (3-4nm). Tunnel dielectric for barrier engineered (BE) device may be a composite O
[15] For MANOS device Al 2O 3 is the preferred blocking oxide since it has a high barrier height. Other composite blocking layers such as AN, ANO, or AHO composite layers may also be used.
[16] SiN is the most common and best known charge trapping layer with relatively deep electron traps that provide good data retention. Other exotic high- m speed SiO2/AlGaN/AlLaO3/TaN memory with good retention, Tech. Digest 2005 International Electron Devices Meeting, pp. 165-168, 2005.) Note that for CT d do not necessarily improve data retention except for high temperature applications.
[17] Trapping efficiency in SiN seems thickness dependent. (Ref: H.T. Lue, et al., Proc. 2007 International Reliability Physics Symposium, 2007). Therefor programming efficiency.
[18] High work function metal gate is the best to prevent gate injection. However, p-type polysilicon may become an interim solution because of its easy processin
[19] The mechanism for endurance degradation for CT devices is not well understood yet. Unlike floating gate device, CT devices are not sensitive to tunnel oxid leak out as in floating gate devices. Published endurance data seem to indicate similar endurance as floating gate device.
[20] The mechanism for data retention loss for BE device seems understood. (Ref: H.T. Lue, et al., "Reliability model of bandgap engineered SONOS (BE-SO mechanism for MANOS device is still not well understood. Published data suggest that data retention is comparable to floating gate devices under certain conditio
[21] NOR Flash traditionally falls behind CMOS and DRAM but has caught up in recent years and is now on par with DRAM.
[22] High- interpoly dielectric is projected at 32 nm and beyond to achieve gate coupling ratio of >0.6 but this offers only limited help to the area factor. Technology for sub 70 nm Body Tied FinFET Flash Memory, pp. 208-209.)
[23] Although virtual ground (VG) array may significantly decrease the cell size in the near term years (Ref: 2005 Symposium on VLSI Technology, 11B-1, R. effect has not been included in the current table because VG is radically different from the conventional array and large development effort is needed to implemen
[24] Although non-planar devices (such as FinFET) are being developed for future Flash scaling, their impact has not been included in the current table. The d has not been completely resolved yet.
[25] Both the cell size and the gate length for NOR Flash have been more aggressively scaled recently with an area factor of approximately 10F2. (Refs: 2005 I
55. 2003 Symposium on VLSI Technology, "Highly Manufacturable 90nm NOR Flash Technology with 0.081m 2 Cell Size, pp. 91-92. 2004 Symposium on VLSI
[26] NOR Flash uses channel hot electron programming which requires steep junction profile to generate, with the consequence of difficulties in controlling th
thickness cannot be scaled, controlling the short channel effect imposes a very difficult challenge for scaling. The gate length generally is substantially larger than note 25).
[27] Tunnel oxides must be thick enough to assure retention but thin enough to allow ease of erase/write. This difficult trade-off problem hinders scaling. Tunnel o
[28] ONO has been used as the interpoly dielectric up to now and most likely in the near future. However, at 32 nm and beyond high- IPD may be necessary sidewalls of the floating gate thus increasing the control gate to floating gate capacitor area. At 32 nm or below, the gap between adjacent gloating gates become
[29] The gate coupling ratio (GCR) is the (control gate to floating gate capacitance)/(total floating gate capacitance). GCR must be greater than about 0.6 for pr
[30] This is the highest voltage relative to ground seen in the cell array, usually supplied by on-chip charge pumping circuits. Low voltage is desired to reduce reduce the erase voltage.
[31] In principle the read current decreases with scaling at a rate W/(L*Cox) to prevent voltage overdrive (read disturb). Since access time depends critically o slower than W/(L*Cox) to maintain performance. This may cause read disturb issues in long term years.
[32] E/W endurance requirements vary with the specifics of an application, but 1E5 cycles have been accepted as the historical minimum acceptable level for a us
[33] Retention is a defect related parameter rather than an intrinsic device characteristic. Improvement in defect control and accumulation of device history is e reduced retention specification as a tradeoff for increased E/W endurance.
[34] Cell read out distinguishes between four levels of charge storage to provide two storage bits (Multilevel cell MLC). Progression to 8 or 16 levels is po challenging. Unlike NAND Flash where density is a key competitive advantage, performance and reliability tend to hold higher importance than density for NOR
[35] Virtual ground array uses junction isolation and buried diffusion for bit line, thus requires no STI isolation or bit line contact in the cell. In principle the are contact. The scaling of buried diffusion is a difficult challenge and junction isolation produces more leakage paths and complicates the design. Large R&D effort
[36] Charge trapping device for NOR application uses mainly a SONOS structure and thus often is confused with the conventional SONOS device. Conventiona electrons from the substrate and the charge is stored in the SiN layer of SONOS. Since the electrons are stored in deep SiN traps it is difficult to de-trap by Fowl into the SiN to erase the device. However, such thin tunnel oxide also allows direct tunneling of holes from the substrate even under weak electric field produced
the SONOS problem in a NOR array 15 . Using channel hot electron to program the cell, electrons are stored in the SiN layer near the edge of S/D junctions. T tunnel oxide is adopted and this solves the data retention issue. NROM also has the advantage of storing two bits of information in one device (source side and dr on a virtual ground array architecture and has a relatively small cell size. It is used not only for NOR Flash, but also for some data storage applications even thou
[37] CT NOR SLC Flash stores one bit on the source side and one bit on the drain side, or 2-bit/cell. The MLC Flash stores 2 bits on the source side and two bits
[38] Although physically storing two bits in the same device, the gate length scaling is not limited by left-right bit interference. The scaling is limited by the sa device window, on the other hand, is affected by left-right bit interference and the L g scaling for MLC may be more gradual than SLC.
[39] Because electrons are trapped in deep levels in SiN, the tunnel oxide can be scaled more aggressively than for floating gate device.
[40] Reducing the thickness of charge trapping SiN will reduce the EOT but will degrade trapping efficiency.
[41] Interpoly dielectric must be thick enough to assure retention. [42] This entry is the critical dimension F within the FeRAM cell for stand-alone memory devices (not embedded devices).
[43] This is the area factor a = cell size/F 2 . FeRAM cell size is presented in terms of F 2 multiples of the FeRAM implementation technology.
[44] FeRAM cell structures have migrated to one transistor, one capacitor (1T1C) formats. (Refs. J.H. Park, et al., "Fully Logic Compatible (1.6V Vcc, 2 Additio
Robust 100 nm thick MOCVD PZT Technology", 2004 IEDM, 23.7.1, pp. 591-594. Y. M. Kang et al., "Sub-1.2V Operational, 0.15m/12F 2 Cell FRAM Techno
Other alternative configurations are under investigation such as Chain-FeRAM. (Refs. H. Kanaya et al., "A 0.602m 2 Nestled Chain Cell Structure Formed by Nagel et al., "New Highly Scalable 3 Dimensional Chain FeRAM Cell with Vertical Capacitor, 2004 Symposium on VLSI Technology, pp. 146-147.)
[45] The geometry of the capacitor is a key factor in determining cell size. Stacked planar films are expected to be replaced by more efficient 3D structures.
[46] This is the footprint of the capacitor in micrometers squared. It is this area that constitutes the capacitor area contribution to the cell size. For 20052006 ~1 [47] This is the actual effective area of the capacitor. It is larger than the footprint for 3D capacitor because of the utilization of area in the third dimension.
[48] This ratio of the effective area to the footprint gives a measure of the impact of utilization of the third dimension.
[49] This is the operating voltage (V op ) applied to the capacitor. Low voltage operation is a difficult key design issue. Generally the ferroelectric film thickness n "Highly Reliable 50nm-thick PZT Capacitor and Low Voltage FRAM Device Using Ir/SrRuO 2 /MOCVD PZT Capacitor Technology", 2005 Symposium on VLSI T
[50] The minimum switching charge density in C/cm 2 is a useful design parameter. It is equal to the cell minimum switching charge divided by the capacitor act
[51] FeRAM is a destructive read-out technology, so every read is accompanied by a write to restore the data. Endurance cycles are taken as the sum of all read 1E15. Testing time is a serious concern. Note that operation at 100 MHz for 3 years would accumulate 1E16 cycles.
[52] MRAM devices are expected to lag the CMOS current technology up until 45 nm half pitch in 2010. This entry provides the F value for designs in the indicate
[53] The MRAM switching field is the magnetic intensity H required to change the direction of magnetization of the cell.
[54] MRAM switching energy per bit is calculated as (write current * power supply voltage * write time). It is preferred to use the median value of switching en writes per second). [55] MRAM active bit area is the area of the magnetic material stack within the cell. It represents the A in the R*A product.
[56] MRAM resistance-area product (i.e., the R*A product) is an intrinsic property of the magnetic material stack that provides a convenient basis for comparin (R low ) of the magnetic tunnel junction and multiply it by the active bit area of the magnetic stack. [57] MRAM magnetoresistive ratio is calculated as 100*(R high R low )/R low . This ratio summarizes the difference between a logic ONE and a logic ZERO, and values are to be measured at low currents. [58]This is the critical dimension, F.
[59] The area factor a = cell area/F 2 . This entry is the expected PCRAM cell area in multiples of the implementation technology F 2 . PCRAM requires signif capable of providing more current per unit area compared to a MOSFET, thus helps to reduce the cell size. Both BJT and nMOSFET access device cells are repre
[60] The area factor a = cell area/F 2 . This entry is the expected PCRAM cell area in multiples of the implementation technology F 2 . PCRAM requires signif capable of providing more current per unit area compared to a MOSFET, thus helps to reduce the cell size. An nMOSFET transistor has larger cell size in the ne cells are represented in this table. PCRAM is capable of MLC multi-bit per cell. This area factor is per cell, not per bit. [61] The expected typical PCRAM cell size with BJT access device is presented in micrometers squared. [62] The expected typical PCRAM cell size with nMOSFET access device is presented in micrometers squared.
[63] PCRAM is capable of MLC multi-bit/cell operation since the resistance ratio between amorphous and crystalline state is typically 1001,000. This entry is th
[64] The expected cell size per MLC bit for the PCRAM with BJT cell. It is the physical cell size divided by the number of MLC bits per cell.
[65] The expected cell size per MLC bit for the PCRAM with nMOSFET cell. It is the physical cell size divided by the number of MLC bits per cell.
[66] PCRAM phase change element must be substantially smaller than the technology F to have efficiency reset operation with reasonable current. This entry is th
[67] PCRAM phase change volume is a key factor for device design and peak power requirement. This entry is the expected phase change volume in nanometer cu
[68] This entry is the expected reset current for PCRAM in microamperes.
[69] The set resistance is a key design factor for PCRAM read speed.
[70] This entry is the expected current density output from the BJT access device required to reset the PCRAM cell (from crystalline to amorphous state). It is requires higher operation voltage). [71] This entry is the expected BJT emitter area that can provide the needed reset current, assuming the BJT current density is met.
[72] This entry is the expected current density output from the nMOSFET access device required to reset the PCRAM cell (from crystalline to amorphous stat current (which requires higher operation voltage or less reliable device). [73] This entry is the expected nMOSFET gate width that can provide the needed reset current, assuming the MOSFET output current density is met.
[74] This entry is the expected PCRAM data retention that will allow it to be used as a nonvolatile memory. Data retention mechanism for PCRAM is not yet thor Ahn et al., "Highly Manufacturable High Density Phase Change Memory of 64Mb and Beyond, 2004 IEDM, 37.2, pp. 907-910. A. L. Lacaita et al., "Electrotherm
[75] This entry is the expected PCRAM W/E cycling endurance. Recent published data indicate cycling endurance from 1E+9 to 1E+13. (Refs. S.J. Ahn et al., "H 907-910. S. Lai et al., "Current Status of Phase Change Memory and Its Future, 2003 IEDM, pp. 255-258.)
Long-term
2011 40 42 2012 35 38 2013 32 34 2014 28 30 2015 25 27 2016 22 24 2017 20 21
32
28
25
22
20
19
18
32 64 CT 1
28 64 CT 1
25 64 CT-3D 2
22 64 CT-3D 2
20 64 CT-3D 2
19 64 CT-3D 2
18 64 CT-3D 2
4.0/1.0 6-7 ONO 10-13 0.60.7 n-Poly 15-17 1.E+05 10-20 4
4.0/1.0 6-7 High-K 9-10 0.60.7 Poly/ metal 15-17 1.E+05 10-20 4
4.0/1.0 6-7 High-K 9-10 0.60.7 Metal 15-17 1.E+05 10-20 4
4.0/1.0 4 High-K 9-10 0.60.7 Metal 15-17 1.E+04 5-10 4
4.0/1.0 4 High-K 9-10 0.60.7 Metal 15-17 1.E+04 5-10 4
4.0/1.0 SiO2 or ONO 3-4
4.0/1.0 SiO2 or ONO 3-4
4.0/1.0 SiO2 or ONO 3-4
4.0/1.0 SiO2 or ONO 3-4
4.0/1.0 SiO2 or ONO 3-4
4.0/1.0 SiO2 or ONO 3-4
4.0/1.0 SiO2 or ONO 3-4
SiO2 or Al2O3 SiO2 or Al2O3 SiO2 or Al2O3 SiO2 or Al2O3 SiO2 or Al2O3 SiO2 or Al2O3 SiO2 or Al2O3 68 SiN 57 68 SiN 57 68 SiN 57 68 SiN 57 68 SiN 46 68 SiN / High-K 46 68 SiN / High-K 46
Metal
Metal
Metal
15-17 1.E+05
15-17 1.E+04
15-17 1.E+04
10-20 4
10-20 4
10-20 4
10-20 4
10-20 4
5-10 4
5-10 4
40
35
32
28
25
22
20
9-11 80 8 ONO 13-15 0.60.7 7-9 19-25 1.00E+06 1020 2
9-11 70 8 ONO 13-15 0.60.7 7-9 17-22 1.00E+06 1020 2
9-11 64 8 High-K 8-10 0.60.7 6-8 15-20 1.00E+06 20 2
9-11 56 7-8 High-K 8-10 0.60.7 6-8 14-19 1.00E+06 20 2
9-11 50 7-8 High-K 8-10 0.60.7 6-8 13-18 1.00E+06 20 2
10-13 44 7-8 High-K 8-10 0.60.7 6-8 1217 1.00E+07 20 2
10-13 40 7-8 High-K 8-10 0.60.7 6-8 1116 1.00E+07 20 2
CC
CC
CC/VG
CC/VG
CC/VG
CC/VG
CC/VG
40 7-8 3.7/1.9 0.11 4.5 4-6 68 6-8 19-25 1.00E+06 1020 4
35 7-8 3.7/1.9 0.1 4.5 4-6 68 6-8 17-22 1.00E+06 1020 4
32 7-8 3.7/1.9 0.1 4 4-6 68 6-8 15-20 1.00E+06 1020 4
28 7-8 3.7/1.9 0.09 4 4-6 68 57 14-19 1.00E+06 1020 4
25 8-9 4.3/2.2 0.09 4 4-5 57 57 13-18 1.00E+06 1020 6
22 8-9 4.3/2.2 0.08 4 4-5 57 57 1217 1.00E+06 1020 6
20 8-9 4.3/2.2 0.08 4 4-5 57 57 1116 1.00E+06 1020 6
130
130
90
90
90
90
90
150 20 0.450 1T1C stack 0.200 0.20 0.20 1.00 1.20 20 1E+14 10 Years
150 20 0.450 1T1C stack 0.200 0.20 0.20 1.00 1.20 20 1E+14 10 Years
130 16 0.270 1T1C stack 0.106 0.106 0.106 1.00 1.20 34.0 1E+15 10 Years
130 16 0.270 1T1C stack 0.106 0.106 0.106 1.00 1.20 34.0 1E+15 10 Years
130 16 0.270 1T1C stack 0.106 0.106 0.106 1.00 1.20 34.0 1E+15 10 Years
90 14 0.113 1T1C 3D 0.041 0.041 0.100 2.46 1.00 30 >1.0E16 10 Years
90 14 0.113 1T1C 3D 0.041 0.041 0.100 2.46 1.00 30 >1.0E16 10 Years
45 18 0.036 35 25 0.013 0.8 70 >10 >3e16 >10
45 18 0.036 35 25 0.013 0.8 70 >10 >3e16 >10
32 19 0.019 35 20 0.009 0.6 70 >10 >3e16 >10
32 17 0.017 35 20 0.009 0.6 70 >10 >3e16 >10
32 17 0.017 35 20 0.009 0.6 70 >10 >3e16 >10
22 18 0.009 35 20 0.007 0.6 70 >10 >3e16 >10
22 16 0.0077 35 20 0.007 0.6 70 >10 >3e16 >10
35 4.0
32 4.0
28 4.0
25 4.0
22 4.0
20 4.0
18 4.0
10.0 4900 12250 2
8.9 4096 9114 4
8.8 3136 6899 4
8.4 2500 5250 4
7.4 1936 3582 4
7.3 1600 2920 4
7.3 1296 2365 4
2450
1024
784
625
484
400
324
6125 22 43,000 80 8.29 1.50E+07 962
2278 20 33,000 70 9.21 1.50E+07 804
1725 18 25,000 62 10.20 1.50E+07 616
1313 16 18,000 52 11.66 1.60E+07 491
895 14 12,000 43 13.56 1.70E+07 380
730 13 9,000 37 15.17 1.90E+07 314
591 12 6,700 32 17.18 2.00E+07 254
1.8
2.1
2.1
2.1
2.4
2.4
2.4
68 >10 1.0E+10
51 >10 1.0E+12
43 >10 1.0E+12
36 >10 1.0E+12
26 >10 1.0E+15
23 >10 1.0E+15
21 >10 1.0E+15
optimized
OT known
vides the F value for designs in the indicated time period.
Long bit line strings reduce the overhead for bit line transistors and increase the packing density, however, at the expense of higher overall resistance and consequently lower read
s talk between neighboring cells, NAND technology is forecasted to migrate gradually from floating gate devices (FG) to charge trapping devices (CT). (Ref: K. Kim, "Technology ectron Devices Meeting, pp. 539-543, 2005.) The statistical fluctuation limit of storing too few electrons imposes new challenges to data retention (Ref: G. Molas, et al., "Impact of national Electron Devices Meeting, pp. 877-880, 2004.) and 3D integration of multiple layers of devices may be required to continue the scaling. (Refs: S.H. Lee et al., "Three layers on ILD and TANOS structure for beyond 30nm node, Tech. Digest 2006 International Electron Devices Meeting, pp. 37-40, 2006. E-K. Lai, et al., "A multi-layer stackable lectron Devices Meeting, pp. 41-44, 2006.)
for Flash cell area in multiples of the implementation technology F 2 . It is possible to store more than 1 bit of information in a Flash cell but increasing the logic levels from (1, 0) es both single-level cell (SLC) and multi-level cell (MLC) devices.
NOR Flash. However, the use of error code correction (ECC) in NAND tolerates tunnel oxide defects to a higher level than that for NOR, thus allowing tunnel oxide of 67 nm.
he near future. However, below 40 nm the spacing between floating gates becomes too narrow to fill effectively with ONO and word line polysilicon, and the loss of sidewall control the device becomes inoperable. Since it is impossible to create additional space, higher dielectric constant IPD or charge trapping (CT) device must be used. Here the path of ve not been demonstrated yet.
total floating gate capacitance). GCR represents the fraction of voltage drop across the tunnel oxide and must be higher than 0.6 for the device to function during write and erase ewalls of the floating gate. This requires tall floating gate and the cross talk along the bit line direction with neighboring cells is a challenge for MLC operation. At below 40 nm , to wrap around and maintaining sufficiently high GCR is a difficult challenge. Planar device with high- IPD is a potential solution.
will continue in the near future. The introduction of high- IPD, with a lower barrier height to Si, will cause severe gate injection during erase operation and high work function
ecreased to allow lower W/E voltage without compromising W/E speed.
ated passing of charges under high electric field. Scaling does not worsen the oxide damage, however, larger array strains the ECC capability and the tolerance for defects is thus n is gradually reduced cycling endurance for future technology. Note that this is not suitable for certain applications, e.g., solid-state drive storage that requires high cycling
n of the number of stored electrons. Both thinner tunnel oxide and fewer number of stored electrons in the long term contribute to the shorter retention forecast.
Flash today and devices with 8 logic levels (3-bit/cell) and 16 logic levels (4-bit/cell) are being developed. 8-bit/cell MLC device requires 256 logic levels and so far seems beyond term years.
a SiN trapping layer for charge storage, Al 2O 3 to increase voltage drop across the tunnel oxide and high work function metal gate to stop gate injection. (Ref: C.H. Lee, et al., "A memories, Tech. Digest 2003 International Electron Devices Meeting, pp. 613-616, 2003.) Barrier engineering uses composite tunneling barriers to allow easy erase operation by Ref: H.T. Lue, et al., "BE-SONOS: a bandgap engineered SONOS with excellent performance and reliability, Tech. Digest 2005 International Electron Devices Meeting, pp. 555omise to help NAND scaling below 30 nm.
unnel dielectric for barrier engineered (BE) device may be a composite ONO (e.g., 2 nm/2 nm/2 nm) or other composites such as OAO.
ier height. Other composite blocking layers such as AN, ANO, or AHO are also potential candidates. For BE device the blocking oxide may be SiO 2, although Al 2O 3 and other
p electron traps that provide good data retention. Other exotic high- material with even deeper traps may be used in the long term years. (Ref: A. Chin, et al., "Low voltage high ational Electron Devices Meeting, pp. 165-168, 2005.) Note that for CT device the charge loss mechanism may be mainly substrate hole tunneling in low field and thus deeper traps
oc. 2007 International Reliability Physics Symposium, 2007). Therefore, thinner SiN or other high- trapping layers forecasted for long-term years may suffer from reduced
polysilicon may become an interim solution because of its easy processing, low cost, and reasonably good performance.
t. Unlike floating gate device, CT devices are not sensitive to tunnel oxide damage since the charge is stored in discrete traps and one weak spot does not cause all stored charge to durance as floating gate device.
T. Lue, et al., "Reliability model of bandgap engineered SONOS (BE-SONOS), Tech. Digest 2006 International Electron Devices Meeting, pp. 495-498, 2006.) Data retention ata retention is comparable to floating gate devices under certain conditions.
years and is now on par with DRAM.
pling ratio of >0.6 but this offers only limited help to the area factor. (Ref: 2005 Symposium on VLSI Technology, 11B-3, E. S. Cho, et al., Hf-silicate Inter-Poly Dielectric
near term years (Ref: 2005 Symposium on VLSI Technology, 11B-1, R. Koval, et al. "Flash ETOX Virtual Ground Architecture: A Future Scaling Direction, pp. 204-205.), this e conventional array and large development effort is needed to implement it and so far there is no industrial consensus to take up this endeavor.
h scaling, their impact has not been included in the current table. The dilemma of filling ONO and control and floating gates in the narrow gap between adjacent vertical devices
caled recently with an area factor of approximately 10F2. (Refs: 2005 ISSCC, "A 90 nm 512Mb 166 MHz Multilevel Cell Flash Memory with 1.5MBytes/s Programming, pp. 54-
chnology with 0.081m 2 Cell Size, pp. 91-92. 2004 Symposium on VLSI Technology, "A 70nm NOR Flash Technology with 0.049m2 Cell Size, pp. 238-239.)
profile to generate, with the consequence of difficulties in controlling the short channel effect, but yet the NOR architecture is vulnerable to device leakage. Since the tunnel oxide
hallenge for scaling. The gate length generally is substantially larger than F in recent years. Despite this difficulty, the area factor has been maintained at 10F 2 in recent years (see
e of erase/write. This difficult trade-off problem hinders scaling. Tunnel oxides less than 7 nm pose fundamental problems for retention reliability.
ar future. However, at 32 nm and beyond high- IPD may be necessary to maintain GCR at 0.6 or above. Currently, the GCR is achieved by wrapping the control gate over the rea. At 32 nm or below, the gap between adjacent gloating gates becomes too narrow for the ONO and control gate to fill in and this semi-vertical structure will cease to function.
al floating gate capacitance). GCR must be greater than about 0.6 for proper device operation.
d by on-chip charge pumping circuits. Low voltage is desired to reduce the charge pumping circuit overhead and simplify processing. The introduction of high- IPD will help to
voltage overdrive (read disturb). Since access time depends critically on the read current and is an important performance parameter for NOR Flash the read current decreases ong term years.
s have been accepted as the historical minimum acceptable level for a useful NOR product.
c. Improvement in defect control and accumulation of device history is expected to eventually allow specification of 20 years retention. Also, it should become possible to accept a
storage bits (Multilevel cell MLC). Progression to 8 or 16 levels is potentially possible but maintaining reasonable V t , read speed and array efficiency beyond 2-bit/cell are nce and reliability tend to hold higher importance than density for NOR Flash, thus the pressure to higher level MLC is not as strong as for NAND Flash.
quires no STI isolation or bit line contact in the cell. In principle the area factor for VG array can be as small as 4F 2 , compared to ~ 10F 2 for an array with cell STI isolation and duces more leakage paths and complicates the design. Large R&D effort is needed to implement VG array and overcome its shortcomings to take advantage of its smaller cell size.
hus often is confused with the conventional SONOS device. Conventional SONOS is more suitable for a NAND array. The device is programmed by Fowler-Nordheim tunneling of he electrons are stored in deep SiN traps it is difficult to de-trap by Fowler-Nordheim tunneling. Instead, a very thin (23 nm) tunnel oxide is used to allow substrate hole tunneling ling of holes from the substrate even under weak electric field produced by the stored electrons and good data retention is difficult to achieve. NROM is a device proposed to solve
, electrons are stored in the SiN layer near the edge of S/D junctions. To erase, band-to-band tunneling generated hot holes are injected into the SiN. A relatively thick (45 nm) ntage of storing two bits of information in one device (source side and drain side) and it applies a reverse read method to distinguish the different states. NROM is built nly for NOR Flash, but also for some data storage applications even though it is not a NAND structure.
r 2-bit/cell. The MLC Flash stores 2 bits on the source side and two bits on the drain side, thus 4-bit/cell.
not limited by left-right bit interference. The scaling is limited by the same factors for floating gate device - junction breakdown voltage and short channel effect. 4-bit/cell MLC ling for MLC may be more gradual than SLC.
more aggressively than for floating gate device.
trapping efficiency.
ory devices (not embedded devices).
F 2 multiples of the FeRAM implementation technology.
ats. (Refs. J.H. Park, et al., "Fully Logic Compatible (1.6V Vcc, 2 Additional FRAM Masks) Highly Reliable Sub 10F 2 Embedded FRAM with Advanced Direct Via Technology and
. Kang et al., "Sub-1.2V Operational, 0.15m/12F 2 Cell FRAM Technologies for Next Generation SoC Applications", 2005 Symposium on VLSI Technology, 6B-4, pp. 102-103.)
H. Kanaya et al., "A 0.602m 2 Nestled Chain Cell Structure Formed by One Mask Etching Process for 64Mbit FeRAM, 2004 Symposium for VLSI Technology, pp. 150-151. N. citor, 2004 Symposium on VLSI Technology, pp. 146-147.)
r films are expected to be replaced by more efficient 3D structures.
titutes the capacitor area contribution to the cell size. For 20052006 ~19F 2 , for 2007 - 2009 ~16F 2 , and for 20102020 ~10F 2 (3D capacitor) are assumed.
D capacitor because of the utilization of area in the third dimension.
ation of the third dimension.
is a difficult key design issue. Generally the ferroelectric film thickness needs to be decreased in order to reduce the V op , with great technological challenges. (Ref. D. C. Yoo et al., RuO 2 /MOCVD PZT Capacitor Technology", 2005 Symposium on VLSI Technology, 6B-3, pp. 100-101.)
equal to the cell minimum switching charge divided by the capacitor actual effective area. The capacitor voltage is taken as V op .
ite to restore the data. Endurance cycles are taken as the sum of all read and all write cycles. For FeRAM to compete with DRAM and SRAM the cycle endurance should be about d accumulate 1E16 cycles.
f pitch in 2010. This entry provides the F value for designs in the indicated time period.
on of magnetization of the cell.
age * write time). It is preferred to use the median value of switching energy measured on a multi-megabit array. A good estimate of power drain is (switching energy * number of
presents the A in the R*A product.
e magnetic material stack that provides a convenient basis for comparing cells of different sizes. The R*A product can be computed by measuring the effective low state resistance c stack.
summarizes the difference between a logic ONE and a logic ZERO, and as such it represents the intrinsic capability of the magnetic stack. The magnetic tunnel junction resistance
multiples of the implementation technology F 2 . PCRAM requires significant reset current to change the phase-change element from crystalline to amorphous. A BJT transistor is educe the cell size. Both BJT and nMOSFET access device cells are represented in this table. PCRAM is capable of MLC multi-bit per cell. This area factor is per cell, not per bit.
multiples of the implementation technology F 2 . PCRAM requires significant reset current to change the phase-change element from crystalline to amorphous. A BJT transistor is educe the cell size. An nMOSFET transistor has larger cell size in the near term years, but offers simple process and low voltage operation. Both BJT and nMOSFET access device a factor is per cell, not per bit.
ometers squared.
in micrometers squared.
n amorphous and crystalline state is typically 1001,000. This entry is the expected number of MLC bits per cell.
ell size divided by the number of MLC bits per cell.
sical cell size divided by the number of MLC bits per cell.
o have efficiency reset operation with reasonable current. This entry is the expected dimension for the phase change element in nanometers.
irement. This entry is the expected phase change volume in nanometer cubed.
red to reset the PCRAM cell (from crystalline to amorphous state). It is a compromise between larger area BJT (which causes larger cell size) and higher output current (which
, assuming the BJT current density is met.
e required to reset the PCRAM cell (from crystalline to amorphous state). It is a compromise between larger width nMOSFET (which causes larger cell size) and higher output
rrent, assuming the MOSFET output current density is met.
onvolatile memory. Data retention mechanism for PCRAM is not yet thoroughly studied. Recent published data indicate >10 years of retention at elevated temperatures. (Refs. S. J. eyond, 2004 IEDM, 37.2, pp. 907-910. A. L. Lacaita et al., "Electrothermal and Phase Change Dynamics in Chalcogenide-Based Materials, 2004 IEDM, 37.3, pp. 911-914.)
ndicate cycling endurance from 1E+9 to 1E+13. (Refs. S.J. Ahn et al., "Highly Manufacturable High Density Phase Change Memory of 64Mb and Beyond, 2004 IEDM, 37.2, pp. EDM, pp. 255-258.)
Long-term
2018 18 19 2019 16 17 2020 14 15 2021 12 13 2022 10 11
16
14
13
11
10
16 64 CT-3D 4
14 64 CT-3D 4
13 64 CT-3D 4
11 64 CT-3D 4
10 64 CT-3D 4
4.0/1.0 4 High-K 9-10 0.60.7 Metal 15-17 1.E+04 5-10 4
4.0/1.0 4 High-K 9-10 0.6-0.7 Metal 15-17 1.E+04 5-10 4
4.0/1.0 4 High-K 9-10 0.6-0.7 Metal 15-17 1.E+04 5-10 4
4.0/1.0 4 High-K 9-10 0.6-0.7 Metal 15-17 1.E+04 5-10 4
4.0/1.0 4 High-K 9-10 0.6-0.7 Metal 15-17 1.E+04 5-10 4
4.0/1.0 SiO2 or ONO 3-4
4.0/1.0 SiO2 or ONO 3-4
4.0/1.0 SiO2 or ONO 3-4
4.0/1.0 SiO2 or ONO 3-4
4.0/1.0 SiO2 or ONO 3-4
SiO2 or Al2O3 SiO2 or Al2O3 SiO2 or Al2O3 SiO2 or Al2O3 SiO2 or Al2O3 68 SiN / High-K 46 68 SiN / High-K 46 68 SiN / High-K 46 68 SiN / High-K 3-4 68 SiN / High-K 3-4
Metal
Metal
Metal
Metal
Metal
15-17 1.E+04
15-17 1.E+04
15-17 1.E+04
15-17 1.E+04
15-17 1.E+04
5-10 4
5-10 4
5-10 4
5-10 4
5-10 4
18
16
14
12
10
10-13 36 7-8 High-K 7-9 0.60.7 6-8 1015 1.00E+07 20 2
10-13 32 7-8 High-K 6-8 0.6-0.7 6-8 9-14 1.00E+07 20 2
10-13 28 7-8 High-K 6-8 0.6-0.7 6-8 8-13 1.00E+07 20 2
10-13 24 7-8 High-K 6-8 0.6-0.7 6-8 7-12 1.00E+07 20 2
10-13 20 7-8 High-K 6-8 0.6-0.7 6-8 6-10 1.00E+07 20 2
CC/VG
CC/VG
CC/VG
CC/VG
CC/VG
18 8-9 4.3/2.2 0.07 4 4-5 57 57 1015 1.00E+06 1020 6
16 9-10 4.8/2.4 0.07 3.5 4 57 57 9-14 1.00E+06 1020 6
14 9-10 4.8/2.4 0.07 3.5 4 57 57 8-13 1.00E+06 1020 6
12 9-10 4.8/2.4 0.06 3.5 4 57 4-6 7-12 1.00E+06 1020 6
10 9-10 4.8/2.4 0.06 3.5 4 57 4-6 6-10 1.00E+06 1020 6
90
65
65
65
65
90 14 0.113 1T1C 3D 0.041 0.041 0.100 2.46 1.00 30 >1.0E16 10 Years
65 12 0.051 1T1C 3D 0.016 0.016 0.069 4.25 0.70 30 >1.0E16 10 Years
65 12 0.051 1T1C 3D 0.016 0.016 0.069 4.25 0.70 30 >1.0E16 10 Years
65 12 0.051 1T1C 3D 0.016 0.016 0.069 4.25 0.70 30 >1.0E16 10 Years
65 12 0.051 1T1C 3D 0.016 0.016 0.069 4.25 0.70 30 >1.0E16 10 Years
22 16 0.0077 35 20 0.007 0.6 70 >10 >3e16 >10
16 17 0.0044 35 20 0.005 0.6 70 >10 >3e16 >10
16 16 0.0041 35 20 0.005 0.6 70 >10 >3e16 >10
16 17 0.0044 35 20 0.005 0.6 70 >10 >3e16 >10
16 16 0.0041 35 20 0.005 0.6 70 >10 >3e16 >10
16 4.0
14 4.0
12 4.0
10 4.0
8 4.0
6.0 1024 1536 4
6.0 784 1176 4
6.0 576 864 4
5.5 480 650 4
5.5 340 450 4
256
196
144
120
85
384 10 4,700 27 19.74 2.10E+07 201
294 9 3,200 22 23.11 2.20E+07 154
216 8 2,000 18 27.72 2.40E+07 113
162 8 1,300 15 31.00 2.50E+07 91
112 7 900 13 35.00 2.70E+07 73
2.88
2.88
2.88
2.88
2.88
16 >10 1.0E+15
14 >10 1.0E+15
12 >10 1.0E+15
10 >10 1.0E+15
9 >10 1.0E+15
overall resistance and consequently lower read
pping devices (CT). (Ref: K. Kim, "Technology data retention (Ref: G. Molas, et al., "Impact of inue the scaling. (Refs: S.H. Lee et al., "Three 2006. E-K. Lai, et al., "A multi-layer stackable
h cell but increasing the logic levels from (1, 0)
or NOR, thus allowing tunnel oxide of 67 nm.
ine polysilicon, and the loss of sidewall control ng (CT) device must be used. Here the path of
r the device to function during write and erase challenge for MLC operation. At below 40 nm ,
during erase operation and high work function
capability and the tolerance for defects is thus -state drive storage that requires high cycling
shorter retention forecast.
uires 256 logic levels and so far seems beyond
to stop gate injection. (Ref: C.H. Lee, et al., "A eling barriers to allow easy erase operation by ernational Electron Devices Meeting, pp. 555-
O.
oxide may be SiO 2, although Al 2O 3 and other
years. (Ref: A. Chin, et al., "Low voltage high ole tunneling in low field and thus deeper traps
for long-term years may suffer from reduced
e weak spot does not cause all stored charge to
s Meeting, pp. 495-498, 2006.) Data retention
Cho, et al., Hf-silicate Inter-Poly Dielectric
Future Scaling Direction, pp. 204-205.), this endeavor.
narrow gap between adjacent vertical devices
mory with 1.5MBytes/s Programming, pp. 54-
m2 Cell Size, pp. 238-239.)
rable to device leakage. Since the tunnel oxide
s been maintained at 10F 2 in recent years (see
on reliability.
chieved by wrapping the control gate over the semi-vertical structure will cease to function.
ng. The introduction of high- IPD will help to
eter for NOR Flash the read current decreases
on. Also, it should become possible to accept a
eed and array efficiency beyond 2-bit/cell are as for NAND Flash.
~ 10F 2 for an array with cell STI isolation and ings to take advantage of its smaller cell size.
programmed by Fowler-Nordheim tunneling of oxide is used to allow substrate hole tunneling o achieve. NROM is a device proposed to solve
jected into the SiN. A relatively thick (45 nm) the different states. NROM is built
oltage and short channel effect. 4-bit/cell MLC
AM with Advanced Direct Via Technology and
sium on VLSI Technology, 6B-4, pp. 102-103.)
mposium for VLSI Technology, pp. 150-151. N.
D capacitor) are assumed.
echnological challenges. (Ref. D. C. Yoo et al.,
nd SRAM the cycle endurance should be about
f power drain is (switching energy * number of
by measuring the effective low state resistance
stack. The magnetic tunnel junction resistance
m crystalline to amorphous. A BJT transistor is r cell. This area factor is per cell, not per bit.
m crystalline to amorphous. A BJT transistor is eration. Both BJT and nMOSFET access device
meters.
ger cell size) and higher output current (which
hich causes larger cell size) and higher output
f retention at elevated temperatures. (Refs. S. J. aterials, 2004 IEDM, 37.3, pp. 911-914.)
y of 64Mb and Beyond, 2004 IEDM, 37.2, pp.
Table PIDS6
Difficult Challenges 22 nm Transistor Reliability
Reliability Difficult Challenges
Summary of Issues
Time dependent dielectric breakdown Negative bias temperature instability Threshold voltage shifts due to traps, carrier injection, program Mobility degradation due to mechanical stress relaxation or inte change New or changed failure mechanisms (TDDB, PBTI, NBTI< mo etc.) resulting from high /metal gate
Interconnect Reliability
Copper electromigration and stress voiding in scaled interconn vias) Electrical breakdown of interconnect dielectrics, especially low Moisture absorption/transport due to voids in porous low die Cu (ionic) migration through cracked or thin barrier metals
Packaging Reliability
New failure mechanisms associated with Pb-free solders and n compounds Electromigration in package traces, vias, and bumps Impact of multichip modules and stacked dies on failure rate Solder ball electromigration, for example in CSP and flip chip Radioactive contaminants in packaging materials
Reliability in Extreme and/or Critical Applications
Automotive (define mission profile for HOT underhood versu substantial cycling) Military (rugged versus shock and dust, highly diverse environ requirements) Space, i.e., radiation hard Aeronautical (singe event effects tolerant and large, fast tempe Medical (corrosive, hermeticity, and safety)
Impact of Variability on Reliability
Statistic variation growing larger and defect size is comparabl Distribution of dopant atoms; subtle ultra-thin gate oxide roughness and other litho "fidelity" issues; surface scatter How to cope with cost-effective screens and qualifications tha "good" units Design for Reliability in face of large percentage process varia How to use yield to drive reliability Summary of Issues
Difficult Challenges<22 nm Reliability of novel devices, structures, materials and applications
ITRS proposes many new materials and structures, yet current about failure mechanisms Need to have reliability characterization in place well in advan develop appropriate reliability requirements and qualifica Design for Reliability tools
ficult Challenges
breakdown instability ue to traps, carrier injection, program or erase to mechanical stress relaxation or interface state density
echanisms (TDDB, PBTI, NBTI< moisture absorption, gh /metal gate
and stress voiding in scaled interconnects (lines and
nterconnect dielectrics, especially low and ultra low port due to voids in porous low dielectrics ugh cracked or thin barrier metals
associated with Pb-free solders and new mold
age traces, vias, and bumps ules and stacked dies on failure rate on, for example in CSP and flip chip s in packaging materials
on profile for HOT underhood versus passenger and
hock and dust, highly diverse environmental
effects tolerant and large, fast temperature swings) eticity, and safety)
g larger and defect size is comparable to feature size: nt atoms; subtle ultra-thin gate oxide defects; line edge litho "fidelity" issues; surface scattering fective screens and qualifications that capture some
face of large percentage process variability reliability
w materials and structures, yet currently very little known isms haracterization in place well in advance of application to reliability requirements and qualification procedures ls
Table PIDS7
Reliability Technology Requirements

2007 502000 502000 1000-2000 1 1 2008 502000 502000 1000-2000 0.83 0.5 2009 502000 502000 1000-2000 0.71 0.5 2010 502000 502000 1000-2000 0.66 0.5
Year of Production Early failures (ppm) (First 4000 operating hours) [1] Long term reliability (FITS = failures in 1E9 hours) [2] SRAM Soft error rate (FITs/MBit) Relative failure rate per transistor (normalized to 2007 value) [3] Relative failure rate per m of interconnect (normalized to 2007 value) [4] Manufacturable solutions exist, and are being optimized Manufacturable solutions are known Interim solutions are known Manufacturable solutions are NOT known
Notes for Table PIDS7a and b: Reliability requirements vary with different applications. For many mainstream customers it will be sufficient to hold current reliability levels s technological change. However, other customers would like reliability levels to be improved. Degradation of current reliability levels is not acceptable. packaged device and include both chip and package related failure modes.
A reliability qualification can always be attempted with available knowledge. The better the knowledge the less risk in the qualification and vice versa. Y Striped indicates a greater risk (due to changed and possible new failure modes). Finally, red indicates an unspecified solution (e.g., what technology wil reliability risk cannot be assessed until details about the solution are provided. [1] Failures during the first 4000 hours of operation (~1 year's use at 50% duty cycle). Early failures are associated with defects. [2] Long term reliability rate applies for the specified lifetime of the IC.
[3] While the overall IC failure rate does not change with time, as the number of transistors per chip increases [from ORTC], the relative failure rate per t [4] As the length of interconnect per chip increases [from Interconnect Technology Requirements tables], the failure rate per m of interconnect must reliability is the increase in the number of vias.
2011 502000 502000 1000-2000 0.57 0.25
2012 502000 502000 1000-2000 0.51 0.25
2013 502000 502000 1000-2000 0.46 0.25
2014 502000 502000 1000-2000 0.4 0.12
2015 502000 502000 1000-2000 0.37 0.12
2016 502000 502000 1000-2000 0.31 0.12
2017 502000 502000 1000-2000 0.29 0.06
2018 502000 502000 1000-2000 0.26 0.06
2019 502000 502000 1000-2000 0.23 0.06
icient to hold current reliability levels steady during this period of rapid urrent reliability levels is not acceptable. Reliability requirements are for the
s risk in the qualification and vice versa. Yellow coloring indicates some risk. pecified solution (e.g., what technology will be used for post-Cu) for which the
ated with defects.
[from ORTC], the relative failure rate per transistor must decrease
e failure rate per m of interconnect must decrease. Even more important for
2020 502000 502000 1000-2000 0.2 0.03
2021 502000 502000 1000-2000 0.18 0.03
2022 502000 502000 1000-2000 0.16 0.03

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ORTC INDEX

2007 ITRS Chapters

Table SYSD3 Table SYSD4

TEXT TEXT TEXT

Test and Test Equipment

Table TST13 Table TST14 Table TST15

RF and AMS for Wireless

Table RFAMS6 Table RFAMS7 Table RFAMS8

Process Integration, Devices, and Structures (PIDS)

Table PIDS4 UPDATED Table PIDS5 Table PIDS6 Table PIDS7

Table INTC4 Table INTC5 UPDATED Table INTC6 Table INTC7

Assembly and Packaging

UPDATED Table AP10 UPDATED Table AP11

UPDATED Table YE7 UPDATED Table YE8 UPDATED Table YE9

Table MET1 Table MET2 Table MET3

Modeling and Simulation

esearch Devices o the ERD summary in the 2008 Update Overview

esearch Materials o the ERM summary in the 2008 Update Overview

WORKING GROUP TABLES

http://www.itrs.net/Links/2008ITRS/Update/2008Tables_FOCUS_B.xls http://www.itrs.net/Links/2008ITRS/Update/2008Tables_CROSSCUT.xls http://www.itrs.net/Links/2008ITRS/Update/2008_Update.pdf http://www.itrs.net/Links/2007ITRS/Home2007.htm

2008 INDEX 2007 ITRS Chapters

Overall Roadmap Technology Characteristics [ORTC]

Roadmap Technology Characteristics [ORTC]

ngs Final Litho Printed Gate Length Proposal

2016 17.9 23 22.5 22.5 15 17.7 8.9 14.0 19 17.7 11 14.0

2017 15.9 20 20.0 20.0 13 15.7 8.0 12.8 17 15.7 10 12.8

2008 59 59 29 6 0.021 56.08% 2G 2.15 81 2.65

2009 52 52 27 6 0.016 56.08% 2G 2.15 61 3.50

2010 45 45 24 6 0.012 56.08% 4G 4.29 93 4.62

2011 40 40 22 6 0.0096 56.08% 4G 4.29 74 5.82

2012 36 36 20 6 0.0077 56.08% 4G 4.29 59 7.33

2013 32 32 18 6 0.0061 56.08% 8G 8.59 93 9.23

2014 28 28 17 6 0.0048 56.08% 8G 8.59 74 11.63

2015 25 25 15 6 0.0038 56.08% 8G 8.59 59 14.65

DRAM Product Table

0.028 56.08% 2G 2.15 107 2.01

Flash Product Table

Bits/cm2 at production MLC [2 bits/cell]

2016 22.5 22.5 14.0 6 0.0030 56.08% 16G 17.18 93 18.46

2017 20.0 20.0 12.8 6 0.0024 56.08% 16G 17.18 74 23.26

2018 17.9 17.9 11.7 6 0.0019 56.08% 16G 17.18 59 29.31

2019 15.9 15.9 10.7 6 0.0015 56.08% 32G 34.36 93 36.93

2020 14.2 14.2 9.7 6 0.0012 56.08% 32G 34.36 74 46.52

2021 12.6 12.6 8.9 6 0.00096 56.08% 32G 34.36 59 58.61

2022 11.3 11.3 8.1 6 0.00076 56.08% 64G 68.72 93 73.85

2007 68 68 32 6 0.028 73.52% 16G 17.18 652

2008 59 59 29 6 0.021 73.76% 16G 17.18 493

2009 52 52 27 6 0.016 73.97% 16G 34.36 745

2010 45 45 24 6 0.012 74.16% 32G 34.36 563

2011 40 40 22 6 0.0096 74.30% 32G 34.36 446

2012 36 36 20 6 0.0077 74.47% 32G 68.72 706

2013 32 32 18 6 0.0061 74.61% 64G 68.72 560

2014 28 28 17 6 0.0048 74.70% 64G 68.72 444

2015 25 25 15 6 0.0038 74.83% 64G 68.72 351

2016 22.5 22.5 14.0 6 0.0030 74.93% 128G 137.44 557

2017 20.0 20.0 12.8 6 0.0024 75.00% 128G 137.44 442

2018 17.9 17.9 11.7 6 0.0019 75.09% 128G 137.44 350

2019 15.9 15.9 10.7 6 0.0015 75.18% 256G 274.88 555

2020 14.2 14.2 9.7 6 0.0012 75.27% 256G 274.88 440

2021 12.6 12.6 8.9 6 0.00096 75.36% 256G 274.88 349

2022 11.3 11.3 8.1 6 0.00076 75.45% 512G 549.76 553

2016 22.5 22.5 14.0

2017 20.0 20.0 12.8