Académique Documents
Professionnel Documents
Culture Documents
Introduction
Bassam Jamil
1
Course Administration
Instructor: Bassam Jamil Mohammed Instructor's e-mail: bassam@hu.edu.jo Text: Advanced Digital Design with Verilog HDL , Michael Ciletti, Pearson Education Inc, 2003 or 2011 Slides : pdf on the course web page after lecture on Moodle (not BB)
Course Content
Synthesis of digital circuits. Advanced digital design topics: FSM/Power/Area Download designs on FPGAs.
Acknowledgement
Based
Virginia Tech Samir Panitkar (Verilog HDL) Morris Mano (Digital Design) Ciletti ( Verilog HDL) And others
Grading Information
Grade determinates
Midterm Exam
Exam
TBD
Project
Outline
1.
Why Digital?
2.
3.
Device Technologies
System Representation
4.
5. 6.
Abstraction
Development Tasks Development Flow
Chapter 1
Advantages
Advantage
of digital devices
Reproducibility of information Flexibility and functionality: easier to store, transmit and manipulate information Economy: cheaper device and easier to design
Moores
law
Chips double its density (number of transistor) in every 18 months Devices become smaller, faster and cheaper Now a chip consists of hundreds of million gates And we can have a wireless-PDA-MP3-playercamera-GPS-cell-phone gadget very soon
Chapter 1 9
customization is done:
In a fab (fabrication facility): ASIC (Application Specific IC) In the field: non-ASIC
Classification:
Full-custom ASIC Standard cell ASIC Gate array ASIC Complex field programmable logic device Simple field programmable logic device Off-the-shelf SSI (Small Scaled IC)/MSI (Medium Scaled IC) components
Chapter 1 10
What an FPGA?
A field-programmable gate array is a gate array that can be reprogrammed after it is manufactured programmable logic device. FPGA vendors: Xilinx, Altera, Lattice Semiconductor, Actel, Cypress, Atmel and QuickLogic. - FPGAs are generally slower than their ASIC counterparts, - draw more power. + shorter time-to-market, + lower development costs. Applications of FPGAs include DSP, Aerospace and defense systems, ASIC Prototyping, Medical imaging, VHDL is used to define the behavior of the FPGA. When compiled, will generate a net list, that can be mapped to the actual FPGA architecture. When done the binary file generated is used to (re)configure the FPGA device.
Chapter 1 11
Cost
Types
of cost:
NRE (Non-Recurrent Engineering) cost: one-time, per-design cost Part cost: per-unit cost Time-to-market cost loss of revenue
Standard
cell: high NRE, small part cost and large lead time low NRE, large part cost and small lead time
Chapter 1 12
FPGA:
Chapter 1
13
Summary of technology
Trade-off
No
Descriptions/abstractions levels:
Behavioral/Algorithm
Describe functionalities and i/o behavior Treat the system as a black box
Register
Has an explicit clock. All operations are scheduled to occur in specific clock cycles, but there are no detailed delays below the cycle level.
Structural
view:
Describe the internal implementation (components and interconnections) Essentially block diagram Chapter 1
15
Descriptions/abstractions levels:
Consists of a network of gates and registers instanced from a technology library, which contains technology-specific delay information for each gate.
Chapter 1
16
Level of abstractions
Chapter 1
17
data file
process
Development
Synthesis
Physical Design
Verification
Flow
RTL description
testbench
synthesis
simulation
netlist
delay file
5 4
simulation
configuration file
delay file
device programming
FPGA chip
Chapter 1
18
Synthesis
A
refinement process that realizes a description with components from the lower abstraction level. resulting description is a structural view in the lower abstraction level of synthesis:
The
Type
High-level synthesis RT level synthesis Gate level synthesis Technology Chapter 1 mapping
19
Physical Design
Placement
and routing
Refining from structural view to physical view Derive lay out of a netlist
Circuit
extraction:
Others
Derivation of power grid and clock distribution network, assurance of signal integrity etc.
Chapter 1
20
Verification
Check
Concern
Two
Chapter 1
21
Method of Verification
Simulation
spot check: cannot verify the absence of errors Can be computation intensive
Timing
analysis verification
Formal
apply formal math techniques determine its property E.g, equivalence checking
Chapter 1 emulation 22
Hardware
Testing
Testing
is the process of detecting physical defects of a die or a package occurred at the time of manufacturing and verification are different tasks. for large circuit
Testing Difficult
Chapter 1
23