Digital System Design Verilog: Finite State Machine

Dr. Bassam Jamil

Finite State Machine (FSM) Definition

FSM

is a behavioral model which is used to represent an software/hardware algorithm. consists of states, transitions

FSM

State: FSM consists of finite number of states, where each state represent unique configuration of the system. Transition is an action initiated by a condition. It starts from one state and ends in another/same state.

FSM Definition: More of Digital Design Definition

Why FSM is Important in Digital Design?

Digital

system design consists of:

Datapath
Adders, subtractors, multipliers, dividers

Memory
Register file, ROMs, Caches

Controller
Controls how the system execute the data

Controllers

are implemented using FSMs

FSM Types: Mealy vs. Moore

FSM Types: FSM Output

The FSM output is specified based on the FSM type: Moore: output is specified in the state Mealy: output is specified on the transition

Mealy vs. Moore

Comparison

Mealy machine uses fewer states Mealy machine responds faster

Mealy machine may be transparent to glitches

Which one is better?

Depends who you ask. In the industry, they prefer Moore. Why?
It is not recommended to have the output influenced by input port. Most of the time you are better off Flopping/Latching the input ports of your design

State Assignment
State

assignment: assign binary representations to symbolic states

a synchronous FSM
All assignments work

In

Good assignment reduce the complexity of nextstate/output logic

Typical

assignment

Binary, Gray, one-hot, almost one-hot

State Assignment (Encoding)

Gray Encoding

10

One-hot Encoding

11

Unused States
Some

binary representations are not used.

Unused means that the binary representation is not associated with any FSM state.

What

happens if the FSM enters an unused state?

Ignore the condition

Safe (Fault-tolerant) FSM: got to an error state or return to the initial state.

Easy No

for the explicit state assignment

portable code for the enumerated data type

12

Other Types of Encoding

13

FSM Example

14

FSM Example: Moore Design

15

FSM Example: Mealy Design

1/0 0/0 S0 0/0

16

S1

1/1

Moore vs. Mealy (again)

Moore

# states = 3 Output is generated by the state only

Mealy

# states = 2 Output is generated by the state and inputs

We

will implement Moore Machine in Verilog

The same ideas/techniques can be implied on Mealy implementation

17

FSM Verilog Implementation: Single Always Block

18

FSM Verilog Implementation: Single Always Block

endmodule

19

FSM Verilog Implementation: Multiple Always Blocks

20

FSM Verilog Implementation: 3-Always Block

This is the recommended implementation of FSM. Last always (output) can be coded with assign statement

if (state == s1) q = 1; else q =0;

endmodule

21

FSM Implementation : Default State

endmodule

22

FSM Implementation: Safe Implementation

23