Combined

Contents i
Handbook of Experiments
in
Electronics and Communication
Engineering
ii Contents
Contents iii
Handbook of Experiments
in
Electronics and Communication
Engineering
S Poornachandra Rao
Assistant Professor
SSN College of Engineering, Chennai
B Sasikala
Senior Lecturer
Crescent Engineering College, Chennai
vikas publishing house pvt ltd
iv Contents
Contents v
To our loving daughters
Niveditha & Nanditha
vi Contents
Contents vii
PREFACE
This lab manual has been primarily designed to cater to the practical requirements of the students
of Electronics and Communication Engineering of various universities globally. Students of other
engineering branches such as EEE, EIE, CSE, IT, ICE and ME may also find it useful. It may
also serve as a reference for polytechnic and science students.
The experiments have been organised in 8 chapters.
Chapter 1 deals with network experiments.
Chapter 2 deals with device characteristics.
Chapter 3 deals with electronic circuit designs.
Chapter 4 deals with op-amp and IC 555 experiments.
Chapter 5 deals with digital design experiments.
Chapter 6 deals with communication experiments.
Chapter 7 deals with microwave communication.
Chapter 8 deals with assembly language programming using 8085 kit.
Each experiment explains the aim, essential theory and statements, equipment required,
procedure, complete circuit diagram, tabulation, model graphs and result.
We welcome suggestions for the improvement in the future editions of the book.
Authors
viii Contents
Contents ix
ACKNOWLEDGEMENTS
We take this opportunity to acknowledge all those who were associated with us in this endeavour.
The management, staff and students of Crescent Engineering College and SSN College of
Engineering for their cooperation and support.
Our parents for our blessings and constant encouragement.
And finally Mr. P.K. Madhavan, members of Vijay Nicole Imprints, and Vikas Publishing
House for publishing this book.
Authors
CONTENTS
Preface vii
Acknowledgements ix
1. BASIC NETWORK 1.1
Kirchhoffs Voltage Law 1.16
Superposition Theorem 1.17
Maximum Power Transfer Theorem 1.19
Thevenins Theorem 1.20
Nortons Theorem 1.23
Reciprocity Theorem 1.25
Transient Response 1.26
Series Resonance 1.28
Parallel Resonance 1.31
Differentiator 1.34
Integrator 1.35
Constant-k LPF 1.38
Constant-k HPF 1.40
Constant-k Band Pass Filter 1.42
Constant-k Band Elimination Filter 1.43
m-Derived LPF 1.45
m-Derived HPF 1.47
Twin-T Filter 1.48
Equalizer 1. 50
Attenuator 1.51
2. DEVICE CHARACTERISTICS 2.1
Diode Characteristics 2.2
Rectifier 2.4
Clipping Circuits 2.7
Clamper Circuits 2.9
Transistor (CE - Configuration) Characteristics 2.10
Transistor (CC - Configuration) Characteristics 2.13
xii Contents
Transistor (CB - Configuration) Characteristics 2.16
Transistor Switch 2.18
Field-effect Transistor 2.20
Unijunction Transistor 2.22
Silicon Controlled Rectifier 2.23
DIAC 2.25
Photo-detector 2.27
Voltage Regulator 2.29
Thermistor 2.32
3. AMPLIFIER CIRCUIT DESIGN 3.1
RC Coupled Amplifier 3.2
Two Stage RC Coupled Amplifier 3.5
Emitter Follower (Common Collector Amplifier) 3.9
Darlington Pair (Common Collector Amplifier) 3. 12
Cascode Amplifier 3.15
Field Effect Transistor 3.18
Differential Amplifier 3.21
Class-A Power Amplifier: Resistive Load 3.24
Class-A Power Amplifier: Inductive Load (Design) 3.26
Class-A Power AmplifierInductive Load (Efficiency) 3.29
Class-A Power Amplifier with Transformer Coupled Load 3.31
Class-B Power Amplifier 3.33
Class-C Power Amplifier (Efficiency) 3.36
Class-C Power Amplifier (Design) 3.39
Current-series Feedback Amplifier 3.40
Voltage-Series Feedback Amplifier 3.44
Current-shunt Feedback Amplifier 3.49
Voltage-shunt Feedback Amplifier 3.54
Wein Bridge Oscillator 3.60
RC Phase Shift Oscillator 3.63
Hartley and Colpitt Oscillator 3.68
Voltage Sweep Generator 3.71
RF Amplifier 3.72
Single Tuned Amplifier 3.75
Bi-stable Multivibrator 3.78
Monostable Multivibrator 3.79
Astable Multivibrator 3.81
Contents xiii
4. OPERATIONAL AMPLIFIER (OP-AMP) 4.1
Characteristics of op-amp 4.1
Linear Applications of Op-amp 4.4
Non-linear Applications: Comparators 4.7
Pulse Detector and Window Comparator 4. 9
Instrumentation Amplifier 4.11
Non-linear Applications: Waveform Generators 4.12
Schmitt Trigger 4.16
Precision Rectifier 4.18
Study of V-I & I-V Converter Using Op-amp 4.19
Voltage to Frequency Converter 4.21
Study of Active Filters Using Op-amp 4.22
Digital to Analog Converter 4.25
Study of Digital to Analog Converter 4.26
Analog to Digital Converter 4.27
Study of Analog to Digital Converter 4.28
Study of Application of 555 Timer 4.30
Phase Locked Loop 4.33
5. DIGITAL ELECTRONICS 5.1
Logic Gates 5.4
Simplification of a Boolean Expression and Its Realisation Using Logic Gates 5.6
Adders 5.10
Subtractor 5.13
Parity Generation and Checking 5.14
Multiplexer 5.16
Demultiplexer 5.17
Encoders 5.18
Decoders 5.19
Study of Flip-flop 5.23
Study of Shift Registers 5.26
Asynchronous Counter 5.30
Synchronous Counter 5.35
Synchronous Sequential Circuit (Design) 5.37
Synchronous Sequential Circuit (State Diagram) 5.39
xiv Contents
6. COMMUNICATION CIRCUITS 6.1
Amplitude Modulation 6.1
Amplitude Demodulation 6.3
Frequency Modulation 6.4
Frequency Demodulation 6.6
Pulse Position Modulator 6.7
Pulse Amplitude Modulation 6.9
Pulse Width Modulation 6.11
Pulse Width Modulation & Pulse Position Modulation 6.12
Amplitude Shift Keying Modulator 6.15
Amplitude Shift Keying Demodulator 6.16
Pseudo Random Binary Sequence Generator 6.17
Frequency Shift Keying Modulator 6.18
Frequency Shift Keying Demodulator 6.20
Pre-Emphasis 6.21
De-Emphasis 6.23
Digital Phase Detector 6.24
Mixer (Using Discrete Component) 6.26
Mixer (Using IC) 6.27
Auto Ranging 6.28
Frequency Counter 6.30
Cross Over Network 6.31
Directional Characteristics of Loud Speaker and Microphone 6.33
Linear Variable Differential Transformer 6.34
AC and DC Measurement Using PMMC 6.36
Squelch Circuit 6.37
Blocking Oscillator 6.39
Frequency Multiplier 6.40
Frequency Synthesizer 6.41
Automatic Gain Control 6.43
7. MICROWAVE COMMUNICATION CIRCUITS 7.1
Voltage Standing Wave Ratio 7.1
Horn Antenna 7.2
Impedance Measurement 7.4
Directional Coupler 7.6
Shunt TEE and Series TEE 7.7
Contents xv
RF Mixer 7.9
Dielectric Measurement 7.10
Directional Characteristics of Microphone 7.13
Performance of Circulator 7.15
Performance of Faradays Rotation Spectrometer 7.16
Measure of Attenuation 7.17
DC Characteristics of LED and PIN Photodiode 7.19
Gunn Oscillator Characteristics 7.20
Reflex Klystron Repeller Mode Characteristics 7.22
Relation Between Frequency and Wavelength in Free Space 7.24
8. MICROPROCESSOR 8085 8.1
Standard Programs 8.9
1. Program to interchange the data byte between two locations 8.9
2. Program to exchange the data byte stored in register-D with register-H and data
byte stored in register-E with register-L 8.10
3. Program to exchange the data byte stored in register-D with register-H and data
byte stored in register E with register-L. 8.10
4. Program to add two 8 bit binary number (overflow considered) 8.11
5. Program to add N 8 bit binary numbers (overflow considered) 8.11
6. Program to add two 16-bit binary numbers 8.12
7. Program to add two 8-bit BCD numbers 8.12
8. Subtraction of two 8-bit numbers 8.13
9. Program to subtract two BCD numbers 8.13
10. Program to subtract two 16-bit numbers 8.14
11. Program to multiply two 8-bit binary numbers 8.15
12. Program to multiply two 8-bit binary numbers (Shifting and adding) 8.15
13. Program to perform multiplication of two 16-bit binary number. 8.16
14. Program to perform division of two 8-bit binary numbers 8.17
15. Program to find number of 1s and 0s in a given 8 bit binary number 8.18
16. Program to find the smallest to N 8-bit binary number 8.19
17. Program to obtain the descending order of N 8-bit binary numbers 8.20
18. Program to convert 8-bit binary number to gray code 8.21
19. Program to convert gray code to 8-bit binary number 8.21
20. Program to convert ASCII hex number into its binary equivalent 8.22
xvi Contents
21. Program to convert binary number into its ASCII equivalent 8.23
22. Program to convert 2 digit BCD to its binary equivalent 8.24
23. Program to convert binary numbers to its equivalent BCD 8.25
24. Program to reverse a string 8.26
25. (a) Program for generating Fibonacci series (upto (FF)H 8.26
(b) Program to generate Fibonacci series {maximum [FFFF]
H
} 8.27
26. Program to solve the given Boolean expression Z Y X Z Y X Z Y X F + + = 8.28
27. Program to find the factorial of a number. 8.30
28. Program to find the square root of a number. 8.30
29. Program to find the square of a number 8.31
30. Program to find the square of a number 8.32
31. Program to find cube root of a number 8.33
32. Program to decimal count from 00 to 99 (using DAA) 8.34
33. Port address 8.35
Hardware Experiments 8.35
Waveform Generation using DAC 8.35
Square wave generation 8.35
Triangular wave generation 8.36
Sawtooth waveform generation 8.37
Staircase wave generation 8.37
Trapezoidal waveform generation 8.38
Sinewave generation 8.38
Matrix Type Keyboard Interface 8.39
Control of Stepper Motor 8.40
Basic Network 1.1
C h a p t e r 1
BASIC NETWORK
UNITS AND ITS RELATIONS
Admittance (mho, ) = 1/impedance (ohm, ) Displacement = charge length (coulomb-m)
Boltzmanns constant (k) = 1.381 10
-23
J/
0
k Electronic charge = 1.602 10
-19
C
Capacitance (Farad, F) = charge/potential Electronic mass = 9.109 10
-31
kg
Charge (Coulomb, C) = current time Energy density = energy/volume (joule/m
3
)
Charge density () = charge/volume (coulomb/m
3
) Permeability of free space (
0
) = 1.257 10
-6
H/m
Conductance (G) = 1/resistance Permittivity of free space (
0
) = 8.854 10
-12
F/m
Current (Ampere, A) = charge/time Plancks constant (h) = 6.626 10
31
J-sec
Current density (J) = current/area (A/m
2
) Velocity of light (c) = 3 10
+8
m/sec
Unit System
The international system of units (SI) is based on fundamental units.
Quantity Unit Abbreviation
Length
Mass
Time
Luminous intensity
Temperature
Charge
Current
Energy
Force
Potential
Power
Frequency
Capacitance
Inductance
Resistance
meter
kilogram
second
candela
kelvin
coulomb
ampere
joule
newton
volt
watt
hertz
farad
henry
ohm
m
kg
sec
Cd
K
C
A
J
N
V
W
Hz
F
H
Prefix Symbol Multiplier

Tera
Giga
Mega
Kilo
Centi
Milli
Micro
Nano
Pico
T
G
M
K
c
m
n
p
10
12
10
9
10
6
10
3
10
-2
10
-3
10
-6
10
-9
10
-12
BASIC DEFINITIONS
Average Value
The average value of a waveform, which swings symmetrically across the zero reference, will be zero for a
complete full-cycle.
Multiples
1.2 Handbook of Experiments in Electronics and Communication Engineering
RMS Value
The RMS value of an alternating voltage or current is the value, which would produce the same heat in a
resistance as a direct voltage or current of the same magnitude.
Peak Value (V
m
)
The amplitude of a waveform is a measure of the extent of its voltage or current excursion from the zero
reference.
Peak-to-peak value = 2 peak value
V
PP
= 2V
m
RESISTOR COLOR CODE
Color coding is used for identifying the value of the given resistor. There are two methods of color coding in
use, namely
1. Four colored band
2. Five colored band
Four Colored Band
Example
Brown; Black; Red; Gold
1 0 10
2

5%
Value is 1000 5%
Five Colored Band
Example
Red; Yellow; Black; Black; Red
2 4 0 10
0
2%
Actual value = 240 2%
Color Band Color Multiplier Color Tolerance
Black 0
Brown 1
Red 2
Orange 3
Yellow 4
Green 5
Blue 6
Violet 7
Grey 8
White 9
Silver 10
-2
Gold 10
-1
Black 10
0
=1
Brown 10
1
=10
Red 10
2
Orange 10
3
Yellow 10
4
Green 10
5
Blue 10
6
Brown 1%
Red 2%
Gold 5%
Silver 10%
No color 20%
Color Band Color Multiplier Color Tolerance
Black 0
Brown 1
Red 2
Orange 3
Yellow 4
Green 5
Blue 6
Violet 7
Grey 8
White 9
Silver 10
-2
Gold 10
-1
Black 10
0
=1
Brown 10
1
=10
Red 10
2
Orange 10
3
Yellow 10
4
Green 10
5
Blue 10
6
Red 2%
Gold 5%
Silver 10%
No color 20%
Basic Network 1.3
COMPONENTS, DEVICES AND THEIR SYMBOLS
Grounding/ Earthing AC voltage source (sinusoidal) V
Fixed DC power supply
V
+
AC voltage source (pulsating)

V
Variable DC power supply V
+
Current source
+
I
Components Fixed Variable
Resistor
Capacitor
Inductor
Transformer
Switches
DIODES AND THEIR SYMBOLS
Basic Network 1.5
Power Supply
230V AC ( 10%), 50 Hz.
Precaution
The cover can be taken off after unplugging the power cords trip contact connector. The case, chassis and all
measuring terminals are to be connected to the protective earth contact of the inlet. The mains plug shall only
be inserted in a socket outlet when it connected to a protective earth contact. The protective action must not
be negated by the use of an extension cord without a protective conductor.
WARNING: Any interruptions of the protection conductors inside or outside the instruments or
disconnection of the protective earth terminals are likely to make the instruments dangerous. The
mains plug should be inserted before connections are made to test circuits.
Under certain conditions, 50 Hz hum voltage can occur in the circuit due to instrumentation with other
mains powered equipment or instrument. This can be avoided by using an insulation transformer between the
mains outlet and power plug of the instrument.
It should be noted that generators always deliver an output but never take an input and hence care should
be taken that no input is given in any form to the output ports. If condensed water exists in the instrument, it
should be acclimatized before switching on. The instruments should be kept in a clean and dry room and must
not be operated in explosive, corrosive, dusty or moist environments. The ventilation holes must not be covered.
Maintenance of Devices
The exterior of the instruments should be dusted with brushes. Dirt can be removed with moist cloth, spirit or
washing with benzene. The display can only be cleaned with water or washing with benzene (not with spirit).
BASIC LAB INSTRUMENTS
Ammeter
Ammeters are connected in series with the circuit whose current is to be measured. Therefore they should have
a low electrical resistance. This is essential in order that they cause a small voltage drop and consequently
absorb small power.
Voltmeter
Voltmeters are connected in parallel with the circuit whose voltage is to be measured. They should have a high
electrical resistance. This is essential in order that the current drawn by them is small and consequently the
power absorbed is also small.
Ohmmeter
They are used for measurement of resistance. They incorporate a source of emf and a current measuring device.
TYPES OF INSTRUMENTS USED AS AMMETERS AND VOLTMETERS
Permanent Magnet Moving Coil (PMMC)
This type can be used for DC measurements only. This is a more accurate type for DC measurement.
Moving Iron and Moving Coil
Both these types depend upon the magnetic effect of current. It can be used for either DC or AC measurements.
Electrodynamics Meter
These types of instruments are used both for AC and DC measurement. The calibration for both DC and AC is
the same and hence they are very useful as transfer instruments.
Induction Type
These types of instruments are used for AC measurement alone. The induction principles are generally used for
watt-hour meter than for ammeters and voltmeters owing to the comparative high cost.
Basic Network 1.7
Electrostatic Type
As voltmeters, they have an advantage that their power consumption is exceedingly small. They can be made
to cover a large range of voltage. Their main disadvantage is that the electrostatic principle is only directly
applicable to voltage measurements.
CATHODE RAY OSCILLOSCOPE (CRO)
The cathode ray oscilloscope is the most versatile measuring instrument available. We can measure the following
parameters using the CRO.
1. AC or DC voltage
2. Time
=
f
t
1
3. Phase relationship
4. Waveform evaluation: Rise time, Fall time, ON-time, OFF-time, Distortion, etc.
We can also measure non-electrical physical quantities like pressure, strain, temperature, acceleration, etc.
by converting them into electrical quantity using suitable transducer.
Fig. 1.1 Cathode Ray Oscilloscope
Major Blocks in a CRO
1. Cathode ray tube (CRT)
2. Vertical amplifier
3. Horizontal amplifier
4. Sweep generator
5. Trigger circuit
6. Associated power supply
A Practical CRO
CRO consists of a Cathode Ray Tube (CRT) and additional control knobs. The main parts of a CRT are
1. Electron gun assembly
2. Deflection plate assembly
3. Fluorescent screen
Electron Gun Assembly
The electron gun assembly produces a sharp beam of electrons, which are accelerated to high velocity. This
focussed beam of electrons strikes the fluorescent screen with sufficient energy to cause a luminous spot on
the screen.
Deflection Plate Assembly
This part consists of two parallel plates in which one pair of plates is placed horizontally and other pair placed
vertically. The signal under test is applied to vertical deflecting plates. The horizontal deflection plates are
connected to a built-in ramp generator which moves the luminous spot periodically in a horizontal direction
from left to right over the screen. These two deflection plates give the actual waveform. The rate at which it
traces the waveform gives stationary appearance to the waveform on the screen. CRO operates on voltage
since the deflection of the electron beam is directly proportional to the deflecting voltage. This means that the
CRT may be used as a linear measuring device.
The voltage being measured is applied to the vertical plates through an iterative network, whose propagation
time corresponds to the velocity of electrons, thereby the voltage applied to the vertical plates is made to
synchronize with the velocity of the beam.
Synchronization of Input Signal
The sweep generator produces a sawtooth waveform, which is used to synchronize the applied signal to obtain
a stationary-applied signal. This requires that the time base be operated at a submultiple frequency of the signal
under measurement. If synchronization is not done, the pattern is not stationary, but appears to drift across the
screen in a random fashion.
Internal synchronization This trigger is obtained from the time-base generator to synchronize with the
signal.
External synchronization An external trigger source can also be used to synchronize the signal being
measured.
Basic Network 1.9
Auto Triggering Mode
The time-base used in this case is in a self-oscillating condition, i.e. it gives an output even in the absence of
any Y-input. The advantage of this mode is that the beam is visible on the screen under all conditions including
the zero input. When the input exceeds a certain magnitude, the internal free-running oscillator locks on to the
frequency of the input signal and provides a stable synchronized display. This is so for all frequencies of the
input higher than the free running frequency of the time-base generator in the auto mode. When the frequency
of the Y-input is less than this, synchronization is not assured and the AC trigger mode has to be used. In the
AC trigger mode, the time-base generator is controlled by a monostable, which in turn is triggered by a set level
obtained from the Y-amplifier output. In HF trigger mode, triggering amplifier is bypassed internally, to avoid
failure of triggering due to delays arising from the triggering amplifier. In this mode, the repetition rate of time
base is higher as compared to that in the auto mode.
The bombarding electrons, striking the screen, release secondary emission electrons. These secondary
electrons are collected by an aqueous solution of graphite.
The bandwidth of an oscilloscope normally refers to the 3dB bandwidth of the vertical amplifier in the
normal sensitivity range.
Position Control
Applying small independent internal DC voltage to the deflecting plates does the positioning of the trace and
control with the help of a potentiometer.
Focus Control
The focussing electrode acts like a lens whose focal length can be changed using a potentiometer. These will
align the beam without spreading outward.
Intensity Control
Varying the potentiometer connected to the grid voltage can vary the intensity of the beam. Intensity basically
refers to the number of electrons ejected (depending upon the filament heating) from the plate of the electron
gun.
Z-modulation
The voltage applied to the grid of the CRT in this case can be controlled by an external signal connected to the
Z-mode input. This is used for brightening the display.
Calibration Circuit
Square wave amplitude and frequency is calibrated to a definite value (say 0.2 V at 1 kHz) for calibration as well
as testing purpose.
INTRODUCTION TO NETWORKS
An electrical network is a combination of electrical elements
like resistors, capacitors, inductors, etc. Network analysis
deals with the analysis of the response of the network for a
given excitation.
If the relationship of response to excitation is linear i.e. change in input results in a corresponding change
in output, then electrical network is called linear.
ACTIVE AND PASSIVE ELEMENTS
Active Elements
An active element is one which is capable of generating energy on its own.
Example: Transistor, FET, etc.
Passive Elements
A passive element is one which is incapable of generating energy on its own. But it is capable of storing and
dissipating energy. It always needs some external source of power.
Example: Resistor, Capacitor, Inductor, etc.
NETWORK ELEMENTS
Resistor
R
A resistor is a passive circuit element, which consumes energy. All electrical devices, which consume energy,
must have resistance in their circuit model. The power consumed by a resistor is given by
P = I
2
R
where I = current flowing through the resistor.
I = DC current
i = AC current
Resistance can be defined by Ohms law i.e. at a constant temperature, the voltage drop between ends of
a conductor is directly proportional to the current flowing through it.
V
R
V k I
V I
1
= =
where k = constant of proportionality =

R
1
R = resistance of the conductor (ohm, )
V = I R
Inductor
L
An inductor is a circuit element which is capable of storing energy in the form of current for some period and
delivers the same after this time. The average power for inductor is zero. Inductor plays a vital role in electric
motor, transformer, etc.
Network
Input
(Excitation)
(Response)
Output
Fig. 1.2 Two Port Network
Basic Network 1.11
They are usually made of many turns of fine wires wound in a coil form. For an ideal inductance, the voltage
is proportional to the rate of change of current i.e.
dt
di
L t v
dt
di
t v
= ) (
) (
where L = inductance (Henry, H).
The current in the inductance can be found out by integrating the above equation with respect to time.
Therefore,
= dt t v
L
t i ) (
1
) (
The energy stored in an inductor is given by
2
2
1
CV P =
Capacitor
C
A capacitor is a circuit element, which is capable of storing energy in the form of voltage, during some period
and returns during other time. Thus the average power for capacitor is zero.
For an ideal capacitor, the voltage is proportional to the integral of current, i.e.
= dt i
C
t v
1
) (
(i)
where C = capacitor (Farad, F)
The voltage is proportional to the change in charge to the change in capacitance.
dC
dQ
t v = ) (
(ii)
The current in the capacitance can be found out by differentiating equation (i) with respect to time, i.e.
dt
dv
C i =
The energy stored in a capacitor is given by
2
2
1
LI P =
ENERGY SOURCE
Ideal Current Source
The ideal current source is one which produces a constant current irrespective
of voltage across it. The current source can be represented symbolically by
Fig. 1.3
It is necessary to connect the current source to some external circuit to
complete the path of the current. An ideal current source must be capable of
supplying infinite power. Fig. 1.3 Ideal Current Source
Ideal Voltage Source
The ideal voltage source is one which produces constant voltage irrespective of current through it. The
voltage source can be symbolically represented by
V DC Voltage
+
I
V(t)
AC Voltage
i
Fig. 1.4a DC Voltage Source Fig. 1.4b AC Voltage Source
When the voltage source becomes open-circuited, it should not draw any current and hence power is zero.
If the voltage source is short-circuited, then infinite amount of current flows through it and hence power is
infinity.
Dependent and Independent Sources
Ideal current and voltage sources are examples of independent sources. In the case of dependent sources, the
source voltage or current is not constant, but it depends on a voltage or current of some other source. They are
broadly divided into the following types.
1. Current controlled current source
2. Current controlled voltage source
3. Voltage controlled current source
4. Voltage controlled voltage source
Mutual Inductance
Mutual inductance is due to mutual interaction of the
magnetic field created by the inductance. Thus,
magnetic field produced by changing current in one
inductor induces a voltage in another inductor.
The above principle is obtained from the Faradays
law. According to this law, a coil containing N turns,
with magnitude of flux linking each turn, has an
induced emf
dt
d
N e

=
A negative sign is frequently included in this equation to signal that the voltage polarity is established
according to Lenzs law.
By definition of self-inductance, the voltage is given by,
Fig. 1.5 Mutual Inductance
Basic Network 1.13
i d
d
N L
dt
d
N
dt
di
L
=
=
where = flux (weber, Wb).
Coupling Coefficient
The total flux f, resulting from current i
1
through N
1
consist of
leakage flux f
11
and coupling flux f
12
. The induced emf in coupled
coils is given by
Therefore,
1
12
2
12
2
i d
d
N M
dt
d
N
dt
di
M e
=
= =
where M = mutual inductance.
As the coupling is bilateral,
2
21
1
i d
d
N M

=
The coupling coefficient k, is defined as the ratio of linking flux to the total flux.
[ ] 1 0
2
21
1
12
= = k k
Therefore, M = k
2 1
L L
If k = 1, then all the flux from one coil is transferred to the other without any leakage in flux (close coupling).
For k = 0, no flux from one coil induces a voltage in the other.
Transformer
An ideal transformer is a hypothetical transformer in which there are no losses and the core has infinite
permeability, resulting in perfect coupling with no leakage flux. In large power transformer, the losses are small
relative to the power transferred.
PASSIVE ELEMENT CONFIGURATION
Resistors in Series
When resistors (R
1
, R
2
, R
3
) are connected in series, the
total voltage (V
T
) across two terminals (1 and 2) is equal
to the algebraic sum of individual voltages (V
1
, V
2
, V
3
)
across each resistance. The current (i
T
) flowing through
all resistors is same. Therefore
3 2 1
R R R R
eq
+ + =
When resistors are connected in series, the equivalent resistance is the addition of all resistors connected
in series.
Fig. 1.6 Flux Linkage in a Transformer
Fig. 1.7a Resistors in Series
Resistors in Parallel
When resistors (R
1
, R
2
, R
3
) are connected in parallel,
the total current (i
T
) is equal to the algebraic sum of
individual currents (i
1
, i
2
, i
3
) flowing through their
resistor. The voltage (V
T
) across each resistor is same
(all are connected in parallel with source). Therefore
3 2 1
1 1 1 1
R R R R
eq
+ + =
Inductors in Series
When inductors (L
1
, L
2
, L
3
) are connected in series, the total
voltage (V
T
) across two terminals (1 and 2) is equal to the algebraic
sum of individual voltages (V
1
, V
2
, V
3
) across each inductor. The
current (i
T
) flowing through all inductors is same. Therefore,
3 2 1
L L L L
eq
+ + =
When inductors are connected in series, the equivalent inductance is the addition of all inductors connected
in series.
Inductors in Parallel
If inductors (L
1
, L
2
, L
3
) are connected in parallel, the
total currents (i
t
) is equal to the algebraic sum of
individual currents (i
1
, i
2
, i
3
) flowing through
individual inductor. The voltage (V
T
) drop across
each inductor remains same. Therefore,
3 2 1
1 1 1 1
L L L L
eq
+ + =
Capacitors in Series
When capacitors (C
1
, C
2
, C
3
) are connected in
series, the total voltage (V
T
) across two terminals
(1 and 2) is equal to the algebraic sum of individual
voltages (V
1
, V
2
, V
3
) across each capacitor. The
current (i
T
) flowing through all capacitors is same.
Therefore,
3 2 1
1 1 1 1
C C C C
eq
+ + =
Fig. 1.7b Resistors in Parallel
Fig. 1.8a Inductors in Series
Fig. 1.8b Inductors in Parallel
Fig. 1.9a Capacitors in Series
Basic Network 1.15
Capacitors in Parallel
When capacitors (C
1
, C
2
, C
3
) are connected in
parallel the total current (i
T
) is equal to the algebraic
sum of individual currents (i
1
, i
2
, i
3
) flowing
through individual capacitor. The voltage drop (V
T
)
across each capacitor remains same. Therefore,
3 2 1
C C C C
eq
+ + =
When capacitors are connected in parallel, the equivalent capacitance is the addition of all parallel connected
capacitors.
NETWORK SIMPLIFICATION
Delta ( ) to Star (Y)
Z
1
= Z
A
Z
B
/ (Z
A
+ Z
B
+ Z
C
)
Z
2
= Z
B
Z
C
/ (Z
A
+ Z
B
+ Z
C
)
Z
3
= Z
C
Z
A
/ (Z
A
+ Z
B
+ Z
C
)
Star (Y) to Delta ( )
Z
A
= (Z
1
Z
2
+ Z
2
Z
3
+ Z
3
Z
1
) / Z
2
Z
B
= (Z
1
Z
2
+ Z
2
Z
3
+ Z
3
Z
1
) / Z
3
Z
C
= (Z
1
Z
2
+ Z
2
Z
3
+ Z
3
Z
1
) / Z
1
OHMS LAW
At a constant temperature, the current flowing through a conductor is directly proportional to the voltage
difference across the conductor. The proportionality constant is given by 1/R.
I
R
V
I V
1
where R = Resistance of the conductor (ohm, ).
KIRCHHOFFS LAW
Kirchhoffs Current Law (KCL)
It states that at any node, the sum of the currents entering a node is
equal to the sum of the current leaving. The connection of two or
more circuit elements (branches) creates a junction called a Node.
Current entering a node (N): I
A
, I
B
Current leaving a node (N): I
C
, I
D
, I
E
According to KCL, I
A
+ I
B
= I
C
+ I
D
+ I
E
Fig. 1.9b Capacitors in Parallel
Fig. 1.10 Star to Delta Conversion, Delta to
Star Conversion
A
B
C
D
N
E
I
B
I
A
I
E
I
D
I
C
Fig. 1.11 Kirchhoffs Current Law
Kirchhoffs Voltage Law (KVL)
For any closed path in any network, the al-
gebraic sum of the emfs is equal to the alge-
braic sum of the IR drops.
Emfs are V
1
and V
2
IR drops are V
R1
= I R
1
; V
R2
= I R
2
;
V
R3
= I R
3
.
According to KVL,
V
1
+ (V
2
) = I R
1
+ I R
2
+ I R
3
Experiment 1.1
Kirchhoffs Voltage Law
Aim To verify the Kirchhoffs voltage law.
Equipment Required
Equipment Range Quantity
Power supply
Voltmeter
Ammeter
(030) V
(030) V
(010) mA
2
3
1
Circuit Diagram
Procedure
1. Connect the circuit as per the circuit diagram.
2. Switch on the power supplies (10 V and 5 V) and note down the readings in the ammeter and
voltmeters.
3. Calculate the IR drop across each resistor.
4. Verify V
1
+ (V
2
) = IR
1
+ IR
2
+ IR
3
Fig. 1.12 Kirchhoffs Voltage Law
Basic Network 1.17
Experiment 1.2
Superposition Theorem
Statement In a linear bilateral network containing more than one generator, the current flowing through any
branch is the algebraic sum of currents flowing through that branch when generators are considered one at a
time and replacing other generator by their internal impedance.
Aim To verify the superposition theorem.
Equipment Required
Power supply
Ammeter
(030) V
(010) mA
2
1
Circuit Diagram
(a)
(b)

(c)
Procedure
1. Connect the circuit as per the circuit diagram [figure (a)].
2. Switch on the DC power supplies (10 V and 5 V) and note down the corresponding ammeter readings
(say I A).
3. Replace the second power supply by its internal resistance [figure (b)].
4. Switch on the power supply (10 V) and note down the corresponding ammeter reading (say I
1
).
5. Connect back the second power supply (5 V) and replace the first power supply by its internal
resistance [figure (c)].
6. Switch on the power supply (5 V) and note down the corresponding ammeter reading (say I
2
).
7. Verify the following condition: I = I
1
+ I
2
Tabular Column
I
1
(mA) I
2
(mA) I
1
+ I
2
(mA) I (mA)
Exercise
1. Repeat the above-mentioned procedure for asymmetrical network and compare with the symmetrical
network.
V
1
+
R
1
V
2
+
R
3
R
2
where R
1
R
2

R
3
2. Verify superposition theorem for -network.
Basic Network 1.19
Experiment 1.3
Maximum Power Transfer Theorem
Statement Maximum power will be delivered by a network to the load, if the impedance of the network (Z
N
) is
a complex conjugate of load impedance (Z
L
) and vice versa.
If we make X
L
= X
N
and R
L
= R
N
, maximum power will be transformed from the network to load. For
maximum power transfer, load impedance (Z
L
) should be complex conjugate of the network impedance (Z
N
).
The maximum power transferred is given by
watts
4
2
L
R
V
P = Aim To verify maximum power transfer theorem.
Circuit Diagram
DRB = Decade Resistance Box, DIB = Decade Inductor Box, DCB = Decade capacitor Box
Procedure
2. Set the input signal (say 1 V, 1 kHz).
3. Set the network DRB and DIB at some random value (say 1 k & 1 mH).
4. Set the load DRB to the value equal to network DRB (1 k) and vary the DCB of the load in regular
steps.
5. Note down the corresponding voltmeter and ammeter readings.
6. Plot the graph: Power vs Capacitance reactance.
7. Now set the load reactance equal to the network reactance.
8. Vary the DRB of the load in regular steps.
9. Note down the corresponding voltmeter and ammeter readings.
10. Plot the graph: Power vs Load resistance.
11. Compare the peak power in both the cases.
Tabular Column
Case (A): R
L
= R
N
= 1 k
X
C
( ) V (Volts) I (mA) P = V I
Case (B): X
L
= X
C
= 1 mH/1 mF
R
L
( ) V (Volts) I (mA) P = V I
Model Graphs
Exercise
Give some practical examples for maximum power transfer theorem.
Experiment 1.4
Thevenins Theorem
Statement Any linear bilateral network containing one or more voltage sources can be replaced by a single
voltage source whose value is equal to the open circuit voltage at output terminal with a series Thevenins
resistance. The Thevenins resistance is equal to the effective resistance looking back from the output terminal
by removing the load resistance.
Aim To verifiy Thevenins theorem.
Basic Network 1.21
Equipment Required
Power supply
Voltmeter
(030) V
(030) V
1
1
Circuit Diagram
(a)
Thevenins Voltage Experimental Setup
(b)
Thevenins Resistance Experimental Setup
(c)
Basic Network 1.29
Circuit Diagram
Series Resonance
The frequency of the series resonance is given by,
( ) f
LC
f
2 Hz
2
1
0

The current at any instant in a series resonance circuit is given by,
2
2
1
,
_
C
L R
V
I
At resonance,
R
V
I
0
Quality Factor
Let us consider the following circuits.
(a) (b)
For RL combination [figure (a)],
R fL Q
f
R I
LI
Q
/ 2
2
2
2
2
max
max
2
,
_

For RC combination [figure (b)].
f
R I
CV
Q
2
max
max
2
2
2
2
,
_

But,
C
V
1
max

Therefore,
fRC CR
Q
2
1 1

Since in series resonance, capacitive reactance is equal to inductive reactance (X
C
= X
L
), the Q-factor of a
series resonance circuit is defined as the ratio of the voltage across inductor or capacitor to the applied voltage.
Therefore,
C R
Q
CR R
L
Q
1 1
1
0
0
Bandwidth
Bandwidth of a series resonance circuit is defined as the difference between the upper and lower half-power
frequencies.
The bandwidth is given by,
Bandwidth
Q
f f
0
1 2
) (

where
2 1

n
and Q = Quality factor.
Selectivity
0
0
0
1 2
0 0
1
y Selectivit Therefore,
factor But,
y Selectivit
) ( y Selectivit
Q
R
L
Q
L
R
f f f
L
R
Procedure
1. Set up the circuit as per the circuit diagram given for plotting resonance curve.
2. Set input voltage, V
i
= 5V using signal generator and vary the frequency from (01) MHz in regular
steps.
3. Note down the corresponding output voltage and current.
Basic Network 1.31
4. Plot the following graph:
a) Current vs Frequency
b) Voltage vs Frequency
To measure the Resonance Frequency
1. Plot the graph: Current vs Frequency.
2. Draw a horizontal line which intersects the curve at
2
1
times the maximum current reading.
3. Lower intersected point and upper intersected point are respectively called lower cut off frequency and
upper cut off frequency on frequency-axis.
Tabular Column
Frequency (Hz) V
R
V
L
V
C
i
T
Model Graph
Experiment 1.9
Parallel Resonance
A parallel AC circuit is said to be in resonance when its susceptance is zero. At parallel resonance, the applied
voltage and resulting current will be in phase.
Let us consider a general parallel circuit.
The frequency of parallel resonance is given by,
2
2
0
2
1
C
L
R
C
L
R
C
L
LC
f
Current at resonance, I
0
= Y
0
V
'
1
1
]
1
+
+
1
1
]
1
2 2 2 2
0
C C
C
L L
L
X R
R
X R
R
V I
Aim To plot the resonance curve for a parallel resonance.
Equipment Required
Signal generator
Voltmeter
Ammeter
(01) MHz
(010) V
(010) mA
1
1
3
Circuit Diagram
(a)
Basic Network 1.33
Quality Factor
L
C
R
L
R
Q
0
0
Reactance
Resistance
Bandwidth and Selectivity

In a parallel resonance circuit, the specified points are the ones at which normalized impedance falls to
2
1
of its value at resonance.
Bandwidth, BW = f
2
f
1
Selectivity = Bandwidth/f
0
= (f
2
f
1
)/f
0
Procedure
1. Rig up the circuit as per the circuit diagram (figure (a)).
i
= 5 V using signal generator and vary the frequency from 10 Hz to 1 MHz in regular
steps.
3. Note down the corresponding output voltage and current.
4. Calculate the impedance by the formula, Z = V
T/i
5. Plot the graph: Impedance vs Frequency.
To Measure the Resonance Frequency
1. Plot the graph: Impedance vs Frequency.
2. Draw a horizontal line, which intersects the curve at
2
1
times the impedance reading.
3. Lower intersected point and upper intersected point are respectively called lower cut-off frequency and
upper cut-off frequency on frequency-axis.
Tabular Column
Frequency (Hz) i
R
i
L
i V
t
Z = V
T
/ i
Model Graph
(b)
Experiment 1.10
Differentiator
A differentiator is a simple RC network. If the time constant (RC) is very small (RC<< ) in comparison with the
time required for the input signal to make an appropriate change, then the circuit results in a differentiated
output.
A differentiator circuit is as shown below.
V
0
Aim To study the given differentiator at different time constants.
Equipment Required
Signal generator
CRO
(01) MHz
(020) MHz
1
1
Circuit Diagram
Design

k 10 then 1 0 If
10 1
msec 1
1
kHz; 1 For
3
C
R F, . C
RC
f
T f ; T
Basic Network 1.35

< < >
> > <
k 10 then , For
k 10 then , For
C
R T
C
R T
Procedure
i
= 5V using pulse generator and vary the frequency from (01) MHz in regular steps.
3. Observe the output waveform using CRO.
4. Change the value of R as per the design and observe the output waveform using CRO.
Model Waveform
Experiment 1.11
Integrator
An integrator is a simple RC network. If the time constant (RC) is very large (RC>> ) in comparison with the
time required for the input signal to make an appropriate change, the circuit results in an integrated output.
V
0
Aim To study the given integrator time constant.
Equipment Required
Signal generator
CRO
(01) MHz
(020) MHz
1
1
Circuit Diagram
Design

k
C
R C
RC
f
T f T
10 then F, 1 0. If
10 1
msec 1
1
kHz; 1 ; For
3
For T < , then R >

C
> 10 k
For T >
,
then R <
C
< 10 k
Procedure
i
= 5 V using pulse generator and vary the frequency from (01) MHz in regular steps.
3. Observe the output waveform using CRO.
4. Change the value of R as per the design and observe the output waveform using CRO.
Basic Network 1.37
Model Waveform
PASSIVE FILTERS
G.A.Campbell and O.I. Lobel of the Bell Telephone Laboratories invented wave filters. A filter is a reactive
network, which passes the desired frequencies only. Ideally, filters should produce no attenuation in the
desired band, called pass band, and should attenuate fully in other frequency region, called attenuation band.
The frequency, which separates the pass band and attenuation band, is termed as cut-off frequency of the wave
filter (f
c
).
Filter finds its application in many fields like data communication, instrumentation, signal processing, etc.
Filters are broadly divided into 4 groups
1. Low pass filter (LPF)
2. High pass filter (HPF)
3. Band pass filter (BPF)
4. Band elimination filter (BEF)
Low Pass Filter
A LPF is one which passes all frequencies up to its
designed/desired cut-off frequency, f
c
, and
attenuates all other frequencies greater than the
cut-off frequency.
Ideal waveform
High Pass Filter
A HPF is one, which passes all frequencies above
designed/desired cut off frequency, f
c
and attenuates
all other frequencies below cut off frequency.
Band Pass Filter
A BPF is one which passes frequencies between two
designed/desired cut-off frequencies (f
l
= lower cut
off frequency, f
h
= upper cut off frequency) and
attenuates all other frequencies.
Band Elimination Filter
A BEF is one which attenuates frequencies between
two designed/desired cut-off frequencies (f
l
= lower
cut off frequency, f
h
= upper cut off frequency) and
passes all other frequencies.
Filters are made of symmetrical T or L or
network. A study of any filter requires the following
parameters.
1. Propagation constant,
2. Attenuation constant,
3. Phase constant,
4. Characteristic impedance, Z
0
where Propagation constant, = + j
Experiment 1.12
Constant-k LPF
Aim To design and test a constant-k LPF and measure its cut-off frequency.
Equipment Required
Equipment
Signal generator
CRO
Ideal waveform
Ideal waveform
Ideal waveform
Basic Network 1.39
Circuit Diagram
Design
inductor) (series ; capacitor) (shunt
1
680 , kHz 2 , 680 Given
C
f
R
L
R f
C
R R R
R f R
k
k C
k s L
s C L

Procedure
i
= 5V using signal generator and vary the frequency from 10 Hz in regular steps up to
1MHz.
3. Note down the corresponding output voltage (V
O
).
4. Plot the following graph: Gain vs Frequency.
Tabular Column
Frequency (Hz) Output Voltage (volts) Gain
Model Graph
Result
Theoretical Practical
Cut-off
frequency
Exercise
Design a -section constant-k LPF and compare the result with T-section constant-k LPF.
Experiment 1.13
Constant-k HPF
Aim To design and test a constant-k HPF and measure its cut off frequency.
Equipment Required
Signal generator
CRO
(01) MHz
(020) MHz
1
1
Circuit Diagram
Design
inductor) (shunt
4
; capacitor) (series
2
1
680 , kHz 2 , 680 Given
C
k
k C
k s L
s C L
f
R
L
R f
C
R R R
R f R

Procedure
i
= 5 V using signal generator and vary the frequency from 10 Hz in regular steps up to
1 MHz.
Basic Network 1.41
0
).
Tabular Column
Model Graph
Result
Cut-off
frequency
Exercise
Design a -section constant-k HPF and compare the result with T-section constant-k HPF.
(a) (b)
Experiment 1.14
Constant-k Band Pass Filter
Aim To design and test a constant-k BPF and measure its cut-off frequency.
Equipment Required
Signal generator
CRO
(01) MHz
(020) MHz
1
1
Circuit Diagram
Design
To evaluate the values for the series arm, consider the equations,
( )
( )
1 2
1
2 1
1 2
1
;
4 f f
R
L
f f R
f f
C
k
k

To evaluate the values for the shunt arm, consider the equations,
( )
( )
1 2
2
2 1
1 2
2
1
;
4 f f R
C
f f
f f R
L
k
k

Procedure
2. Set input voltage, v
i
= 5V using signal generator and vary the frequency from 10 Hz in regular steps upto
1 MHz.
0
).
Basic Network 1.43
Tabular Column
Model Graph
Result
Lower cut-off
frequency
Upper cut-off
frequency
Experiment 1.15
Constant-k Band Elimination Filter
Aim To design and test a constant-k BEF and measure its cut-off frequency.
Equipment Required
Signal generator
CRO
(01) MHz
(020) MHz
1
1
Circuit Diagram
Design
To evaluate the values for the shunt arm, consider the equations,
( )
( )
1 2
2
2 1
1 2
2
4
;
f f
R
L
f f R
f f
C
k
k

To evaluate the values for the series arm, consider the equations,
( )
( )
1 2
2
2 1
2 1
1 2 2
2 1
4
1
/ ;
f f R
R L C
f f
f f R
R C L
k
k
k
k

Procedure
i
= 5V using signal generator and vary the frequency from 10 Hz in regular steps up to
1 MHz.
0
).
Tabular Column
Basic Network 1.45
Model Graph
Result
Lower cut-off
frequency
Upper cut-off
frequency
Experiment 1.16
m-Derived LPF
Aim To design and test a m-derived LPF and measure its cut-off frequency.
Equipment Required
Signal generator
CRO
(01) MHz
(020) MHz
1
1
Circuit Diagram
Design
0 < m < 1 (m = 0.5, say); f = 2 kHz
Assume C = 0.01F

? ;
1
;
) 1 (
1
2

L
LC
f
m LC
f
r r
Procedure
i
= 5V using signal generator and vary the frequency from 10Hz in regular steps upto
1MHz.
O
).
Tabular Column
Model Graph
Result
Cut-off
frequency
Exercise
1. Design a -section m-derived LPF and calculate its parameter. Compare the result with T-section m-derived
LPF.
2. Explain the characteristic difference between constant-k LPF over m-derived LPF.
Basic Network 1.47
Experiment 1.17
m-Derived HPF
Aim To design and test a m-derived HPF and measure its cut-off frequency.
Equipment Required
Signal generator
CRO
(01) MHz
(020) MHz
1
1
Circuit Diagram
Design
0 < m <1 (m = 0.5, say); f = 2 kHz
Assume C = 0.01 F
? ;
4
1
;
4
1 .
2
L
LC
m
f
LC
f
r

Procedure
i
= 5V using signal generator and vary the frequency from 10 Hz in a regular steps upto
1MHz.
O
).
Tabular Column
Model Graph
Result
Cut-off
frequency
Exercise
1. Design a -section m-derived HPF and calculate its parameter. Compare the result with T-section
m-derived HPF.
2. Explain the characteristic difference between constant-k HPF over m-derived HPF.
Experiment 1.18
Twin-T Filter
Aim To design twin-T filter for the given frequency and to obtain its frequency response.
Equipment Required
Power supply
Functional generator
(030) MHz
(01) MHz
1
1
Components Required
Components Value Quantity
Resistor
Capacitor
0.1 F
3
3
Basic Network 1.49
Circuit diagram
Design
RC
f
) 2 ( 2
1
0
Assume C = 0.1F : f
0
= 5 kHz; R = ?
Procedure
1. Connections are made as per the circuit diagram.
2. Set the input signal (say 1V at 5 kHz) using function generator.
3. Vary the frequency of the signal using function generator in regular steps and note down the
corresponding output voltage (V
O
).
4. Plot the graph: Output Voltage (volts) vs Frequency (Hz).
Tabular Column
V
i
= 1 V
Frequency (Hz) Output voltage (Volt)
Model Graph
Experiment 1.19
Equalizer
Aim To design equalizers and study their characteristics.
Equipment
CRO
Signal generator
(020) MHz
(01) MHz
1
1
Components Required
Resistor
DCB
DIB
680
2
2
2
Circuit Diagram
(a) (b)
Design
For inverse impedance,
2 1 0
Z Z R
1 Therefore
1
power output
power input
1
] (b) Fig [ of inverse be will ; : 1 Case
1
0
2
1
2
0
2
1
2
0
2
1
2
0 2 1
1 2 1 1

1
1
]
1
,
_
M
R
L
R
X
M
R
C
L
R
L
L
R X X
X X L X
o
Basic Network 1.51
o
o
R
M
L
R
C
L
a X
X
L
X
1
)] ( Fig [
of inverse be will ;
1
: 2 Case
2
2
1
2
1
2
1
1
Procedure
1. Connections are made as per the circuit diagram
2. Set the input signal say 1 V at 1 kHz using function generator.
3. Vary the signal frequency from 1 Hz to 1 kHz and note down the corresponding output voltage (V
O
)
4. Plot the graph: V
O
(volts) vs Frequency.
Tabular Column
V
l
= 1 V
Frequency (Hz) V
o
(Volt)
Model Graph
Experiment 1.20
Attenuator
An attenuator is a two-port network (purely resistance) and is used to reduce the signal level to a designed/
desired level. It will introduce a loss without affecting the impedance matching between source and the
terminating load. Attenuators can be symmetrical or asymmetrical, and also can be fixed or variable.
Attenuation (dB) = 10 log
10
,
_
2
1
P
P
where P
1
= input power and P
2
= output power
Aim To design a -attenuator, which attenuates given signal to the desired level.
Equipment Required
Signal generator
CRO
(01) MHz
(020) MHz
1
1
Circuit Diagram
Design
Given D = 2 dB; R
s
= R
L
= 680 = R
0
,
_

,
_
,
_
20
antilog ;
1
1
;
2
) 1 (
0 2
2
0 1
dB
D
N
N
N
R R
N
N
R R
Procedure
i
= 5V using signal generator and vary the frequency from 10 Hz in regular steps upto
1 MHz.
O
).
4. Plot the graph: Output voltage vs Frequency.
Tabular Column
Frequency (Hz) Output Voltage (volts)
Basic Network 1.53
Model Graph
Result
Attenuation (D) Theoretical Practical
Exercise
Repeat the procedure for other types of attenuators.
(a) T- type attenuator
(b) Bridge T-type attenuator
(c) Lattice attenuator
Device Characteristics 2.1
C h a p t e r 2
DEVICE CHARACTERISTICS
TESTING OF ELECTRONIC DEVICES
Diode
1. Connect a multimeter (in resistance mode) across the diode.
2. Observe the resistance of the diode in that position. If it shows lower resistance value, diode is in
forward bias. Then, the terminal connected to the positive terminal of the multimeter is p-junction
and other terminal is n-junction.
3. Now, reverse the multimeter position and observe the resistance value. If it shows high resistance
then the given diode is good.
Transistor
1. Transistor follows the same rules as that of a diode.
2. For an npn transistor, connect the multimeter positive terminal to base terminal of the transistor and
negative terminal to the emitter terminal of the transistor.
3. Follow the procedure given for diode. If it is successful, then given transistors base-emitter junction
is good.
4. Now, shift the negative terminal of the multimeter to the collector terminal of the transistor by
maintaining the positive terminal same.
5. Follow the procedure given for diode. If it is successful, then the given transistors base-collector
junction is good.
6. Observe the collector to emitter resistance of the given transistor. It should be a high resistance in
both the directions.
7. Above said procedure can be executed for pnp transistor. Here, multimeter positions should be
interchanged. Remaining procedure remaining same.
Unijunction Transistor
1. In the case of UJT, emitter to base
1
(configuration-1) and emitter to base
2
(configuration-2) should
exhibit a typical diode characteristic except the diode resistance in forward and reverse case is different
for two configurations.
2. The resistance across base
1
to base
2
should be a fixed resistance in either direction.
Field Effect Transistor
1. In the case of FET, drain to source should be fixed resistance in either direction.
2. Gate to drain or gate to source should be an open circuit or very high resistance.
Experiment 2.1
Diode Characteristics
Aim To study the diode characteristics under forward and reverse bias condition using.
1. Junction diode
2. Zener diode
Equipment Required
Power supply
Ammeter
Voltmeter
(030) V
(030) mA
(0250) A
(01) V
(020) V
1
1
1
1
1
Circuit Diagram
Forward bias Reverse bias
Procedure
Forward biasing
2. Vary the power supply voltage in such a way that readings should be taken in steps of 0.1 V in the
voltmeter till the power supply shows 20 V.
3. Note down the corresponding ammeter readings.
4. Plot the graph: V against I
5. Find the dynamic resistance,
I
V
r
=
Reverse biasing
2. Vary the power supply voltage in steps of 1V till the power supply shows 15V.
3. Note down the corresponding ammeter readings.
4. Plot the graph: V against I.
5. Find the dynamic resistance,
I
V
r
=
Follow the above-mentioned procedure for other diodes (say zener diode, point-contact diode, etc.)
Result
Forward and reverse bias characteristics of junction and zener diodes are plotted and their dynamic resistance
is as follows:
Dynamic Resistance r Junction Diode Zener Diode
Forward bias
Reverse bias
Note: Connect an ammeter (010) mA in reverse bias circuit configuration for zener diode experiment only.
Model Graph
Junction diode
Zener Diode
Experiment 2.2
Rectifier
Aim To study the following rectifiers with and without capacitor filter.
1. Half-wave rectifier
2. Full-wave rectifier
3. Bridge rectifier
To find its
1. Percentage regulation
2. Ripple factor
3. Transformer utilisation factor
4. Efficiency
Equipment Required
CRO
Multimeter
(020) MHz 1
1
Circuit Diagram
Half-wave rectifier
Full-wave Rectifier
Bridge Rectifier
Procedure
Without capacitor filter
1. Test your transformer. Give 230 V, 50 Hz source to the primary coil of the transformer and observe AC
waveform of rated value without any distortion at the secondary of the transformer.
2. Connect your circuit to the secondary terminals of the transformer.
3. Connect your CRO across the load.
4. Keep the CRO switch in ground-mode, observe the horizontal line and adjust it to the X-axis.
5. Switch the CRO into DC mode and observe the waveform. Note down its amplitude, V
m
and frequency
from the screen along with its multiplication factor.
6. Calculate V
dc
using the relation:
m
dc
V
V =
or directly from the multimeter in DC mode.
7. Switch the CRO into AC mode and observe the waveform. Note down its amplitude, V
m
and frequency
from the screen along with its multiplication factor.
8. Calculate V
ac
using the relation: V
2
rms
= V
2
ac
+ V
2
dc

2
m
rms
V
V =

or directly from the multimeter in AC mode.
9. Calculate the ripple factor from the given formula:
dc
ac
V
V
=
.
10. Remove the load and measure the output AC voltage (AC-mode) and calculate the percentage of voltage
regulation using the formula:
Percentage regulation %
V
V V
load
load load no
100
=
11. To measure ratio of rectification, observe the power (DC and AC) using wattmeter across the load. The
ratio of rectification is given by
ac
dc
P
P
.
With capacitor filter
1. Calculate the value of R by assuming C = 1000 F and f = 50 Hz using the formula:
for HWR, the ripple factor,
fRC 3 2
1
=
(Assume as 0.002 or any small value).
for FWR, the ripple factor,
4
=
(Assume
as 0.002 or any small value)

2. Connect the capacitor across the load resistance (with polarity of the capacitor as shown in circuit diagram).
3. Switch the CRO in DC-mode. Measure the peak amplitude with respect to ground reference. Let us call
the voltage V
dc
.
4. Switch the CRO in AC-mode. Measure the peak-to-peak voltage of the signal. Let us call the AC voltage
m
V =
5. The practical ripple factor can be calculated by the formula, .
dc
ac
V
V
=
Result
Parameters Half-wave Full-wave Bridge
Ripple factor with filter : theoretical
practical
0.002 0.002 0.002
Ripple factor without filter : theoretical
practical
1.21 0.48 0.48
Percentage regulation : theoretical
practical
Experiment 2.3
Clipping Circuits
Aim To observe the clipping waveform in different clipping configurations.
Equipment Required
Signal generator
CRO
Power supply
(01) MHz
(020) MHz
(030) V
1
1
1
Circuit Diagram
1.
2.
Procedure
2. Set input signal voltage (say 5 V, 1 kHz) using signal generator.
3. Observe the output waveform using CRO (DC-mode).
4. Sketch the observed waveform on the graph sheet.
Experiment 2.4
Clamper Circuits
Aim To study the clamping circuits
a) positive clamping circuit
b) negative clamping circuit
Equipment Required
Signal generator
CRO
Power supply
(01) MHz
(020) MHz
(030) V
1
1
1
Circuit Diagram
Design
Given f = 1 kHz,
RC
f
T = = = =

sec 10 1
1
3
Assume, C = 0.1 F
Then, R = 10 k
Procedure
2. Set input signal voltage (say 5 V, 1 kHz) using signal generator.
3. Observe the output waveform using CRO (DC-mode).
4. Sketch the observed waveform on the graph sheet.
Experiment 2.5
Transistor (CE - Configuration) Characteristics
Aim To plot the transistor characteristic of common-emitter configuration and to find the h-parameters for the
same.
Equipment Required
Power supply
Ammeter
Voltmeter
(030) V
(0100) A
(010) mA
(01) V
2
1
1
Circuit Diagram
Procedure
Input characteristic
2. Set V
CE
= 5 V (say), vary V
BB
in steps of 1 V to 20 V and note down the corresponding I
B
and V
BE
. Repeat
the above procedure for 10 V, 15 V, etc.
BE
vs I
B
for a constant V
CE.
4. Find the h-parameters:
a) h
ie
: input impedance
= constant
1 2
1 2
CE
B B
BE BE
CE
B
BE
ie
V
I I
V V
V
I
V
h
b) h
re
: reverse voltage gain
= constant
1 2
1 2
B
CE CE
BE BE
B
CE
BE
re
I
V V
V V
I
V
V
h
Output Characteristic
2. Set I
B
= 20A (say), vary V
CC
in steps of 1V and note down the corresponding I
C
and V
CE
. Repeat the
above procedure for 40A, 60A, 80A.
CE
vs I
C
for a constant I
B
.
a) h
fe
: forward current gain
= constant
2 2
1 2
CE
B B
c c
CE
B
c
fe
V
I I
I I
V
I
I
h
b) h
oe
: output admittance
= constant
1 2
1 2
B
CE CE
c c
B
CE
c
oe
I
V V
I I
I
V
I
h
Tabular Column
Input characteristicsV
CE
constant
V
BE
(volts) I
B
( A)
Output characteristicsI
B
constant
V
CE
(volts) I
C
(mA)
Result
Parameters Practical Readings
h
fe
h
ie
h
re
h
oe
Model Graph
Input characteristics
Output characteristics
Experiment 2.6
Transistor (CC - Configuration) Characteristics
Aim To plot the transistor characteristic of common-collector configuration and to find the h-parameters for
the same.
Equipment Required
Power supply
Ammeter
Voltmeter
(030) V
(010) mA
(0100) A
(030) V
2
1
1
1
Circuit Diagram
Procedure
Input characteristic
2. Set V
EC
= 5 V (say), vary V
BB
insteps of 0.1 V up to 20 V and note down the corresponding I
B
and V
BC
.
Repeat the above procedure for V
EC
10 V, 15 V, etc.
BC
vs I
B
for a constant V
EC.
a) h
rc
: reverse voltage gain
= Constant
1 2
1 2
B
EC EC
EB EB
B
EC
EB
rc
I
V I
V V
I
V
V
h
b) h
ic
: input impedance
= Constant
1 2
1 2
BC
B B
BE BE
CE
B
BE
ic
V
I I
V V
V
I
V
h
Output Characteristic
2. Set I
B
= 20 A (say), vary V
EE
in steps of 1V upto 20 V and note down the corresponding I
E
and V
CE
.
Repeat the above procedure for I
B
40 mA, 80 mA, etc.
CE
vs I
C
for a constant I
B
.
a) h
oc
: output admittance Constant
1 2
1 2
=
=
B
EC EC
E E
B
EC
E
oc
I
V V
I I
I
V
I
h
b) h
fc
: forward current gain Constant
1 2
1 2
=
=
CE
B B
E E
CE
B
E
fc
V
I I
I I
V
I
I
h
Model Graph
Input Characteristics
Amplifier Circuit Design 3.1
C h a p t e r 3
AMPLIFIER CIRCUIT DESIGN
TEST FOR ACTIVE REGION
1. According to our design, V
CC
= I
C
R
C
+ V
CE
+ I
E
R
E
(RC - coupled amplifier design).
2. Since V
CE
= V
CC
/2 (to set transistor in active region), after applying biasing voltage (V
CC
), the drop
across collector to emitter should be half of biasing voltage (V
CC
).
3. If it is not satisfied, connect a potentiometer in series with R
B2
whose value should be 10 k with
respect to R
B2
.
4. Vary the potentiometer in such a way that the voltage drop across emitter collector V
CE
of the transistor
is half of the biasing voltage.
5. If any non-linearity occurs in your output waveform, introduce a negative feedback in the circuit. This
can be done by connecting a potentiometer in the emitter side whose value is above the designed
value. (top terminal of the potentiometer should be connected to the emitter terminal of the transistor,
centre terminal should be connected to the positive terminal of the capacitor and the lower terminal
should be connected to the ground of the circuit.)
6. On the other hand, by reducing the amplifier gain, we can reduce the non-linearity in the output
waveform. This can be done by replacing the fixed collector resistor (R
C
) by a potentiometer of the
same order and varying it in the opposite direction.
GENERAL PROCEDURE OF CALCULATION
1. Input Impedance
a) Connect a Decade Resistance Box (DRB) between input voltage source and the base of the transistor
(series connection).
b) Connect ac voltmeter (0100 mV) across the biasing resistor R
2
.
c) Vary the value of DRB such that the ac voltmeter reads the voltage half of the input signal.
d) Note down the resistance of the DRB, which is the input impedance.
2. Output Impedance
a) Measure the output voltage when the amplifier is operating in the mid-band frequency with load
resistance connected (V
load
).
b) Measure the output voltage when the amplifier is operating in the mid-band frequency without load
resistance connected (V
no-load
).
c) Substitute these values in the formula,
% 100
0

load
load no load
V
V V
Z
3. Bandwidth
a) Plot the frequency response.
b) Identify the maximum gain region.
c) Drop a horizontal line by 3dB.
d) The 3dB line intersects the frequency response plot at two points.
e) The lower intersecting point of 3dB line with the frequency response plot gives the lower cut-off
frequency.
f) The upper intersecting point of 3dB line with the frequency response plot gives the upper cut-off
frequency.
g) The difference between upper cut-off frequency and lower cut-off frequency is called Bandwidth.
Thus, Bandwidth = f
h
f
l
Experiment 3.1
RC Coupled Amplifier
Aim To design and implement the RC coupled amplifier circuit and to find:
1. Cut-off frequencies
2. Bandwidth
3. Mid-band gain
4. Input/Output impedance
Equipment Required
Power supply
CRO
Function generator
(030) V
(020) MHz
(01) MHz
1
1
1
Circuit Diagram
Design
Given: V
CC
= 15 V; I
C
= 1 mA; A
V
= 50; f
L
= 500 Hz; Stability factor = [210].
Gain formula is given by,
ie
Leff fe
V
h
R h
A
Assume,
10
; condition) (Active
2
CC
E
CC
CE
V
V
V
V
Effective load resistance is given by R
Leff
= R
C
|| R
L
Internal emitter resistance is given by
E
e
I
r
mV 26
h
ie
= r
e
where r
e
is internal emitter resistance of the transistor.
h
ie
= h
fe
r
e
On applying KVL to output loop, we get
V
CC
= I
C
R
C
+ V
CE
+ I
E
R
E
where V
E
= I
E
R
E
R
C
= ?
The emitter current is given by the equation I
E
= I
B
+ I
C
Since I
B
is very small when compared with I
C
,
?
E
E
E
E C
I
V
R
I I
The voltage at the base of the transistor is given by
V
B
= V
BE
+ V
E
From voltage divider rule, the voltage at the base of the transistor is given by
2 1
2
B B
B
CC B
R R
R
V V
+
(i)
The equation for stability factor is given by
E
B
R
R
S + 1
Find R
B
R
B
= R
B1
|| R
B2
(ii)
From equations (i) and (ii), solve for R
B1
, and R
B2
Input coupling capacitor is given by,
( )
?
2
1
10
||
i
i
Ci
B ie
Ci
C
C f
X
R h
X
Output coupling capacitor is given by

?
2
1
10
||
0
0
0
0
C
C f
X
R R
X
C
L C
C
By-pass capacitor is given by,

10
E
CE
R
X
where,
( )
1
1
]
1
+

fe
ie B
E E
h
h R
R R ||
?
2
1
E
E
CE
C
C f
X

Procedure
2. Set V
S
= 50 mV (say) using the signal generator.
3. Keeping the input voltage constant, vary the frequency from 0 Hz to 1 MHz in regular steps of 10 and note
down the corresponding output voltage.
4. Plot the frequency response: Gain (dB) vs Frequency (Hz).
5. Find the input and output impedance.
6. Calculate the bandwidth from the graph.
7. Note down the phase angle, bandwidth, input and output impedance.
Tabular Column
V
i
= 50 mV
Frequency V
0
(volts) Gain = V
0
/V
i
Gain (dB) = 20 log(V
0
/V
i
)
Model Graph: (Frequency Response)
Result
Input impedance
Output impedance
Gain(Mid-band)
Bandwidth
Experiment 3.2
Two Stage RC Coupled Amplifier
Aim To design and test a two stage RC coupled amplifier circuit and to find:
1. Bandwidth
2. Mid-band gain
3. Input / Output impedance
Equipment Required
Power supply
CRO
Function generator
(030) V
(020) MHz
(01) MHz
1
1
1
Circuit Diagram
Design
Given data: A
V2
=10; A
V1
= 20; f
L
= 50 Hz; I
E2
= 1.2 mA; I
E1
= 1.5 mA; V
CC
= 12 V
2
2
2
ie
Leff fe
V
h
R h
A
R
Leff
= R
2
|| R
L
h
fe2
= 200 (from multimeter)
r
e2
= 26 10
3
/ I
E2
= ?
h
ie2
= h
fe2
r
e2
From DC bias analysis, on applying Kirchhoffs voltage law to the output loop, we get
V
CC
= I
C2
R
C2
+ V
CE2
+ V
E2
V
CE2
= V
CC
/2; V
E2
= V
CC
/10;
Since I
B2
is very small when compared with I
C2
I
C2
I
E2
Find R
C2
The equation for the voltage gain is given by
2
2
2
ie
Leff fe
v
h
R h
A

Find, R
L
|| R
C2
from above equation.
Since, R
C2
is known, calculate R
L
The emitter current is given by,
?
E
E
E
E E E
I
V
R
R I V
The stability factor is given by
?
1
2
2
2
+
B
E
B
R
R
R
S
The base resistance of II stage is the parallel combination of biasing resistors R
3
and R
4
R
B2
= R
3
|| R
4
(i)
From voltage divider rule, the voltage at the base of BJT is given by
4 3
4
2
R R
R
V V
CC B
+
(ii)
The base voltage of BJT is sum of voltage drop across base-emitter and emitter voltage, which is given by
V
B2
= V
BE2
+ V
E2
on solving (i) and (ii),
R
3
= ?
Therefore, find R
4
.
Z
i2
= h
ie2
|| R
B2
Z
i2
= ?
R
Leff1
= Z
i2
|| R
C1
Find R
Leff1
from the gain formula given above
?
1
1 1
1
Leff
ie
Leff fe
v
R
h
R h
A
On applying KVL to the first stage, we get
V
CC
= I
C1
R
C1
+ V
CE1
+ V
E1
Since I
C1
I
E1
R
C1
= ?
The emitter resistance,
1
1
1
E
E
E
I
V
R
R
E1
= ?
The equation for stability is given by,
?
1
1
1
1
+
B
E
B
R
R
R
S
The base resistance of I stage is parallel combination of biasing resistors R
1
and R
2
R
B1
= R
1
|| R
2
(iii)
From voltage divider rule, the base voltage is given by
2 1
2
1
R R
R
V V
CC B
+
(iv)
The base voltage is sum of V
BE
drop and emitter resistor drop, which is given by
V
B1
= V
BE2
+ V
E2
on solving (iii) and (iv),
Find R
1
Therefore, find R
2
.
Gain (including source resistance) is given by,
?
||
1 1 1
1
1
VS
B ie i
S i
i
VI VS
A
R h Z
R R
R
A A
Total gain including source resistance is given by,
A
VT
= A
VS
A
V2
The input coupling capacitor can be obtained from
( )
?
2
1
10
||
1 1
i
i
Ci
B ie
Ci
C
fC
X
R h
X
The output coupling capacitor can be obtained from

?
2
1
10
||
0
0
2
,
_
C
fC
X
R R
X
CO
Leff C
CO
The by-pass capacitor can be obtained from

?
2
1
|| where
10
2
2
2
2 2
2 2
2
2
,
_
,
_
E
E
CE
fe
ie B
E E
E
CE
C
fC
X
h
h R
R R
R
X
Similar calculation can be incorporated to find the value of C

E1
Procedure
2. Set V
i
= 50 mV (say), using the signal generator.
3. Keeping the input voltage constant, vary the frequency from 0 Hz to 1 MHz in regular steps and note down
the corresponding output voltage.
4. Plot the graph: Gain (dB) vs Frequency (Hz).
5. Find the input and output impedance
7. Note down the phase angle, bandwidth, input and output.
Tabular Column
V
i
= 50 mV
Frequency V
0
(volts) Gain = V
0
/V
i
0
/V
i
)
Model Graph (Frequency Response)
Result
Input impedance
Output impedance
Gain (Mid-band)
Bandwidth
Experiment 3.3
Emitter Follower (Common Collector Amplifier)
Aim To design and test a common collector current amplifier and to find the following parameters:
1. Current gain
2. Voltage gain
3. Bandwidth
4. Input and output impedance
Equipment Required
Power supply
CRO
Function generator
(030) V
(020) MHz
(01) MHz
1
1
1
Circuit Diagram
Design
Given: V
CC
= 12 V; f
L
= 50 Hz; I
E
= 1 mA; S = [110]; = h
fe
e fe ie
E
e
r h h
I
r
mV 26
where r
e
is internal resistance of the transistor.
The voltage gain is given by,
e E
E
V
r R
R
A
+
1
The current gain is given by,
e E
E
fe I
r R
R
h A
+
V
CC
= V
CE
+ V
E
; V
CE
= V
CC
/2
V
E
= I
E
R
E
R
E
= ?
The stability is given by,
E
B
R
R
S + 1
R
B
= ?
The base resistance is the parallel combination of biasing resistors R
1
and R
2
R
B
= R
1
|| R
2
(i)
From voltage divider rule, the base voltage is given by,
2 1
2
R R
R
V V
CC B
+
(ii)
The base voltage is equal to sum of V
BE
drop and emitter resistance drop, which is given by
V
B
= V
BE
+ V
E
on solving (i) and (ii).
Find R
2
Therefore, R
1
= ?
( )
( )
?
2
1
10
?
2
1
10
?
1
||
||
||
?
) 1 ( ) (
0
0
0
1
1
]
1
+
+
+ +
E
E
CE
CE
i
i
Ci
ieff
Ci
eff
fe
ie B S
E
BB i Leff
fe E ie i
C
C f
X
Z
X
C
C f
X
Z
X
Z
h
h R R
R Z
R Z Z
Z
h R h Z
Procedure
2. Set V
i
= 1 V (say), using the signal generator.
Tabular Column
V
i
= 1V
Frequency V
0
(volts) Gain = V
0
/V
i
Gain (dB) = 20
0
log(V
0
/V
i
)
Result
Input impedance
Output impedance
Gain (Mid-band)
Bandwidth
Experiment 3.4
Darlington Pair (Common Collector Amplifier)
Aim To design and test a Darlington current amplifier and to find the following parameters:
1. Current gain
2. Voltage gain
3. Bandwidth
Equipment Required
Power supply
CRO
Function generator
(030) V
(020) MHz
(01) MHz
1
1
1
Circuit Diagram
Design
Given: V
CC
= 12 V; f
L
= 50 Hz; I
E
= 1 mA; S = [110]; h
fe1
= h
fe2
A
V
1, A
I
= A
I1

A
I2
Since h
fe1
=

h
fe2
; A
I
= (h
fe
)
2
V
CC
= V
CE
+ V
E
; V
CE
=V
CC
/2
V
E
= I
E
R
E
R
E
= ?
The stability factor is given by,
E
B
R
R
S + 1
R
B
= ?
The base resistance is the parallel combination of biasing resistors R
1
and R
2
, which is given by
R
B
= R
1
|| R
2
(i)
The base voltage can be calculated by applying the voltage divider rule to base, which is given by
2 1
2
R R
R
V V
CC B
+
(ii)
The base voltage is the sum of V
BE
drop and emitter resistance drop, which is given by
V
B
= V
BE
+ V
E
on solving (i) and (ii),
R
2
= ?
Therefore, find R
1
Z
i
= (h
fe1
h
fe1
) R
E
Z
i
= ?
Z
ieff
= Z
i
|| R
BB
( )
( ) 1
1
]
1
+
+
2
0
1
2 ||
||
fe
ie B S
E
h
h R R
R Z
Z
0eff
= ?
i
Ci
ieff
Ci
fC
X
Z
X
2
1
10
C
i
= ?
E
CE
CE
fC
X
Z
X
2
1
10
0
C
E
= ?
Procedure
2. Set V
i
= 1 V (say), using the signal generator.
Tabular Column
V
i
= 1 V
Frequency V
0
(volts) Gain = V
0
/V
i Gain (dB) = 20
0
log (V
0
/V
i
)
Result
Input impedance
Output impedance
Gain (Mid-band)
Bandwidth
Experiment 3.5
Cascode Amplifier
Aim To design and test the cascode amplifier for the given specification and find the following parameters:
1. Mid-band gain
Equipment Required
Power supply
CRO
Function generator
(030) V
(020) MHz
(01) MHz
1
1
1
Circuit Diagram
Design
Given V
CC
= 15 V; I
E1
= I
E2
= 1 mA; A
V
= 100; f
L
= 50 Hz; R
L
= 4.7 k; h
fe1
= h
fe2
, Stability factor = [210]
Assume, V
CE1
= V
CC
/3 (transistor Active); V
CE2
= V
CC/3
Effective load resistance is given by, R
Leff
= R
C
|| R
L
Emitter resistance is given by,
E
e
I
r
mV 26
h
ie1
=
1
r
e1
Since
1
=
2
; I
E1
= I
E2
;
r
e1
= r
e2
Gain is given by A
V1
= V
01
/V
i
R
L
/ r
e1
With R
L
= r
e2
= h
ib2
of transistor-2 and A
V1
= r
e2
/ r
e1
= 1
A
V2
= R
Leff
/ r
e2
= ?
Total gain is given by,
A
V1
A
V2
= 100 (given)
R
Leff
= A
V2
r
e2
.
Calculate R
C
from R
Leff
= R
C
|| R
L
.
On applying KVL to output loop, we get
V
CC
= I
C
R
C
+ V
CE2
+ V
CE1
+ I
E
R
E
where, V
E
= I
E
R
E
R
E
= ?
then
2
2
2
1
1
1
1
;
mA 1 Let
fe
C
B
fe
C
B
h
I
I
h
I
I
I

?
?
?
1
1
1
2 2 3
1 1 2

I
V V
R
I I I
I I I
B CC
B
B
E CE BE B
V V V V + +
1 2 1
where
?
2
2 1
2

I
V V
R
B B
E BE B
V V V +
2 2
where
?
3
2
3

I
V
R
B
Input coupling capacitor is given by,
i
Ci
ie
C
fC
X
R R h
X
2
1
10
|| ||
3 2 2
2
,
_
C
i
= ?
Output coupling capacitor is given by,
?
2
1
10
||
0
0
0
0
,
_
C
fC
X
R R
X
C
L C
C
By-pass capacitor is given by, X

CE
= R
E
/10
?
2
1
E
E
CE
C
fC
X
Procedure
2. Set V
i
Tabular Column
V
i
= 50 mV
Frequency V
0
(volts) Gain = V
0
/V
i
Gain (dB) = 20 log (V
0
/V
i
)
Result
Input impedance
Output impedance
Gain (Mid-band)
Bandwidth
Experiment 3.6
Field Effect Transistor
Aim To determine the parameters of the single-stage JFET amplifier (common-drain amplifier)
1. Bandwidth
2. Midband gain
Equipment Required
Power supply
CRO
Function generator
(030) V
(020) MHz
(01) MHz
1
1
1
Circuit Diagram
Design
Given I
DSS
= 10 mA; V
P
= 4V; f
L
= 50 Hz; V
DD
= 12 V
From the DC bias condition,
?
2

DSS
D
I
I
For which I
D
= I
DSS
[1 (V
GS
/V
P
)]
2
V
GS
= ?
V
D
=
2
DSS
V
(Assume)
Therefore, V
DD
= I
D
R
D
+ V
D
R
D
= (V
DD
V
D
) / I
D
= ?
?
| |
2
0

P
DD
m
V
I
g
The value of g
m
at the bias voltage is given by
g
m
= g
m0
[1(V
GS
/V
P
)]
Find g
m
r
m
= 1/ g
m
r
m
= ?
With R
S
completely by-passed, the largest amplifier gain is given by
A
V
= R
D
/ r
m
A
V
= ?
R
S
= V
GS
/ I
D
= ?
R
G1
= open and R
GS
= 100 M
Input coupling capacitor is given by
?
2
1
10
,
_
i
i
Ci
GS
Ci
C
fC
X
R
X
Output coupling capacitor is given by

?
2
1
10
||
0
0
0
0
,
_
C
fC
X
R R
X
C
L D
C
By-pass capacitor is given by

?
2
1
10
,
_
S
S
CS
S
CS
C
fC
X
R
X
Procedure
2. Set V
i
7. Note down the phase angle, Bandwidth, input and output impedance.
Tabular Column
V
i
= 50 mV
Frequency V
0
(volts) Gain = V
0
/V
i
0
/V
i
)
Result
Input impedance
Output impedance
Gain (Mid-band)
Bandwidth
Experiment 3.7
Differential Amplifier
Aim To construct a differential amplifier for dual input balanced output and unbalanced output in the common
mode and differential mode configuration and to study the output waveform and find common-mode rejection
ratio (CMRR).
Equipment Required
Power supply
CRO
Function generator
(030) V
(020) MHz
(01) MHz
1
1
1
Circuit Diagram
Dual Input Unbalanced Output
Design Dual input unbalanced output differential amplifier
Given mA; 2 . 1 ); multimeter from ( ; 1 . 0 ; 150
E fe C d
I h A A differential gain is given by,
e
C
d
r
R
A
2
where
E
e
I
r
mV 26
R
C
= ?
Common-mode Rejection Ratio is given by,
C
d
A
A
CMRR
Common-mode gain is given by,
E e
C
C
R r
R
A
2 +
R
E
= ?
Dual Input Balanced Output
Design Dual input balanced output differential amplifier
Given mA 2 . 1 ); multimeter from ( ; 1 . 0 ; 150
E fe C d
I h A A
Differential gain is given by
e
C
d
r
R
A
2
where
E
e
I
r
mV 26
R
C
= ?
Common-mode Rejection Ratio is given by,
C
d
A
A
CMRR
Common-mode gain is given by
E e
C
C
R r
R
A
2
2
+
R
E
= ?
Procedure
1. Connect the circuit as per the circuit diagram (Common-mode configuration).
2. Set V
i
Tabular Column
V
i
= 50 mV
Frequency V
0
(volts) Gain = V
0
/V
i
0
/V
i
)
Result
Input impedance
Output impedance
Gain (Mid-band)
Bandwidth
Experiment 3.8
Class-A Power Amplifier: Resistive Load
Aim To calculate efficiency of a class-A power amplifier operated with resistive load.
Equipment Required
DC power supply
Function generator
CRO
Ammeter
(030) MHz
(01) MHz
(020) MHz
(030) mA
1
1
1
1
Components Required
BJT (Power series)
Resistor
Capacitor
SL100
47 k(pot)
220
33 k
47F
1
1
2
1
2
Circuit Diagram
Design
mW 500 ; 220 Given
o L
P R
L
CC
o
R
V
P
8
by, given is power Output
2
?
2
?

CC
CE
CC
V
V
V
loop output to KVL Apply
?
+
C
CE CC
C
CE C C CE
R
V V
I
V R I V
by, given is power Collector
?
CC CC C
I V P
Maximum output power is given by
L
o
o
R
V
P
2
max ,

Note: Maximum output voltage can be obtained from the experiment result.
? , Efficiency
max ,

c
o
P
P
circuit. the of impedance input

where
2
i
i
i
in
Z
Z
V
P
Procedure
2. Set the function generator (say 0.2 V, at 1 KHz).
3. Vary the frequency from 10 Hz to 1 MHz in a regular steps and note down the corresponding output
voltage.
4. Calculate the gain (dB) = 20log
10
(V
o
/V
i
)
5. Plot the graph : Gain (dB) vs

Frequency (Hz)
: V
0
(volts) vs Frequency (Hz)
Tabular Column
Frequency (Hz) Output voltage (Volts) Gain = V
o
/V
i
o
/V
i
)
Model Graph
Experiment 3.9
Class-A Power Amplifier: Inductive Load
Aim To design and construct a class-A power amplifier and to determine its efficiency
Equipment Required
Power supply
CRO
Function generator
(030) V
(020) MHz
(01) MHz
1
1
1
Circuit Diagram
Design
Given P
0max
= 0.4 W; R
L
= 470 ; f
L
= 50 Hz
For a DC, since there is no drop across L, V
CE
= V
CC
(neglecting ammeter drop)
Current across emitter and collector = I
CQ
+ I
C
sin t
Therefore, V
C
= (I
C
sin t)R
L
+ V
CC
At maximum I
CQ,
V
C
= 0V; t = /2;
I
CQ
= V
CC
/R
L
Output power is given by
P
0max
= I
2
CQ
R
L
/2 = V
2
CC
/2R
L
V
CC
= ?
Since collector current is given by
I
CQ
= V
CC
/R
L
I
CQ
= ?
) (
max
, efficiency
DC in
o
P
P

L
CC
DC in
L
CC
o
R
V
P
R
V
P
2
) (
2
max
;
2
where
in
o
P
P
gain Power
ie
in
i
in
in
L
o
h
V
Z
V
P
R
V
P
2 2 2
0
; where
C
e e fe ie
I
r r h h
mV 26
;
Input coupling capacitor is given by
X
Ci
= h
ie
/10
i
Ci
fC
X
2
1
C
i
= ?
Output coupling capacitor is given by, X
C0
= R
L
/10
0
0
2
1
fC
X
C
C
0
= ?
Choose a transistor satisfying the following specifications:
P
D max
= 2 P
0 max
V
CE
= 2 V
CC
I
C max
= 2 I
CQ
Procedure
2. Set V
i
3. Keeping the input voltage constant, vary the frequency from 0Hz to 1MHz in regular steps and note down
4. Plot the graph: Gain (dB) vs Frequency (Hz)
7. Note down the phase angle, Bandwidth, input and output impedance.
8. Calculate the efficiency, = P
0
/P
in
9. Plot the graph; Output power vs load resistance.
Tabular Column
V
i
= 50 mV
Frequency V
0
(volts) Gain = V
0
/V
i
0
/V
i
)
Result
Input impedance
Output impedance
Gain (Mid-band)
Bandwidth
Tabular Column
V
i
= 50mV
Output power (watt)
(P
0
)
Load resistance
(R
L
)
Load Characteristic
Experiment 3.10
Class-A Power AmplifierInductive Load
Aim To calculate efficiency of class -A power amplifier with inductive load and hence determine maximum
efficiency.
Equipment Required
CRO
Signal generator
Power supply
DC Ammeter
(020) M Hz
(01) MHz
(030) V
(030) mA
1
1
1
1
Components Required
BJT (Power series)
Inductor
Resistor
Capacitor
SL100
1H
47 k (pot)
220
47F
1
1
2
1
2
Circuit Diagram
Design
Given P
L, max
= 500mW; R
L
= 200
Output power is given by;
L
cc
o
R
V
P
2
2
?
?

L
cc
c
cc
R
V
I
V
Collector power is given by,
c cc c
I V P
Maximum output power is given by,
o
P
Maximum output voltage can be obtained from the tabulation
input power is given by,
i
in
in
Z
V
P
2
where Z
i
= input impedance of the circuit
efficiency is given by ?
c
o
P
P
power given =
?
in
o
P
P
Procedure
2. Set the signal (say 0.2V at 1 kHz) using function generator.
3. Vary the frequency from 0 to 1 MHz at regular steps and note down the respective output voltage.
4. Calculate gain (dB) = 20 log
10
(V
o
/V
i
)
5. Plot the graphs: Gain(dB) vs Frequency (Hz)
Tabular Column
o
/V
i
Gain (dB)
Model Graph
Experiment 3.11
Class-A Power Amplifier with Transformer Coupled Load
Aim To calculate efficiency of class - A power amplifier with transformer coupled load and also obtain the
power gain.
Equipment Required
CRO
Function generator
Power supply
DC Ammeter
(020) MHz
(01) MHz
(030) V
(030) mA
1
1
1
1
Components Required
Transformer
BJT (Power series)
Resistor
Capacitor
N:1
SL100
47 k(pot)
220
47F
1
1
1
2
1
Circuit Diagram
Design
Given V
CC
= 15V; R
C
= 220
1 2
1 N
x
N
N

Therefore
L L
R x R
2

Collector power is given by,
?
2
L
CC
c
R
V
P
Maximum output power is given by
?
2
2
max ,

L
o
o
R
V
P
Input power is given by,
i
in
in
Z
V
P
2
where Z
i
= input impedance of the circuit
power efficiency,
?
c
o
P
P
Power gain is given by, ?

in
o
P
P
Procedure
2. Set the signal (say 0.2V at 1kHz) using function generator.
3. Vary the frequency of the function generator from 0 to 1MHz and notedown the corresponding output
voltage.
Tabular Column
V
i
= 0.2V
o
/V
i
Gain(dB)
Model Graph
Experiment 3.12
Class-B Power Amplifier
Aim To design and construct a class-B (complementary symmetry) power amplifier and to determine its
efficiency
Equipment Required
Power supply
CRO
Function generator
(030) V
(020) MHz
(01) MHz
1
1
1
Circuit Diagram
Design
Given V
CC
= 15 V; R
L
= 470 ; f
L
= 50 Hz
Output voltage is same as the input voltage since two transistors is in CC-mode. Therefore, load voltage
is given by
V
L
(ac) = 15 V
Output power, P
0
(ac) = V
2
L
(ac) /2R
L
= ?
I
L
(ac) = V
L
(ac)/R
L
= ?
The DC current is given by,
?
I
I
L(ac)
dc

2
Therefore, the power supplied to the circuit is
P
i
(dc) = V
CC
I
dc
= ?
Circuit efficiency, = P
0
(ac)/ P
i
(dc) = ?
Power dissipation by each transistor is given by
P
Q
= [P
0
(ac) P
i
(dc)]/2 = ?
At DC biasing condition:
V
CE1
= V
CE2
= V
CC
/2 = ?
V
B1
= V
BE1
+ V
CE2
= ?
R
1
= [V
CC
V
B1
]/I
1
If I
1
is assumed (say 5 mA), find R
1
=?
R
2
(V
CC
/2)/(R
1
+ R
2
) =V
CC
/2 + V
BE2
R
1
= ?
R
B1
= (S1) R
E1
= ?
R
B1
= R
1
|| R
2
find R
1
and R
2
Input impedance is given by
Z
i1
= R
B1
|| [h
ie1
+ (1 + h
fe1
) R
f1
]
Output impedance is given by
Z
o1
= R
C1
The feedback factor is given by
2 1
1
f f
f
R R
R
+
=
where, R
f2
>> R
f1
assume R
f2
= 10 k; find R
f1
overall voltage gain is given by
2 1 V V V
A A A =
Parameter Analysis with Feedback
The desensitive factor, D = 1 + A
V
Output impedance with feedback is given by
D
Z
Z
o
of
2
=
Input impedance with feedback is given by
D Z Z
i if
=
1
The gain with feedback is given by
D
A
A
V
Vf
=
The output capacitor is given by
10
2
0
o
C
Z
X =
where
0
0
2
1
fC
X
C
=
C
0
= ?
The input capacitor is given by,
10
1 i
Ci
Z
X =
where
Ci
Ci
f
X
2
1
=
C
i
= ?
OP-AMP 4.1
C h a p t e r 4
OPERATIONAL AMPLIFIER (OP-AMP)
Experiment 4.1
Characteristics of OP-AMP
Aim To determine the following characteristics of an op-amp:
1. Input off-set voltage
2. Slew rate
3. Common mode rejection ratio
4. Bandwidth
5. Input bias current
Equipment Required
Signal generator
CRO
Regulated power supply
Dual power supply
(01) MHz
(020) MHz
(030) V
(12012) V
1
1
1
1
Procedure
Input Off-Set Voltage
2. Switch on the dual power supply and note down the output voltage from the CRO.
3. Calculate the input offset voltage from the given formula,
+
=
1 2
1
0
R R
R
V V
Slew Rate
2. Give a sinusoidal input of 1 V
pp
.
3. Switch on the dual power supply.
4. Vary the input frequency and observe the output.
5. Note down the value of the input frequency at which the output gets distorted.
6. Determine the slew rate from the given formula,
Slew Rate s
V f
m
/ V
10
2
6
=
7. Repeat the above procedure by giving square wave input.
8. Increase the frequency till the output becomes a triangular wave.
9. Find the slew rate from the given formula,
t
V
=
0
SR
Common Mode Rejection Ratio
pp
.
OP-AMP 4.3
4. Note down the output voltage from the CRO.
5. Determine the CMRR by the following procedure.
Common Mode Gain =
1
0
V
V
A
C
=
Differential Mode Gain =
1
2
R
R
A
d
=
CMRR = 20 log
C
d
A
A
Bandwidth
pp
.
4. Increase the frequency until the output voltage reduces to 0.7 times the input voltage.
5. Note down the frequency at this point and this gives the bandwidth of the op-amp at unity gain.
Input Bias Current
Inverting Mode Non-inverting Mode
3. Note down the output voltage from the CRO.
4. Calculate the input bias current in the inverting mode from the following formula,
R
V
I
0
0
=
5. Repeat the above procedure in the non-inverting mode and calculate the current from the following
formula,
R
V
I
0
0
=
+
Result
The characteristics of the op-amp were studied and the results are tabulated below,
Parameters Readings
Input off-set voltage
Slew rate
CMRR
Bandwidth
Input bias current Inverting
Noninverting
Exercise
1. Discuss any two methods of measuring the input off-set voltage.
2. How is frequency compensation done in an op-amp ?
3. Define CMRR, PSRR and the maximum output voltage swing of an op-amp.
Experiment 4.2
Linear Applications of OP-AMP
Aim To study the following applications of op-amp using ICLM 741.
1. Voltage Follower.
2. Inverting Amplifier.
3. Non-inverting Amplifier.
4. Variable Voltage Gain Amplifier.
5. Adder.
6. Subtractor.
7. Differential Amplifier.
8. Integrator.
9. Differentiator.
OP-AMP 4.5
Equipment Required
Dual power supply
Signal generator
CRO
(15015) V
(1 Hz 1 MHz)
(030) V
(0100) KHz
1
1
2
1
Voltage Follower
Inverting Amplifier
Non-inverting Amplifier
Adder
Subtractor
Differentiator
Integrator
Differential Amplifier
OP-AMP 4.7
Procedure
1. Connect the circuit as shown in the circuit diagram.
2. Give the input signal as specified.
4. Note down the outputs from the CRO.
5. Draw the necessary waveforms on the graph sheet.
6. Repeat the procedure for all the circuits.
Result
The applications of the LM1 741 were studied.
Exercise
1. Explain the difference between differentiators and integrators and give one application for each.
2. Explain why integrators are preferred over differentiators in an analog computer.
3. Draw a practical differentiator circuit that overcomes the drawbacks of an ordinary differentiator circuit.
4. Design an adder circuit to get the following output
[ ]
3 2 1 0
10 1 0 V V V . V + + =
Experiment 4.3
Non-linear Applications: Comparators
Aim To design a comparator circuit and to study the non-linear applications of op-amp.
Equipment Required
Dual power supply
Signal generator
CRO
(15015) V
(01)M Hz
(030) V
(020) MHz
1
1
1
1
Circuit Diagram
Comparator: Zero Crossing Detector
0 when ,
0 when ,
sat 0
sat 0
> =
< + =
i
i
V V V
V V V
Positive Comparator
ref i
ref i
V V V V
V V V V
> =
< + =
when ,
when ,
sat 0
sat 0
Negative Comparator
ref i
ref i
V V V V
V V V V
> =
< + =
when ,
when ,
sat 0
sat 0
Comparator with zener diode at the output
Zero crossing comparator (non-inverting mode)
Negative non-inverting comparator
OP-AMP 4.9
Positive non-inverting comparator
Procedure
Comparator
PP
to the inverting terminal.
3. For a zero crossing detector, connect the non-inverting terminal to ground.
5. Observe the output waveform on a CRO.
6. For a positive and negative comparator give a reference voltage of 1VDC respectively to the non-
inverting input.
7. Observe the output waveform on a CRO.
8. Draw the output and input waveforms for all the three circuits on a graph sheet.
Result
Using op-amps the comparator were studied and waveforms were verified.
Experiment 4.4
Pulse Detector and Window Comparator
Aim To study the operation of a
1. Pulse Detector
2. Window comparator
Equipment Required
Signal generator
CRO
Dual power supply
(01) MHz
(020) MHz
(12-0-12) V
1
1
1
Circuit Diagram
Pulse Detector
Window Comparator
Procedure
2. Setup the input signal from the signal generator.
3. Observe the input of the squarewave, the differentiated output and then pulses of the diode in the case of
pulse detector
4. Set the voltages accordingly and observe the LED glow (for ckt (2)).
5. Plot the graph for the pulse detector (for ckt (1))
1. Comparator output
2. Differentiator output
3. Pulse output (also with diode reversed)
Tabular Column (Window Comparator)
Input Voltage (V
i
) LED 1 LED 2 LED 3
V
i
< 5V
5V < V
I
< 10 V
V
i
> 10 V
ON
OFF
OFF
OFF
ON
OFF
OFF
OFF
ON
OP-AMP 4.11
Result
The operation of pulse detector and window comparator were studied.
Experiment 4.5
Instrumentation Amplifier
Aim To study the performance of an instrumentation amplifier.
Equipment Required
Signal generator
CRO
Dual power supply
(01) MHz
(020) MHz
(12012) V
1
1
1
Circuit Diagram

= =
R
R
R
R
A
2
1 Gain,
1
2
Procedure
2. Set the inputs E
1
and E
2
at different values but at the same frequency.
3. Adjust R
1
to a particular value.
5. Calculate the theoretical gain from the given formula and verify with the practical values.
6. Repeat the above procedure for different values of R
1
.
Experiment 4.6
Non-linear Applications: Waveform Generators
Aim To design a circuit and study the non-linear applications of op-amp.
1. Sine wave generator.
2. Square wave generator.
3. Triangular wave generator.
4. Sawtooth wave generator.
Equipment Required
Dual power supply
Signal generator
CRO
(15015) V
(01) MHz
(030) V
(020) MHz
1
1
1
1
Circuit Diagram
Sinewave Generator
To produce sustained oscillation, gain should be equal to 3 i.e.,
i f
i
f
R R .
R
R
2 Then 3 1 = = +
Square Wave Generator
OP-AMP 4.13
Asymmetric square wave generator
Triangular Wave Generator
Sawtooth wave generator
Design
Sine Wave Generator
?
10 01 . 0 10 2 / 1
F 01 . 0 , Choose
2
1
kHz 1 , Let
2 / 1 , know We
6 3
=
=
=
=
=
=
R
C
fC
R
f
RC f
=
=
=
=
=
=
=
=
k 6 . 11 Then,
k 10 If,
16 . 1 , Choose
k 10
10 05 . 0 10 2 / 1
F 05 . 0 , Choose
kHz 1 , Let
2
1
, know We
1
2
2 1
6 3
0
0
R
R
R R
R
R
C
f
RC
f
Chose 10 k in series with a 10 k
potentiometer.
Design for the square wave generator is given above. Design for the integrator circuit as follows,
If,
Let,
R
R
OP-AMP 4.15
?
10 01 . 0 10 100 2 / 1 Then,
F 01 . 0 Choose,
, 100 Given,
2
1
M 1 Then,
6 3
0
2
3
2 3
0
4
=
=
=
=
=
=
f
C
k R
C R
f
R
Procedure
Sine Wave Generator
2. Switch on the dual power supply and observe the output waveform on a CRO.
3. Adjust the potentiometer to get an undistorted waveform.
4. Calculate the time period and determine the frequency.
5. Verify it with the theoretical frequency calculated by using the formula,
f =1 / 2 RC
Repeat the above procedure for different values of R and C.
2. Switch on the dual power supply and observe the output on a CRO.
3. Adjust the potentiometer to obtain an undistorted output.
4. Calculate the output frequency and verify it with the theoretical frequency obtained from the formula,
RC
f
2
1
=
1. Connect the output of the square wave generator to an integrator circuit.
2. Observe the output waveform on a CRO and determine the frequency.
Sawtooth Wave Generator
1. Connect the circuit as shown in the
2. Adjust the potentiometer and observe the circuit diagram output for applied negative voltage.
3. Adjust the potentiometer in the opposite direction and observe the output for applied positive voltage.
Result
The non-linear applications of the op-amp were studied.
Exercise
1. Design a circuit to convert a square wave into a series of positive pulses.
2. What is a window detector?
3. What is the difference between a sawtooth wave and a triangular wave?
4. How do you recognize that positive feedback is being used in an op-amp oscillator circuit ?
Experiment 4.7
Schmitt Trigger
Aim To design and test the schmitt trigger for the given UTP and LTP.
Equipment Required
Signal generator
CRO
Dual Power supply
(01) MHz
(020) MHz
(12012) V
1
1
1
Circuit Diagram
Schmitt trigger with zero-reference
Schmitt trigger with positive reference
OP-AMP 4.17
Schmitt trigger with negative reference
Design
Given, V
R
= 0 and V
sat
=
12 V.
Assume, V
b1
= V
b2
+
= =
+
+
= =
2 1
SAT
1 2
2 1
SAT
1 1
R R
-V
R LTP V
R R
V
R UTP V
b
b
Procedure
2. Set input signal (say 1V, 1kHz) using signal generator.
3. Observe the input and output waveforms on the CRO
4. Plot the graphs: V
i
vs Time
V
0
vs Time
Model Graph
Result
Parameter Theoretical Practical
Experiment 4.8
Precision Rectifier
Aim To design a precision rectifier and study its operation using IC 741.
Equipment Required
Dual power supply
Signal generator
CRO
(15015) V
1 MHz
15 MHz
1
1
1
Circuit Diagram: Half-wave rectifier
+
+
2 1
1
2 1
1
R R
V
R LTP
R R
V
R UTP
Sat
Sat
OP-AMP 4.19
Full-wave rectifier
Procedure
2. Give a sinusoidal input of V
pp
, 1 kHz from a signal generator.
3. Switch on the dual power supply and note down the output from the CRO.
4. Repeat the above procedure by reversing the diodes.
Result
The operation of the precision rectifier is studied using IC 741.
Exercise
1. What is virtual ground?
2. What is the significance of a precision rectifier ?
3. Explain the operation of a precision full wave rectifier.
Experiment 4.9
Study of V-I & I-V Converter Using OP-AMP
Aim To design a voltage to current (V/I) and current to voltage converter (I/V) and study their operation using
IC 741.
Equipment Required
Dual power supply
Signal generator
CRO
Ammeter
(15015) V
(030) V
(01) MHz
(015) MHz
(030) A
1
1
1
1
1
Circuit Diagram
Voltage to Current Converter
Current to Voltage Converter
Procedure
Voltage to Current Converter
2. Set the ac input to any desired value.
3. Switch on the dual power supply and note down the reading from an ammeter.
4. Repeat the above procedure for varying input voltages.
5. Tabulate the readings in the given tabular column.
Current to Voltage Converter
2. Connect the dc bulb to a regulated power supply and give a dc voltage less than 6V to it.
3. Focus the dc bulb on the photo-diode.
4. Switch on the dual power supply and note down the voltage at the output.
5. Vary the regulated power supply voltage so that it would vary the intensity of the bulb.
6. Measure the diode current and the corresponding output voltage.
7. Tabulate the readings in the given tabular column.
Digital Electronics 5.1
C h a p t e r 5
DIGITAL ELECTRONICS
Digital signal consists of only 2 values, 0 and 1. These two values are logical, i.e. 1 represents the existence
of a particular condition and 0 represents the absence of that condition.
Boolean Algebra
It is a technique of mathematical manipulation, it uses two binary numbers, 0 and 1. There are several laws
in boolean algebra and are used in digital circuits.
Boolean Postulates
X = 0
X = 1
0 0 = 0
1 1 = 1
1 + 1 = 1
1 0 = 0 1 = 0
1 + 0 = 0 + 1 = 1
1 = 0 and 0 = 1
Theorems of Boolean Algebra
Boolean algebra deals with logical relations between the Boolean variables. A fundamental rule relating Boolean
variable is called a Boolean theorem. The following are some of the Boolean theorems,
1. Commutative law:
X + Y = Y + X
Its dual, X Y = Y X
2. Associative law:
(X + Y) + Z = X + (Y + Z)
Its dual, (X Y) Z = X (Y Z)
3. Distributive law:
X (Y+Z) = X Y + X Z
Its dual, X + (Y Z) = (X + Y) (X + Z)
4. Negative law:
Complement of

X X
X X
=
=
5. Identity law: 8. 1 + X = 1
X + X = X Its dual, 0 X = 0
Its dual, X X = X
6. Redundance law: 9.
1 X X = +
X + X Y = X Its dual,
X X
Its dual, X (X + Y) = X
7. 0 + X = X 10. Y X Y X X + = +
Its dual, 1 X = X Its dual, X
X
+ Y = X Y
De Morgans Theorem
Statement: Complementary of the product is equal to sum of the complements and complement of the sum is
equal to product of the complements.
Y X
Y X
+
Both are dual of each other.

Realisation of Basic Gates Using Universal Gates
NOT equivalent of NAND GATE
AND equivalent of NAND GATE
OR equivalent of NAND GATE
NOR equivalent of NAND GATE
EX-OR equivalent of NAND GATE
EX-NOR equivalent of NAND GATE
NOT equivalent of NOR GATE
OR equivalent of NOR GATE
AND equivalent of NOR GATE
NOR equivalent of NOR GATE
EX-OR equivalent of NOR GATE
EX-NOR equivalent of NOR GATE
Experiment 5.1
Logic Gates
Aim To realise the logic gates using diodes and transistor.
Circuit Diagram
Procedure
2. Low level refers to 0 V; High level refers to +5 V.
3. Switch on the input according to the truth table condition.
4. Verify the output and compare it with truth table result.
5. Continue the above procedure for all other gates.
Truth Tables
OR GATE
Input
A
Input
B
Output
Y
LOW
HIGH
LOW
HIGH
LOW
LOW
HIGH
HIGH
LOW
HIGH
HIGH
HIGH
AND GATE
Input
A
Input
B
Output
Y
LOW
HIGH
LOW
HIGH
LOW
LOW
HIGH
HIGH
LOW
LOW
LOW
HIGH
NOT GATE
Input
A
Output
Y
LOW
HIGH
HIGH
LOW
NOR GATE
Input
A
Input
B
Output
Y
LOW
HIGH
LOW
HIGH
LOW
LOW
HIGH
HIGH
HIGH
LOW
LOW
LOW
NAND GATE
Input
A
Input
B
Output
Y
LOW
HIGH
LOW
HIGH
LOW
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
EX-OR GATE
Input
A
Input
B
Output
Y
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
HIGH
LOW
EX-NOR GATE
Input
A
Input
B
Output
Y
LOW
LOW
HIGH
HIGH
LOW
HIGH
LOW
HIGH
HIGH
LOW
LOW
HIGH
Experiment 5.2
Simplification of a Boolean Expression and
Its Realisation Using Logic Gates
Aim To simplify the given boolean expression and realise the resultant expression using
a) Basic gates
b) Universal gates
Equipment Required
Equipment Quantity
Digital IC trainer kit
Patch cords
1
20
Components Required
IC Name Quantity
IC 74LS00
IC 74LS02
IC 74LS04
IC 74LS08
IC 74LS32
1
1
1
1
1
Circuit Diagram
Sum of Products
ABC C B A C B A Y + + =
Logic Implementation Using NAND Gates
Logic Implementation Using NOR Gates
Product of sums
) ( ) ( ) ( C B C A B A Y + + + =
Logic Implementation Using Basic Gates
Logic Implementation Using NOR Gates
Logic Implementation Using NAND Gates
Procedure
1. Connect the circuit and pin configurations of the IC, as per the circuit diagram.
2. Switch on the supply and note down the outputs for all the possible combination of inputs.
3. Repeat the same using Universal gates.
E.g.
XZ XY
] Y Y [ XZ XY
Z Y X XYZ XY
+
+ +
+ +
This equation can be realised using NAND gates. On converting equation into product of sum form, we
get ). Z X ( ) Y X ( + + This equation can be realised using NOR gates.
Observation and Tabulations
1
1
0
0
0
1
0
1
0
0
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
X Z X XY Z X XY Z Z Y X +
) Z X ( ) Y X ( + +
0
0
1
1
1
0
1
0
1
1
1
1
1
0
1
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
Z) (X ) Y X ( Z X Y X Y X Z Y X + + + +
Result
The given boolean expressions were simplified and realised using logic gates.
Exercise
1. Write the logic, boolean expression and truth table of an EX-OR gate.
2. Realise the EX-OR gate using NOR gates.
3. Justify the statement UNIVERSAL gates.
Experiment 5.3
Adders
Aim To construct and verify the operation of a half-adder and a full-adder using logic gates.
Equipment Required
Equipment Quantity
Patch cords
1
20
Components Required
Name of the Component Quantity
IC 74LS08
IC 74LS32
IC 74LS86
1
1
1
Circuit Diagram
Using Basic Gates
Using NAND Gates
Using NOR Gates
Using EX-OR Gate
Full-adder
Block Diagram of Full-adder Using Two Half-adders
Procedure
2. Give logical inputs as per the respective truth table.
3. Observe the logical output and verify with your truth table.
Truth Table
Half-adder
A B Sum (S) Carry (CY)
0
0
1
1
0
1
0
1
0
1
1
0
0
0
0
1
Full-adder
A B C Sum (S) Carry (CY)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
1
Result
The operation of a half-adder and full-adder were studied.
Experiment 5.4
Subtractor
Aim To design of half-subtractor and full-subtractor.
Half-subtractor
Truth Table
X Y
Borrow
(B)
Output
(D)
0
0
1
1
0
1
0
1
0
1
0
0
0
0
1
0
Y X B
Y X Y X Y X D
=
= + =
Using Basic Gates
Using NAND Gate
Using NOR Gate
Full-subtractor
Truth Table
A B C
Borrow
(B)
Output
(D)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
1
0
0
0
1
0
1
1
0
1
0
0
1
YZ Z X Y X B
XYZ X Z Y Y Z X Z Y X D
+ + =
+ + + =
Note: Try your circuit and implement it.
Procedure
Experiment 5.5
Parity Generation and Checking
Aim To design even parity generator and checker.
Equipment Required
Power supply (05) V 1
Even Parity Generator
Truth Table
X Y Z Parity Bit (P)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
0
1
Z Y X XYZ X Z Y Y Z X Z Y X P = + + + =
Even Parity Checker
Truth Table
X Y Z Parity (P) Parity Error Checker (C)
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
1
0
1
0
0
0
1
1
0
0
1
0
1
1
0
0
C = X Y Z P
Procedure
1. Set up the circuit as per the circuit diagram.
2. Give logical inputs as per their respective truth table.
3. Observe the logical output and verify that with your truth table.
Experiment 5.6
Multiplexer
Aim To design and implement a 4:1 multiplexer using logic gates.
Equipment Required
Circuit Diagram
Truth Table
Input Output
X Y
0
0
1
1
0
1
0
1
D
1
D
2
D
3
D
4
Procedure
Exercise
Obtain EX-OR operation on a multiplexer.
Experiment 5.7
Demultiplexer
Aim To design and implement a 4:1 demultiplexer using logic gates.
Equipment Required
Circuit Diagram
Truth Table
Input Output
A B Y
0
Y
1
Y
2
Y
3
0
0
1
1
0
1
0
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
Procedure
Experiment 5.8
Encoders
Aim To design and implement encoders using logic gates.
Equipment Required
Circuit Diagram
Truth Table
Inputs Outputs
D
0
D
1
D
3
D
4
X Y
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
1
0
1
Procedure
Exercise
1. Compare an encoder with a multiplexer.
2. Explain the operation of a priority encoder.
3. Design a decimal to BCD encoder using universal gates.
4. Conduct the decimal to BCD encoder using IC 74147.
Experiment 5.9
Decoders
Aim To design and implement decoders using logic gates.
Equipment Required
Circuit Diagram
Truth Table
Input Output
X Y D
0
D
1
D
2
D
3
0
0
1
1
0
1
0
1
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
Decimal BCD Code 7-segment OP-code
D C B A a b c d e f g
0
1
2
3
4
5
6
7
8
9
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
0
1
1
0
1
0
1
0
1
0
0
0
1
0
1
0
1
0
0
0
1
1
1
0
1
1
0
0
1
1
1
1
1
0
1
1
Procedure
2. Give logical inputs as per their respective truth tables.
Exercise
1. Conduct the BCD to Decimal encoder using IC 7445.
2. Design a BCD to Excess-3 decoder using logic gates.
3. Compare a decoder and a demultiplexer.
4. Discuss the operation of a BCD/7 segment decoder.
5. Discuss about a strobe signal.
Note: Decoders permits one of the n outputs to be selected, depending on the address on the select lines or
control lines. Any of the demultiplexers can be used as a binary decoder by providing a constant, continuous
1 (or removing permanently the input signal channel) on the signal input line.
BCD To 7 Segment Display Decoder
This circuit facilitates the operation of 7 segment devices such as incandescent lamps, LED and LCD. The
output of the decoder is designed in such a way that segments of the corresponding decimal digit is enabled.
For example, consider the segments of the display i.e. a-g. The segments other than g should glow if the
digit is 0. The inputs A, B, C, D will be 0 and the decoder outputs to the segments a-f should be high and to
the segment g should be low for the digit 0 to glow. Similar analysis can be done for the other digits also as
given below.
DIGITAL LOGIC FAMILIES
Digital Integrated Circuits
In electronic digital circuits, 0 and 1 are always represented as low and high values. Many functions are being
preferred with these two inputs and are realised by using logic gates. A logic gate is an electronic circuit, which
can take in one or more inputs and give a single output. A logic circuit can be operated in two logics namely:
1. Positive logic
2. Negative logic
Positive logic In positive logic convention, logic 1 is assigned the more positive value of the two voltage
levels and logic 0 is assigned the less positive value.
Negative logic In this, logic 0 is assigned the more positive value and logic 1 is assigned the less positive
value. Digital ICs are circuits, which perform logic functions using these inputs. It is basically classified as
bipolar ICs and MOS ICs. The digital ICs are classified into different logic families depending on the components
and logic used. RTL, DTL, TTL, ECL, HTL, etc. are a few logic families commonly used.
CHARACTERISTICS OF DIGITAL ICs
1. Logic flexibility
2. Operating speed
3. Availability of complex functions
4. Power dissipation
5. Supply voltage
6. Noise immunity
7. Noise generation
8. Fan-in /Fan-out
9. Cost
10. Operating temperature range
Logic Flexibility
This is a measure of the utility of the IC in meeting the needs of the system.
Wired logic capability Connecting the gate output together or using them directly to perform additional
logic functions without any external hardware.
Complementary outputs If the IC has complementary output facility, then the requirement of extra inverters
can be avoided.
Driving non-standard loads Non-standard loads like long lines electromagnetic relays have to be driven
so that the need for the coupling elements can be avoided.
I/O facilities The number of inputs of the gate, the input impedance and the output impedance at both logic
0 and 1 determines the I/O capacity of the IC.
Ability to drive other logic forms This character avoids the necessity of external interfacing circuits and
hence reduces the space and system cost.
Types of gates The logic family should have many types so that when used in a system, interconnections
and power supply requirements can be simplified.
Operating Speed
The operating speed of an IC should be very high, as it reduces the operating and execution time. When high
speed ICs are available, then system can be designed to operate in the serial mode rather than in a parallel
mode, as this would reduce the system cost.
Speed of an IC is limited by the following factors
Propagation delay This is due to the finite operating speed of the active devices and RC time constants of
the associated circuitry. Since the delay from logic 1 to logic 0 is different from the delay of logic 0 to
logic 1, the average of both is taken as the propagation delay.
Pair delay This is a measure of the propagation delay through two inverters.
Complex Functions
Grouping of basic gates in a single packaged chip is termed as complexity of the IC. The chip size, number of
pins per gate and the overall number of input/output pins per package are important factors of consideration.
With increase in complexity, the number of input/output terminals for the IC increases but at a decreased rate,
and the reliability and assembling cost of the IC is increased.
Power Dissipation
This factor should be low as it reduces cooling, power supply and distribution cost. With decrease in power
dissipation of a gate f of the active device decreases and RC time constants increases. This increases the
propagation delay. Hence a decrease in power dissipation is achieved at the cost of increase in propagation
delay.
Supply Voltage
A standard supply voltage is used for every logic family. A +5 V supply is usually used.
Noise Immunity
An IC should have a high noise immunity. This is a characteristic term of noise voltage and pulse width that can
be tolerated by the circuit or the total noise energy required to cause a false output at the logic gate. This noise
immunity depends on the following factors.
Parameters of a gate are:
1. Supply voltage
2. Fan-in
3. Fan-out
4. Stray inductance
5. Stray capacitance
6. Source of noise
7. Shape of the noise source
To specify the noise immunity of an IC the following definitions are considered.
dc noise immunity This is specified in terms of noise margin. The dc noise margin is defined as the
difference between the guaranteed logic state voltage limits of a driving gate and the voltage requirements of
a driven gate.
ac noise immunity This considers the amplitude and pulse width of the noise signal. If the pulse width is
more, noise immunity is less. But if it is less than the propagation delay, the noise immunity is high.
Noise Generation
External noise Noise radiated into the system due to the make and break contacts, which are present near
the IC accounts for the external noise.
Power line noise This noise is generated due to ac or dc power distribution system.
Cross talk This is due to interference from adjacent signal lines.
Signal current noise Noise from unterminated or mismatched transmission lines.
Current Spikes There are many causes for this type of noise
1. Unequal currents drawn from the supply under logic 0 and 1 conditions.
2. Charging of load capacitor.
3. Conduction overlap at the output when going from one state to another. This noise is an internal noise
and hence can be reduced by suitable design.
Fan-in
This indicates how many input terminals are there for the gate. This depends on the number of diodes for DTL
logic and the number of emitters for TTL logic. Normally fan-in is less than or equal to 15.
Fan-out
This indicates how many gates it can drive. This is governed by the output and input currents of an IC at logic
0 and 1.
Fan-out = I
out
(1) (min) for logic 1.
I
in
(1) (max)
Fan-out = I
out
(0) (min) for logic 0.
I
in
(0) (max)
Cost
The overall cost of an IC depends on the fabrication technique, packing, shielding, etc.
Operating Temperature Range
The operating range of temperature of an IC should be very wide. In general it is as follows:
a) Consumer and Industrial applications: 0 to 70
0
C
b) Military and Space applications: 55
0
C to +125
0
C.
BUILDING BLOCKS OF A DIGITAL SYSTEM
Digital systems are broadly classified as
1. Combinational system
2. Sequential system
Combinational system This is based on the combinational logic where the output of the system depends
only on the inputs at that instant e.g., Binary adders, Decoder, Multiplexer, PLA, etc.
Sequential system This is based on sequential logic where the output of the system depends not only on
the input but also on the previous outputs. e.g. Flip-flops, Counters, Shift Registers.
Experiment 5.10
Study of Flip-flop
Aim To study the operation of the following flip-flops and verify their truth tables.
1. SR Flip-flop
2. JK Flip-flop
3. D Flip-flop
4. T Flip-flop
Equipment Required
Equipment Quantity
Chords
1
20
Components Required
Components Quantity
IC 74LS00
IC 74LS02
IC 74LS73
IC 74LS74
1
1
1
1
Circuit Diagram
SR Flip-flop Using NOR and NAND Gates
JK Flip-flop
D Flip-flop and D-F/F (Using JK-F/F)
T Flip-flop (Using D-F/F and JK-F/F)
Procedure
1. Connect the IC as per the configuration.
2. Give the inputs as per the truth table and verify the outputs.
3. Verify for all the flip-flops and then realise the same using logic gates.
Truth Table
SR Flip-flop (Using NAND Gate)
Clock S R Q
n+1
0
0
1
1
0
1
0
1
Unused
1
0
Q
n
SR Flip-flop (Using NOR Gate)
Clock S R Q
n+1
0
0
1
1
0
1
0
1
Q
n
0
1
Not used
JK Flip-flop
Clock J K Q
n+1
0
0
1
1
0
1
0
1
Q
n+1
0
1
Toggle
D Flip-flop
Clock D Q
n+1
0
1
0
1
T Flip-flop
Clock T Q
n+1
0
1
1
0
Result
The operations of the flip-flops are studied and their truth tables are verified.
Exercises
1. Define race around condition.
2. Explain how race around condition is overcome in a master-slave flip-flop.
3. Realise T flip-flop using other flip-flops.
Experiment 5.11
Study of Shift Registers
Aim To construct and study the operation of a 4 bit shift register in the following modes
1. Serial in serial out
2. Serial in parallel out
3. Parallel in serial out
4. Parallel in parallel out
Equipment Required
Equipment Quantity
Patch chords
1
20
Components Required
Components Quantity
IC 74LS00
IC 74LS74
1
1
Circuit Diagram
Procedure
Serial Mode
1. Connect the circuit as per the circuit diagram and pin configuration of the ICs.
2. Clear all the flip-flops by applying a low signal to the clear input.
3. Feed the data into the serial input one bit per clock pulse.
4. Observe the output at Q
1
, if the output is taken serially.
5. Observe the output at Q
1
, Q
2
, Q
3
, Q
4
, if the output is taken parallely.
Parallel In Parallel Out
1. Connect the circuit as per the diagram and pin configuration of the ICs.
2. Clear all the flip-flops by applying a low signal to the clear input.
3. Make the serial input low.
4. Enable the preset and clock by applying a high signal.
5. Feed in the data at P
1
, P
2
, P
3
, and P
4
.
6. Observe the outputs at Q
1
, Q
2
, Q
3
, and Q
4
.
Parallel In Serial Out
1. Repeat the above steps till step No.5.
2. Disable the present input by connecting it to a low signal.
3. Apply clock pulses to obtain data serially at Q
1
.
Tabular Column
Serial Mode
Mode of Operation Clock Serial Input Q
3
Q
2
Q
1
Q
0
Serial in serial out
Serial in parallel out
0
1
2
3
4
0
1
2
3
4
0
1
0
0
0
0
1
1
1
1
0
1
0
0
0
0
1
1
1
1
0
0
1
0
0
0
0
1
1
1
0
0
0
1
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
1
Parallel Mode
Mode of Operation Clock P
3
P
2
P
1
P
0
Q
3
Q
2
Q
1
Q
0
Parallel in serial out
Parallel in parallel out
0
1
2
3
4
5
0
1
2
3
0
1
0
0
0
0
0
1
1
0
0
1
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
1
1
1
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
1
1
1
0
0
1
0
0
Result
The operations of the shift registers are studied for all the modes of operation.
Exercise
1. Discuss about synchronous and asynchronous mode of operation.
2. What is a universal shift register? Explain its operation with a neat circuit.
Mod-4 Counter
Clock Q
2
Q
1
0
1
2
3
4
0
0
1
1
0
0
1
0
1
0
Mod-3 Counter
Clock Q
2
Q
1
0
1
2
3
0
0
1
0
0
1
0
0
Mod-5 Counter

Clock Q
3
Q
2
Q
1
0
1
2
3
4
5
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
1
0
0
Mod-8 Counter
Clock Q
3
Q
2
Q
1
0
1
2
3
4
5
6
7
8
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Modulo-10 Counter Using Feedback
Mod-10 Counter
Clock Q
4
Q
3
Q
2
Q
1
0
1
2
3
4
5
6
7
8
9
10
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
Experiment 5.12
Asynchronous Counter
Aim To construct a binary and modulo-n asynchronous counter.
1. Binary counter (4-bit).
2. Modulo-11 counter.
Equipment Required
Circuit Diagram
Binary Counter
Modulo-11 Counter
Procedure
2. Connect the clock input.
3. Observe the output and verify it with its count sequence.
Design Concept
1. Take the (n+1)th state.
2. Observe the output that are at 1 in the (n+1)
th
state.
3. Combine all those outputs in a NAND gate and give the output of the gate to clear the terminals of flip-
flops.
4. When the (n+1)th state arrives, the output of NAND gate will be zero (low), which will clear all flip-flops.
5. Hence instead of (n+1)th state, we get the first state (0000).
Count Sequence
Binary Counter Modulo-11
Clock Outputs
Q
3
Q
2
Q
1
Q
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16 (0)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Clock Outputs
Q
3
Q
2
Q
1
Q
0
0
1
2
3
4
5
6
7
8
9
10
11 (0)
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
1
0
1
0
0
Exercise
1. Design a mod-9 counter.
2. Design a mod-5 counter.
3. Design an up-down counter.
SYNCHRONOUS COUNTERS
Decade Counter Using Feedback
Ring Counter
Clock Q
4
Q
3
Q
2
Q
1
0
1
2
3
4
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
Down Counter
Clock Q
4
Q
3
Q
2
Q
1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Up-down Counter
Pre-setable Counter
Applications of Synchronous Counter
1. Direct counting
2. Divide by N
3. Measurement of frequency and time
4. Waveform generation
5. ADC
Experiment 5.13
Synchronous Counter
Aim To design and test the count sequences of a synchronous counter.
Given sequence: 0, 7, 1, 6, 2, 5, 0, 7, (repeating)
Equipment Required
Circuit Diagram
Procedure (Circuit Design)
1. Write the count sequence in binary.
2. For each flip-flop using excitation table, obtain the inputs for the transitions it has to make for each
applied clock pulse.
Excitation Table (J-K Flip-flop)
Q
n
Q
n+1
J K
0
0
1
0
1
1
0
1
X
X
X
0
Maximum number is 7, [i.e., 2
3
= 8], so 3 binary bit of data is sufficient to design the counter.
Truth Table
Decimal Number Present State Next State
0
7
1
6
2
5
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
0
J
1
/K
1
J
2
/K
2
J
3
/K
3
J
1
/K
1
J
2
/K
2
J
3
/K
3
Using excitation table, write the logical table.
F/F 1 F/F 2 F/F 3 Decimal Number
J
1
K
1
J
2
K
2
J
3
K
3
Initial
state
Final
state
1
X
X
0
1
X
X
0
1
X
X
1
1
X
1
X
X
0
X
0
X
0
1
X
1
X
1
X
1
X
X
1
X
1
X
1
0
7
1
6
2
5
7
1
6
2
5
0
Draw the K-map for the inputs and implement the circuit.
Note: A synchronous counter is one in which all flip-flops are clocked simultaneously.
Exercise
Design the following synchronous counters:
1. Count 3-bit odd number.
2. Count 3-bit even number.
3. Count mod-5 sequence.
4. Count 4-bit binary sequence.
Synchronous Sequential Circuit
Obtain the truth table and state diagram of the synchronous sequential circuit shown.
Circuit Diagram
State Transition Table
0
1
0
1
0
0
0
0
1
0
1
0
1
1
0
0
1
0
1
0
0
0
0
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1 n n n n n
Q yQ Q x K y Q J y x Q
+
+ = =
State diagram is shown below
Experiment 5.14
Aim To design a synchronous sequential circuit for a given state transition diagram.
Procedure (Design)
1. Given the state transition diagram, form the truth table.
2. Fill in the inputs to be applied to the flip-flops in order to have transitions from a previous state to next
state of output of flip-flops using excitation table.
3. With inputs to the circuit and past outputs of flip-flops, obtain an expression for the flip-flop inputs.
4. Design the circuit from equations obtained.
State Transition Diagram Excitation Table (J-K Flip-flop)
Q
n
Q
n+1
J K
0
0
1
1
0
1
0
1
0
1
X
X
X
X
1
0
Truth Table
x y Q
0n
Q
1n
Q
0(n+1)
Q
1(n+1)
J
1
K
1
J
2
K
2
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
0
0
1
X
1
X
X
0
X
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
1
1
X
X
X
X
0
0
0
X
0
X
X
1
X
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
X
X
X
X
1
1
1
X
1
X
X
0
X
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
X
X
X
X
1
1
0
X
0
X
X
1
X
1
Combination of inputs
and previous state
Next state from the
state diagram
From the excitation table
Obtain expressions for J
1
, J
2
, K
1
and K
2
using K-map:
Circuit Diagram
Experiment 5.15
Aim To obtain the state diagram for the given synchronous sequential circuit.
Circuit Diagram
Design Procedure (Design)
1. Form a table with all combination of inputs to the circuit (x, y, etc.) and outputs of all flip-flops.
2. Write down the entries for the flip-flop inputs using the circuit equations.
3. Obtain the next states using the truth table of flip-flop.
4. Draw the state diagram.
Step I: Table with
combination of all
input and outputs
Step II: Entries for flip-flop inputs
Step III: Obtain the
next states using
truth table
x y Q
1
Q
2
J
1
= Q
1
K
1
= x + Q
2
J
2
= Q
2
K
2
= y Q
1 (n+1)
Q
2 (n+1)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
State transition diagram:
Communication Circuits 6.1
C h a p t e r 6
COMMUNICATION CIRCUITS
Experiment 6.1
Amplitude Modulation
Aim To construct an amplitude modulation circuit and to calculate the modulation index.
Equipment Required
CRO
Function Generator
Power supply
(020) MHz
(01) MHz
(030) V
1
2
1
Components Required
Transistor
Capacitor
Resistor
BC107
0.1 F; 10 F
22 k, 10 k, 1.2 k
1
Circuit Diagram
figure (a)
Design
The design of amplitude modulation circuit is same as simple single stage RC coupled amplifier with function
generator (V
m
) replaced by its output resistance (50 ).
Procedure
1. Connections are made as shown in the figure (a).
2. Set the carrier signal to 3.2 V, 10 kHz using function generator.
3. Set the modulating signal frequency to 1 kHz and vary the amplitude around the carrier voltage.
4. Note down the maximum and minimum voltages from the CRO.
5. Calculate the modulation index using the formula, modulation index, % 100
V V
V V
m
min max
min max
=
Model waveform (Observed on CRO)
Tabular Column
V
m
(Volts)
V
max
(Volts)
V
min
(Volts)
m(%)
Experiment 6.2
Amplitude Demodulation
Aim To construct an amplitude demodulation circuit and to plot the wave form.
Equipment Required
CRO
AM kit
(020) MHz 1
1
Components Required
Diode
Capacitor
Resistor
IN4001
0.01 F;10 F
1 k
1
Circuit Diagram
figure (a)
Procedure
1. Connections are made as shown in the figure (a).
2. Apply AM signal to the given circuit.
3. Observe the amplitude demodulated output on the CRO.
4. Compare the demodulated signal with original modulating signal. (Both must be same in all parameters).
Model Graph
Experiment 6.3
Frequency Modulation
Aim To construct the frequency modulation circuit and to calculate the modulation index.
Equipment Required
CRO/Spectrum analyser
Function generator
Power supply
(020) MHz
(01) MHz
(030) V
1
1
1
Components Required
Components Values Quantity
Capacitors
Resistors
Potentiometer
1 F;
0.01 F
10 F
47 k
4.7 k
100 k
150
100 k
1
2
1
2
1
1
1
1
Circuit Diagram
Procedure
1. Connections are made as per circuit
diagram.
2. Without signal applied, measure
carrier signal at pin No 2 of IC 2206
3. Apply modulating AF signal at pin
No 7 of IC 2206
4. Observe frequency modulated
signal on CRO/spectrum analyser.
5. Calculate modulation index,
m f
f m / ) ( =
where,
) (
= maximum frequency
deviation
f
m
= modulating frequency
6. Calculate the bandwidth, BW = 2
(f
m
+ )
Model Graph
Experiment 6.4
Frequency Demodulation
Aim To construct the frequency demodulation circuits and to observe waveform.
Equipment Required
Components Required
IC565
Capacitors
Resistors
10 F
100 F
470 pF
560
10 k
1
1
1
1
2
1
Circuit Diagram
Procedure
1. Connections are made as per circuit diagram.
2. Check if PLL (IC565) is functioning or not by giving square wave to input and observe output.
3. Frequency of input signal (square wave) is varied till input and output are locked.
4. Now frequency modulated signal is fed as input and frequency demodulated signal (modulating signal) is
observed on CRO/Spectrum analyser.
Model Graph
Experiment 6.5
Pulse Position Modulator
Aim To study and implement PPM using IC555 and to observe waveform.
Equipment Required Components Required
CRO
Power supply
(020) MHz
+5 (fixed)
(05) V
1
1
1
TIMER IC
Resistor
Capacitor
555
10 k
1 k
0.01 F
2
2
1
3
Circuit Diagram
Procedure
2. Vary the input (DC Voltage) from 05V at pin No 5 of first timer IC.
3. Observe the corresponding output waveform on the CRO at pin No 3 of second timer IC.
4. Plot the observed waveform for any one reading.
Model Graph
Experiment 6.6
Pulse Amplitude Modulation (PAM)
Aim To construct a pulse amplitude modulation and demodulation circuit and to observe the waveforms.
Equipment Required
CRO
Function Generator
PAM kit
(020) MHz
(01) MHz
1
2
1
Components Required
Transistor
Capacitor
Resistor
BC107/2N2222
1.7 F
10 k
22 k
1
1
2
1
Circuit Diagram
Pulse Amplitude Modulation
Pulse Amplitude Demodulation
Procedure
Pulse amplitude modulation
2. Modulating signal is given to collector and carrier signal (pulse signal) of high frequency is given to
base of the transistor.
3. Output is taken at emitter and observe CRO.
Model Graph
Experiment 6.7
Pulse Width Modulation
Aim To study and implement pulse width modulation using IC555.
Equipment Required
CRO
Power supply
(020) MHz
(05) V
1
Components Required
Timer IC
Capacitor
Resistor
IC555
0.1 F
47 k
10 k
1
1
1
1
Circuit Diagram
Procedure
2. Vary the control voltage (05) V and observe the corresponding change in output square waveform using
CRO.
3. Change in control voltage changes the width of the square wave.
4. Note down the T
ON
and T
OFF
.
5. Plot the observed waveform.
Model Graph
Experiment 6.8
Pulse Width Modulation (PWM) &
Pulse Position Modulation (PPM)
Aim To construct and test a PWM and PPM circuit and to observe the waveforms.
Equipment Required
CRO
Function generator
Power supply
(020) MHz
(01) MHz
5V
1
2
1
Components Required
PLL IC
EX-OR gate
Resistor
Capacitor
565
7486
390 k
33 k
10 k
4.7 k
5.6 k
5 k(pot)
0.1F
0.01 F
0.47 F
0.0047 F
1
1
1
1
1
2
1
2
3
2
1
1
Circuit Diagram
Procedure
2. Check the free running frequency of the PLL (IC565) and adjust the potentiometer to produce 15 kHz
at pin No 4.
3. Set the carrier signal (say 2V
pp
,15.9 kHz) which must be approximately in the middle of tracking range of
PLL (IC565).
4. Apply modulating signal (say 1.3 V
pp
, 300 Hz) at pin No 7.
5. Observe the PPM waveform in CRO as shown in the figure (a).
6. Observe the output of EX-OR gate (7486) using CRO adjust the frequency of the modulating signal to
obtain a stable PWM output.
Model Graph
figure (a)
Experiment 6.9
Amplitude Shift Keying (ASK) Modulator
Aim To study and implement ASK modulator and to observe the waveform.
Equipment Required
Equipments Range Quantity
CRO
Function generator
Power supply
(020) MHz
(01) MHz
(030) V
12V
1
1
1
1
Components Required
Component Value Quantity
Op-amp
Transistor
Resistor
Capacitor
A741
BC107
1 k
10 k (pot)
0.01F
1
1
5
1
2
Circuit Diagram
Procedure
2. Set input signal (square wave) say 1V, 1 kHz using function generator.
3. Observe the output waveform on the CRO.
4. Plot the observed waveform on the graph.
Model Graph
Experiment 6.10
Amplitude Shift Keying Demodulator
Aim To study and implement ASK demodulator and to observe waveform.
Equipment Required
CRO
ASK modulator
Power supply
(020) MHz
5 V
(05) V
1
1
1
1
Components Required
Op-amp
Diode
Resistor
Capacitor
A741
IN4001
1 k
1F
1
1
1
1
Circuit Diagram
Procedure
2. Give the FSK modulated signal as input the circuit.
3. Observe the output waveform on the CRO
4. Vary the V
ref
(05 V) and observe the corresponding waveform on the CRO.
Experiment 6.11
Pseudo Random Binary Sequence Generator
Aim To study the functioning of a PRBS generator and to calculate the balance, run and correlation properties.
Clock generator
Power supply
(01) MHz
(05) V
1
1
D F/F
LED Resistor
EX-OR gate
NOT gate
7473
330
7486
7404
2
1
1
1
Circuit Diagram
1. Balance
2. Run property
3. Correlation property
Procedure
2. Observe the output sequence.
Experiment 6.12
Frequency Shift Keying (FSK) Modulator
Aim To implement and study FSK modulator circuit.
CRO
Function generator
Power supply
(020) MHz
(01) MHz
(030) V
1
1
1
Timer IC
PLL IC
Transistor
Resistor
Capacitor
XR2206
555
565
C107
1 k
10 k
4.7 k
100 k
1nF
22 F
0.01 F
1
1
1
1
2
3
2
1
1
1
2
Circuit Diagram (Using PLL)
Using Timer 555
Procedure
2. Set the AF input (say 1V
pp
, 150 Hz) using function generator.
3. Observe the output on CRO.
4. Draw the observed waveform on the graph.
5. Identify the mark frequency and space frequency.
6. Find the mark frequency (f
m
) and space frequency (f
s
).
7. Calculate modulation Index (MI) = ,
2 /
| |
0
f
f f
s m
where f
0
= fundamental frequency of the input signal.
Using XR2206
Note: (XR2206): If voltage at pin No. 9 is less than 1volt, only resistor R
2
is actuated. For voltage greater
than 2 V, resistor R
1
is actuated. Thus the output signal frequency can be keyed between two levels f
1
and f
2
.
Model Graph
Experiment 6.13
Frequency Shift Keying Demodulator
Aim To design and implement FSK demodulator and observe the waveform.
Equipment
CRO
FSK Modulator
Power supply
PLL IC
Op-amp
Resistor
Capacitor
565
A741
10 k
1 k
33 k
10 k(pot)
0.02 F
0.01 F
1
1
3
2
1
1
3
2
Circuit Diagram
Procedure
2. The FSK waveform (input signal) is given to pin No. 2
3. The FSK demodulated output is observed on the CRO.
Experiment 6.14
Pre Emphasis
Aim To construct and verify pre-emphasis network and plot the waveform.
CRO
Function generator
Power supply
(020) MHz
(01) MHz
(030) V
1
1
1
Transistor
Capacitors
Inductor
Resistors
BC107/2N2222
10 F
0.1 F
100pF
0.75 kH
100 k
32 k
2.5 k
10 k
75 k
1
1
1
1
1
1
1
1
1
2
Circuit Diagram
Pre-emphasis (passive)
Pre-emphasis (active)
Procedure
2. Set input signal amplitude (say 1V
pp
) using function generator.
3. Vary the input signal frequency from 0Hz to 100 kHz in regular steps.
4. Note down the corresponding output voltage.
Tabular Column
V
i
= 1V
PP
Frequency (Hz)
Output voltage
(V
o
, Volts)
Gain (dB)=20log (V
o
/V
i
)
Model Graph
Experiment 6.15
De-Emphasis
Aim To construct and verify de-emphasis network and to plot waveform.
Equipment Required
CRO
Function generator
(020) MHz
(0100) kHz
1
1
Components Required
Capacitors
Resistors
1000 pF
75 k
1
2
Circuit Diagram
Procedure
2. Set input signal amplitude say 1 V
pp
3. Vary the signal frequency from 0Hz to 100 kHz in regular steps.
4. Note down the corresponding output voltage.
Tabular Column
V
i
= 1V
pp
Frequency (Hz) Output voltage (V
o
, Volts) Gain (dB) = 20log (V
o
/V
i
)
Experiment 6.16
Digital Phase Detector
Aim To construct a digital phase measurement detector and to detect phase difference between two sinusoidal
waves and plot the waveforms and calculate phase angle.
Equipment Required
CRO
Function Generator
Power supply
Ammeter (dc)
(020) MHz
(01) MHz
12 V
(0-10 mA)
1
1
1
1
Components Required
Op-amp
Ex-OR gate
Transistor
Resistor
Potentiometer
Capacitor
A741
IC7486
BC 107
1 k
100 k
0.01 F
1
1
1
1
1
1
Circuit Diagram
Procedure
2. Set input signal (say 1 V
pp
, 1 kHz) using function generator.
3. Observe the square waves at the output (pin No 6) of both op-amps.
4. Vary the resistance and note down the corresponding current using DC ammeter.
5. Also observe the output waveform across the emitter resistance of the transistor.
6. Phase angle can be calculated using the formula,
= tan
1
[ RC]
7. Plot the graph: Phase angle () Vs Current (mA).
Tabular Columns
Resistance
(k )
Current
(mA)
Phase angle
= tan
1
( RC)
Model Graph
Experiment 6.17
Mixer (Using Discrete Component)
Aim To implement and study the mixer circuit.
Equipment Required
CRO
Function generator
Power supply
(020) MHz
(01) MHz
(030) V
1
2
1
Components Required
Transistor
Resistors
Capacitor
BC107
10 k
470
1 k
0.0 F
1 F
1
4
1
1
2
1
Circuit Diagram
Procedure
2. Apply both the input signal to the base and emitter terminal of the transistor.
3. Observe the output waveform on the CRO.
Experiment 6.18
Mixer (Using IC)
Aim To construct and test a mixer circuit and study its working characteristics.
Equipment Required
CRO
Function generator
Power supply
(020) MHz
(01) MHz
5V
1
1
1
Components Required
PLL
Resistor
Capacitor
C565
33 k
10 k
1 k
0.01 F
10 F
0.1 F
1
1
1
1
2
1
1
Circuit Diagram
Procedure
2. Set f
c
= 100 kHz; f
s
= 95 kHz and observe the output on the CRO. Note down the output frequency.
Tabular Column
f
s
(kHz) f
c
(kHz) Output Frequency (kHz)
Experiment 6.19
Auto Ranging
Aim To design a circuit to perform the auto ranging operation.
Equipment Required
Voltmeter
Power supply
(02) V
15 V
(02) V
1
1
1
Components Required
Op-amp
LED
Resistors
A741
330
10 k (pot)
3
3
3
1
Circuit Diagram
Design
mV 5 V 005 . 0 1 . 0
1 . 111
5
, Point
mV 50 V 05 . 0 1 . 1
1 . 111
5
, Point
mV 500 V 5 . 0 1 . 11
1 . 111
5
, Point At
= = =
= = =
= = =
C
B
A
V C
V B
V A
Procedure
2. A +5V supply is given to the voltage divider network which is connected to the inverting terminal of the
op amps.
3. A (02V) variable supply is given to the non-inverting terminal of the op amp through a potentiometer
(010k).
4. Vary the resistance of the potentiometer and observe the LED glow.
5. Note down the range which each LEDs glows and tabulate the result.
Tabular Column
Voltage Range (mV) LED1 LED2 LED3
0
1
1
1
0
0
1
1
0
0
0
1
Experiment 6.20
Frequency Counter
Aim To design and implement a frequency counter using IC74121.
Equipment Required
Function generator
Power supply
(0-1) MHz
(0-30)V
1
1
Components Required
IC
AND gate
Resistors
Capacitor
OR gate
74121
7408
4.7 k
1.5 k
1F
7432
1
2
1
1
1
1
Circuit Diagram
Design
T = 0.69 RC
T = 1sec and C = 1 F
Therefore R = 1.5k
Procedure
2. Counter display the frequency value of the signal.
Tabular Column
Frequency (Hz) V
o
(Volt)
Experiment 6.21
Cross Over Network
Aim To design a cross-over network for a given frequency.
Equipment Required
CRO
Function generator
(020) MHz
(01) MHz
1
1
Components Required
Inductors (DIB)
Capacitor (DCB)
Resistors
Variable
Variable
1 k
2
2
2
Circuit Diagram
Design
2
0
2 ;
2
1
R
C
L
C L
f
o
= =
Set f
o
= 1 kHz ; R
o
= 1 k = R
1
= R
2
Find L and C.
Procedure
2. Set the input signal say 1 V
pp
using function generator.
3. Vary the frequency from 10 Hz in a regular step.
4. Note down the corresponding output voltages across both woofer and tweeter terminals or CHI and CHII
of CRO.
5. Plot the graph: Gain (dB) vs. Frequency (Hz).
Tabular Column
V
i
= 1 V
pp
Frequency (Hz) Output voltage (V
o
) Gain (dB) = 20log (V
o
/V
i
)
Model Graph
Experiment 6.22
Directional Characteristics of
Loud Speaker and Microphone
Aim To study the directional characteristics of a loud speaker and microphone using sound level meter.
Equipment Required
CRO
Function generator
Sound level meter
Audio amplifier kit
Microphone
(020) MHz
(01) MHz
1
1
1
1
1
Block Diagram
Microprocessor 8085 8.1
C h a p t e r 8
MICROPROCESSOR 8085
INSTRUCTIONS TO USE YOUR MICROPROCESSOR KIT
Know Your Microprocessor
The Microprocessor (8085) is a 8 bit, 40 pin dual-in-line package IC. The CPU includes the 3 pairs of registers
B & C, D & E and H & L, which can be used as individual 8-bit register or paired 16-bit registers. Other internal
registers are stack pointer, status register (Flags) and temporary registers. 8085 has 16-bit address bus and 8-bit
data bus. It can address 2
16
address locations.
Use Your Microprocessor Kit
To enter data/program
1. Press MEM
2. Enter the required memory location address (on the address field).
3. Press Next
4. Enter the required data/program on the data/field program.
5. Enter the data/program on the immediate location {address location changes to next location on
pressing Next}
To run the program
1. Press Go
2. Enter the starting address of the program.
3. Press EXEC
4. If program is incorrect, address field displays Err.
To check the content register for result
1. Press REG followed by register name (say A, B, C,.) .
2. The content of that register will be displayed in data fields.
To check the content of the memory location
1. Press MEM
2. Enter the required memory address.
3. Press NEXT , content of the location is displayed in data field.
Supporting IC and Its Name
8279 : Keyboard/display interface controller
8253 : Programmable interval timer/counter
8251 : USART
8255 : Programmable Peripheral Interface (PPI)
8259 : Programmable Interrupt Controller (PIC)
6116 : RAM
2716 & 2816 : EPROM
Memory Mapping
Location Purpose
0000 Key-board Monitor
RDKBD 03BA STA
UPDAD 0440 : LSB 8EEF Address field location
MSB SFFO Address field location
UPDDT 044C : STA 8FFI data field display
OUTPUT 0389
07FF Serial Monitor
0FFF User Expansion
1FFF
87FF
User Expansion ROM/RAM
8000 User portion RAM (Program/data location)
8FFF RAM for System manufacturer usage
MOV A B C D E H L M
A 7F 78 79 7A 7B 7C 7D 7E
B 47 40 41 42 43 44 45 46
C 4F 48 49 4A 4B 4C 4D 4E
D 57 50 51 52 53 54 55 56
E 5F 58 59 5A 5B 5C 5D 5E
H 67 60 61 62 63 64 65 66
L 6F 68 69 6A 6B 6C 6D 6E
M 77 70 71 72 73 74 75 76
MVI A B C D E H L M
3E 06 0E 16 1E 26 2E 36
PUSH B D H PSW
C5 D5 E5 F5
POP B D H PSW
C1 D1 E1 F1
XCHG
EB

XTHL
E3
1. Arithmetic Instruction
ADD A B C D E H L M
87 80 81 82 83 84 85 86
ADC A B C D E H L M
8F 88 89 8A 8B 8C 8D 8E
ADI ACI
C6 CE
SUB A B C D E H L M
97 90 91 92 93 94 95 96
SBB A B C D E H L M
9F 98 99 9A 9B 9C 9D 9E
SBI SUI
DE D6
DAD B D H SP DAA
09 19 29 39 27
2. Logical Instructions
ANA A B C D E H L M ANI
A7 A0 A1 A2 A3 A4 A5 A6 E6
ORA A B C D E H L M ORI
B7 B0 B1 B2 B3 B4 B5 B6 F6
XRA A B C D E H L M XRI
AF A8 A9 AA AB AC AD AE EE
3. Compare Instructions
CMP A B C D E H L M
BF B8 B9 BA BB BC BD BE
4. Compliment Instructions
CMA CMC
2F 3F
5. Jump Instructions
JC JM JMP JNC JNZ JP JPE JPO JZ
DA FA C3 D2 C2 F2 EA E2 CA
6. Load/Store Instructions
LXI B D H SP LDAX B D
01 11 21 31 0A 1A
LDA LHLD
3A 2A
STAX B D SHLD SPHL STA STC
02 12 22 F9 32 37
7. Interrupt Instructions
RST 0 1 2 3 4 5 6 7
C7 CF D7 DF E7 EF F7 FF
SIM RIM EI DI
30 20 FB F3
8. Bit Rotation Instructions
RLC RAL RRC RAR
07 17 0F 1F
9. Return Instructions
RET RZ RC RPE RM RNZ RNC RPO RP
C9 C8 D8 E8 F8 C0 D0 E0 F0
10. Increment/Decrement Instructions
INR A B C D E H L M
3C 04 0C 14 1C 24 2C 34
INX B D H SP
03 16 23 33
DCR A B C D E H L M DCX B D H SP
3D 05 0D 15 1D 25 2D 35 0B 1B 2B 3B
11. Halt Instructions
HLT
76
12. No Operation Instruction
NOP
00
13. Port Instructions
IN OUT
DB D3
14. Call Instructions
CALL CZ CC CPE CM CNZ CNC CPO CP CPI
CD CC DC EC FC C4 D4 E4 F4 FE
8085 PROGRAMMING
Practice Session - 1
1. Program to load register A, B, C, D with same constant.
Address Label Mnemonic Operand Hex Code Comment
8800 MVI A, FF 3E [A] [FF]
H
8801 FF (FF)
H
is transferred to Accumulator
A-register
8802 MVI B, FF 06 [B] [FF]
H
8803 FF (FF)
H
is transferred to B-register
8804 MVI C, FF 0E [C] [FF]
H
8805 FF (FF)
H
is transferred to C-register
8806 MVI D, FF 16 [D] [FF]
H
8807 FF (FF)
H
is transferred to D- register
8808 HLT 76 Halt the program
2. MVI instruction takes 2 bytes of memory whereas MOV instruction takes only 1 byte of memory.
8800 MVI A, FF 3E [A] [FF]
H
8801 FF (FF)
H
8802 MOV B, A 47 [B] [A]
Content of A is transferred to
B-register
8803 MOV C, A 4F [C] [A]
C- register
8804 MOV D, A 57 [D] [A]
8805 HLT 76 Content of A is transferred to
D-register
*Square bracket [B] indicates the content of B-register
3. [FF]
H
: FF in Hexadecimal Code
8800 MVI A, FF 3E [A] [FF]
8801 FF (FF)
H
8802 MOV B, A 47 [B] [A]
B-register
8803 MOV C, B 48 [C] [B]
Content of B is transferred to
C- register
8804 MOV D, C 51 [D] [C]
Content of D is transferred to
C-register
8805 RST5 EF Reset
4. Four bytes of data are stored in consecutive data memory location of starting at address x. Write a program
to load E with [x], D with [x + 1], C with [x + 2] and A with [x + 3]
By Direct Addressing Mode
8800 LDA 8900 3A [A] [8900]
H
8801
8802
00
89
Content of address [8900]
H
is loaded
to Accumulator
8803 MOV E, A 5F [E] [A]
8804
8805
LDA 8901 3A
01
8806 89
[A] [8901]
H
Content of address [8901]
H
is loaded
to Accumulator
8807 MOV D, A 57 [D] [A]
8808
8809
LDA 8902 3A
02
880A 89
[A] [8902]
H
Content of address (8902)
H
is loaded
to Accumulator
880B MOV C, A 4F [C] [A]
880C LDA 8903 3A
880D 03
880E 89
[A] [8903]
H
Content of address (8903)
H
is loaded
to Accumulator
880F HLT 76 Halt the program
By Register Indirect Addressing Mode
8800 LXI H, 8900 21
8801 00
8802 89
Memory pointer is pointed to
[8900]
H
[8900]
H
[M] [HL]
8803 MOV E, M 5E [E] [M]
8804 INX H 23 Next [HL] location
8805 MOV D, M 56 [D] [M]
8806 INX H 23 [D] [A]
8807 MOV C, M 4E [C] [M]
8808 INX H 23 [D] [A]
8809 MOV A, M 7E [A] [M]
880A HLT 76 Halt
Note: Direct addressing is simple but occupies large program memory location than indirect addressing. Indirect
addressing mode is more flexible but it takes more time for execution.
Program to move bytes of data to other memory location.
Direct Addressing Mode
8800
8801
8802
LDA 8900 3A
00
89
[A] [8900]
8803
8804
STA 8950 32
50
8805 89
[8950]
H
[A]
Content of Accumulator is stored in
memory address [8950]
H
8806
8807
8808
LDA 8901 3A
01
89
[A] [8901]
H
8809 STA 8951 32
890A 51
890B 89
Content of Accumulator is
stored in memory address
[8951]
H
.
890C HLT 76 Halt
Indirect Addressing Mode
8800 LXI H, 8900 21 [M] [HL] [8900]
H
8801 00 Memory location to store the data
8802 89
8803 LXI B, 8950 01
8804 50
8805 89
[BC]
H
[8950]
H
Memory location to store the result
8806 MOV A, M 7E [A] [[N] [L]]
8807 STAX B 02 [8950]
H
[[B] [C]] [A]
8809 INX B 03 Next [BC] location
880A MOV A, M 7E [A] [M]
880B STAX B 02 [8951]
H
[[B] [C]] [A]
880C HLT 76 Halt
STANDARD PROGRAMS
1. Program to interchange the data byte between two locations.
8800 LXI H,8900 21 [M] [HL] [8900]
H
8802 89
8803 LXI D, 8950 11 [DE] [8950]
H
8805 89
8806 MOV B, M 46 [B] [M]
8807 LDAX D 1A [8950]
H
[DE]
H
[A]
8808 MOV M, A 77
8809 MOV A, B 78
880A STAX D 0A
880B HLT 76 Halt
Note: The examples given in this book uses 8800 as the starting memory location for programs and 8900 as
the starting memory location for data storage.
2. Program to exchange the data byte stored in register-D with register-H and data byte stored in register-E
with register-L.
8800 LHLD 8900 2A [L] [8900]
H
8801 00 [H] [8901]
H
8802 89
8803 MOV D, H 54 [D] [H]
8804 MOV E, L 5D [E] [L]
8805 LHLD 8902 2A [L] [8902]
8806 02 [D] [H]
8807 89 [E] [L]
8808 XCHG EB
8809 HLT 76
3. Program to exchange the data byte stored in register-D with register-H and data byte stored in register E
with register-L.
8800 LXI H, 8900 21 [M] [HL] [8900]
H
8801 00
8802 89
8803 MOV D, M 56 [D]
H
[M]
8805 MOV E, M 5E [E] [M]
8806 LHLD 8902 2A [L] [8902]
8807 02 [H] [8903]
8808 89
8809 XCHG EB [E] [L] ; [D] [H]
880A HLT 76 Halt
4. Program to add two 8 bit binary number (overflow considered)
8800 LXI H, 8900 21 [M] [HL]
H
[8900]
H
8801 00
8802 89
8803 MVI C, 00 0E
8804 00
[C] 00
H
: Carry (over flow)
indication
8805 MOV A, M 7E [A] [M]
8806 INX H 23 [HL] + 1
8807 ADD M 86 [A] [A] + [M]
8808 JNC LOOP1 02 If [CY] = 00: Go to 880B location
8809 0C If [CY] = 01: Go to 880C location
880A 88
880B INR C 0C [C] [C]+1
880C LOOP1 MOV M, A 77 [M] [A] : Value of Accumulate
transferred to memory [8903]
H
880D INX H 23 Next [HL] location
880E MOV M, C 71 [M] [C]: Value of carry
indication transferred to memory
[8904]
H
880F HLT 76 Halt
5. Program to add N 8 bit binary numbers (over flow considered)
8800 MVI B, N 06 [B] N
H
Counter for count number
of data to be added
8801 [N]
8802 LXI H, 8900 21 [M] [HL] [8900]
H
8803 00
8804 89
8805
8806
MVI C, 00 0E
00
[C] 00
H
: Carry or overflow
indicator
8807 MOV A, C 79 [A] [C]
8808 ADD M 86 [A] [M]+[A]
8809 LOOP2 JNC LOOP1 02, OE, 88 If [CY] = 0 go to location [880D)
H
880C INR C OC If [CY] = 01: go to location (880C)
H
880D INX H 23 [C] [C]+1; [HL]+1
880E LOOP1 DCR B 05 [B] = [B] - 1
880F JNZ LOOP2 C2, 09, 88 If [Z] = 0 : go to location [8808]
H
[Z] = 1 : go to location [8812]
H
8812 MOV M, A 77 8902 [M] [A]
8813 INX H 23
8814 MOV M, C 71
8815 INX H 23 [HL]+1
8816 HLT 76 Halt
6. Program to add two 16-bit binary numbers
8800 LHLD 8900 2A [HL] [8900]
8801 00 [H] [8901]
8802 89
8803 XCHG B, H EB [E] [H]
8804 4D [D] [L]
8805 LHLD 8902 2A [L] [8902]
8806 02 [H] [8903]
H
8807 89 [L] [L]+[E]
8808 DAD B 19 [H] [H]+[D]+[CY]
8809 SHLD 8904 22 [8904] [L]
880A 04 [8905]
H
[H]
880B 89
880C HLT 76 Halt
Input data : [8900] [Data 1] LOB, [8901] [Data 1] HCB
7. Program to add two 8-bit BCD numbers
8800 LXI H, 8900 21 [M] [HL] [8900]
8801 00
8802 89
8803 MOV A, M 7E [A] [M]
8804 INX H 23
8805 ADD M 86 [A] [A] + [M]
8806 DAA 27 If [A]<9:[A] [A]
If [A]>9:[A] [A]+6
8807 STA 8902 32
8808 02 [8902]
H
[A]
8809 89
880A HLT 76 Halt
8. Subtraction of two 8-bit numbers
8800 MVI C, 00 0E [C] [00]
H
; Carry register
8801 00
8802 LXI H, 8900 21 M [HL] [8900]
H
8803 00
8804 89
8805 MOV B, M 46
8806 INX H 23
8807 MOV A, M
7E
[B] [M]
[8901] [HL] [HL]+1
[A] [M]
8808 SUB B 90 [A] [A][B]
8809 JNC LOOP1 D2 If [CY]=0: go to location [880F]
880A 0F If [CY]=1 go to location [880C]
880B 88
880C INR C 0C [C] [C]+1
880D CMA 2F [A] [A]
880E INR A 3C [A] [A]+1
880F LOOP1 INX H 23 [8902] [HL] HL+1
8810 MOV M, A 77 [M] [A] Difference in 8902
8811 MOV A, C 79 [A] [C]
8812 INX H 23 [8903] [HL] HL+1
8813 MOV M, A 77 [M] [A] Carry in 8903
8814 HLT 76 HALT
9. Program to subtract two BCD numbers
8800 LHLD 8900 2A [HL] [8900]
H
8801 00 [+1] [8901]
H
8802 89
8803 MVI A, (99)
H
3E [A] [99]
H
8804 (99)
H
8805 SUB L 95 [A] [A]-[L]
8806 ADI (01)
H
C6 [A ] [A]+[01]
H
8807 (01)
H
8808 DAA 27 Decimal Accumulator adjust
8809 ADD H 84 [A] [A]+[01]
H
880A DAA 27
880B STA 8902 32 [8902]
H
[A]
880C 02
880D 89
880E HLT 76 Halt
10. Program to subtract two 16-bit numbers
8800 MVI C, 00 OE [C] [00]
H
8801 00
8802 LHLD 8900 2A
8803 00 [HL] [8900]
8804 89
8805 XCHG EB [D] [H]; [E] [L]
8806 LHLD 8902 2A [HL] [8902]
H
8807 02
8808 89
8809 CALL SUB CD Call "SUB" subroutine
880A 50
880B 88
880C DAD D 19 [HL] [HL]+[DE]
880D JC LOOP1 DA If [CY]=1: go to location [8814]
H
880E 14 If [CY]=0: go to location [8810]
H
880F 88
8810 CALL SUB CD Call "SUB" subroutine
8811 50
8812 88
8813 INR C OC [C] [C]+1
8814 LOOP1 SHLD 8904 22 [8904] [L]
8815 04 [8905] [H]
8816 89
8817 MOV A, C 79 [A] [C]
8818 STA 8906 32 [8906] [H]
8819 06
881A 89
881B HLT 76 Halt
8850 SUB MOV A, H 7C [A] [H]
8851 CMA 2F [A] [A]
8852 MOV L, A 67 [L] [A]
8853 MOV A, H 7D [A] [H]
8854 CMA 2F [A] [A]
8855 MOV H, A 6F [H] [A]
8856 INX H 23 [HL] [HL]+1
8857 RET C9 Return to "SUB" called
11. Program to multiply two 8-bit binary numbers
8800 LXI H, 8900 21 [M] [HL]

[8900]
H
8801 00
8802 89
8803 MOV B, M 46 [B] [M]
8804 INX H 23 [HL] [HL]+1
8805 MOV C, M 4E [C] [M]
8806 XRA A AF [A] [00]
H
8807 LOOP1 ADD C 81 [C] [C]+1
8808 DCR B 05 [B] [B]-1
8809 JNZ LOOP1 C2
880A 07 If [Z] = 0: goto location [8807]
H
880B 88 If [Z] = 1: goto location [880C]
H
880C STA 8902 32 [8902]
H
[A]
880D 02
880E 89
880F HLT 76 Halt
12. Program to multiply two 8-bit binary numbers (Shifting and adding)
8800 LXI H, 8900 21 [M] [HL]

[8900]
H
8801 00
8802 89
8803 MOV C, M 4E [C] [M]
8804 MVI B, 00 06 [B] 00
H
8805 00
8806 MVI D, 08 16 [D] 08
H
: to count 8-bit
8807 08 [HL] [HL]+1
8808 INX H 23 [A] [M]
8809 MOV A, M 7E [HL] 0000
H
880A LOOP2 RAR 1F Rotate the bit of Accumulator right
880B JNC LOOP1 D2 If [CY]= 0: go to location [8811]
H
880C OF If [CY] = 1: go to location [8810]
H
880D 88
880E DAD D 19 [HL]
H
[HL]
H
+[DE]
H
880F LOOP1 XCHG EB [D] [H]; [E] [L]
8810 DAD H 29
8811 XCHG EB [D] [H]; [E] [L]
8812 DCR D 15 [D] [D] 1
8813 JNZ LOOP2 C2
8814 0A If [Z]=0: go to location [8818]
H
8815 88 If [Z]=1: go to location [881C]
H
8816 SHLD 8FEF 22 Monitor program location for
address field display
8817 EF
8818 8F
8819 CALL UPDAD CD
881A 40
881B 04
Display routine for address field
881C HLT 76 Halt
13. Program to perform multiplication of two 16-bit binary number.
Address Label Mnemonics Operand Hexcode Comment
8800 LHLD 8900 2A [L] [8900]
H
8801 00 [H] [8901]
H
8802 89
8803 XCHG EB [L] [E]
8804 LHLD 8902 2A [H] [D]
8805 02 [L] [8902]
H
8806 89 [H] [8903]
H
8807 DCX H 2B [HL] [HL]-1
8808 LOOP1 DCX H 2B [HL] [HL]-1
8809 MOV A,E 7B [A] [E]
880A ADD E 83 [A] [A]+[E]
880B MOV E,A 5F [E] [A]
880C MOV A,D 7A [A] [D]
880D ADC D 8A [A] [A]+[D]+[CY]
880E MOV D,A 57 [D] [A]
880F MOV A,H 7C [A] [H]
8810 ORA L B5 [A] [A] OR [L]
8811 JNZ LOOP1 C2 If [z]=0: go to location [8808]
8812 08 If [z]=1: go to location [8814]
8813 88
8814 MOV A,D 7A [A] [D]
8815 STA 8FF0 32
8816 F0
8817 8F
8818 MOV A,E 7B
8819 STA 8FEF 32
881A EF
881B 8F
881C CALL UPDAD CD
881D 40
Address field display routine
881E 04
881F HLT 76 Halt
14. Program to perform division of two 8-bit binary numbers.
8800 LXI H, 8900 21 [M] [HL] [8900]
8801 00
8802 89
8803 MOV A, M 7E [A] [M]
8804 INX H 23 [HL] [HL]+1
8805 MOV C, M 4E [C] [M]
8806 MVI B, 00 06 [B] 00
8807 00
8808 LOOP2 SUB C 91 [A] [A][C]
8809 JC LOOP1 DA If [CY] = 1: go to location [8810]
880A 10 If [CY] = 0: go to location [8800]
880B 88
880C INR B 04 [B] [B]+1
880D JMP LOOP2 C3 Go to location (8808)
H
880E 08
880F 88
8810 LOOP1 MOV A, B 78 [A] [B]
8811 STA 8902 32 [8902] [A]
8812 02
8813 89
8814 HLT 76 Halt
15. Program to find number of 1s and 0s in a given 8 bit binary number.
8800 MVI B, 00
H
06 [B] [00]
H
: storing 1s
8801 00
8802 MVI C, 00
H
0E [C] [00]
H
: Storing 0's
8803 00
8804 MVI D, 08
H
16 [D] [08]: Bit
8805 [08]
H
8806 MVI A, XX
H
3E
8807 XX
H
[A] X
H
: X
H
is the number to be
evaluated
8808 LOOP3 RAR 1F Rotate right through carry
8809 JNC LOOP1 D2 If [CY]=0: go to location [8810]
880A 10 If [CY]=1: go to location [880C]
880B 88
880C INR B 04 [B] [B]+1
880D JMP LOOP2 C3 Go to location [8811]
H
880E 11
880F 88
8810 LOOP1 INR C 0C [C] [C]+1
8811 LOOP2 DCR D 15 [D] [D]1
8812 JNZ LOOP3 C2 If [Z]=0: go to location [8808]
8813 08 If [Z]=1: go to location [8815]
8814 88
8815 MOV A, B 78 [A] [B]
8816 STA 8850 32 [8850]
H
[A]:1s total
8817 50
8818 88
8819 MOV A, C 79 [A] [C]
881A STA 8851 32 [8851]
H
[A]: 0s total
881B 51
881C 88
881D HLT 76 Halt
16. Program to find the smallest to N 8-bit binary number
8800 LXI H,8900 21 [M] [HL] [8900]
H
8801 00
8802 89
8803 MOV B, M 46 [B] [M] Count in B-register
8804 DCR B 05 [B] [B]1
8805 INX H 23 [8901] [HL] [HL]+1
8806 MOV A, M 7E [A] [M] First data in Act
8807 LOOP2 INX H 23 [8902] [HL] [HL]+1
8808 CMP M BE Compare [M] with [A]
8809 JC LOOP1 DA If [CY]=1: go to location [880D]
H
880A 0D If [CY]=0: go to location [880C]
H
880B 88
880C MOV A,M 7E [A] [M]
880D LOOP1 DCR B 05 [B] [B]1
880E JNZ LOOP2 C2 If [Z]=0: go to location [8807]
H
880F 0 7 If [Z]=1: go to location [8811]
H
8810 88
8811 STA 8FF1 32
8812 F1
8813 8F
Monitor program location for data
field display
8814 CALL 044C CD
8815 4C
8816 04
8817 HLT 76 Halt
Note: Largest number in a N 8-bit binary numbers can be obtained by replacing JC to JNC.
17. Program to obtain the descending order of N 8-bit binary numbers.
8800 LXI H, 8900 21 [M] [HL] [8900]
8801 00
8802 89
8803 MOV B, M 46 [B] [M]:Counter to count 8-bit
8804 DCR B 05 [B] [B]-1
8805 INX H 23` [8901] [HL] [HL]+1
8806 MOV A, M 7E [A] [M]
8807 LOOP2 INX H 23 [8902] [HL] [HL]+1
8808 CMP M BE Compare [HL] with [A]
8809 JC LOOP1 DA If [CY]=1: go to location [880D]
880A OD If [CY]=0: go to location [880C]
880B 88
880C MOV A, M 7E [A] [M]
880D LOOP1 DCR B 05 [B] [B]-1
880E JNZ LOOP2 C2 If [Z]=0: go to location [8807]
880F 07 If [Z]=1: go to location [8812]
8810 88
8811 STA 8FF1 C2
8812 F1
8813 8F
8814 CALL 004C CD
8815 4C
8816 04
Monitor program location for data
field display
8817 HLT 76 Halt
To covert the above program for ascending order, replace JC by JNC .
18. Program to convert 8-bit binary number to gray code
Address Label Mnemonics Operand Hex Code Comment
8800 MVI A, [X]
H
3E A X
H
: Value to be converted
8801 X
H
8802 MOV B, A 47 [B] [A]
8803 RAR 1F Rotate right the Accumulator
8804 XRA B A8 [A] [A]"XRA"[B]
8805 STA 8FF1 32 Display routine
8806 F1
8807 8F
8808 CALL 044C CD
8809 4C
880A 04
880B HLT 76 Halt
19. Program to convert gray code to 8-bit binary number
8800 MVI A, X
H
3E [A] X
H
: value to be converted
8801 X
H
8802 MVI C, [07]
H
0E [C] 07
H
8803 07
H
8804 LOOP1 MOV B, A 47 [B] [A]
8805 RAR 1F Rotate right the Accumulator
8806 XRA B A8 [A] [A] "XOR" [B]
8807 DCR C 0D [C] [C]1
8808 JNZ LOOP1 C2 If [Z] = 0 : go to location [8804]
8809 04 If [Z] = 1 : go to location [880A]
880A 88
880B STA 8FF1 32 Display routine
880C F1
880D 8F
880E CALL 044C CD
880F 4C
8810 04
8811 76 Halt
20. Program to convert ASCII hex number into its binary equivalent
8800 LDA 8900 3A [A] [8900]
H
8801 00
8802 89
8803 CPI 40 FE Compare [40]
H
with [A]
8804 40
8806 13 If [CY] = 0: go to location [8808]
8807 88
8808 SUI 40 D6 [A] [A] [40]
H
8809 40
880A ADI 09 C6 [A] [A] + 09
H
880B 09
880C LOOP2 STA 8FF1 32
880D F1
Monitor program for data field
display
880E 8F
880F CALL 044C CD
8810 4C
8811 04
8812 HLT 76
8813 LOOP1 SUI 30 D6 [A] [A][30]
H
8814 30
8815 JMP LOOP2 C3 Go to location [880C]
H
8816 0C
8817 88
ASCII codes 30 to 39 represents 0 to 9 in binary and 41 to 46 represent A to F.
If the ASCII code is less than 40, then 30 is subtracted to get the binary equivalent.
If the ASCII code is greater than 40, then the equivalent number lies between A and F.
21. Program to convert binary number into its ASCII equivalent.
8800 LDA 8900 3A [A] [8900]
8801 00
8802 89
8803 MOV B, A 47 [B] [A]
8804 CALL ASCII CD Call subroutine "ASCII"
8805 16
8806 88
8807 STA 8901 32 [8901] [A]
8808 01
8809 89
880A MOV A, B 78 [A] [B]
880B RRC 0F
Rotate the content of Accumulator
right through carry
880C RRC 0F
880D RRC 0F
880E RRC 0F
880F CALL ASCII CD Call subroutine "ASCII"
8810 16
8811 88
8812 STA 8902 32 [8902] [A]
8813 02
8814 89
8815 HLT 76
8816 ASCII ANI [0F]
H
E6 "AND"[0F]
H
with [A]
8817 0F
8818 CPI [0A]
H
FE Compare [0A]
H
with [A]
8819 0A
881A JC LOOP1 DA If [CY] = 1: go to location [881F]
H
881B 1F If [CY] = 0: go to location [881D]
H
881C 88
881D ADI [07]
H
C6 [A] [A]+[07]
H
881E 07
881F LOOP1 ADI 30
H
C6 [A] [A]+[30]
H
8820 30
8821 RET C9 Return to subroutine called place
For binary numbers from 0 to 9, the ASCII code is 30 to 39 and for A to F, the ASCII code is 41 to 46.
If the numbers are between 0 to 9, 30 must be added to the ASCII code.
If the numbers are between A to F, 37 must be added.
22. Program to convert 2 digit BCD to its binary equivalent.
8800 LDA 8900 3A
8801 00
[A] [8900
]H
BCD number
in 8900
8802 89
8803 MOV B, A 47 [B] [A]
8804 ANI 0F
H
E6 "AND" [0F]
H
with [A]
8805 0F
8806 MOV C, A 4F [C] [A]
8807 MOV A, B 18 [A] [B]
8808 ANI 0F E6 "AND" [F0]
H
with [A]
8809 F0
880A RRC 0F Rotate right without carry
880B RRC 0F
880C RRC 0F
880D RRC 0F
880E MOV B, A 47 [B] [A]
880F MVI D, 0A 16 [D] [0A]
H
8810 0A Set a counter for multiply
8811 XRA A AF A AA+AA [XOR]
8812 LOOP1 ADD B 80 [A] [A]+[B]
8813 DCR D 15 [D] [D]1
8814 JNZ LOOP1 C2 If [Z] = 0: go to location [8812]
8815 12 If [Z] = 1: go to location [8817]
H
8816 88
8817 ADD C 81 [A] [A]+[C]
8818 STA 8FF1 32 Display the binary equivalent
8819 F1
881A 8F
881B CALL 044C CD
881C 4C
881D 04
881E HLT 76 Halt
23. Program to convert binary numbers to its equivalent BCD.
8800 LXI H, 8900 21
8801 00
[M] [HL] [8900]
H
- Binary
number in 8900
8802 89
8803 MOV A, M 7E [A] [M]
8804 MOV D, A 57 [D] [A]
8805 MVI B, 00
H
06 [B] [00]
H
8806 [00]
H
8807 LOOP1 INR B 04 [B] [B]+1
8808 SUI 0A
H
D6 [A] [A][0A]
H
8809 0A
H
880A JNC LOOP1 D2 If [CY] = 0 : go to location [8807]
880B 07 If [CY] = 0 : go to location [880D]
880C 88
880D DCR B 05 B [B]1
880E MOV E, B 58 [E] [B]
880F XRA A AF [A] [A][A][A] [A]
8810 LOOP2 ADI 0A
H
C6
8811 0A
H
8812 DCR E 5F E [E]1
8815 88
8816 MOV E, A 5F E [E]1
8817 MOV A, D 7A [A] [D]
8818 SUB E 93 [A] [A][E]
8819 MOV C, A 4F [C] [A]
881A MOV A, B 78 [A] [B]
881B RLC 07 Rotate left
881C RLC 07
881D RLC 07
881E RLC 07
881F ORA C B1 [A] [C] "OR" [A]
8820 STA 8FF1 32 CURDT location
8821 F1
8822 8F
8823 CALL 044C CD
8824 4C
Display routine UPDDT-Display
the BCD equivalent
8825 04
8826 HLT 76 Halt
24. Program to reverse a string
8800 LDA H, 8900 3A [A] [8900]
H
String in 8900 3A
8801 00
8802 89
8803 MOV B, A 47 [B] [A]
8804 MVI C, 08 0E [C] [08]
H
8805 08
H
8806 MVI D, 00 16 [D] [00]
H
8807 00
8808 LOOP1 MOV A, B 78 [A] [B]
8809 RAL 17 Rotate left without carry
880A MOV B, A 47 [B] [A]
880B MOV A, D 7A [A] [D]
880C RAR 1F Rotate right without carry
880D MOV D, A 57 [D]

[A]
880E DCR C 0D [C] [C]1
880F JNZ LOOP1 C2 If [Z] = 0: go to location [8807]
8811 88
8812 MOV A, D 7A [A] [D]
8813 STA 8FF1 32
8814 F1
8815 8F
8816 CALL 044C CD
8817 4C
Data field display routine
Reversed string displayed
8818 04
8819 HLT 76 Halt
25. (a) Program for generating Fibonacci series (upto (FF)
H
8800 MVI A, N
H
3E N : Number of values
8801 N
H [D] [N]
H
8802 MVI B, 00 06 [B] [00]
H
8803 00
H
8804 MVI C, 01 0E [C] [01]
8805 01
H
8806 LXI H, 8900 21 [M] [HL] [8900]
H
8807 00
8808 89
8809 LOOP1 MOV A, B 78 [A] [B]
880A MOV M, A 77 [8900] [M] [A]
880B ADD C 81 [A] [C]+[A]
880C MOV B, C 41 [B] [C]
880D MOV C, A 4F [C] [A]
880E INX H 23 [HL]

[HL]+1
880F DCR D 15 [D] [D]1
8810 JNZ LOOP1 C2
8813 HLT 76 Halt
(b) Program to generate Fibonacci series {maximum [FFFF]
H
}
8800 LXI H, 8900 21 [M] [HL] [8900]
8801 00
8802 89
8803 MOV A, M 7E [A] [M]
8804 INX H 23 [HL] [HL]+1
8805 MOV C, M 4E [C] [M]
8806 MVI B, [00]
H
06 B [00]
H
8807 00 [L] [A]
8808 MOV L, A 6F [H] [00]
8809 MVI H, [00]
H
26
880A 00
880B LOOP2 DAD D 19 [HL]
H
[DE]
H
+[HL]
H
880C MOV A, H 7C [A] [H]
880D CPI [FF]
H
FE Compare [FF]
H
with [A]
880E [FF]
H
880F JC LOOP1 DA If [CY] = 1: go to location [8819]
8811 88
8812 MOV A, L 7D [A] [L]
8813 CPI [FF]
H
FE Compare [FF]
H
with [A]
8814 FF
8817 88
8818 HLT 76
8819 LOOP1 SHLD 8FEF 22
881A EF
881B 8F
881C PUSH H E5
881D PUSH D D5
881E CALL 0440 CD Delay monitor subroutine
881F 40
8820 04
8821 CALL DELAY CD Delay subroutine to be stored in
[882A]
H
Location
8822 2A
8823 88
8824 POP D D1
8825 POP H E1
8826 XCHG EB [H] [D]
8827 JMP LOOP2 C3 [L] [E]
8828 0B Go to location [880B]
8829 88
26. Program to solve the given Boolean expression
Z Y X Z Y X Z Y X F + + =
880D MOV E, A 5F
880E MOV A, H 7C [Y] [C] [A]
880F CMA 2F
8810 MOV L, A 6F [Z] [L] [A]
8811 ANA E A3 YZ [A] [A]"AND"[E]
8812 ANA B A0 XYZ [A] [B]"AND"[A]
8813 STA 8903 32
8814 03
8815 89
8816 MOV A, L 70
8817 ANA D A2
8818 ANA C A1
8819 STA 8904 32
881A 04
881B 89
881C MOV H, M 66
881D ANA E A3
881E ANA D A2
881F STA 8905 32
8820 05
8821 89
8822 LXI H, 8903 21
8823 03
8824 89
8825 MOV A, M 7E
8826 INX H 23
8827 ORA M B6
8828 INX H 23
8829 ORA M B6
882A STA 8FF1 32
882B F1
882C 8F
882D CALL 044C CD
882E 4C
882F 04
8830 HLT 76 Halt
27. Program to find the factorial of a number.
8800 MVI A, X
H
3E
8801 X
H
[XX]
H
: Number whose factorial has
to be found [A] X
H
8802 MVI B, [XX-2]
H
06 [B] [XX2]
H
8803 [XX2]
H
8804 LOOP2 MOV C, B 48 [C] [B]
8805 MOV D, A 57 [D] [A]
8806 LOOP1 ADD D 82 [A] [D]+[A]
8807 DCR C OD [C] [C][1]
H
8809 06 If [Z] = 1: go to location [880B]
880A 88
880B DCR B 05 [B] [B]1
880C JNZ LOOP2 C2 If [Z] = 0: go to location [8804]
H
880D 04 If [Z] = 1: go to location [880F]
H
880E 88
880F STA 8FF1 32
8810 F1
8811 8F
8812 CALL 044C CD
8813 4C
Data field display monitor routine
8814 04
8815 HLT 76
28. Program to find the square root of a number.
8800 MVI C, 01
H
0E [C] [01]
H
8801 01
8802 LXI H, 8900 21
8803 00
[M] [HL] [8900]-Number
in 8900
H
8804 89
8805 LOOP2 MOV A, M 7E [A] [M]
8806 CALL ROOT CD CALL subroutine "ROOT"
8807 50
8808 88
8809 CMP C B9 Compare '[C]' with 'A'
880A JZ LOOP1 CA If [Z] = 0: go to location [8811]
H
880B 11 If [Z] = 1: go to location [880D]
H
880C 88
880D INR C 0C [C] [C]+1
880E JMP LOOP2 C3 Go to location [8805]
H
880F 05
8810 88
8811 LOOP1 STA 8FF1 32
8812 F1
8813 8F
8814 CALL 044C CA
8815 4C
Data field display monitor routine
8816 04
8817 HLT 76 Halt
8850 ROOT MVI B, 00
H
06 [B] [00]
H
8851 00
8852 LOOP3 SUB C 91 [C] [C]1
8853 INR B 04 [B] [B]+1
8854 CMP C B9 Compare [C] with [A]
8855 JNC LOOP3 D2 If [CY] = 0 : go to location [8852]
H
H
8857 88
8858 MOV A, B 78 [A] [B]
8859 RET C9 Return to "ROOT'
29. Program to find the square of a number
8800 MVI C, 01 0E [C] [01]
H
8801 [01]
H
8802 MOV B, C 41 [B] [C]
8803 MVI A, X
H
3E [A] [XX]
H
8804 X
H
8805 LOOP3 SUB B 90 [A] [A][B]
8806 JZ LOOP1 CA If [Z] = 0: go to location [8809]
H
H
8808 88
8809 JC LOOP2 DA If [CY] = 0 : go to location [880C]
H
880A 16 If [Z] = 0: go to location [8816]
H
880B 88
880C INR C 0C [C] [C]+1
880D INR B 04 [B] [B]+1
880E INR B 04 [B] [B]+1
880F JMP LOOP3 C3 Go to location [8805]
H
8810 05
8811 88
8812 LOOP1 MOV A, C 19 [A] [C]
8813 STA 8900 32 [8900] [A]
8814 00
8815 89
8816 LOOP2 HLT 76 Halt
30. Program to find the square of a number
8800 MVI C, 01 0E [C] [0]
H
8801 [01]
H
8802 LDA 8900 3A [A] [8900]
H
: Data location
8803 00
8804 89
8805 MOV B, A 47 [B] [A]
8806 MOV D, A 57 [D] [A]
8807 MVI A, 00
H
3E [A] [00]
H
8808 00
H
8809 LOOP2 ADD B 80 [A] [A]+[B]
880A JNZ LOOP1 C2 If [Z] = 0: go to location [880E]
H
880B 0E If [Z] = 1: go to location [880D]
H
880C 88
880D INR C 0C [C] [C]+1
880E LOOP1 DCR D 15 [D] [D]1
880F JNZ LOOP2 C2 If [Z] = 0: go to location [8809]
H
H
8811 88
8812 STA 8901 32 [8901]
H
[A]: result location
8813 01
8814 89
8815 MOV A, C 79 [A] [C] : Carry content
8816 STA 8902 32 [8902] [A]
8817 02
8818 89
8819 HLT 76 Halt
31. Program to find cube root of a number
8800 LXI H, 8900 21 [H] [HL] [8900]
8801 00
8802 89
8803 MVI B, 01 06 [B] [01]
H
8804 01
8805 LOOP2 CALL CUBE CD Call subroutine "CUBE"
8806 50
8807 88
8808 CMP M BE [A] Compare '[M]' with [A]
8809 JZ LOOP1 CA If [Z] = 1: go to location [8810]
880A 10
880B 88 If [Z] = 0: go to location [880C]
880C INR B 34 [B] [B]+1
880D JMP LOOP2 C3 Go to location [8805]
880E 05
880F 88
8810 LOOP1 MOV A, B 78 [A] [B]
8811 STA 8FF1 32
8812 F1
8813 8F
8814 CALL 044C CD
8815 4C
Display routine
8816 04
8817 HLT 76 Halt
8850 CUBE MOV C, B 48 [C] [B]
H
8851 MVI A, [00]
H
3E [A] [00]
H
8852 00
8853 MOV D, C 51 [D] [C]
8854 ADD C 81 [A] [A]+[C]
8855 DCR D 15 [D] [D]-1
8856 JNZ LOOP1 C2 If [Z] = 0 : go to location [8810]
8857 10
8858 88 [Z] = 1: go to location [8859]
8859 MOV D, A 57 [D] [A]
885A MVI A, 00 3E [A] [00]
H
885B 00
885C ADD D 82 [A] [D] + [A]
885D DCR C 0D [C] [C] [1]
885E JNZ LOOP2 C2 If [Z] = 0; go to [8805]
885F 05 If [Z] = 1; go to [8861]
8860 88
8861 RET C9
32. Program to decimal count from 00 to 99 (using DAA)
8800 LOOP2 XRA A AF [A] [00]
8801 LOOP1 STA 8FF1 32 [8FFI] [A]
8802 F1
8803 8F
8804 PUSH PSW F5 [A] to stock location
8805 CALL 044C CD
8806 4C
8807 04
8808 CALL SUB CD CALL delay routine from (8850)
H
8809 50
880A 88
880B POP PSW F1 [A] stock location
880C ADI 01
H
C6 [A] [A]+1
880D 01
H
880E DAA 27 Decimal Accumulator adjust
880F CPI 9A
H
FE Compare [A] with 99
8810 [9A]
H
8811 JC LOOP1 DA If [CY] = 1 go to location [8801]
H
8812 01 If [CY] = 0 go to location [8814]
H
8813 88
8814 JMP LOOP2 C3 go to location [8800]
H
8815 00
8816 88
8850 SUB LXI D, [FFF]
H
11
8851 [FF]
H
8852 [FF]
H
8853 LOOP3 DCX D 1B
8854 MOV A, D 7A
8855 ORA E B3
8856 JNZ LOOP3 C2
8857 53
Delay routine for a delay of [FFFF]
H
8858 88
8859 RET C9
33. Port address:
CS Hex Address Port
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
0 1 0 0 0 0 0
0
1
1
0
1
0
1
40
41
42
43
A
B
C
Control word register
HARDWARE EXPERIMENTS
Waveform Generation using DAC
Block Diagram
1. Square wave generation
8800 MVI A, [80]
H
3E, [80]
H
Control register control
word
8802 OUT [43]
H
D3, [43]
H
8804 LOOP1 MVI A, [00]
H
3E, [00]
H
[A] [00]
H
8806 OUT [40]
H
D3, [40]
H
Port A : output
8808 CALL DELAY [8850] CD, 50, 88 Call delay
880B MVI A, [FF]
H
3E, [FF]
H
[A] [FF]
H
880D OUT [40]
H
D3, [40]
H
Port A : output
880F CALL DELAY [8850] CD, 50, 88 Call delay
8812 JMP LOOP1 C3, 06, 88
2. Delay program
8850 DELAY PUSH PSW F5 Store the [A] stock register
8851 LXI D, [FFFF]
H
11 [DE] [FFFF]
H
8852 [FF]
H
8853 [FF]
H
8854 LOOP2 DCX D IB [DE] [DE]1
8855 MOV A, D 7A [A] [D]
8856 ORA E B3 [A] [A] OR [E]
H
8858 54 If [Z] = 1: go to location [885A]
H
8859 88
885A POP PSW F1 Remove the [A]& [F] stock register
885B RET C9 Return to main program
3. Triangular wave generation

8800 MVI A, [80]
H
3E
8801 [80]
H
Control word in control word
register
8802 OUT [43]
H
D3
8803 [43]
H
8804 MVI A, [00]
H
3E [A] [00]
H
8805 [00]
H
8806 LOOP1 OUT [40]
H
D3 Port A: Output
8807 [40]
H
8808 INR A 3C [A] [A]+1
8809 CPI [FF]
H
FE [A] Compare [A] with [FF]
H
880A [FF]
H
880B JNZ LOOP1 C2 If [Z] = 0 : go to location [8805]
H
880C 06 If [Z] = 1 : go to location [880E]
H
880D 88
880E LOOP2 OUT [40]
H
D3
880F [40]
H
8810 DCR A 3D [A] [A]1
8811 CPI [00]
H
FE
8812 [00]
H
8813 JNZ LOOP2 C2 If [Z] = 0: go to location [880E]
H
8814 OE If [Z] = 1: go to location [8816]
H
8815 88
8816 JMP LOOP1 C3
8817 06
8818 88
4. Sawtooth waveform generation
8800 MVI A, [80]
H
3E, [80]
H
8802 OUT [43]
H
D3, [43]
H
Control word : control word register
8804 LOOP2 MVI A, [00]
H
3E, [00]
H [A] [00]
8806 LOOP1 OUT [40]
H
3E, [40]
H
Port A : output
8808 INR A 3C [A] [A]+1
8809 CPI [FF]
H
FE, [FF]
H [A] compare [A] with [FF]
H
880B JNZ LOOP1 C2, 06, 88 If [Z] = 0 : go to location [8806]
H
880E OUT [40]
H
D3, [40]
H
If [Z] = 1 : go to location [880E]
H
8810 JMP LOOP2 C3, 04, 88
5. Staircase wave generation
8800 MVI A, [80]
H
3E, 80]
H
8802 OUT [43]
H
D3, [43]
H
Control word
8804 LOOP3 MVI A, [55]
H
3E, [55]
H [A] [55]
H
8806 LOOP1 OUT [40]
H
D3, [40]
H
Port A : output
8808 CALL DELAY
[8850]
CD, 50, 88 Call delay subroutine
880B ADI [55]
H
C6, [55]
H [A] [A]+[55]
H
880D JNC LOOP1 D2, O6, 88 [CY]=0: go to location [8806]
H
[CY]=1: go to location [8810]
H
8810 MVI A,[FF]
H
3E, FF [A] [FF]
H
8812 LOOP2 SUI [55]
H
D6, [55] [A]
H
[A][55]
H
8814 OUT [40]
H
D3, [40]
H
Port A : output
8816 CALL DELAY CD, 50, 88 Call delay subroutine
8819 CPI [00]
H
FE, [00]
H [A] compare[A] with [00]
H
881B JNZ LOOP2 C2, 12, 88 [Z] = 0: go to location [8812]
H
[Z] = 1: go to location [881E]
H
881E JMP LOOP3 C3, 04, 88 Go to location [8804]
H
6. Trapezoidal waveform generation
8800 MVI A, [80]
H
3E, [80]
H
8802 OUT [43]
H
D3, [43]
H
Control word
8804 MVI A, [00]
H
3E, [00]
H [A] [00]
8806 LOOP1 OUT [40]
H
D3, [40]
H
Port A : output
8808 INR A 3C [A] [A]1
8809 CPI [FF]
H
FE, [FF]
H [A] Compare [A] with [FF]
H
880B JNZ LOOP1 C2, 06, 88 [Z] = 0: go to location [8806]
H
[Z] = 1: go to location [880E]
H
880E CALL DELAY CD, 50, 88 Call delay subroutine
8811 LOOP2 DCR A 3D [A] [A]1
8812 OUT [40]
H
D3, [40]
H
Port A: output
8814 CPI [00]
H
FE, [00]
H [A] Compare [A] with [00]
H
8816 JNZ LOOP2 C2, 11, 88 [Z] = 0: go to location [8811]
H
[Z] = 1: go to location [8820]
H
8819 CALL DELAY CD, 50, 88 Call delay subroutine
882C JMP LOOP1 C3, 06, 88 Go to location [8806]
H
7. Sinewave generation
8800 MVI A, [80]
H
3E, [80]
H
8802 OUT [43]
H
D3, [43]
H
Control word
8804 LOOP2 MVI C, [48]
H
0E, [48]
H [C] [48]
8806 LXI H, 8900 21, 00, 89 [M] [HL] [8900]
H
8809 LOOP1 MOV A, M 7E [A] [M]
880A OUT [40]
H
D3, [40]
H
Port A : output
880C INX H 23 [HL] [HL]+1
880D DCR C 0D [C] [C]1
880E JNZ LOOP1 C2, 09, 88 [Z] = 0: go to location [8809]
H
[Z] = 1: go to location [8811]
H
8811 JMP LOOP2 C3, 04, 88 Go to location [8804]
H
2
[FF]
] sin [1 : data code Hex
H
+

(degree)
sin Address
0 0 [75]
H
8900
5 0.087 [8A]
H
8901
10
.
.
.
360
Matrix Type Keyboard Interface
Block Diagram
Address Label Mnemonics Operand Hexcode Comment
8800 MVI A, [92]
H
3E, [92]
H
8802 OUT [43]
H
D3, [43]
H
Control word
8804 BACK CALL KEY CD, 11, 88 Call "KEY" subroutine
8807 MOV A, C 79 [A][C]
8808 STA 8FF1 32, F1, 8F
880B CALL UPDDT C2, 4C, 04 Data field display routine
880E JMP BACK C4, 04, 88
8811 KEY MVI D, [02]
H
16, [02]
H [D] [02]
H
8813 MVI C, [10]
H
0E, [10]
H [C] [10]
H
8815 MVI B, [04]
H
06, [04]
H [B] [04]
H
8817 REPT MOV A, B 78 [A] [B]
8818 OUT [42]
H
D3, [42]
H
Output
881A RRC OF Rotate right the [A] by a bit
881B MOV B,A 47 [B] [A]
881C IN [40]
H
DB, [40]
H
Input [A]
881E CPI [00]
H
FE, [00]
H [A] Compare [00]
H
with [A]
8820 JNZ NXT
KEY
C2, 31, 88 If [Z] = 0: go to location [8831]
If [Z] = 1: go to location [8820]
8823 MOV A, C 79 [A] [C]
8824 SUI [08]
H
D6, [08]
H
[A] [A][08]
H
2
[FF]
sin] [1 : code Hex
H
+
8826 MOV C, A 4F [C] [A]
8827 DCR D 15 [D] [D]1
8828 MOV A, D 7A [A] [D]
8829 CPI [FF]
H
FE, [FF]
H [A] Compare [A] with [FF]
H
882B JNZ REPT C2, 17, 88 If [Z] = 0: go to location [8817]
[Z] =1: go to location
882E JMP KEY C2, 11, 88 Go to location on [8811]
8831 NXT KEY RRC 0F Rotation right [A] by a bit
8832 RC D8
8833 PUSH PSW F5 Stock register [A]
8834 MOV A, C 79 [A] [C]
8835 ADI [01]
H
C6, [01]
H [A] [A]+[01]
H
8837 MOV C, A 4F [C] [A]
8838 POP PSW FI [A] Stock register
8839 JMP NXT KEY C3, 31, 88 Go to location [8831]
Control of Stepper Motor
Block Diagram
8800 MVI A, [80]
H
3E, [80]
H
8802 OUT [43]
H
D3, [43]
H
Control word
8804 MVI A, [88]
H
3E, [88]
H [A] [88]
H
8806 BACK OUT [40]
H
D3, [40]
H Port A output
8808 CALL Delay C0, 50, 88 Call delay routine
880B RRC OF rotate the [A] right
880C JMP BACK C3, 06, 88 go to location 8806
8800 DELAY PUSH PSW F5 Stock register [A]
8851 LXI H, [0001] 21, 01, 00 [HL] [0001]
H
8854 LOOP2 LXI D, FFFF 11, FF, FF [DE] [FFFF]
H
8857 LOOP1 DCX D IB [DE] [DE] 1
8858 MOV A, D 7A [A] [D]
8859 ORA E B3 [A] [A] OR [E]
885A JNZ LOOP1 C2, 57, 88 If [Z] = 0 : go to location 8857
885D DCX H 2B If [Z] = 1 : go to location 8850
885E MOV A, H 7C [HC] [HL] 1
885F ORA L B5 [A] [A] OR [L]
8860 JNZ LOOP2 C2, 54, 88 If [Z] = 0 : go to location [8854]
If [Z] = 1 : go to location [8864]
8863 POP PSW F1 [A] stock register
8864 RET C9 Return
Note: To change the direction of stepper motor rotation, change the Mnemonic RRC (OF) to RLC (07).

Combined

Transféré par

Informations du document

Description originale:

Copyright

Formats disponibles

Partager ce document

Partager ou intégrer le document

Options de partage

Avez-vous trouvé ce document utile ?

Ce contenu est-il inapproprié ?

Droits d'auteur :

Formats disponibles

Combined

Transféré par

Droits d'auteur :

Formats disponibles

Contents i

Prefix Symbol Multiplier

AC voltage source (pulsating)

where k = constant of proportionality =

1.30 Handbook of Experiments in Electronics and Communication Engineering

Bandwidth and Selectivity

Basic Network 1.35

For T < , then R >

Basic Network 1.51

as 0.002 or any small value)

Output coupling capacitor is given by

By-pass capacitor is given by,

Amplifier Circuit Design 3.5

Amplifier Circuit Design 3.7

The output coupling capacitor can be obtained from

The by-pass capacitor can be obtained from

Similar calculation can be incorporated to find the value of C

By-pass capacitor is given by, X

Output coupling capacitor is given by

By-pass capacitor is given by

circuit. the of impedance input

Power gain is given by, ?

Chose 10 k in series with a 10 k

Both are dual of each other.

Vous aimerez peut-être aussi