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System CoreWare ARM926EJ-S Processor System

OVERVIEW
The ARM926EJ-S Processor System from LSI Logic is an OS-ready processor system that is available for both RapidChip Platform ASIC and standard-cell ASIC designs. The processor system significantly reduces design time, complexity and risk for customers in the communications, consumer and storage markets. This offering also provides the core IP for designers in markets such as security, medical, consumer electronics, industrial, defense, instrumentation and imaging with the ability to get their products manufactured quickly and at low cost.

FEATURES
Based on popular ARM926EJ-S processor core - GflxR Landing Zone hardmac (200 MHz) - FlexCore (up to 230 MHz) - G12P hardmac (200 MHz) - GflxP hardmac (266 MHz) OS-ready processor subsystem Available on RapidChip platform and standard-cell ASIC technologies Available in Gflx 0.11 micron and G12 0.18 micron technologies Extendable via AHB Expansion busses Expert Field CoreWare Engineer (FCE) design support LynuxWorks - BlueCat 4.1 for ARM BSP - LynuxWorks tools support - www.lynuxworks.com Virtio - VPCS926 Virtual Platform - www.virtio.com

The ARM926EJ-S Processor System consists of high-value proven CoreWare IP functions such as the ARM926EJ-S core, Ethernet controller, vectored interrupt controller, UARTs, GPIOs, IIC, and an external bus interface unit. The processor system provides everything needed to run popular operating systems and is easy to use and extend by customers. The expansion AMBA ports allow customers to easily integrate their own value-added logic or additional cores from LSI Logics extensive CoreWare IP library such as the multi-ported DDR SDRAM memory controller. To significantly reduce software development time, the ARM926EJ-S Processor System leverages the broad availability of standard ARM development tools. Additionally, LynuxWorks Inc. provides BlueCat Linux OS and software driver support for the processor system. Virtio Corp. provides a Virtual Platform for fast full-function software emulation of the processor system that customers can extend to include their logic and develop application software even before silicon availability of their custom SoC. By using System CoreWare solutions like the ARM926 Processor System, customers can reduce both development times and design risks, allowing them to focus development resources on their particular end applications, where they add the most value.
Memory Controller AHB

Instruction AHB ARM926EJ-S Data AHB Bridge Slave Exp. AHB

Figure 1. ARM926EJ-S Processor System

Master Exp. AHB

APB Bridge Vec Int Ctlr


EBIU

10/100 Ethernet MAC

APB

2x UART

Timers

GPIO

2x I2C

System CoreWare ARM926EJ-S Processor System

FUNCTIONALITY
Architecture High performance ARM926EJ-S processor core 32-bit data bus expansion port for additional external AHB master - 133 MHz in Gflx and 100 MHz in G12 Two 32-bit memory controller expansion ports 32-bit AHB Synchronous Segmentation Bridge for external AHB slaves - Same or divided down bus frequency External 32-bit SRAM/Flash/ROM memory controller - Programmable read wait state - Programmable write wait state APB peripheral set including UART, GPIO, Timers, and an I2C controller Vectored Interrupt Controller - Up to 32 interrupt sources - 8 priority levels per interrupt - Read-in register containing ISR vector or index to vector 10/100 Mbit/s Ethernet MAC with DMA controller - RMON1757 compliant statistics counters - Broadcast and multicast filtering - Automatic bad packet filtering

For more information please call:

LSI Logic Corporation


North American Headquarters Milpitas, CA Tel: 866-574-5741

North America
Milpitas, CA Tel: 1-408-490-8000 Fax: 1-408-490-8590 Quebec, Canada Tel: 1-514-426-5011 Fax: 1-514-426-7119

Europe
European Headquarters United Kingdom Tel: 44-1344-413200 Fax: 44-1293-651119

Hong Kong
Kowloon Tong, Hong Kong Tel: 852-2192-1789 Fax: 852-2511-6939

LSI Logics extensive library of CoreWare and System CoreWare IP offers proven, easy to integrate, performance-leading cores and system solutions, including GigaBlaze and HyperPHY high-speed standards-compliant SerDes, ARM and MIPS processors and associated systems, licensable ZSP DSP cores, processor peripherals and AMBA on-chip-bus structures, USB cores, Memory PHYs and Controllers, Ethernet MAC and PHY cores, PCI Express, XGXS, SPI4.2 and other protocol layer IP.
DDR CoreWare

China
Beijing, China Tele: 86-10-626-38296 Fax: 86-10-626-38322 Chengdu, China Tel: 86-28-667-8831 Fax: 86-28-667-8054

Japan
Tokyo, Japan Tel: 81-3-5463-7821 Fax: 81-3-5463-7820

RapidChipTM Platform ASIC or Standard-cell ASIC SoC Design


DDR Controller

Korea
Seoul, Korea Tele: 82-2-528-3400 Fax: 82-2-528-2250
LSI Logic, the LSI Logic logo, Gflx, ZSP, HyperPHY, GigaBlaze, RapidChip, G12 and CoreWare are trademarks or registered trademarks of LSI Logic Corporation. ARM is a registered trademark of ARM Limited. ARM926EJ-S, AMBA, and Jazelle are trademarks of ARM Limited. Java is a trademark of Sun Microsystems, Inc. All other brand and product names may be trademarks of their respective companies. LSI Logic Corporation reserves the right to make changes to any products and services herein at any time without notice. LSI Logic does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by LSI Logic; nor does the purchase, lease, or use of a product or service from LSI Logic convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of LSI Logic or of third parties. Copyright 2004 by LSI Logic Corporation. All rights reserved. Order No. P20031 0304.DH.Web - Printed in USA

System CoreWare

ARM926EJ-S Processor System AHB Slave Bus Multi-Core Communication Module UART I2C MII

Customer Value-added Logic

Interrupts Flash

Figure 2. Typical System Application