Académique Documents
Professionnel Documents
Culture Documents
CS623
CS623
Rise Time (tr), the time required for a signal to transition from 10% of its maximum value to 90% of its maximum value. Fall Time (tf), the time required for a signal to transition from 90% of its maximum value to 10% of its maximum value. Propagation Delay (tpLH, tpHL), the delay measured from the time the input is at 50% of its full swing value to the time the output reaches its 50% value.
1 April 2007 1 April 2007
0 tr tf
time
CS623
CS623
Using gates with finite propagation delays, tpLH and tpHL instead of zero gate delays used in functional analysis.
Gate tpLH tpHL INV 3 ns 2 ns XOR 5 ns 4 ns
t p = 2 + 4 = 6 ns
3 gd
3 gd 2 gd
6 gd
t p = max {( 2 + 5 ) , ( 3 + 5 ) , ( 3 )} = 8 gd
5 gd 3 gd
1 April 2007
1 April 2007
t p = max {( 2 + 5 ) , ( 3 + 5 ) , ( 3 ) , ( 6 + 3 )} = 9 gd
CS623
01 Transition on Vin Vin V1 V2 V3 Vout
t=0 4 2 3 2 5 8 ns
CS623
Setup time, tsu, is the time period prior to the clock becoming active (edge or level) during which the flip-flop inputs must remain stable. Hold time, th, is the time after the clock becomes inactive during which the flip-flop inputs must remain stable. Setup time and hold time define a window of time during which the flip-flop inputs cannot change quiescent interval.
Vin V1 V2 V3
3 2 3 4 5
10 Transition on Vin
1 April 2007
9 ns
7
1 April 2007
Vout
CS623
CS623
Propagation Delay
Propagation delay, tpHL and tpLH , has the same meaning as in combinational circuit beware propagation delays usually will not be equal for all input to output pairs. There can be two propagation delays: tC-Q (clockQ delay) and tD-Q (dataQ delay). For a level or pulse triggered latch:
Data input should remain stable till the clock becomes inactive. Clock should remain active till the input change is propagated to Q output. That is, active period of the clock,
1 April 2007 1 April 2007
10
CS623
CS623
Characterizing Timing
Setup time, hold time Propagation delays
tD-Q
th tsu tC-Q
Q
Q
1 April 2007
tC-Q
11
tC-Q tD-Q
12
CS623
CS623
Clk-Output [ps]
Setup
Hold
Sampling Window
50 0 -200 -150 -100 -50 0 50 100 150 200
1 April 2007
Data-Clk [ps]
13
1 April 2007
14
CS623
CS623
Timing Parameters
Global setup time (Tsu) Global hold time (Th) Maximum clock frequency Clock skew.
These parameters are derived using the circuit (known) delays described below.
tio delay from input of IFL to output of OFL tif delay from circuit inputs of flip-flop inputs tfo delay from flip-flop outputs to circuit outputs tff delay from flip-flop outputs to flip-flop inputs tc-q clock to Q propagation delay of flip-flops tsu setup time of flip-flops
1 April 2007
D (at FF input)
th hold time of flip-flops tc clock delay; time required for clock to reach all flip-flops
15
Similarly, hold time of the circuit inputs relative to the system clock at the source is given by Th = thmax tif min + tcmax
16
CS623
CS623
Clock Frequency
The limiting factor on the clocking rate is the propagation delay through the IFL block:
Clock Frequency
The limiting factor on the clocking rate is the propagation delay through the combinational logic block (input forming logic):
Dj
Qj
Comb. logic
CKj
Di
CKi CLK tff
Qi
1 April 2007
17
1 April 2007
Changes on the Qs must propagate through the IFL before they can affect the next state
Changes on the Qs must propagate through the combinational logic before they can affect the next state
18
CS623
CS623
CKi Qi
tC-Q
Dj
tff
tsu
Comb. logic
CKj
Di
CKi
Qi
tC-Q
Dj
tff
tsu
Tck (=Tclk)
Edge Triggering
CLK
tff
Tck (=Tclk)
Edge Triggering
f clk
1 April 2007
1 Tclk
f clk
20
1 Tclk
CS623
CS623
Timing Violations
Tclk tC Qmax + t f f max + tsumax
The clock period (Tclk) has a lower bound of tff.max . If the clock period is equal to (tff.max + tC-Q.max) then the flip-flop state changes can violate setup times. Remedy :
Clock Skew
The previous discussion assumes that clock signals arrive at all flip-flops simultaneously - this is not a good assumption since it is not true in practice. Because of different wire lengths over which the clock signals travel and the load at the destination, there is a slight difference in clock arrival times at different flip-flop inputs. Clock skew, tskew, is the difference in time between triggering edges seen at different flip-flops. Clock skew affects minimum Tclk.
22
21
CS623
1 April 2007
CS623
Dj
Qj
CKi CKj
tskew
Comb. logic
CKj
Di
CKi
Qi
Qj
Di
Di
Tck (=Tclk)
Tck (=Tclk)
23
24
CS623
CS623
CKi
tskew tC-Q th
tC Q + t ff t skew + th
Comb. logic
CKj
Di
CKi
Qi
tskew CKj
Qi
CLK
tff
tff
Dj
state of Dj before clock becomes active state of Dj after clock becomes active
For a D flip-flop use: tsu = 2ns, th = 15ns and tC-Q = 20ns For a NAND gate use: tp,max = 10ns and tp,min = 3ns
1 April 2007
1 April 2007
25
26
CS623
CS623
tif ,max = 3t p ,max,nand = 30ns tif ,min = 2t p ,min,nand = 6ns t ff ,max = 2t p ,max,nand = 20ns t ff ,min = 2t p ,min,nand = 6ns tc ,max = 2t p ,max,nand = 20ns tc ,min = 2t p ,min,nand = 6ns
Tsu = t su ,max + tif ,max tc ,min = 2 + 30 6 = 26ns Th = th ,max tif ,min + tc ,max = 20 + 15 6 = 29ns Tclk tC Q ,max + t ff ,max + tsu ,max = 20 + 20 + 2 = 42ns f clk ,max = 1/ 42ns = 23.8MHz tskew,max = tC Q ,min + t ff ,min th ,max = 20 + 6 15 = 11ns
1 April 2007 1 April 2007
For a D flip-flop use: tsu = 2ns, th = 15ns, tC-Q = 20ns For a NAND gate use: tp,max = 10ns, tp,min = 3ns
Latch must be open for less than the shortest combinational logic delay but more than the worst setup time.
and
( (t
t w > t sumax or
+ tl min t w thmax
CS623
CS623
tw tsu tw tskew
Comb. logic
CKj
Di
CKi
CKj
tD-Q
Di
CKi
Qi
tskew
Qi
tff th
CLK
tff
Dj
Use narrow-width clock whose pulse width is less than the fastest possible path through the combinational logic.
1 April 2007 1 April 2007
To guarantee correct next state, make sure that the clock period is longer than the worst-case propagation delay through the combinational logic.
29
CS623
Dj
Comb. logic
CKj
Di
CKi
Qi
tskew
Qj
CLK
tff
Di
31