2012 International Conference on Design & Technology of Integrated Systems in Nanoscale Era

ALU Based Address Generation for RAMs

I. Voyiatzis1, C. Efstathiou1, S. Hamdioui2, C. Sgouropoulou1 1 Department of Informatics, TEI of Athens, Greece 2 Delft University of Technology, The Netherlands Abstract
Memory Built-In Self-Test has become a standard industrial practice. Its quality is mainly determined by its fault detection capability in combination with its required area overhead. Address Generators have a significant contribution to the area overhead. Previously published schemes have proposed the address generator implementations based on counter modules. In this work we present an ALU-based address generator implementation; the proposed scheme present lower hardware overhead compared to the previously proposed one, provided the availability of the ALU or the counter in the circuit. Keywords: Memory BIST, Address Generation, ALU-based implementation. capability. Hence, the detection of different memory fault classes requires different address generators [3, 6, 8, 9, 11, 20]. Table 1 highlights two of the most well-established counting methods by giving an example for a memory with N=4 words. The Linear (LI) counting method specifies the address sequence: 0, 1, 2, 3,..., N-1 when going Up ; and N-1,..., 3, 2, 1 , 0 when going Down . The Linear counting method is used for detecting single-cell and coupling faults. The Address Complement (AC) counting method specifies an address sequence: 0000, 1111, 0001, 1110, 0010, 1101, etc. [10]. Each bold address is the ones complement of the previous address, as shown in column denoted AC in Table 1. The AC counting method stresses the address decoders, because all address bits switch upon address transitions. This causes lots of noise, a large power surge, and maximal delay and is used for detecting speed-related faults.
Step 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LI 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 AC 0000 1111 0001 1110 0010 1101 0011 1100 0100 1011 0101 1010 0110 1001 0111 1000

1. Introduction
Built-In Self-Test (BIST) has become a standard industrial practice for testing memories since memory cores constitute a major part of the die area [1, 4, 5, 15, 12]; it is anticipated that by 2014 memories will take up 94% of the die area [16]. In addition, memories are more susceptible to defects, and hence, to faults due to that they are designed with minimal design rule tolerances. In memory BIST, accesses are performed at-speed [2]-[5], [7][9], while the technology (45 nm and beyond) results in speed-related faults [3, 8, 11, 19]. Therefore low-cost, memory BIST schemes should support a variety of algorithms, while allowing for a simple implementation. One of the key components of memory BIST is the address generator (AG). In order to detect speedrelated faults, the address generator has to generate different address sequences to allow for appropriate address transitions. Its complexity is a major design issue since it requires large area and limits the BIST speed. It has been shown that the relative area (in %) occupied by the address generator for the schemes proposed in [4, 15, 12] varies between 26% and 33% of the memory BIST scheme. For memory testing, the address generator has to generate different Counting Methods (CMs) since each counting method has its own detection

Table 1: Linear and Address Complement counting methods In this work we contribute to the field of memory BIST by proposing a novel address generator based on an ALU. ALU modules commonly exist in current circuits; moreover, the outputs of ALU modules drive the address input of RAM modules, as shown in the elementary schematic diagram of the MIPS architecture of Figure1 [13]. Therefore, the utilization of the existing ALUs as address

978-1-4673-1928-7/12/$31.00 2012 IEEE

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2012 International Conference on Design & Technology of Integrated Systems in Nanoscale Era

generators for the testing of RAMs may drive down the hardware overhead.

[14] also proposed the scheme shown in Figure 2(b) which uses the signal M1 to control the multiplexers. The scheme presented in Figure 2(b), apart from the n-stage counter, requires n 4-to-1 multiplexers and one 2-to-1 multiplexer, as well as some logic to control the value of the 2-bit signal M1.

3. Proposed scheme
In this work we propose an ALU based address generator; the proposed scheme assumes an accumulator-like structure, like the one shown in Figure 3(a).

Figure 1: Basic diagram of the MIPS architecture

2. Previous Work
Address generator implementations that can combine linear and address complement counting methods have been proposed in [14]. In [20] the implementation proposed in [14] was integrated into a more generic scheme to generate more counting methods. In Figure 2(a) we present the address complement address generator implementation using a counter proposed in [14]. The U/D signal controls the most-significant address bit O3, which is the least-significant counter bit 0, because O3 of address complement changes with each clock period. The output of bit0 controls the muxes of all bitsx, with x>0. The address generator module shown in Figure 1(a), generates the sequence shown in Table 1 (third column) or its inverse, depending on the value of the signal Up/Down.
R in ALU Add/sub cin en

(a)

Li in ALU Add/sub

en

cin

(a)

(b) Figure 3: The proposed scheme for the generation of the counting methods (a) Address Complement (b) combined Linear and Address Complement We utilize the following signals: (a) the in signal provides the value to be fed to the one input of the ALU. (b) the add/sub decides on the addition/subtraction to be performed by the ALU. (c) the en signal enables the register (R) to capture the ALU output; when en=0, the register does not change value. (d) the cin signal provides the carry input to the ALU. for the case where a combined Linear/Address Complement address generator is required, an additional signal

(b)
Figure 2: 4-bit address generator (a) Address Complement and (b) combined Address Complement and Linear proposed in [14] In order to generalize the generator in order to also generate the linear counting method, the authors of

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(e) Li/Ac enables the multiplexer to select the low-order input of the ALU between the in and the steady 1 signal. For the case of the combined Linear/Address Complement address generator shown in Figure 3(b), when Linear count is required: (a) the Li/Ac signal enables the low order inut of the ALU to be constantly to 1, (b) the in signal is constantly to 0, (c) the en; signal is enabled in every cycle, (d) the cin signal is constantly 0 The add/sub is 0/1 depending on whether up or down linear count is required.
cycle# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 in 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 add/sub (+/-) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 R 0000 0000 0000 0001 0001 0010 0010 0011 0011 0100 0100 0101 0101 0110 0110 0111 en 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 cin 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ALU 0000 1111 0001 1110 0010 1101 0011 1100 0100 1011 0101 1010 0110 1001 0111 1000

address generator is presented in Table 2 and illustrated in Figures 4, 5.

(#0) 0 +

0 0 0 0 en 1

(#1) 1

0 0 0 0 en 0

0 0 0 0

1 1 1 1 en 0

(#2) 0 +

0 0 0 0 en 1

(#3) 1

0001

0 0 0 1

1 1 1 0

(#4) 0 +

0001

en 1

(#5) 1

0 0 1 0 en 0

0 0 1 0

1 1 0 1 en 0

Table 2(a): Address complement counting method generated by the proposed address generatorincreasing order
cycle# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 in 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 add/sub (+/-) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 R 0111 1000 1000 1001 1001 1010 1010 1011 1011 1100 1100 1101 1101 1110 1110 1111 en 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 cin 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ALU 1000 0111 1001 0110 1010 0101 1011 0100 1100 0011 1101 0010 1110 0001 1111 0000

(#6) 0 +

0 0 1 0 en 1

(#7) 1

0011

0 0 1 1
en 1

1 1 0 0
0 1 0 0 en 0

(#8) 0 +

0011

(#9) 1

0 1 0 0

1 0 1 1

(#10) 0 +

0 1 0 0 en 1

(#11) 1

0101

en 0

Table 2(b): Address complement counting method generated by the proposed address generatordecreasing order For the address complement counting method, the signal denoted Li is constantly 0. The operation of the proposed scheme for the case of a 4-stage

0 1 0 1

1 0 1 0

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2012 International Conference on Design & Technology of Integrated Systems in Nanoscale Era

(#8)
en 1

1011

en 1

(#9) 1

1 1 0 0 en 0

0
(#13) 1 0 1 1 0 en 0

(#12) 0 +

0101

1 1 0 0

0 0 1 1

0 1 1 0

1 0 0 1

(#10)
en 1

1 1 0 0 en 1

(#11) 1

1101

en 0

0 + 1

(#14) 0 +

0 1 1 0 en 1

(#15) 1

0111

1 1 0 1

0 0 1 0

0 1 1 1

1 0 0 0 (#12) 0 + 1101

Figure 4: Operation of the proposed scheme for Address Complement generation (increasing sequence)
en 1

en 1

(#13) 1

1 1 1 0 en 0

(#0) 0 +

0111

(#1) 1

1 0 0 0 en 0

1 1 1 0

0 0 0 1

(#14) 0

1 1 1 0 en 1

(#15) 1

1111

en 0

1 0 0 0

0 1 1 1

(#2) 0 +

1 0 0 0 en 1

(#3) 1

1001

en 0

1 1 1 1

0 0 0 0

1 0 0 1

0 1 1 0

Figure 5: Operation of the proposed scheme for Address Complement generation (decreasing sequence)

(#4) 0 +

1001

en 1

(#5) 1

1 0 1 0 en 0

4. Comparisons and discussion

Assuming the existence of the ALU-based accumulator-like structure of Figure 1, the hardware overhead of the proposed scheme consists of the multiplexers required to multiplex between the normal inputs of the ALU and the test input in. This is also the case for the scheme proposed in [14]. For the case where both linear and AG addressing is targeted (as is the case in modern memory BIST schemes), the proposed scheme requires an additional multiplexer to multiplex between the in and 1 signals in the low-order input of the RAM. The scheme proposed in [14] requires n 4-input multiplexers. Since a 4-to-1 multiplexer is typically 3 2-to-1 multiplexers, it is trivial to see that the hardware overhead of the

1 0 1 0

0 1 0 1

(#6) 0 +

1 0 1 0 en 1

(#7) 1

1011

en 0

1 0 1 1

0 1 0 0

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scheme [14] requires 3 times more than the proposed here. An additional merit of the proposed scheme is that in typical configuration (like the MIPS architecture shown in Figure 1) an ALU driving the address inputs of the memory is either already available, or can be easily incorporated in the design while counter modules usually must be inserted in the design of the circuit.

5. Conclusions
In this work we have proposed the utilization of ALU modules for the address generation for memory BIST. The proposed generator can generate the linear and address complement counting methods. The proposed method evolves naturally in systems where the address inputs of memories are driven by ALU modules. Comparatively to a previously proposed scheme based on counters, the proposed one presents lower hardware overhead when the combined power of linear and address complement counting methods are required.

Acknowledgments
This research has been co-funded by the European Union (European Social Fund) and Greek national resources under the framework of the Archimedes III: Funding of Research Groups in TEI of Athens project of the Education & Lifelong Learning Operational Programme.

References
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[19] S. Hamdioui, Z. Al-Ars, A.J. van de Goor, M. Rodgers, Dynamic Faults in Random-AccessMemories: Concept, Fault Models and Tests, Journal of Electronic Testing: Theory and Applications, pp. 195-205, April 2003. [20] S. Hamdioui, A.J. van de Goor, J.D. Reyes, and M.Rodgers, Memory test experiment: industrial results and data, IEE Proceedings of Computers and Digital Techniques, Vol. 153, Issue: 1, pp. 1-8, 2006.

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