Microcontroller Based System Design Module 1

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Syllabus
Module 1
Various logic families - features comparison PLA PALGAL -comparison combinational PAL PAL with flip-flops study of 16L8, 22V10 GAL dual port RAM FIFO - FPGA gate arrays.

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Logic Families
Definition : A group of compatible ICs with the same logic levels and supply voltages for performing various logic functions have been fabricated using a specific circuit configuration which is referred to as a logic family.

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Logic Families
Two types 1. Bipolar Logic Families 2. Unipolar Logic Families.

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Bipolar Logic families

Main Elements Resistors, Diodes, Transistors. Type of operation

Saturated Transistor driven to saturation Non Saturated Transistor not driven to saturation

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Bipolar Logic families

Saturated Bipolar Logic Families

1. Resistor - Transistor Logic (RTL) 2. Direct-Coupled Transistor Logic (DCTL) 3. Integrated Injection Logic (I2L) 4. Diode Transistor Logic (DTL) 5. High Threshold Logic (HTL) 6. Transistor Transistor Logic (TTL) Non-saturated Bipolar Logic Families 1. Schottky TTL 2. Emitter Coupled Logic (ECL)
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UNIPOLAR LOGIC FAMILIES

Elements : MOSFETS Types 1. PMOS 2. NMOS 3. CMOS

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Assignment
1.Describe the various logic families, features & compare them Submission date : 05-07-2012 (Thursday)

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Digital Circuits
Combinational
Outputs at any instant of time depends upon the inputs present at that instant of time. No memory

Sequential
Outputs at any instant of time depends upon the present input as well as past inputs/outputs. Memory present.

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TYPES OF ICs
Fixed Function ICs Perform Specific fixed functions. ASIC (Application Specific Integrated Circuits) to meet the specific requirements of a circuit. PLDs (Programmable Logic Devices) It is user configurable & is capable of implementing logic functions.

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PROGRAMMABLE LOGIC DEVICES (PLDs)

logic device in which the logic function is programmed by user and, in some cases, can be reprogrammed many times.

Advantages
More logic circuits can be stuffed into a much smaller area with PLDs. logic designs can be readily changed without rewiring or replacing components. PLD design can be implemented faster than one using fixed-function ICs once the required programming language is mastered.
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Programmable Arrays
Grid of conductors that forms rows and columns with a fusible link at each cross point. Arrays can be either fixed or programmable. Two types OR arrays AND array
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AND ARRAY
Consist of an array of AND gates. It has fusible links at each cross point of a row & column. Programmed by blowing fuses to eliminate selected variables from output functions. For each input to an AND gate only 1 fuse is left intact. One time programmable.
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OR ARRAY
Consist of an array of OR gates. It has fusible links at each cross point of a row & column. Programmed by blowing fuses to eliminate selected variables from output functions. For each input to an OR gate only 1 fuse is left intact. One time programmable.
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TYPES OF PLDS
Three major types of PLDs are SPLD CPLD FPGA

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SPLD (Simple Programmable Logic Devices)

SPLDs are the least complex form of PLDs. 24 to 28 pin packages

A few categories of SPLD are listed below PAL (programmable array logic) GAL(generic array logic) PLA(programmable logic array) PROM(programmable read-only memory)
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CPLD (Complex programmable logic devices)

They have much higher capacity than SPLDs permitting more complex logic circuits to be programmed into them. A typical CPLD is the equivalent of from two to 64 SPLDs. 44 to 160 pin packages.

FPGA (Field programmable gate array)

Consists of an array (sixty-four to thousands) of logic-gate groups that are sometimes called logic blocks. Two basic classes of FPGA are course-grained and fine-grained. The course grained FPGA has large logic blocks. The fine-grained FPGA has much smaller logic blocks. Pins upto 1000 pins or more.
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Classification Of SPLDs
readProgrammable read-only memory (PROM) A PROM consists of a set of fixed (nonprogrammable) AND gates connected as a decoder and a programmable OR array

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Programmable logic array (PLA) A PLA is an SPLD that consists of a programmable AND array and a programmable OR array. PLA is also called an FPLA(Field PLA)

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Programmable array Logic (PAL)

A PAL is an SPLD that was developed to overcome certain disadvantages of the PLA such as longer delays due to the additional fusible links that result from using two programmable arrays and more circuit complexity. The basic PAL consists of a programmable AND array and a fixed OR array with output logic.

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Generic Array Logic (GAL)

The GAL has a reprogrammable AND array and a fixed OR array with programmable output logic. The two main differences between GAL and PAL devices are (a) GAL is reprogrammable and (b) GAL has programmable output configurations. The GAL can be reprogrammed again and again because it uses EEPROM technology instead of bipolar technology and fusible links.

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PAL (Programmable Array Logic)

It consists of a programmable array of AND gates that connects to a fixed array of OR gates. PALs are implemented with fuse process technology, and are, therefore, one time programmable (OTP). PAL structure allows any sum-of-products (SOP) logic expression. A simple PAL structure is shown here for two input variables and one output; most PALs have many inputs and many outputs.
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PAL (Programmable Array Logic)

A programmable array is essentially a grid or matrix of conductors that form rows and columns with a programmable link at each cross point. Each programmable link, which is a fuse in the case of a PAL is called a cell. Each row is connected to the input of an AND gate, and each column is connected to an input variable or its compliment. By programming the presence or absence of a fuse connection, any combination of input variables or complements can be applied to an AND gate to form any desired product term. The AND gates are connected to an OR gate, creating a sum of products output. Prepared by Emil Raj,Dept. Of ECE,MLMCE

Implementing SOP Expression

An eg. of a simple PAL is programmed as shown in fig so that the product term AB is produced by the top AND gate, AB is produced by the middle AND gate, and AB is produced by the bottom AND gate. The fuses are left intact to connect the desired variables or their complements to the appropriate AND gate inputs. The fuses are opened where a variable or its complement is not used in a given product term. The final output from the OR gate is the SOP
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expression, X=AB+AB

+AB

GAL(Generic Array Logic)

GAL is essentially a PAL that can be reprogrammed. It has the same type of AND/OR organization that the PAL does. Reprogrammable AND array & fixed OR array. The basic difference is that GAL uses a re programmable process technology such as EEPROM (E2CMOS) instead of
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fuses.

GAL(Generic Array Logic)

Each row is connected to the input of an AND gate and each column is connected to an input variable or its complement. E2CMOS cell can be programmed to either ON or OFF such that any input combination can be applied to the input of an AND gate. A cell that is ON connects corresponding row & column A cell that is OFF disconnects the row & column. The cells can be electrically erased & reprogrammed.
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Implementing a SOP Expression for GAL

X=B+AB+ AB

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Simplified Notation for PAL/GAL Diagrams

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Q) Show how a PAL is programmed for the following 3-variable logic function: X=ABC +ABC+AB+AC

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PLA (Programmable Logic Array)

The PLA has a programmable AND array followed by a programmable OR array.

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PAL/GAL General Block Diagram

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MACROCELL
A macrocell generally consists of one OR gate and some associated output logic. The macrocells vary in complexity, depending on the particular type of PAL or GAL. A macrocell can be configured for Combinational logic, Registered logic, or Combination of both. Registered logic means that there is flip-flop in the macrocell to provide for sequential logic functions. Combinational have no flipflops. Prepared by Emil Raj,Dept. Of ECE,MLMCE

Combinational PAL

Three basic types

Combinational Output Combinational input/output Programmable polarity output
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Combinational Output
A macrocell with the OR gate and an inverter with a tristate control that can make the inverter like an open circuit to completely disconnect the output.

The output of the tristate inverter can be either

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LOW,HIGH or disconnected .

Combinational input/output
A macro cell that can be either an input or an output.

When the output is used as an input, the tri state inverter is disconnected, and the input goes to the buffer that is connected to the AND array.
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Programmable polarity output

A macrocell that can be programmed to have either an active-HIGH or an active LOW output, or it can be used as an input. One input to the exclusive OR(XOR) gate can be programmed to be either HIGH or LOW. When the programmable XOR input is HIGH, the OR gtae output is inverted because 0 xor 1=1 and 1 xor 1=0. Similarly when the programmable XOR input is LOW, the OR gate output is not inverted because 0 xor 0=0and 1 xor
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0=1.

Standard PAL Numbering

Eg:- PAL16L8
Each PAL is identified by a unique part number. Part number begins with the prefix PAL First two digits following PAL indicates the number of inputs including the outputs that can be configured as inputs. The letter following the number of inputs designates the type of output. L-active LOW H-active HIGH P-Programmable polarity
Prepared One or twoby Emil Raj,Dept. Of ECE,MLMCE digits follow the output type is the number of outputs.

PAL16L8
10 dedicated inputs(I).

2 dedicated outputs(O).

6 pins that can be either as inputs or outputs.

Each of the output is active LOW.

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Registered PAL
PALs having flip flops at the output. Flip flops stores the output. Several flip flops forms a register the output of register can be controlled because these outputs have tri state buffers such PALs are called registered PALs. The flip flop outputs are made available as an input to be used in the generation of additional product terms.
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Registered PAL

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Registered PAL
1-of-4 MUX connects 1 of its 4 input lines to the tristate output buffer based on the states of two select inputs, S0 and S1. The inputs to the 1-of-4 MUX are the
OR gate output, Complement of the OR gate output Flip flop output Complement of the flip flop output

The 1-of-2 MUX connects either the output of the tristate buffer or the flip flop back through a buffer to the AND array based on the state of S1. The select bits S0 and S1 for each OLMC are programmed.
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Standard GAL Numbering

Eg:- GAL22V10
Each GAL is identified by a unique part number. Part number begins with the prefix GAL First two digits following GAL indicates the number of inputs including the outputs that can be configured as inputs. The letter V following the number of inputs designates a variable output configuration. One or two digits follow the output type is the number of outputs.
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GAL22V10
12 dedicated inputs(I). 10 pins that can be either as inputs or outputs(I/O). Macrocells have inputs from the AND gates that
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vary from 8 to 16.

OLMC Configurations

Combinational mode with active LOW output Combinational mode with active HIGH output Registered mode with active LOW output Registered mode with active HIGH output

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FPGA
Field Programmable Gate Array Basic elements in an FPGA Configurable logic block (CLB) The interconnections The input output (I/O) blocks Fine grained CLBs are relatively simple. Coarse grained CLBs are larger and more complex. FPGAs are reprogrammable.
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Configurable Logic Block

FPGA logic block consists of several smaller logic modules. Basic building units. Analogous to macro cells in a CPLD. Made up of Multiple smaller logic modules. Local programmable interconnect that is used to connect logic modules within the CLB.
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Basic CLB

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Logic Module
A logic module in an FPGA logic block can be configured for combinational logic, registered logic, combination of both. A flip-flop is part of the associated logic and is used for registered logic. LUT (look-up table) is a type of memory that is programmable and used to generate SOP combinational logic functions.
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The LUT essentially does the same job as the PAL or PLA does.

Basic Concept of LUT

Generally, LUT consists of a number of memory cells equal to 2n, where n is the number of input variables. For example, 3 inputs can select up to 8 memory cells, so an SOP expression with up to 8 product terms. A pattern of 1s and 0s can be programmed into the LUT memory cells. 1 means the associated product term appears in the SOP output 0 means that the associated product term does not appear in the SOP output. The resulting SOP output expression is

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DUAL PORT RAM

Provides a common memory accessible to both processors that can be used to share and transmit data and system status between the two processors. Totally asynchronous 256byte dual port memory. Accessed via 8 bit Multiplexed address and data ports. Dual port memory cell allows random access with minimum arbitration. Each port has standard independent RAM control signals.
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FEATURES
Fast access time. Low power CMOS design. 24pin DIP or 24pin SOIC surface mount package. Both CMOS and TTL compatible. Operating temperature of 40C to +85C.

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DUAL PORT RAM

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DUAL PORT RAM

Read/Write access of either port is transferred as 8 bits address, followed by 8 bits of data. For a write cycle,
"active-low OE" is inactive, "active-low CE becoming active latches the address to be accessed "active-low WE is made active.

In a read cycle to a port,

"active-low WE" is inactive, "active-low CE" goes active, which with the address is latched, data is retrieved. "active-low OE goes active.

The rising edge of either "active-low CE or "active-low OE" terminates the read cycle.
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DUAL PORT RAM

Allows simultaneous access from two ports. No arbitration required for read cycles occurring at the same instant. Argument for arbitration can be made for
Reading & writing the cell at the exact same instant. Or a write from both ports at the same instant.

If a write cycle occurs while a read cycle is in progress the read cycle will likely recover the old data or new data and not combination of both.
Write cycle will update the memory with correct data.

Simultaneous write cycle to same memory location will lead to meta stable state. Raj,Dept. Of ECE,MLMCE Prepared by Emil

FIFO
First In First Out Memories. Used in Buffering applications b/w devices that operate at different speeds Applications where data must be stored temporarily. Data is released from buffer in the order of its arrival. It can be unidirectional or bidirectional.

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FIFO
It varies in terms of
Density capacity of the chips in bits No. of words no of rows each of which stores a memory word. Bits per word no of columns each of which connects to a sense/write circuit. Supply voltage. Temperature.

It is formed by arrangement of shift register. First databy Emilwrites Of ECE,MLMCE is the first to be read out. bit Raj,Dept. in memory Prepared

Difference b/w Conventional Shift Register & FIFO

Conventional - A data bit moves through the register only when new data bits are entered FIFO - A data bit immediately goes through the register to the right most location that is empty.

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FIFO Applications
Irregular telemetry data can be stored and retransmitted at a constant rate. Data input at a slow keyboard rate can be stored and then transferred at a higher rate for processing. Data input at a constant rate can be stored and then output it in bursts. Data in bursts can be stored and reformatted into a constant rate output.

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