Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm

Abstract
Based on fast FIR algorithms (FFAs), this brief proposes new parallel FIR filter architectures, which are beneficial to symmetric convolutions of odd length in terms of the hardware cost. The proposed parallel FIR architectures exploit the inherent nature of symmetric coefficients reducing half the number of multipliers in the subfilter section at the expense of increase in adders in preprocessing and postprocessing blocks. Exchanging multipliers with adders is advantageous because adders weigh less than multipliers in terms of silicon area, and in addition, the overhead from the increase in adders in preprocessing and postprocessing blocks stay fixed, not increasing along with the length of the FIR filter, whereas the number of reduced multipliers increases along with the length of the FIR filter. For example, for a three-parallel 81-tap filter, the proposed structure saves 26 multipliers at the expense of five adders, whereas for a three-parallel 591-tap filter, the proposed structure saves 196 multipliers at the expense of five adders still. Overall, the proposed parallel FIR structures can lead to significant hardware savings for symmetric convolution in odd length from the existing FFA parallel FIR filter, particularly when the length of the filter is large.

Aim
To design Parallel Linear-Phase FIR Digital Filter.

Objective
The objectives of this works are, 1. To design Parallel Linear-Phase FIR Digital Filter using VHDL.

2. Functional verification of the above design

3. Result analysis in terms of a. Area b. Power c. Speed

Tools to be used:
For functional simulation For synthesis and implementation Mentor Graphics ModelSim 6.5 or later Xilinx Incs Xilinx ISE 13.1or later version

For FPGA based implementation, the FPGA Details are,

Manufacturer Family FPGA Series Xilinx Spartan 3/Spartan 3E XC3S400PQ208/XC3S250EPQ208

For CPLD based implementation, the CPLD Details are,

Manufacturer Family CPLD Series Xilinx XC9500 XC9572-XL

HDL to be used:
VHDL/Verilog HDL

Project Report Details:

Soft copy of documents referred by our guide to do the project will be given to prepare the report.