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Principles of the 1-T DRAM Concept on SOI

Jean-Michel Sallese, Serguei Okhonin, Pierre Fazan Mikhail Nagoga


LEG Laboratory, Swiss Federal Institute of Technology, EPFL, 1015 Lausanne, Switzerland

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Introduction
1T/1C DRAM cell area : 8F (F: min. feat. size)
WL

T C
BL

Capacitor does not scale below 100 nm (30 fF) Alternate Memory Solutions: exotic materials, large cells and complex:
FERAM: 1T / 1 FeCap - MRAM: 1T / 1 MTJ - OUM: 1T / 1 R

Capacitor-less DRAM Cells: some attempts, still complex:


2T cell on bulk Si or SOI, Tunnel diode.

Objective of this work: a 1T cell


Use SOI MOSFETs Scales with CMOS < 100 nm
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Introduction
PD SOI-Mosfet Floating Body Effects:
Floating Body Device operation instabilities: Kink effect Self heating Transient effects: Current overshooting Current undershooting PD-SOI Nmosfet

Gate
SiO2

+ + +

Buried Oxide Si

1T DRAM: exploits such effects:


Use SOI body charging to store information. Use SOI transistor to read stored information.

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1T-DRAM Concept
Store excess of + or - charges in the Body of PD SOI-MOSFETs Use the transistor amplifying mode: 1T Gain Cell

1T/1C-DRAM
VG > VON VDD/2

True 1T-DRAM
Store 1
+ + +

VDD VG > VON

VDD

Store 0
Vcc/2
- - -

+/V
CBL

BL1 BL1

CCell

Read by charge sharing


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Read by current sensing I1, I0

1T-DRAM Operation Modes


Samples :
0.25 m PD-SOI N&P MOSFETs from LETI 0.13 m PD-SOI N&P MOSFETs from IMEC

Data Writing (PD N-mosfet): Write a 1 : Channel impact ionization : excess Write a 0 :

of holes

Forward biasing body junction: default of holes Data Reading: Read the information stored by current sensing Non destructive read Data Refreshing: DRAM= data loss with time Refresh operations needed
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1T-DRAM Operation Modes


Writing 1 Use impact ionization mechanism: Example of voltage for 0.25m NMOS devices for writing 1 in 3 ns
PD-SOI NMOS

0V
SiO2

0.6V Gate 2V
+ + +

Buried Oxide Si

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1T-DRAM Operation Modes


Writing 0 Use hole removal mechanism: Example of voltage for 0.25 m NMOS devices for writing 0 in 3 ns
PD-SOI NMOS

0V
SiO2

0.6V Gate
+

-2.3V
D

- - +

Buried Oxide Si

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1T-DRAM Operation Modes


Writing 1 & Writing 0
( 0.25 m PD N-mosfet, W/L = 25/0.5 m )
5 10
-5

Read Current [A]

4 10 3 10 2 10 1 10

-5

"1"
-5

-5

"0"

-5

W/L=25/0.5 m 0 0 5 10 15 20

Time [s]
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1T-DRAM Operation Modes


Data reading: current sensing 0.6V
Read Current [uA] 50 40 30 20 10 0
180 mV

VD = 0.2 V 1 & 0 meas. 1 ms after pulse

"1"
te Sta y ad Ste

Iread

"0"

0.3V

-10

0.5 1 Gate Voltage [V]

1.5

Key difference vs 1T/1C-DRAM: Non destructive read But refresh needed: charge loss due to generations & recombinations
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2D Simulation & Mechanisms


Device structure

Source

Gate

Drain

N-channel FET on SOI (0.3m) Gate oxide: 4.5nm

Body: 3.1017 to 1.1018 oxide 400nm

Si-substrate
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2D Simulation & Mechanisms


During Writing 1 VG= 0.6V
Holes generated by Impact Ionization at high VD (2V) VS= 0V VD= 2V

Hole Flux due to Impact Ionization: Positive charge in the body

Gate S D S

Gate D

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2D Simulation & Mechanisms


After Writing 1 VG= 0.6V
Excess of holes in the body Excess of channel electrons: Drain current increases
Hole density

VS= 0V VD= 0.3V

until holes are evacuated through forward junction leakage


Hole Flux density

Gate S D S

Gate D

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2D Simulation & Mechanisms


After Writing 1
Decay of the body potential as a function of time after Writing 1

0 ms

1 ms 4 ms 14 ms 100 ms 400 ms 3s
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2D Simulation & Mechanisms


During Writing 0 VG= 0.6V
Hole current density after 1 ns
VS= 0V VD= -1V

Holes are removed after a few ns after 3 ns

Gate

Gate

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2D Simulation & Mechanisms


During Writing 0
after 10 ns after 100 ns: steady state

Gate S D S

Gate D

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2D Simulation & Mechanisms


After Writing 0 VG= 0.6V
Default of holes in the body Default of channel electrons: Drain current decreases
Hole density

VS= 0V VD= 0.3V

Reverse junction leakage generates holes in the body

Gate S D S

Gate D

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2D Simulation & Mechanisms


After Writing 0
Decay of the body potential as a function of time after Writing 0

3s 1.5 s 700 ms 300 ms 10 ms 0 ms


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1T-DRAM Cell Scaling


Demonstration for small W/L and 3 ns operation High endurance: >1015 extrapolated
60 50 40 L = 150 nm W = 400 nm
80 L = 0.2 m W = 10 m

60

I [A/m]

I [A/m]

30 20 10 0 -10

40 Writing "1" 3ns drain pulse embedded into 7ns gate pulse

20

Writing "0"

3ns drain pulse

-20 0 50 100 Time [s] 150 200

-20 0 50 100 150 200 250 300 350 400 Time [ns]

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Conclusion
1T/1C-DRAM cells: does not scale below 100 nm SOI DRAM = true 1T-DRAM = 4F2 cell Exploits Floating Body charging of PD SOI-MOSFETs No capacitor, no new materials, no additional masks Standard CMOS logic or memory process Ideal for merged logic/memory SOC applications Non destructive read in a refresh interval High switching speed: 3 ns demonstrated Scalable

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