EXPERIMENT NO.

15
Aim
To implement VHDL code for clock divider and pulse counter.

Tool Required
Mentor Graphics FPGA advantage tool 8.1PS Model sim 6.3a

Theory
Pulse counter The frequency counter has to count the number of cycles per second of an incoming signal. Hence we need a device to count. In electronics circuits, counter ICs are available for counting. These IC's can count the input pulses. Clock Divider In some designs, you need to provide a number of phase-related clocks to various components. In most cases, you generate the needed clocks by dividing a master clock by a power of two (synchronous division). However, sometimes, it is desirable to divide a frequency by an odd or even fractional divisor. In these cases, no synchronous method exists without generating a higher frequency master clock.

A frequency divider also called a clock divider or scalar or presale, is a circuit that takes an input signal of a frequency, fin, and generates an output signal of a frequency:

Where n is an integer. Phase-locked loop frequency synthesizers make use of frequency dividers to generate a frequency that is a multiple of a reference frequency. Frequency dividers can be implemented for both analog and digital applications.

VHDL Code for Pulse Counter LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY pulse_counter IS generic(max_count:natural:=8); port(clk,sample:instd_logic; count:out integer range 0 to max_count-1; overflow:outboolean); END ENTITY pulse_counter; -ARCHITECTURE beh_pulc OF pulse_counter IS BEGIN process(clk,sample) variablelocal_cntr:natural; variablestart_counting:boolean; begin ifsample'event then if sample='1'then overflow<=false; start_counting:=true; local_cntr:=0; elsif sample='0' then start_counting:=false; end if; elsifclk'event and clk='1' then ifstart_counting then local_cntr:=local_cntr+1; iflocal_cntr>max_count then local_cntr:=0; overflow<=true; start_counting:=false; end if; end if; end if; count<=local_cntr; end process; END ARCHITECTURE beh_pulc;

Output:

VHDL Code for Clock divider

LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY clk_divider IS generic(n:positive:=1); port(rst,clk:instd_logic; clk_div:bufferstd_logic); END ENTITY clk_divider; -ARCHITECTURE beh_clkdiv OF clk_divider IS BEGIN process(clk,rst) variablecount:natural; begin ifrst='0'then count:=0; clk_div<='0'; elsifclk'event and clk='1' then count:=count+1;

if count=n then clk_div<=not clk_div; count:=0; end if; end if; end process; END ARCHITECTURE beh_clkdiv;

Output:

Result:
The VHDL code for Pulse Counter and Clock Divider were simulated successfully.