9.

Bandgap Bias Network

How to generate voltages and currents that are relatively independent of supply voltage and/or temperature?

9.1 Introduction
We have specially considered the design of on-chip Bi-CMOS bandgap bias network optimized with respect to noise behavior. And is implemented using MOSFETs operating in subthreshold region with BJTs. The bandgap bias network and its response both are shown at the end of this chapter.

Why Bi-CMOS We have chosen Bi-CMOS technology for bandgap bias network considering following points and drawbacks in present design approacha) The most useful biasing idioms are actually based on bipolar circuit b) CMOS offers relatively limited options for realizing bias circuit c) A parasitic bipolar device exists in every CMOS technology, and may be used in a bandgap voltage reference. Even though the characteristics of parasitic transistors are far from ideal, the performance of bias circuits made with such devices is frequently vastly superior to that of pure CMOS bias circuits.

The Bandgap Voltage reference concept Since IC technology directly offers no reference voltages that are inherently constant, the only practical option is two combine two voltages with precisely complementary temperature behavior. Thus, the general recipe for making temperature-independent references is to add a

voltage that goes up with temperature to one that goes down with temperature. If the two slopes are equal in magnitude but opposite in sign, the sum will be independent of temperature. Without question, the most elegant realization of this idea is the bandgap voltage reference, for it produces an output voltage that is traceable to fundamental constants, and therefore is relatively insensitive to process, temperature and supply variations.

9.2 Current and Voltage References

Here we are using current and voltage references made by active devices as a biasing element. They are required to establish current references in our VCO design. Current and voltage references have to be precise and well characterized rather than constant. Use of these references in biasing can results in superior insensitivity of circuit performance to power-supply variations and to temperature. They are frequently more economical than resistors in terms of die area required to provide bias current of certain value, particularly when the value of bias current required is small. Various important parameters measuring the performance of a reference areLine Regulation a) Load Regulation b) Temperature Coefficient c) Power Dissipation d) Supply Voltage Range To most of the designers the above parameters are self-explanatory but they will be introduced as we proceed.

9.3 CTAT(Complementary to Absolute Temperature) Voltage Reference

CTAT Voltage reference shows negative temperature coefficient. Most commonly used reference is a diode voltage in a CMOS Process or a diode connected bipolar transistor in a BiCMOS Process. Figure 9.1 shows a diode connected BJT. From basic semiconductor devices

qAD n ni VBE IC = e T N a Lp

(equ. 9.1)

In equ 9.1, minority carrier current is neglected and base width is replaced by diffusion length in base. Most of the collector current is electron current.

IB =

qAD p ni N d Ln

VBE VT

(equ. 9.2)

In equ. 9.2, recombination current is neglected. Base current is hole current. The total current flowing through a diode connected BJT is same as the diode current which can be derived as

Dn Dp I D = I C + I B = qAni + N L a p N d Ln
2

VBE e VT

(equ. 9.3)

In equ. 9.3, temperature dependent terms are-

ni = N C NV e
2

Eg KT Eg KT

(equ. 9.4)
3

or

ni = N C 0 NV 0T e
2

(equ. 9.5)

D n = nV T
or D n = (CT
n

(equ. 9.6)
) k T = C T q
' 1 n

(equ. 9.7)

SimilarlyD p = DT

) k T = D T q
'

1 n

(equ. 9.8)

Substituting equ. 9.8, 9.7 and 9.5 in equ. 9.3 gives-

C' D' I D = qAN CO N VO + N L a p N d Ln

4 n qVBE E g T e KT

(equ. 9.9)

Performing natural log on both the sides of the equ. 9.9 and simplifyingEg KT I KT (4 n ) ln (T ) = VBE or ln k D q q A q

Replacing natural log of T with Tylor Series, ignoring all the higher order terms and replacing all temperature independent terms with constants give I V BE = a o ln k D a1 T + V BE 0 A

(equ. 9.10)

For a typical BJT-

a0 = 9.001x10 5 V / K , k = 1x10 6 m 2 / A , a1 = 0.0017574V / K , VBE 0 = 1.2108V

Fig. 9.1: CTAT Voltage Reference and its performance

9.4 PTAT (Proportional to Absolute Temperature) Current Reference

Figure 9.2 shows a basic circuit topology for PTAT current reference. As the name suggests, the output current increases proportional to the absolute temperature.

Fig. 9.2: Typical PTAT Current Source Topology

TP1 and TP2 act as a 1:1 current mirror to force same current through Q1 and Q2. TP3 mirrors the same current to the output. Kirchoffs voltage loop law gives-

V BE1 =V BE 2+ I ptat R
Equ. 9.11 has two solutions(a) I ptat = 0 , which implies V BE1 =V BE 2= 0 (b) Using equ. 9.1 and equ. 9.11 givesA I ptat R = V BE1 V BE 2= VT ln 2 A 1

(equ. 9.11)

or I ptat =

VT A2 ln R A1

K A or I ptat = ln 2 qR A1

(equ. 9.12)

As visible from equ. 9.12, if Q1 and Q2 are matched, the output current is independent of the process variations and is directly proportional to the absolute temperature. The slope of the

output characteristics with respect to the change in temperature is approximately linear. It is

A directly proportional to ln 2 and inversely proportional to R as shown in figure 9.11 and equ. A 1

9.12. The circuit has two basic problemsa) Use of diode connected BJT shows deteriorated performance in case of low supply voltage and low current. This is due to the current drawn into the base of both the transistors Q1 and Q2. To circumvent this problem a -helper (Q3) can be used as shown in figure 9.3. b) The circuit has two stable states as visible from equ. 9.11. These are-(a) I ptat = 0 and (b)

K A I ptat = ln 2 qR A1

T = TC * T . The stable state (a) which occurs mostly when supply

voltage is switched on, is undesirable. Thus a start-up circuit as shown in figure 9.4 is required to avoid state (a). Figure 9.4 shows a state dependent start-up circuit. Capacitor C is initially discharged. When the circuit is switched on, C charges to the supply voltage in a finite time. During this finite charging time TP4 is on and draws current from TP2 thus correctly biasing the current mirror to result in the stable state (b). When the capacitor C is fully charged, TP4 switches off. There is no bleeder resistor required across C in practical circuits due to backplane tie down in most of the MIM Capacitors in most of the processes. Other option for start-up circuit not frequently used is continuously on TP4 with TP4 made as small as possible.

For reliable operation of the PTAT reference, Q1-Q2 and TP1-TP2 transistor pairs should be layout in common-centroid fashion for proper matching, cascode-current mirror should be used for better line regulation (so that the output resistance of the current mirror does not mismatch the current in the two legs) and trimming of resistor R can be used.

Approximate Design Process parameters for a typical high speed CMOS Process

n C ox = 180 x10 6 A / V 2 p C ox = 90 x10 6 A / V 2

Vt = 0.662V

Temperature dependent parameters for BJT in a typical process

a0 = 9.001x10 5 V / K
k = 1x10 6 m 2 / A
a1 = 0.0017574V / K

VBE 0 = 1.2108V

Generic constants

K = 1.38x10 23 J / K , q = 1.609x10 19 C

Assumptions

A1 = 10m 2 , A2 = 200m 2 , Tmax = 120 o C , Tmin = 120 o C , I120o C = 800A, I 120o C = 300A,VCC = 3.4V ,Vov = 10%of (VCC ) = 0.34V
Design is done at Tnom=25C=298.16K I 120o C I 120o C Tmax Tmin

TC =

= 2.0833x10 6 A / o C

I 25 o C = TC (T nom T min ) + I 120 o C = 602 . 08 A

Using equ. 9.12-

R=

K A2 ln qTC A1

= 123.33

The resistance may have to be varied slightly to compensate for the other temperature dependent changes in the circuit.

TP1 and TP2 Sizing-

2 I 25o C W = = 115.74 L 1, 2 p C oxVov 2

Choosing the gate length to be four times the minimum gate length in a typical CMOS Process ( Lmin = 0.5A )-

L1, 2 = 2 A W 1, 2 = 230 A

TP3 is choosen to be same size as that of TP1

L3 = 2 A
W 3 = 230 A
Q3 used as -helper is chosen to be of same size as that of Q1. TP4 used in start-up circuit is choosen to be small. Capacitor C is choosen to be sufficiently large and not requiring lot of chip area. Figures 9.3 and 9.4 show device sizes used. R is slightly modified. Figure 9.5 shows the response of the circuit.

Fig.9.3: Designed PTAT Circuit with -helper

Fig.9.4: Circuit with Start-up showing voltages and currents

Circuit Voltages and Currents

Voltage V BE1 can be determined from equ. 9.10.

I V BE1 = a o ln k D a1 T + V BE 0 0.8V A

Other voltages areV2 = 2V BE1 1.59V due to Q1=Q3

V1 = VCC (Vov + Vt ) 2.4V

From previous calculations-

I ptat = I 25o C = 602.1A

VR = I 25o C R = 74.3mV

From the above calculations it is visible that TP1 and Q2 are well into the desired regions of operation suggesting that circuit will operate reliably in the designed temperature range.

Fig.9.5: Response of the designed PTAT Current Reference

9.5 Temperature independent current reference or Bandgap bias Network

CTAT voltage reference in section 9.3 and PTAT current reference in section 9.4. can be combined to give a voltage reference independent of temperature over a wide range of temperature. Design in section 9.4. for PTAT current reference is used as it is. Design for CTAT voltage reference in section 9.3. is slighly modified to give a response as shown in figure 9.6.

Fig. 9.6: Modified CTAT Voltage Reference and its response

This modification is in the form of a resistor ( Rcor ) in the emitter. The idea is to use drop across this resistor to provide same slope to the voltage reference for two extreme currents given by PTAT Current Reference.

Assumption from section 9.4

I 120o C = 300uA I 120o C = 800uA A4 = 10um 2

Using equ. 9.10 @ T= -120C gives-

I o V BE 4 _ 120o C = a o ln k 120 C A4
Similarly @ T= 120C gives-

a1 T + V BE 0 0.98876V

I o V BE 4 _ 120o C = a o ln k 120 C A 4

a1 T + V BE 0 0.67515V

Reference voltage across the series combination of the diode and the resistor ( Vref ) has to be same at the two extreme temperatures. This gives the following approximate relationV BE 4 _ 120o C + I 120o C R = Vref = V BE 4 _ 120o C + I 120o C R

(equ. 9.13)

or Using equ. 9.13 gives-

R=

VBE 4 _ 120o C VBE 4 _ 120o C I 120o C I 120o C

= 627.21

Vref = V BE 4 _ 120o C + I 120o C R = 1.77V

Vref is expected to be slightly higher due to the positive temperature coefficient of the resistance

Rcor as shown in figure 9.6.

To finally get a bandgap voltage reference, PTAT Current Source designed in section 9.4 is used to force current through the CTAT voltage reference designed above as shown in figure 9.7. Figure 9.8. shows the response of the designed bandgap voltage reference.

Fig. 9.7: Bandgap Voltage Reference

Fig. 9.8: Response of the Bandgap Voltage Reference

Slight curvature is due to the natural log nature of the diode voltage with respect to the diode current as given in equ. 9.10. Though the linear component of the diode voltage reference has been cancelled the higher order effects have to be cancelled by using higher order PTAT current references. In most of the designs such a curvature correction is not required. Temperature coefficient of a bandgap reference is given by equ. 9.14.

TC bandgap =

Vmax Vmin *10 6 ( ppm / o C ) Tmax Tmin

(equ. 2.14)

or TC bandgap = 12 ppm / o C

Apart from the voltage and the current references, a bias circuit uses buffers to give application specific bias circuits. Voltage mode, current mode and mixed mode techniques are used to adjust reference voltage and current as required for a specific application.

9.6 Summary
We have the designed on-chip Bi-CMOS bandgap bias network allowing the stable biasing. The self-biased cell is quite versatile, permitting the generation of currents proportional to the ratio of a voltage in one branch to the resistance in the other. The voltage may be provided by a variety of elements, such as a forward-biased junction. While a VBE by itself has limited utility as a voltage reference because of its negative TC, its CTAT behavior is valuable in compensating the PTAT VBE in a bandgap reference circuit to yield an output voltage with extremely small temperature variation. Because of the use of both Bipolar and MOSFETs, the bandgap bias network designed is found more accurate and stable voltages or currents than possible with ordinary CMOS circuits.

9.7 References
[1] Voltage References and Biasing, 1993 Thomas H. Lee; rev. November 19, 2001 (Handout #20: EE214 Fall 2001) [2] Analysis and design of analog integrated circuits, by Gray and Mayer, John Wiley Press,1996

[3] MOSFET Theory and Design, R.N.Warner,Jr and B.L.Grung Oxford University Press,1999 [4] Semiconductors Academia to Industry, Anurag Nigam private notes.