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Discontinued Product (PCN #06-07). Contact Rochester Electronics for Availability. www.latticesemi.com/sales/discontinueddevicessales.cfm
...
K0
D Q
G3
K1 K2
D Q
OR Array
D Q
G2 G1
AND Array
D Q
K3
D Q
Twin GLB
G0
OR Array
D Q
D Q
N0
D3
N1 N2
D2
D1
N3
D0
A0
A1
A2
A3
C0
C1
C2
C3
...
OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS Complete Programmable Device Can Combine Glue Logic and Structured Designs Enhanced Pin Locking Capability Five Dedicated Clock Inputs Synchronous and Asynchronous Clocks Programmable Output Slew Rate Control to Minimize Switching Noise Flexible I/O Placement Optimized Global Routing Pool Provides Global Interconnectivity ispDesignEXPERT LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING Superior Quality of Results Tightly Integrated with Leading CAE Vendor Tools Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER PC and UNIX Platforms
Description
The ispLSI 3448 is a High-Density Programmable Logic Device containing 672 Registers, 224 Universal I/Os, five Dedicated Clock Inputs, 14 Output Routing Pools (ORP) and a Global Routing Pool (GRP) which allows complete inter-connectivity between all of these elements. The ispLSI 3448 features 5V in-system programmability and in-system diagnostic capabilities. The ispLSI 3448 offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 3448 device is the Twin Generic Logic Block (Twin GLB) labelled A0, A1...N3. There are a total of 56 of these Twin GLBs in the ispLSI 3448 device. Each Twin GLB has 24 inputs, a programmable AND array and two OR/Exclusive-OR Arrays, and eight outputs which can be configured to be either combinatorial or registered. All Twin GLB inputs come from the GRP.
Copyright 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
February 2000
3448_06
D Q
...
...
GOE0
GOE1
TOE
Input Bus
Input Bus
A0 A1 A2 A3
J3 J2 J1 J0
I/O 159 I/O 158 I/O 157 I/O 156 I/O 155 I/O 154 I/O 153 I/O 152 I/O 151 I/O 150 I/O 149 I/O 148 I/O 147 I/O 146 I/O 145 I/O 144
Input Bus
B2 B3
Input Bus
B0 B1
I3 I2 I1 I0
I/O 143 I/O 142 I/O 141 I/O 140 I/O 139 I/O 138 I/O 137 I/O 136 I/O 135 I/O 134 I/O 133 I/O 132 I/O 131 I/O 130 I/O 129 I/O 128
Input Bus
Input Bus
C0 C1 C2 C3
H3 H2 H1 H0
I/O 127 I/O 126 I/O 125 I/O 124 I/O 123 I/O 122 I/O 121 I/O 120 I/O 119 I/O 118 I/O 117 I/O 116 I/O 115 I/O 114 I/O 113 I/O 112
D0
D1
D2
D3
E0
E1
E2
E3
F0
F1
F2
F3
G0
G1
G2
G3
CLK0 CLK1 CLK2 IOCLK1 IOCLK0 Y0 Y1 Y2 Y3 Y4
0130/3448
C1 C2
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL PARAMETER Output Low Voltage Output High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current ispEN Input Low Leakage Current I/O Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current IOL= 8 mA IOH = -4 mA 0V VIN VIL (Max.) 3.5V VIN VCC 0V VIN VIL 0V VIN VIL VCC = 5V, VOUT = 0.5V VIL = 0.0V, VIH = 3.0V, fCLOCK = 1 MHz CONDITION MIN. 2.4 TYP. 470
3
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Guaranteed but not 100% tested. 2. Measured using 28 16-bit counters. 3. Typical values are at VCC = 5V and TA= 25C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum I CC .
Table 2-0007/3448
DESCRIPTION
-90
3
-70 70.0 50.0 83.0 9.0 0.0 11.0 0.0 12.0 6.0 6.0 5.0 0.0 15.0 18.0 9.0 10.0 15.0 30.0 30.0 12.0 12.0 15.0 15.0
MIN. MAX. MIN. MAX. 12.0 15.0 7.5 8.0 14.0 25.0 25.0 10.0 10.0 13.0 13.0
tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis ttoeen ttoedis twh twl tsu3 th3
1. 2. 3. 4. 5.
1 Data Propagation Delay, 4PT Bypass, ORP Bypass 2 Data Propagation Delay 3 Clock Frequency with Internal Feedback 5 Clock Frequency, Maximum Toggle
4
90.0
1 tsu2 + tco1
62.5 100 7.0 0.0 8.5 0.0 9.0 5.0 5.0 4.5 0.0
6 GLB Reg. Setup Time before Clock, 4 PT Bypass 7 GLB Reg. Clock to Output Delay, ORP Bypass 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 9 GLB Reg. Setup Time before Clock 10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable 18 Test OE Output Enable 19 Test OE Output Disable 20 Ext. Synchronous Clock Pulse Duration, High 21 Ext. Synchronous Clock Pulse Duration, Low 22 I/O Reg Setup Time before Ext. Synchronous Clock (Y3, Y4) 23 I/O Reg Hold Time after Ext. Sync Clock (Y3, Y4)
Unless noted otherwise, all parameters use 20 PTXOR path and ORP. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Reference Switching Test Conditions section.
Table 2-0030/3320
DESCRIPTION
-90
-70
MIN. MAX. MIN. MAX. 7.5 -3.0 1.5 5.4 3.7 2.3 14.0 8.3 8.3 3.2 1.0 4.0 3.5 5.0 5.0 6.2 0.5 0.5 1.0 8.9 15.0 3.7 1.5 0.0 9.0 -4.0 2.5 6.3 4.5 3.2 18.2 10.2 10.2 3.5 1.6 5.3 3.8 5.8 5.8 7.3 0.5 1.0 1.0 10.5 18.3 4.5 2.0 0.0
UNITS
24 I/O Register Bypass 25 I/O Latch Delay 26 I/O Register Setup Time before Clock 27 I/O Register Hold Time after Clock 28 I/O Register Clock to Out Delay 29 I/O Register Reset to Out Delay 30 GRP Delay 31 Feedback Delay 32 4 Product Term Bypass Path Delay (Comb.) 33 4 Product Term Bypass Path Delay (Reg.) 34 1 Product Term/XOR Path Delay 35 20 Product Term/XOR Path Delay 36 XOR Adjacent Path Delay
3
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tgrp tfeedback
GLB
t4ptbp t4ptbr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck
ORP
37 GLB Register Bypass Delay 38 GLB Register Setup Time before Clock 39 GLB Register Hold Time after Clock 40 GLB Register Clock to Output Delay 41 GLB Register Reset to Output Delay 42 GLB Product Term Reset to Register Delay 43 GLB Product Term Output Enable to I/O Cell Delay 44 GLB Product Term Clock Delay 45 ORP Delay 46 ORP Bypass Delay
torp torpbp
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros.
Table 2-0036/3448
DESCRIPTION
-90
-70
MIN. MAX. MIN. MAX. 3.5 3.0 2.5 13.0 4.5 4.5 3.5 3.0 9.0 5.5 8.5 4.0 4.0 3.0 13.0 5.0 5.0 4.0 4.0 9.0 7.0 10.0
UNITS
47 Output Buffer Delay 48 Output Buffer Delay, Slew Limited Adder 49 I/O Cell OE to Output Enabled 50 I/O Cell OE to Output Disabled 51 Clock Delay, Y0 or Y1 or Y2 to Global GLB Clock Line 52 Clock Delay, Y3 or Y4 to I/O Cell Global Clock Line 53 Global Reset to GLB and I/O Registers 54 Global OE Pad Buffer 55 Test OE Pad Buffer
ns ns ns ns ns ns ns ns ns
tgy0/1/2 tioy3/4
Global Reset
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details.
Table 2-0037/3448
I/O (Input)
GRP #30
#47, 48
I/O (Output)
#49, 50
Y0,1,2
#51
GOE0,1 TOE
#54 #55
0902/3448
Derivations of tsu, th and tco from the Product Term Clock 1 tsu
= = = 2.8 ns = = = = 4.1 ns = = = = 13.7 ns = Logic + Reg su - Clock (min) (tiobp + tgrp + t20ptxor) + (tgsu) - (tiobp + tgrp + tptck(min)) (#24+ #30+ #35) + (#38) - (#24+ #30+ #44) (2.3 + 3.2 + 5.0) + (1.5) - (2.3 + 3.2 + 3.7) Clock (max) + Reg h - Logic (tiobp + tgrp + tptck(max)) + (tgh) - (tiobp + tgrp + t20ptxor) (#24+ #30+ #44) + (#39) - (#24+ #30+ #35) (2.3 + 3.2 + 3.7) + (5.4) - (2.3 + 3.2 + 5.0) Clock (max) + Reg co + Output (tiobp + tgrp + tptck(max)) + (tgco) + (torp + tob) (#24 + #30 + #44) + (#40) + (#45 + #47) (2.3 + 3.2 + 3.7) + (0.5) + (1.5 + 2.5)
th
tco
Table 2-0042/3448
Note: Calculations are based on timing specs for the ispLSI 3448-90L.
ispLSI 3448
ICC (mA)
30
60
90
fmax (MHz)
Notes: Configuration of 28 16-bit Counters Typical Current at 5V, 25 C
ICC can be estimated for the ispLSI 3448 using the following equation: ICC = 60 + (# of PTs * 0.46) + (# of nets * Max. freq * 0.01) where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max. freq = Highest Clock Frequency to the device The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified.
0127A/3448
10
TDI/SDI
Signal Locations
Signal GOE0, GOE1 TOE RESET BSCAN/ispEN TDI/SDI TCK/SCLK TMS/MODE TRST TDO/SDO GND R2, W1 H3 AA31 AD29 K29 AG29 F31 E3 AH3 A1, A2, A16, A30, A31, B1, B5, B9, B13, B19, B23, B27, B31, E2, E30, J2, J30, N2, N30, T1, T31, W2, W30, AC2, AC30, AG2, AG30, AK1, AK5, AK9, AK13, AK19, AK23, AK27, AK31, AL1, AL2, AL16, AL30, AL31 A3, A10, A22, A29, B14, B18, C1, C31, K1, K31, P2, P30, V2, V30, AB1, AB31, AJ1, AJ31, AK14, AK18, AL3, AL10, AL22, AL29 B2, B3, B30, C3, C7, C11, C14, C18, C21, C25, C29, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, D26, D27, D28, E4, E28, F4, F28, G3, G4, G28, G29, H4, H28, J4, J28, K4, K28, L3, L4, L28, L29, M4, M28, N4, N28, P3, P4, P28, P29, R4, R28, T4, T28, U4, U28, V3, V4, V28, V29, W4, W28, Y4, Y28, AA3, AA4, AA28, AA29, AB4, AB28, AC4, AC28, AD4, AD28, AE3, AE4, AE28, AE29, AF4, AF28, AG4, AG28, AH4, AH5, AH6, AH7, AH8, AH9, AH10, AH11, AH12, AH13, AH14, AH15, AH16, AH17, AH18, AH19, AH20, AH21, AH22, AH23, AH24, AH25, AH26, AH27, AH28, AJ3, AJ7, AJ11, AJ14, AJ18, AJ21, AJ25, AJ29, AK2, AK30 432-Ball BGA
VCC NC1
11
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 I/O 36 I/O 37
T30 U29 U31 V31 W31 W29 Y31 Y30 Y29 AA30 AB30 AB29 AC31 AC29 AD31 AD30 AE31 AE30 AF31 AF30 AF29 AG31 AH31 AH30 AJ30 AH29 AJ28 AK29 AK28 AJ27 AL28 AL27 AJ26 AK26 AL26 AK25 AL25 AJ24
I/O 38 I/O 39 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 I/O 48 I/O 49 I/O 50 I/O 51 I/O 52 I/O 53 I/O 54 I/O 55 I/O 56 I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 I/O 64 I/O 65 I/O 66 I/O 67 I/O 68 I/O 69 I/O 70 I/O 71 I/O 72 I/O 73 I/O 74 I/O 75
AK24 AL24 AJ23 AL23 AJ22 AK22 AK21 AL21 AJ20 AK20 AL20 AJ19 AL19 AL18 AJ17 AK17 AL17 AJ16 AK16 AJ15 AK15 AL15 AL14 AL13 AJ13 AL12 AK12 AJ12 AL11 AK11 AK10 AJ10 AL9 AJ9 AL8 AK8 AJ8 AL7
I/O 76 I/O 77 I/O 78 I/O 79 I/O 80 I/O 81 I/O 82 I/O 83 I/O 84 I/O 85 I/O 86 I/O 87 I/O 88 I/O 89 I/O 90 I/O 91 I/O 92 I/O 93 I/O 94 I/O 95 I/O 96 I/O 97 I/O 98 I/O 99 I/O 100 I/O 101 I/O 102 I/O 103 I/O 104 I/O 105 I/O 106 I/O 107 I/O 108 I/O 109 I/O 110 I/O 111 I/O 112 I/O 113
AK7 AL6 AK6 AJ6 AL5 AL4 AJ5 AK4 AK3 AJ4 AJ2 AH2 AG3 AH1 AG1 AF3 AF2 AE2 AE1 AD3 AD2 AD1 AC3 AC1 AB2 AA2 AA1 Y3 Y2 Y1 W3 V1 U3 U2 U1 T3 T2 R3
I/O 114 I/O 115 I/O 116 I/O 117 I/O 118 I/O 119 I/O 120 I/O 121 I/O 122 I/O 123 I/O 124 I/O 125 I/O 126 I/O 127 I/O 128 I/O 129 I/O 130 I/O 131 I/O 132 I/O 133 I/O 134 I/O 135 I/O 136 I/O 137 I/O 138 I/O 139 I/O 140 I/O 141 I/O 142 I/O 143 I/O 144 I/O 145 I/O 146 I/O 147 I/O 148 I/O 149 I/O 150 I/O 151
R1 P1 N1 N3 M1 M2 M3 L2 K2 K3 J1 J3 H1 H2 G1 G2 F1 F2 F3 E1 D1 D2 C2 D3 C4 B4 C5 A4 A5 C6 B6 A6 B7 A7 C8 B8 A8 C9
I/O 152 I/O 153 I/O 154 I/O 155 I/O 156 I/O 157 I/O 158 I/O 159 I/O 160 I/O 161 I/O 162 I/O 163 I/O 164 I/O 165 I/O 166 I/O 167 I/O 168 I/O 169 I/O 170 I/O 171 I/O 172 I/O 173 I/O 174 I/O 175 I/O 176 I/O 177 I/O 178 I/O 179 I/O 180 I/O 181 I/O 182 I/O 183 I/O 184 I/O 185 I/O 186 I/O 187 I/O 188 I/O 189
A9 C10 B10 B11 A11 C12 B12 A12 C13 A13 A14 C15 B15 A15 C16 B16 C17 B17 A17 A18 A19 C19 A20 B20 C20 A21 B21 B22 C22 A23 C23 A24 B24 C24 A25 B25 A26 B26
I/O 190 I/O 191 I/O 192 I/O 193 I/O 194 I/O 195 I/O 196 I/O 197 I/O 198 I/O 199 I/O 200 I/O 201 I/O 202 I/O 203 I/O 204 I/O 205 I/O 206 I/O 207 I/O 208 I/O 209 I/O 210 I/O 211 I/O 212 I/O 213 I/O 214 I/O 215 I/O 216 I/O 217 I/O 218 I/O 219 I/O 220 I/O 221 I/O 222 I/O 223
C26 A27 A28 C27 B28 B29 C28 D29 C30 D30 E29 D31 E31 F29 F30 G30 G31 H29 H30 H31 J29 J31 K30 L30 L31 M29 M30 M31 N29 P31 R29 R30 R31 T29
12
9
I/O 152 GND I/O 151 NC1
8
I/O 150 I/O 149 I/O 148 NC1
7
I/O 147 I/O 146 NC
1
6
I/O 145 I/O 144 I/O 143 NC1
5
I/O 142 GND I/O 140 NC1
4
I/O 141 I/O 139 I/O 138 NC1 NC1 NC1 NC
1
3
VCC NC1 NC
1
2
GND NC1 I/O 136 I/O 135
1
GND GND VCC I/O 134 I/O 133 I/O 130 I/O 128 I/O 126 I/O 124 VCC Y2 I/O 118 I/O 116 I/O 115 I/O 114 GND I/O 110 I/O 107 GOE 1 I/O 105 I/O 102 VCC I/O 99 I/O 97 I/O 94 Y4 I/O 90 I/O 89 VCC GND GND
GND NC1 I/O 198 I/O 199 GND I/O 204 I/O 205 I/O 208 GND I/O 212 I/O 213 I/O 216 GND VCC I/O 221 I/O 0 Y0 VCC GND I/O 7 I/O 9 I/O 10 GND I/O 15 I/O 17 I/O 19
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL
NC1
NC1
NC1
NC1
NC1
NC1
I/O 137
I/O 131 I/O 129 I/O 127 GND I/O 122 I/O 121 I/O 119 GND VCC GOE 0 I/O 112 I/O 109 VCC GND I/O 104 I/O 101 I/O 100 GND I/O 96 I/O 93 I/O 92 GND I/O 87 I/O 86 NC1 GND
I/O 206 I/O 209 I/O 211 VCC I/O 214 I/O 217 Y1 I/O 219 I/O 222 GND I/O 2 I/O 3 I/O 4 I/O 6
RESET
I/O 207 I/O 210 TDI/ SDI NC1 I/O 215 I/O 218 NC
1
NC1 NC1 NC
1
NC1 NC1 NC
1
TOE I/O 125 I/O 123 NC1 I/O 120 I/O 117 NC
1
NC1 NC1 NC
1
ispLSI 3448
Bottom View
NC1 NC1 NC
1
I/O 113 I/O 111 I/O 108 NC1 I/O 106 I/O 103 NC
1
VCC I/O 12 I/O 14 I/O 16 I/O 18 I/O 21 I/O 22 VCC GND GND
I/O 11 I/O 13
NC1 NC1
NC1 NC1 NC NC
1
Y3 I/O 98 I/O 95 NC
1
NC
NC
I/O 20
NC1 NC1 NC1 I/O 26 I/O 28 I/O 30 NC1 I/O 29 GND I/O 31 NC1 I/O 32 I/O 33 I/O 34 NC1 NC
1
NC1 NC1 NC1 I/O 37 I/O 38 I/O 39 NC1 I/O 40 GND I/O 41 NC1 I/O 42 I/O 43 VCC NC1 NC
1
NC1 NC
1
NC1 NC
1
NC1 NC
1
NC1 NC
1
I/O 27 VCC
I/O 35 I/O 36
I/O 44 I/O 45
VCC I/O 51
VCC I/O 60
I/O 67 I/O 66
I/O 76 I/O 75
I/O 84 VCC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
1. NCs are not to be connected to any active signals, VCC or GND. Note: Ball A1 indicator dot on top side of package.
13
X
Grade Blank = Commercial Package B432 = BGA Power L = Low
0212/3448
Ordering Information
COMMERCIAL
FAMILY ispLSI fmax (MHz) 90 70 tpd (ns) 12 15 ORDERING NUMBER ispLSI 3448-90LB432 ispLSI 3448-70LB432 PACKAGE 432-Ball BGA 432-Ball BGA
Table 2-0041/3448
14