Code No: R05311403 Set No.

1
III B.Tech I Semester Regular Examinations, November 2007
SWITCHING THEORY AND LOGIC DESIGN
(Mechatronics)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. Convert the following to Decimal and then to Hexadecimal.

(a) 32148
(b) 45678
(c) 101011012
(d) 11001012
(e) 75610
(f) 53310 [3+3+3+3+2+2]

2. (a) Express the following functions in sum of minterms and product of maxterms.
[8]
i. (xy + z) ( y + xz)
ii. B’D + A’D + BD
(b) Obtain the complement of the following Boolean expressions. [8]
i. AB’C + AB’D + A’B’
ii. A’B’C + ABC? + A’B’C’D
iii. ABCD + ABC’D’ + A’B’CD
iv. AB + ABC’

3. Minimize
P the the following multiple output functions.
f1 = P m(0, 2, 6, 10, 11, 12, 13) + d(3, 4, 5, 14, 15)
f2 = m(1, 2, 6, 7, 8, 13, 14, 15) + d(3, 5, 12). [16]

4. (a) Design a 32:1 Multiplexer using two 16:1 and 2:1Multiplexers.

(b) Design a circuit to convert Excess-3 code to BCD code Using a 4-bit Full
adder. [8+8]

5. (a) List the PLA programming table for the BCD to excess-3 code converter.
(b) A ROM chip of 4,096 x 8 bits has two clip select inputs and operates from
a 5-volt power supply. How many pins are needed for the integrated circuit
package? Draw the block diagram of this ROM. [8+8]

6. (a) Find a modulo-6 gray code using k-Map & design the corresponding counter.
(b) Compare synchronous & Asynchronous. [10+6]

1 of 2
Code No: R05311403 Set No. 1
7. A clocked sequential circuit is provided with a single input x and single output Z.
Whenever the input produce a string of pulses 1 1 1 or 0 0 0 and at the end of the
sequence it produce an output Z = 1 and overlapping is also allowed.

(a) Obtain State - Diagram.

(b) Also obtain state - Table.
(c) Find equivalence classes using partition method & design the circuit using D
- flip-flops. [4+4+8]

8. (a) Draw the ASM chart for the following state transistion, start from the initial
state T1 , then if xy=00 go to T2 , if xy=01 go to T3 , if xy=10 go to T1 , other
wise go to T3 .
(b) Show the exit paths in an ASM block for all binary combinations of control
variables x, y and z, starting from an initial state. [8+8]

⋆⋆⋆⋆⋆

2 of 2
Code No: R05311403 Set No. 2
III B.Tech I Semester Regular Examinations, November 2007
SWITCHING THEORY AND LOGIC DESIGN
(Mechatronics)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. Convert the following to Binary and then to gray code.

(a) 101016
(b) AB3316
(c) 33238
(d) 17648
(e) 18710
(f) 226610 [2+2+2+2+4+4]

2. (a) Reduce the following Boolean expressions. [8]

i. B ‘C’D + (B + C + D)’ + B’C’D’E
ii. AB + (AC)’ + AB’C(AB + C)
iii. A’B’C’ + A’BC’ + AB’C’ + ABC’
iv. A + B + A’B’C
(b) Obtain the complement of the following Boolean expressions. [8]
i. x’y’ + xy + x’y
ii. xy’ + y’z’ + x’z’
iii. x? + xy + xz’ + xy’z’
iv. (x + y)(x + y’)

3. (a) Explain ,the determination of all possible minimal expressions from a reduced
prime implicant chart. [8]
(b) Make a K-map of the following expression and obtain the minimal SOPand
POS forms. (AC̄) + (AB) + (C) + (AD) + (AB̄C) + (ABC). [8]

4. Implement
P the following Boolean function by a Hazard free OR-AND network.
f = m(3, 4, 5, 7) and explain in detail what are the Hazards encountered in
implementing the above function. [16]

5. (a) Derive the PLA programming table for the combinational circuit that squares
a 3 bit number.

1 of 2
Code No: R05311403 Set No. 2
(b) For the given 3-input, 4-output truth table of a combinations circuit,tabulate
the PAL programming table for the circuit. [8+8]
Inputs Output
x y z A B C D
0 0 0 0 1 0 0
0 0 1 1 1 1 1
0 1 0 1 0 1 1
0 1 1 0 1 0 1
1 0 0 1 0 1 0
1 0 1 0 0 0 1
1 1 0 1 1 1 0
1 1 1 0 1 1 1

6. (a) Give the design of 4 bit Ring counter and explain a with the waveforms. Also
give the application of this ring counter.
(b) Design a modulo-9 counter T flipflops with preset and clear inputs. [8+8]

7. (a) Find the minimal table equivalent to the state table given below:
(b) And obtain equivalent classes using partition method. [8+8]
Present state Next State q v+1 Output Z
q v
x=00 01 10 11 00 01 10 11
1 6 2 1 1 0 0 0 0
2 6 3 1 1 0 0 0 0
3 6 9 4 1 0 0 1 0
4 5 6 7 8 1 0 1 0
5 5 9 7 1 1 0 1 0
6 6 6 1 1 0 0 0 0
7 5 10 7 1 1 0 1 0
8 6 2 1 8 0 0 0 0
9 9 9 1 1 0 0 0 0
10 6 11 1 1 0 0 0 0
11 6 9 4 1 0 0 1 0

8. (a) Draw the ASM chart for the following state transistion, start from the initial
state T1 , then if xy=00 go to T2 , if xy=01 go to T3 , if xy=10 go to T1 , other
wise go to T3 .
(b) Show the exit paths in an ASM block for all binary combinations of control
variables x, y and z, starting from an initial state. [8+8]

⋆⋆⋆⋆⋆

2 of 2
Code No: R05311403 Set No. 3
III B.Tech I Semester Regular Examinations, November 2007
SWITCHING THEORY AND LOGIC DESIGN
(Mechatronics)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) Perform subtraction with the following unsigned decimal numbers by taking
10’s complement of the subtrahend. Verify the result. [4 X 3 = 12]
i. 5250- 1321
ii. 1753 - 8640
iii. 20 - 100
iv. 1200 - 250
(b) Convert the given gray code number to equivalent binary [4]
1001001011110010

2. (a) Draw the logic diagram corresponding to following expressions without sim-
plifying them. [8]
i. (A + B) (C + D) ( A’ + B + D)
ii. (AB + A’B’)(CD’ + C’D)
(b) Obtain the complement of the following Boolean expressions. [8]
i. x’yz + x’yz’ + xy’z’ + xy’z
ii. x’yz + xy’z’ + xyz + xyz’
iii. x’z + x’y + xy’z + yz
iv. x’y’z’ + x’yz’ + xy’z’ + xy’z + xyz’

3. (a) What are dominating rows & dominating columns? [4]

(b) Minimize the following
P function using tabular minimization
F (A, B, C, D) = m(1, 2, 3, 5, 9, 12, 14, 15) + d(4, 8, 11) [12]

4. (a) Design a 32:1 Multiplexer using two 16:1 and 2:1Multiplexers.

(b) Design a circuit to convert Excess-3 code to BCD code Using a 4-bit Full
adder. [8+8]

5. (a) Given a 32 x 8 Rom chip with an enable input, show the external connection
necessary to construct a 128 x 8 Rom with four chips and a decoder.
(b) Tabulate the PLA programming table for the four Boolean functions listed
below
A(x,y,z) = ε(1, 2, 4, 6)
B(x,y,z) = ε(0, 1, 6, 7)
C(x,y,z) = ε(2,6)
D(x,y,z) = ε(1, 2, 3, 5, 7). [8+8]

1 of 2
Code No: R05311403 Set No. 3
6. (a) Design a sequence detector which detects 110010 Implement the sequence
detector by using D - type flipflops
(b) Classify the required circuits into synchronous, asynclironus, clockmode, pulse
mode with suitable examples. [8+8]

7. A clocked sequential circuit is provided with a single input x and single output Z.
Whenever the input produce a string of pulses 1 1 1 or 0 0 0 and at the end of the
sequence it produce an output Z = 1 and overlapping is also allowed.

(a) Obtain State - Diagram.

(b) Also obtain state - Table.
(c) Find equivalence classes using partition method & design the circuit using D
- flip-flops. [4+4+8]

8. (a) Draw the ASM chart for the following state transistion, start from the initial
state T1 , then if xy=00 go to T2 , if xy=01 go to T3 , if xy=10 go to T1 , other
wise go to T3 .
(b) Show the exit paths in an ASM block for all binary combinations of control
variables x, y and z, starting from an initial state. [8+8]

⋆⋆⋆⋆⋆

2 of 2
Code No: R05311403 Set No. 4
III B.Tech I Semester Regular Examinations, November 2007
SWITCHING THEORY AND LOGIC DESIGN
(Mechatronics)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. Convert the following to Decimal and then to Octal.

(a) 423416
(b) 125F16
(c) 100100112
(d) 101111112
(e) 39210
(f) 77910 [3+3+3+3+2+2]

2. (a) Simplify the following Boolean expressions. [8]

i. A’C’ + ABC + AC’ to three literals
ii. (x’y’ + z)’ + z + xy + wz to three literals
iii. A’B(D’ + C’D) + B(A +A’CD) to one literal
iv. (A’ + C)(A’ + C’)(A + B + C’D) to four literals
(b) Obtain the complement of the following Boolean expressions. [8]
i. B’C’D + (B + C + D)’ + B ’C’D’E
ii. AB + (AC)’ + (AB + C)
iii. A’B’C’ + A?BC’ + AB’C’ + ABC’
iv. AB + (AC)’ + AB’C

3. Minimize the following function using tabular

P minimization and verify the same
with K-map minimization F (A, B, C, D) = m(0, 1, 2, 5, 7, 8, 9, 10, 13, 15). [8+8]

4. (a) Design a 32:1 Multiplexer using two 16:1 and 2:1Multiplexers.

(b) Design a circuit to convert Excess-3 code to BCD code Using a 4-bit Full
adder. [8+8]

5. Write a brief note on:

(a) Architecture of PLDs

(b) Capabitation and the limitations of threshold gates. [8+8]

6. (a) Compare synchronous & Asynchronous circuits

(b) Design a Mod-6 synchronous counter using J-K flip flops. [6+10]

1 of 2
Code No: R05311403 Set No. 4
7. (a) Convert the given Mealy machine to Moore Machine.
Present State Next State Output
x=0 x=1
P R,0 Q, 0
Q P,1 S,0
R Q,1 P,1
S S,1 R,0
(b) Give the state diagram of a binary serial adder and design the circuit for carry
output using D - flip-flop. [8+8]

8. (a) Draw the ASM chart for the following state transistion, start from the initial
state T1 , then if xy=00 go to T2 , if xy=01 go to T3 , if xy=10 go to T1 , other
wise go to T3 .
(b) Show the exit paths in an ASM block for all binary combinations of control
variables x, y and z, starting from an initial state. [8+8]

⋆⋆⋆⋆⋆

2 of 2