Journal of ELECTRONIC MATERIALS, Vol. 33, No.

10, 2004

Special Issue Paper

Under Bump Metallurgy Study on Copper/Low-k Dielectrics for Fine Pitch Flip Chip Packaging
SEUNG WOOK YOON,1,2 VAIDYANATHAN KRIPESH,1 SU YONG JI JEFFERY,1 and MAHADEVAN K. IYER1
1. Institute of Microelectronics, Singapore Science Park II, Singapore 117685. 2.E-mail: yoonsw@ime.a-star.edu.sg

Because the semiconductor speed increases continuously, more usage of low-k dielectric materials to enhance the performance in Cu chips has taken place over the past few years. The implementation of copper (Cu) as an interconnect, in conjunction with the ultra-low-k materials as interlevel dielectrics or intermetal dielectrics in the fabrication of ultra-large-scale integrated circuits, has been used in the semiconductor community worldwide, especially for high-speed devices. The objective of this study is to investigate the under bump metallurgy (UBM) characterization with low-k dielectric material used in damascene Cu-integrated circuits. This paper focuses on electroless Ni/Au, Cu/Ta/Cu, and Ti/ Ni(V)/Cu/Au UBM fabrication on 8-in. damascene Cu wafers and ip chip package reliability with Pb-bearing and Pb-free solders. The interfacial diffusion study and bump shear test were carried out to evaluate the bump bonding, and the failure was analyzed with optical microscopy, scanning electron microscopy (SEM), and transmission electron microscopy (TEM). In order to investigate the thermal stability of the UBM system with Pb-free solder, high-temperature aging (above the melting temperature) was performed and each interface between the solder and UBM was observed with optical microscopy, SEM, and TEM, respectively. The failures observed and the modes are reported in the paper. Key words: Under bump metallurgy (UBM), Cu/low-k, dielectrics, packaging

INTRODUCTION As CMOS transistor scaling proceeds into the deep submicron regime, the number of transistors on high-performance, high-density ICs is in the tens of millions, in accordance with the historical trend of Moores Law. The signal integration of this many active elements has necessitated that such ICs feature as many as eight layers of high density metal interconnect. The electrical resistance and parasitic capacitance associated with these metal interconnections has become a major factor that limits the circuit speed of such high-performance ICs. It is also the fundamental motivating factor causing the semiconductor industry to move away from aluminum to copper (Cu) as chip metallization and from SiO2 to low-k dielectric materials as interlayer dielectrics and intermetal dielectrics.13
(Received March 12, 2004; accepted April 22, 2004) 1144

Copper reduces the resistance of the metal interconnect lines (and increases their reliability), while low-k dielectrics reduce the parasitic capacitance between the metal lines. Low-k materials are mechanically, chemically, thermally, and electrically less stable than the historical material of choice, SiO2. Therefore, the challenge lies not only in identifying and characterizing the candidate materials, but also in devising the best methods to integrate those materials. The International Technology Roadmap for Semiconductors has identied the under bump metallurgy (UBM) integrity and underll compatibility as a key area of challenge in the Cu/low-k integrated circuits assembly and packaging.3 The impact of UBM integrity in Cu metallization has been reported,4 and the major failure mechanism observed is UBM metal peeling from low-k dielectric. However, investigations with different UBM metallizations and failure analyses of UBM

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with Cu in the metallization process, particularly with low-k dielectrics, are lacking. This study investigates UBM characterization of the ip chip packaging with low-k dielectric material used in Cu damasceneintegrated circuits. This paper focuses on electroless Ni/Au, Cu/Ta/Cu, and Ti/Ni(V)/Cu/Au UBM fabricated on 200-mm Cu damascene wafers and their package reliability with Pb-free Sn-4.0Ag-0.5Cu solder. EXPERIMENTAL PROCEDURE In this research work, test vehicles are designed based on the in-house fabrication capabilities on 200-mm silicon wafer. Silicon wafer with a thin layer of undoped silica glass (USG, SiO2) and low-k is used to fabricate backend of line (BEOL) damascene Cu interconnects. Damascene structures are fabricated with a Cu seed layer and the electroplated Cu encapsulated by a Tantalum (Ta) barrier layer along the bottom and sidewalls of the metal stripes, as shown in Fig. 1. Test Vehicles The Cu damascene/SiO2 and Cu/low-k test wafers are used in the baseline and fundamental UBM characterization study, which is comprised of Cu a bond pad with a 200-m pitch. In this work, a spinon-dielectrics type low-k dielectric material was used. The bond pad has a passivation opening of 80-m diameter. The chip dimensions are 6.8 mm 7.2 mm. The chip has 29 29 rows and 25 25 depopulation, and thus 216 I/Os. For the ip chip package integration study, low-k/Cu damascene test wafers were fabricated and evaluated. Figure 1 shows the schematics of the stack structure and test vehicles. The physical dimensions of the die are the same for both Cu/SiO2 and Cu/ultra low-k test wafers. UBM Preparation The electroless Ni/Au chemical process on the Cu chip is established on 200-mm Si wafers with low-k dielectric. The process optimization is carried out with emphasis on uniform electroless Ni/Au bump thickness, low surface roughness, and bump bonding

strength. Cu/Ta/Cu and Ti/Ni(V)/Cu/Au are deposited on the 200-mm test wafers using a physical vapor deposition process. A detailed process optimization is carried out to select the thickness of respective metallizations. Electroless Ni/Au The bond pads of semiconductor devices require pretreatment steps to enable the deposition of electroless Ni plating. To begin with, a mixture of H2SO4 and HNO3 is used to clean the Cu surface. Following this, the surface is activated by exposure to palladium. For the plating of electroless Ni on the Pd-activated bond pads, acid-based Ni solution is prepared. It is an acidic hypophosphoite bath with a pH value of 4.04.4 (nominal 4.2). The bath temperature is controlled at 85C using a heating element and is stirred using a magnetic stirrer bar. The deposited thickness of Ni is about 4 m. After Ni plating, thin gold is deposited with an immersion process at 85C (1000- thickness). Cu/Ta/Cu The refractory metals Ta, Ti, W, Mo, Nb, and Ti-W, because of their high melting temperatures and low diffusivity, are applicable as a barrier layer for Cu. Especially, the diffusivity of Ta in Cu is 9 10 4 cm2/sec in the temperature range of 400700C and the high melting temperature, 2996C, of Ta produces a high-temperature stability. Both Ta and Cu exhibit very limiting mutual solid solubility for each other and will not form any compound.5 The UBM process can be incorporated into a BEOL of Cu/low-k integration, since Ta deposition and plating of Cu are general process modules in the Cu/low-k integration process. So the feasibility and thickness effect of Ta as a barrier layer for solder bumps is investigated. In this study, Ta thickness is 500 , 1000 , and 2000 , and the thickness of the top Cu layer is 1 m. Ti/Ni(V)/Cu/Au It has been reported that Al/Ni(V)/Cu is a stable UBM for eutectic and Pb-free solder in comparison

c a b Fig. 1. Schematics of stack structure of (a) SiO2/Cu, (b) low-k/Cu wafers, and (c) layout of test vehicles.

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Table I. The Thickness of Each Layer for Ti/Ni(V)/Cu/Au UBM Processes (m) Ti 1 2 3 0.1 0.1 0.1 NiV 0.3 0.8 0.8 Cu 0.7 1 Au 0.1 0.1 0.1

with AlNi(V).6,7 As a top metallization, Au usually provides oxidation and corrosion protection to the Ni layer underneath during storage. In general, the Ti layer is the adhesion layer and Ni plays the role of diffusion barrier. So, in this work, three different thickness Ti/Ni(V)/Cu/Au UBM processes are selected and the role of the Cu layer between the Ni and Au layers is investigated for lead-free solder, as shown in Table I. Solder Bumping Process A photosensitive negative dry lm resist is laminated to the wafer, which is hardened and insoluble when exposed to light. First, dry lm with 100-m thickness is laminated on the wafers. Then, the laminated wafer is exposed to UV light with a bright-eld bump mask. Dry lm development is performed in a spray spin tool using sodium carbonate. Sn-4.0Ag0.5Cu Pb-free solder paste printed on the dry lm laminated wafers and squeezed with polyurethane blade. Reow is carried out in a N2 atmosphere using a six-zone reow oven and is maintained above the liquidus temperature (220C) for about 60 seconds. After stripping the dry lm with sodium hydroxide at 60C, reow is performed once more at the same prole. As the dry lm restricts the solder ow during the post-print reow, a second reow is needed to ensure complete solder coalescence. The height of the solder bump is about 110 m. Figure 2 shows the scanning electron microscopy (SEM) micrographs of solder bump on the Cu interconnect test vehicle. Thermal Aging During the bumping or soldering process, the intermetallic compound (IMC) forms at the interface between the solder and substrate. The initial formation of the IMC at the interface indicates good metallurgical bonding. However, the IMCs that grow during aging and eld service inuence the interfacial microstructure and the strength, and affect the mechanical solder joint reliability.8 In order to study the interfacial reaction with diffusion at the interface, the solder-bumped samples were subjected to a thermal aging test at 250C for 10, 20, and 30 min, respectively, in a N2 atmosphere box oven in order to evaluate the UBM stability and solder bump integrity. This severe thermal aging condition was used to explore the accelerated condition to investigate the UBM characterization with the lead-free soldering process. With this high-temperature process, similar solder bulk microstructures are expected to have different IMC

Fig. 2. SEM micrographs of solder bump on the Cu interconnect test vehicle.

morphologies because there would be no grain growth or coarsening in the bulk solder. Microstructure Observation In order to study the interfacial reactions after heat treatment, the samples are cross-sectioned, ground, and polished up to 1 m using diamond suspensions. The interfacial microstructure observation is performed using optical microscopy and SEM (JEOL JSM-5600LV scanning electron microscope; Japan Electron Optics Ltd., Tokyo) equipped with an Oxford INCA energy-dispersive spectrometer and Hitachi S-4100 scanning electron microscope. For further diffusion study between UBM and the solder, a Philips CM-200 FEG transmission electron microscope was used. Bump Shear Test A solder bump shear test (BST) is performed using a Dage-24T shear tester on samples as-cast and after aging at 250C. The tool lift-off height is set at 20 m and a shear speed of 0.25 mm/s is selected for a 200-m width shear tool. A total of 30 bump shear readings are taken at different locations for each test chip. The sheared surfaces are examined using the optical microscopy and electron microscopy Flip Chip Packgaing A ip chip package assembly of 27 mm 27 mm BGA is carried out to investigate the reliability with the ip chip package. So, a two metal layer daisy chain BT substrate was prepared, as shown in Fig. 3. After ip chip die fabrication with bump, the die attachment was carried out with a KME ip chip bonder (FB30T-M). No-cleaning type ux was used for bonding. After ip chip die attachment, the samples were reowed in a reow furnace with Tmax 255C, and then underlled with capillary ow. The resistance was measured to check the daisy chain interconnection, and then the samples were sent for reliability tests. Details of the reliability tests are

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Fig. 3. Daisy-chained BT substrate for ip chip packaging.

Table II. Reliability Test Conditions Reliability Tests Temperature cycle ( 40C to 125C, JESD22-A 104-A, condition B) Thermal shock ( 55C to 125C, JESD22-A106-A, condition C) Reliability Level 1000 cycles 1000 cycles

described in Table II. The failure criterion was a 20% increase of the initial resistance of the overall daisy chain. RESULTS AND DISCUSSION UBM Study with SiO2/Cu Wafers Interfacial Microstructure: Electroless Ni/Au UBM The electroless Ni/Au UBM is one of the most commonly used metallurgical structures for the

bumping process. The SEM micrographs of the samples as-reowed and then aged at 250C for 30 min are shown in Fig. 4. The Ni3Sn4 (IMC) is found at the interface and after aging at 250C; the Ni layer is quite good at withstanding the diffusion into the solder and played a role as a barrier layer. With energy-dispersive x-ray (EDX) line scanning, we conrm the stability of the Ni layer after aging. Figure 5 shows the transmission electron microscopy (TEM) micrographs of the interface between the Ni solder and the Cu pad-Ni, respectively. The Ni-Sn-P IMC is found at the interface region and the P content continuously changes with distance. From the TEM analysis, the evidence of the higher P concentration at the interface between the solder and UBM is clearly seen. The as-deposited P concentration is 13 at.%, from the TEM/EDX analysis. This analysis clearly shows that, with the Ni diffusion into Sn, the P concentration increases at the interface to

Fig. 4. SEM micrographs of electroless Ni/Au UBM of sample (a) as-cast and (b) aged at 250C for 30 min.

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Fig. 5. TEM micrographs of interfacial region of sample aged at 250C for 30 min. (a) Ni and SnAgCu solder; and (b) Ni and Cu .

22 at.%, followed by 20 at.%. It shows a gradient of P concentration from 22 at.% to 13 at.% with an increase of P at the interface. It decreases the Ni diffusion into the solder, making Ni a good barrier layer. There is no major interaction between Cu and Ni, as shown in Fig. 5b, but a CuNiP IMC was found, with chemical composition Cu:Ni:P 37:53:11. With SEM and TEM works, a 4-m-thick Ni layer is quite good as a diffusion barrier for lead-free solder application. Interfacial Microstructure: Cu/Ta/Cu UBM In this study, the effect of the thickness of the Ta layer is investigated for UBM stability. So, three different Ta layers are prepared: 500 , 1000 , and 2000 . Figure 6 shows that the all Ta layer remained at 250C for 30 min after reow and aging. However, the top Cu layer nearly dissolved and formed Cu6Sn5 IMC, and the Cu6Sn5 IMC phase formed locally and nonuniformly along the interface. Its shape is octagonal and is identied as Cu6Sn5 IMC by microetching, SEM, and EDX. Interfacial Microstructure: Ti/Ni(V)/Cu/Au UBM The Ni UBM system forms a IMC with Sn, but the IMC growth rate is slower than that of Cu. In this study, we investigate the microstructural change with or without Cu between the Ni and Au layers. As shown in Fig. 7, Ti/Ni(V)/Au UBM without Cu shows the IMC spalling from the interface just after reow. The spalled IMC composition was Sn:Ni 62:38, thus Ni3Sn4 IMC. But for Ti/Ni(V)/Cu/Au UBM processes, as shown in Fig. 8, even after aging at 250C for 30 min, no UBM spalling was seen. There was a signicant change in microstructures of the solder bump joint after aging, as shown in Fig. 8. It must be related with dissolution and precipitation

during aging. As the time of aging increased, the Cu6Sn5 IMCs grew at the interface and their size increased, probably by coarsening, and eventually they formed a continuous IMC layer. Fig. 9a shows that the Ni(V) layer was strong enough to withstand high-temperature aging and there was not any other reaction. The TiNi IMC was formed between the Ti and Ni(V) layers, as shown in Fig. 9b. Bump Shear Strength: Electroless Ni/Au UBM According to Fig. 10a and b, electroless Ni/Au UBM shows that the cohesive solder failure and its shear strength are fairly consistent up to aging at 250C for 30 min, as shown in Fig. 10c. As mentioned in the above section, the Ni layer is shown to be quite a good barrier layer for Cu and Sn diffusion, showing very good adhesion properties. Bump Shear Strength: Cu/Ta/Cu UBM After the BST test, Cu/Ta/Cu shows lower adhesion strength in comparison with electroless Ni/Au. As shown in Fig. 11, the strength is about 20 gf. The thickness effect of the Ta layer for shear strength is not critical. After aging at 250C for 30 min, the strength slightly decreases for all tested samples. As shown in Fig. 12a, the failure is found at the Ta/Cu interface. As described at the interfacial microstructural part, the top Cu layer is dissolved and forms the Cu6Sn5 IMC. The total consumption of Cu causes dewetting of solder, and its IMC formation is not uniform, not continuous, and partially localized. This is in agreement with the interfacial microstructure, as shown in Fig. 6, where IMC phases are totally localized. More localized IMC formation is found after aging at 250C for 30 min. Thus, this interfacial microstructure change results

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Fig. 6. Micrographs of (a) and (b) Cu/500 Ta/Cu UBM system of samples as-cast and aged at 250C for 30 min; and (c) and (d) Cu/1000 Ta/Cu UBM system of samples as-cast and aged at 250C for 30 min.

in the slightly lower shear strength after heat treatment. With EDX analysis of Fig. 12c and d, the background of failure site is identied to be a mixture of Cu and Ta layers with the remaining part being solder materials. A 1-m-thick Cu layer is too thin for SnAgCu Pb-free solder. So, increasing the top Cu thickness is one way to increase the adhesion strength. Nah and Baik9 reported that thicker Cu layers show cohesive solder failure and unreacted Cu layer plays an important role as a stress buffer

layer for thick Cu UBM. Using the electroplating method, the 5-m-thick Cu layer was deposited on the Cu/Ta/Cu UBM, and its shear value increased from 20 gf (thin top 1 m)Cu to 50 gf (thick 5-m EPCu). However, the major failure site was found to be the intermetallic layers (-Cu6Sn5), which is due to too thick of an IMC formation, as shown in Fig. 13. Bump Shear Strength: Ti/Ni(V)/Cu/Au UBM Figure 14 shows the variation of the shear strength as a function of aging time for Ti/Ni(V)/

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Fig. 7. (a) Micrograph of Ti/NiV/Au UBM with Pb-free solders and (b) EDX results at the arrow of (a).

(Cu)/Au UBMs. Overall, Ti/Ni(V)/Cu/Au showed a tendency to maintain the stable shear strength with aging times. However, Ti/Ni(V)/Au without Cu showed a decrease of shear strength with aging time. Ti/Ni(V)/Cu/Au had a continuous intermetallic layer and there was no IMC separation from the interface. However, as shown in Fig. 7a, Ti/Ni(V)/Au had an IMC separation from the interface and formed island-type IMCs in the solder bulk. The sudden decrease of the solder joint strength after aging can be related to the coarsened morphology of the separated Ni3Sn4 IMC. Coarsening of the interfacial particles Ni3Sn4 degraded the strength of solder itself and the solder joint. Even after aging at 250C for 30 min, the failures are found at the solder region, not at the interface. The Ti/Ni(V)/Au had a fractured surface morphology, showing that failure looked different; however, from the EDX analysis, it could be concluded that the failure is in the bulk solder very close to the IMC. Ti/Ni(V)/Cu/Au 1 and Ti/Ni(V)/Cu/Au 3 showed solder cohesive failure for both as-cast and aged at 250C for 30 min conditions, which is an acceptable failure mode in the industry. There was a difference in shear strength between Ti/Ni(V)/Cu/Au UBMs. The thicker UBM showed less bump shear strength. The thicker metal lm layer is known to increase the overall UBM lm stress because Cu and Ni(V) have tensile stress. It may also affect the UBM adhesion strength with solder. Higher Cu and Ni(V) content also could change the interface and solder microstructure, which affects the bump shear strength. Flip Chip UBM Integrity Study with Hybrid Low-k/Cu Wafer In order to investigate the UBM reliability study on the low-k/Cu wafer, solder bumps on electroless Ni/Au and Ti/Ni(V)/Cu/Au with low-k/Cu wafer are prepared by the same process as that for the UBM study. After the bump shear test, UBM failure is found. Using SEM/EDX analysis, the failure is

located at the interface between Ta and low-K materials, as shown in Fig. 15, and its adhesion strength is between 25 and 30 gf. Same failure mode is also found after two different types of heat treatment: multiple reow and high-temperature storage test. So, a different stack structure was introduced and additional SiO2 layer was deposited on the low-k dielectrics layer, as shown Fig. 16. Then, solder was bumped on the test vehicles with two different UBM processes: electroless Ni/Au and Ti/Ni(V)/Cu/Au. Solder cohesive failure was found with both UBM processes, as shown in Fig. 17. Using the hybrid type Cu/low-k test vehicle of Fig. 16, a ip chip package assembly of 27 27 mm BGA is carried out to investigate the reliability with the ip chip package. The ip chip package is tested as the temperature cycle and temperature shock. For ip chip bump solder joints, the Weibull parameters were determined by tting to the daisy chain ip chip unit sample data and can be expressed as x f (x) = 1 exp

where x is the number of cycles, f(x) is the failure rate after x cycles, is the characteristic lifetime, and is the shape parameter (Weibull slope). Figure 18 showed the logarithm Weibull plot of the accumulated failure rate of thermal shock (TS) and temperature cycle (TC). The characteristic lifetime of the TS and TC tests are 1668 cycles and 1890 cycles, respectively. These SiO2/low-k hybrid ip chip packages passed the 1000 cycles of TC and TS. The rst TC failure was found after 1200 cycles. CONCLUSIONS Electroless Ni/Au and Ti/Ni(V)/Cu/Au UBM processes show reasonable thermal stability and have solder cohesive failure after BST. Cu/Ta/Cu is one of the most promising processes because Ta and Cu processes are now used at the low-k/Cu interconnect process. After BST and EDX, the failure is mostly

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Fig. 8. Micrographs of Ti/Ni(V/)Cu/Au 1 UBM sample (a) as-cast and (b) aged at 250C for 30 min; and Ti/Ni(V)/Cu/Au 3 UBM sample (c) as-cast and (d) aged at 250C for 30 min.

found at the Cu/Ta interface and partially at the solder region. With microstructural observation, the top Cu layer is found to be almost consumed by IMC formation, Cu-Sn IMC. Thus, there is weak bonding between Ta and solder materials due to dewetting of solder. The Ta plays a role as a diffusion barrier of solder, but the adhesion issue can be solved. In order to get more reliable UBM stability, a thicker Cu layer was deposited with electroplating and shear strength was increased. Its failure mode was a mixture of solder and IMC due to thicker IMC formation.

The low-k material used in this experiment showed the dielectrics/metal interfacial failure. It could be due to stress induced from coefcient of thermal expansion mismatch among solder, UBM, Cu, passivation, and dielectrics. High induced stress leads to UBM failure. To obtain a low stress UBM system, the minimization of localized stress is required. More detailed characterization of the UBM system, low-k dielectrics, and their compatibility need to be studied. A simple way to overcome this issue is to have a new stack structure using SiO2 as the top dielectric layer instead of low-k dielectrics.

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Fig. 9. TEM micrographs of interfacial region of sample aged at 250C for 30 min. (a) Ti/NiV/Cu and (b) Ti and Ni.

Fig. 10. Fractographs of the eNiAu UBM system (a) as-cast and (b) aged at 250C for 30 min. (c) BST results with aging time.

So, an additional layer of SiO2 was deposited on the low-k dielectrics layer and showed the solder cohesive failure in BST. The reliabil- ity performance of this new stack scheme test vehicle was evaluated. The ip chip package was assembled using the electroless Ni/Au UBM ip chip. The rst failure was found after 1200 cycles in both TC and TS tests. Thus, Cu/low-k ip chip packages successfully passed the 1000 cycles of TC and TS tests. ACKNOWLEDGEMENTS This work is the result of a project initiated by the IME Wafer Technology Consortium (WTC)Project 1B, the members of which are Amkor Technology Inc, ASM Technology Singapore Pte. Ltd., The Dow Chemical Company, Institute of Microelectronics (IME), Honeywell (S) Pte. Ltd., Motorola SDN, BHD, and ST Assembly Test Services Ltd.

Fig. 11. Plot of results of BST for as-cast and aged sample at 250C for 30 min for Cu/Ta/Cu UBM processes with different Ta thickness.

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Fig. 12. SEM micrographs of samples (a) as-cast and (b) aged at 250C for 30 min of Cu/1000 Ta/Cu. EDX results of (c) location A and (d) location B in (a).

Fig. 13. Micrographs of sample (a) as-cast and (b) aged at 250C for 30 min of electroplated Cu on Cu/1000 Ta/Cu UBM.

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Fig. 14. Plots of BST result for Ti/Ni(V)/Au and Ti/Ni(V)/Cu/Au UBM processes with aging times at 250C.

Fig. 16. New stack structure of hybrid Cu/low-k test vehicle.

Fig. 15. Fractographs of (a) eNi/Au and (b) Ti/Ni(V)/Cu/Au UBM processes of Cu/low-k test vehicle.

Fig. 17. Fractographs of (a) electroless Ni/Au and (b)Ti/Ni(V)/Cu/Au UBM processes of hybrid Cu/low-k test vehicle of Fig. 16.

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Analysis (DMA) group for their advice and support in test vehicle fabrication and failure analysis with SEM/TEM. REFERENCES
1. G. Deltoro and N. Sharif, Proc. The 1999 IEMT/IMC Symposium, pp.185188, Japan (1999). 2. Anatomy of a Breakthrough: How Copper Came of Age, IBM Research, vol. 35, no. 4, (1997). 3. Assembly & Packaging Update, International Technology Roadmap for Semiconductors (2001). 4. Jamin Ling, Joseph Sanchez, Ralph Moyer, Mark Bachman, Dave Stepniak, and Pete Elenius (Paper presented at Proc. 52nd Electronic Components & Technology Conf., May 2002, San Diego, CA). 5. P.R. Subramanian and D.E. Laughlin, Bull. Phase Diagram 10, 652 (1989). 6. C.Y. Liu, K.N. Tu, T.T. Sheng, C.H. Tung, D.R. Frear, and P. Eleniu, J. Appl. Phys. 87, 750 (2000). 7. S.-Y. Jang, J. Wolf , W.-S. Kwon, and K.-W. Paik (Paper presented at Proc. 52nd Electronic Components & Technology Conf., May 2002, San Diego, CA). 8. S.W. Yoon, J.H. Kim, S.W. Jeong, and H.M. Lee, Mater. Trans., JIM 44, 290 (2003). 9. J.-W. Nah and K.-W. Paik, IEEE Trans. Components Packaging Technologies 25, 32 (2002).

Fig. 18. Weibull logarithm plot for TS and TC tests of Cu/low-k ip chip package.

The authors thank Dr. Gopal Krishnan for his precious comments on this paper, and the members from Advanced Interconnect (AI) group, Microsystems Reliability (MR) group, and Device & Materials