Semiconductor memories

Contents
DRAM 3- Transistor DRAM Cell 2- Transistor DRAM Cell 1- Transistor DRAM cell Timing Waveform EE-PROM

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ReadRead-Write Memories (RAM)

DYNAMIC (SRAM)
Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended

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VARIOUS CONFIGURATION OF DRAM CELL

2-T DRAM CELL

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1-T DRAM CELL

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3-TRANSISTOR DRAM CELL WITH PULL UP AND READ/WRITE CIRCUITRY

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VOLTAGE WAVEFORMS WITH 3-T DRAM

Pre-charge Cycle

Charge-sharing during write 1 sequence

Read 1 operation

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Write 0 Sequence

Read 0 cycle

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VOLTAGE WAVEFORMS WITH 3-T DRAM

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LatchLatch-Based Sense Amplifier (DRAM)

EQ BL VDD SE BL

Initialized in its metastable point with EQ Once adequate voltage gap created, sense amp enabled with SE Positive feedback quickly forces output to a stable operating point.
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SE

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Differential Sense Amplifier

VDD M3 M4 y bit M1 M2 bit Out

SE

M5

Directly applicable to SRAMs

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Differential Sensing - SRAM

V DD PC V DD BL EQ WL i x BL y M3 M1 SE M2 M5 V DD M4 2 x x SE V DD 2 y 2 x

SE SRAM cell i Diff. x Sense 2 x Amp V DD y Output

SE Output (a) SRAM sensing scheme

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(b) two stage differential amplifier

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Sense Amp Operation

V BL

V(1) V PRE

DV(1)

V(0) Sense amp activated Word line activated t

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ONEONE-TRANSISTOR DRAM CELL

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One Transistor DRAM circuit

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3-Transistor DRAM Cell

BL 1 WWL RWL M3 M1 CS X M2 WWL RWL X BL 1 BL 2 V DD V DD 2 V T DV V DD 2 V T BL 2

No constraints on device ratios Reads are non-destructive Value stored at node X when writing a 1 = V WWL-VTn
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DRAM memory cells are single ended in contrast to SRAM cells. The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a 1 into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD

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NonNon-Volatile Memories (NVM) Basics

The Floating-gate Avalanche-injection MOS transistor loatingvalanche(FAMOS) FAMOS)
Floating gate Source tox tox n+ Substrate p n+_ S Gate Drain G D

Device cross-section cross-

Schematic symbol

Allow threshold voltage to be altered electrically and retained indefinitely.

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FloatingFloating-Gate Transistor Programming

20 V 5V

VT ~ 7V
10 V S 5V 20 V S - 2.5 V 5V

D 0V

Avalanche injection

Programming results in higher V T . 0V

- 5V S

Removing programming voltage leaves charge trapped

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Note on NVMs
NVM structure is identical to the ROM except that it uses FAMOS transistors or similar devices at the cell level instead. The method of erasing is the main differentiating factor between the classes of NVM The programming of the NVM
Is typically an order of magnitude slower than the reading operation. Requires high voltage power supply - no less than twice the supply voltage need in the reading operation
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EPROM Summary
Based on ROM structure and FAMOS devices. Extremely simple and dense suitable for large dense: low-cost memories that do not require regular programming. Erased by shining UV lights through a transparent window in the package.
UV makes oxide slightly conductive, leaking charges very slowly from the floating gate.
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QuickTime and a TIFF (Uncompressed) decompressor are needed to see this picture.

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EPROM Drawbacks
Erasure process is slow from 10s to 1000s sec and must be done Off System. Limited Endurance Number of erase/program Endurance: cycles is generally limited to at most 1000. Reliability Problems device threshold might Problems: vary with repeated programming.
Use on-chip circuitry to control the threshold voltage to within an acceptable range during programming.

High power dissipation during programming.

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EEPROM: FLOTOX Device

The FLOating-gate Tunneling OXide (FLOTOX) transistor FLOatingOXide
Floating gate Source 2030 nm n1 n1 10 nm Gate Drain -10 V 10 V Substrate p I

V GD

FLOTOX cross section

FowlerFowler-Nordheim I-V characteristic

Injecting electrons onto the gate raises VT. Reverse operation (voltage) lower VT
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Bidirectional Programming
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EEPROM Cell
Absolute threshold control for FLOTOX transistor is hard. Over-erasing programmed transistor might end up with a depletion device.
FLOTOX always ON

BL WL

NMOS

VDD
FLOTOX

Solution: 2 transistor cell

Write FLOTOX Read NMOS
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EEPROM Summary
Larger Area than EPROM of the same capacity
FLOTOX is inherently larger than FAMOS 2T cells as to 1T cell for the EPROM.

Thin oxide is hard to fabricate and expensive.

Cost/bit is higher than the EPROMs

Higher versatility: in situ programming/erasure versatility: Last longer (up to 105 erase/program cycles) but repeated programming can cause VT to drift due to permanently trapped charges in SiO2
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Flash EEPROM: ETOX Device

Control gate
Floating gate erasure n1 source Thin tunneling oxide

programming p- ubstrate s

n1 drain

Many other options

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CrossCross-sections of NVM cells

Flash
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EPROM
Courtesy Intel
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Erase in a NOR Flash Memory

BL 0 array BL 1

G 12 V
0V WL 0

D
12 V 0V WL 1

open

open

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Write in a NOR Flash Memory

12 V G

BL 0
6V

BL 1

12 V
S D

WL 0

0V 0V WL 1

6V

0V

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Read in a NOR Flash Memory

5V G 1V
5V WL 0 BL 0 BL 1

D
0V 0V WL 1

1V

0V

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Advanced 1T DRAM Cells

Word line Insulating Layer Cell plate Capacitor dielectric layer

Cell Plate Si Capacitor Insulator Storage Node Poly Si Substrate 2nd Field Oxide

Refilling Poly

Transfer gate

Isolation Storage electrode

Trench Cell
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StackedStacked-capacitor Cell
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CAM in Cache Memory

Address Decoder

Hit Logic

CAM ARRAY

SRAM ARRAY

Input Drivers

Sense Amps / Input Drivers

Address

Tag

Hit

R/W

Data

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ContentsContents-Addressable Memory (CAM)

I/O Buffers
Data (64 bits)

Commands

Comparand Mask
Address Decoder

Control Logic

R/W Address (9 bits)

CAM Array
29 word x 64 bits

Priority Encoder

29 Validity Bits

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CAM Operations
3 Modes of CAM Operation: Read Write and Match Read, Write, In Match mode, the data are compared to the content in the memories to locate where the data are kept, i.e. its address.
The Comparand keeps the data pattern to match and the Mask indicates which bits are significant. All 512 rows of the CAM array then simultaneously compare the significant bits of the comparand with the data contained in that row. Validity bits are set for the rows that contain matched pattern. If there are more than one matched row, the Row address of the CAM array is used to break the tie. Match Found bit is set if there is a match.
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Static CAM Memory Cell

Bit Word CAM CAM M6 Word M7 Bit Bit Bit Bit M4 M8 M9 M5 Bit

CAM

Word CAM Match S M3 int S M2 M1

Wired-NOR Match Line

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END
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