Digital Circuits &amp Logic Design

Atmiya Infotech
"Yogidham", Kalawad Road, Rajkot Ph : 572365, 576681

||lz| ||rs1|ls
|
|1|s ss|1

PREPARED BY
SONAL CHAVDA
Atmiya Infotech
# Syllabus

Intorduction

Overview of number system and codes. Elements and functions of digital logic gates, gate
propagation delay time, logic gate applications.

Boolean Algebra

Boolean operations, SOP and POS forms, and simplification using Karnaugh maps, realization
of expressions using goals.

Combinational Logical Circuits

Design of binary adder - serial, parallel, carry look ahead type, full subtractor, code
converters, MUX and DMUX, encoders and decoders.

Sequential logical circuits

Flip-flop: R-S, J-K, Master Slave J-K, D and T flip-flop using NAND gates.

Counters

Design of asynchronous and synchronous, up-down and programmable counters.

Registers

Shift registers, various types and their applications.

Detection and correction codes

Detecting and correcting an error.
Atmiya Infotech

# Syllabus........................................................................................................................................ 2
Intorduction............................................................................................................................... 2
Boolean Algebra........................................................................................................................ 2
Combinational Logical Circuits............................................................................................... 2
Sequential logical circuits......................................................................................................... 2
Counters..................................................................................................................................... 2
Registers..................................................................................................................................... 2
Detection and correction codes................................................................................................ 2
#1 Introduction............................................................................................................................... 6
Digital Computers..................................................................................................................... 6
Logic Gates ................................................................................................................................ 6
Gate Propagation Delay ........................................................................................................... 8
Universal Gates ......................................................................................................................... 8
NAND gate as a Universal Gate ............................................................................................. 8
#2 Boolean Algebra...................................................................................................................... 10
Boolean Algebra...................................................................................................................... 10
Boolean Operations................................................................................................................. 10
Basic Identities of Boolean Algebra....................................................................................... 10
DeMorgans theorem.............................................................................................................. 11
Complement of a function...................................................................................................... 12
Simplification using Karnaugh Maps ................................................................................... 12
Variable Maps....................................................................................................................... 12
Sum-of-Products Simplification ............................................................................................ 13
Product-of-Sums Simplification ............................................................................................ 15
NAND and NOR Implementation ........................................................................................ 17
Don't Care Conditions............................................................................................................ 17
#3 Combinational Logical Circuits ............................................................................................. 18
Combinational Circuits .......................................................................................................... 18
Half-Adder............................................................................................................................... 18
Full-Adder ............................................................................................................................... 18
Parallel Adder ......................................................................................................................... 19
Operation............................................................................................................................... 20
Serial Adder............................................................................................................................. 20
Atmiya Infotech
Construction.......................................................................................................................... 20
Operation............................................................................................................................... 21
Subtractors .............................................................................................................................. 22
Half-subtractor ...................................................................................................................... 22
Full-subtractor....................................................................................................................... 22
Code Converters...................................................................................................................... 23
Decoders................................................................................................................................... 25
NAND Gate Decoder............................................................................................................ 27
Decoder Expansion............................................................................................................... 27
Encoders................................................................................................................................... 28
Multiplexer .............................................................................................................................. 29
DeMultiplexer.......................................................................................................................... 29
#4 Sequential logic circuits.......................................................................................................... 32
Flip-flops .................................................................................................................................. 32
SR Flip-Flop ............................................................................................................................ 32
SR Flip-Flop circuit with NAND gate.................................................................................. 33
D Flip-Flop............................................................................................................................... 33
D Flip-Flop with NAND gate ............................................................................................... 34
JK Flip-Flop ............................................................................................................................ 34
T Flip-Flop............................................................................................................................... 35
Master-Slave JK Flip-Flop..................................................................................................... 36
Flip-Flop Excitation Tables.................................................................................................... 37
Sequential Circuits.................................................................................................................. 38
Design Procedure.................................................................................................................. 38
#5 Registers .................................................................................................................................. 39
Registers................................................................................................................................... 39
Shift Registers.......................................................................................................................... 40
Bidirectional Shift Register with parallel load..................................................................... 40
Application of Shift Registers ................................................................................................ 41
#6 Counters .................................................................................................................................. 42
Introduction............................................................................................................................. 42
Binary Counters...................................................................................................................... 42
Synchronous Counters .......................................................................................................... 42
Up counters ....................................................................................................................... 42
Binary Up-Down counters ................................................................................................ 43
Asynchronous counters......................................................................................................... 43
Atmiya Infotech
Up Counters ...................................................................................................................... 43
Down counters .................................................................................................................. 44
Error detection and correction codes.................................................................................... 44
Atmiya Infotech

#1 Introduction

Digital Computers

Digital computers use the binary number system, which has two digits, 0 and 1.
A binary digit is called a bit.
Bits are grouped together as bytes and words to form some type of representation within the
computer.
A sequence of instructions for the computer is known as program.

Fig. 1.1 Block diagram of a digital computer

The hardware of the computer is usually divided into three major parts.
The Central processing Unit (CPU) contains an arithmetic and logic unit for manipulating data,
a number of registers for storing data and control circuits for fetching and executing
instructions.
The memory of a computer contains storage for instructions and data, it is called a Random
Access Memory(RAM) because the CPU can access any location in memory at random and
retrieve the binary information within a fixed interval of time.
The input and output processor contains electronic circuit for communication and controlling
the transfer of information between the computer and the outside world.
The input and device connected to the computer include keyboards, printers, terminals,
magnetic disk drives and other communication devices.

Logic Gates

Binary information is represented in digital computers using electrical signals.
These signals can be represented by voltage to specify one of two possible states.
For example, if a wire contains a signal of 3 volts, it is considered to contain the digital value
1.
Likewise, if the wire contains 1.5 volts, then it represents the digital value 0.
The manipulation of binary information in a computer is done using logic circuits called gates.
The gates are as shown in figure 1.2

Random Access Memory
Central Processing Unit
Output
Devices
Input-Output Processor
Input
Devices
Atmiya Infotech

Figure 1.2 Digital Logic Gates

Atmiya Infotech
Gate Propagation Delay

Propagation delay is the average transition delay time for a signal to propagate from input to
output when the binary signals change in value. The signals through a gate take a certain
amount of time to propagate from the inputs to the outputs. The interval of time is defined as
the propagation delay of the gate. Propagation delay is expressed in nanoseconds (ns), and 1
ns is equal to 10
-9
of a second.

The signals that travel from the inputs of a digital circuit to its output pass through a series of
gates. The sum of the propagation delay through the gates is the total propagation delay of
the circuit. When speed of operation is important, each gate must have a small propagation
delay and the digital circuit must have a minimum number of series gates between inputs and
outputs.

Universal Gates

NAND and NOR gates are Universal gates because any digital circuit can be implemented with
it. Combinational circuits and sequential circuits as well can be constructed with these gates
because the flip-flop circuit (the memory element most frequently used in sequential circuits)
can be constructed from two NAND gates or NOR gates connected back to back.

To show that any Boolean function can be implemented with NAND or NOR gates, it is needed
to show that the logical operations AND, OR, and NOT can be implemented with these gates.

NAND gate as a Universal Gate

Figure 1.3 Implementation of NOT, AND, OR by NAND gates

Atmiya Infotech

NOR gate as a Universal Gate

Figure 1.4 Implementation of NOT, OR, AND by NOR gates

Atmiya Infotech
#2 Boolean Algebra

Boolean Algebra

In 1854 George Boole introduced a systemic treatment of logic and developed for this purpose
an algebric system called Boolean Algebra.

A Boolean function can be represented by either:
a. Truth tables
b. Logic diagrams
c. Algebraic expression

Boolean algebra is an algebra that deals with binary variables and logic operations.
Variables are designated by letters such as A, B, x, and y.
A Boolean function can be expressed algebraically with binary variables, the logic operation
symbols, parentheses, and equal sign.
The result of a Boolean function is either 0 or 1.

Boolean Operations

There are three basic logical operations:

AND: This operation is represented by a dot or by the absence of an operator. For example,
x.y = z or xy = z is read "x AND y is equal to z. The logical operation AND is interpreted to
mean that z=1 if and only if x=1 and y=1; otherwise z=0.
OR: This operation is represented by a plus sign. For example, x+y = z is read "x OR y is
equal to z, meaning that z=1 if x=1 or if y=1 or if both x=1 and y=1. If both x=0 and y=0,
then z=0.
NOT: This operation is represented by a prime (sometimes by a bar). For example, x = z (or x
= z) is read "x not is equal to z, meaning that z is complement of x. In other words, if x=1,
then z=0, but if x=0, then z=1.

Basic Identities of Boolean Algebra

Table 2.1 Postulates and theorems of Boolean Algebra

Atmiya Infotech

DeMorgan's theorem
It is very important in dealing with NOR and NAND gates. It states that :

A NOR gate that performs the (x+y) function is equivalent to the function xy.
(x+y) = xy
Figure 2.1 Two graphic symbols for NOR gate

A NAND function can be expressed by either (xy) = x+y

Figure 2.2 Two graphic symbols for NAND gate

So, according to DMorgans theorem instead of representing a NOR gate with an OR graphic
symbol followed by a circle,we can represent it by an AND graphic symbol preceded by circles
in all inputs.
OR-invert = invert-AND
Similarly,
AND-invert = invert-OR
To see how Boolean algebra manipulation is used to simplify digital circuits, consider the
following example :
F = ABC + ABC + AC
= AB(C + C) + AC
= AB + AC
Atmiya Infotech
Note that (C+C) = 1 according to the identity 3 from above table.

Complement of a function

The complement of a function F when expressed in a truth table is obtained by interchanging
1s and 0s in the values of F in the truth table.

When the function is expressed in algebraic form the complement of the function can be
derived by means of De-Morgans Theorem.

The general form of DeMorgans theorem can be expressed as follows:
(x1+x2+x3+..Xn) = x1x2x3.xn
(x1x2x3.xn)=x1+x2+x3+.+xn

By changing all OR operation to AND operation and all OR operations and then complementing
each individual letter variable we can derive a simple procedure for obtaining the complement
of an algebraic expression.
Eg.
F = AB+CD+BD
F=(A+B)(C+D)(B+D)

The complement expression is obtained by interchanging AND and OR operations and
complementing each individual.

Simplification using Karnaugh Maps

In addition to using Boolean algebra to simplify a Boolean function, a technique called map
simplification can also be utilized. The map method is known as the Karnaugh map or K-map.

Each combination of the variables in a truth table is called a minterm.

There are 2
n
minterms for a function of n variables.

A fourth representation of a Boolean function can be given as the sum of the functions
minterms. (Sum-of-Products)

Examples

F(x,y,z)= (1,4,5,6,7)

Variable Maps

The following are maps for two, three and four-variable function:

Figure 2.3 Maps for two, three and four variable functions
Atmiya Infotech

The variable names are listed across both the sides of the diagonal line into the corner of the
map.
The 0s and the 1s marked along each row and each column designate the value of the
variables.
Each variable under the brackets contain half of the squares in the map where that variable
appears unprimed.
The minterm represented by a square is determined from the binary assignment of the
variable along the left top edges in the map.
Here the min term 5 in the three variable maps are 101 of the second column. This minterm
represents a value for the binary variables A, B and C with A and C being unprimed and B
being primed.

Sum-of-Products Simplification

A Boolean function represented by a truth table is plotted into the map by inserting 1's into
those squares where the function is 1.
Boolean functions can then be simplified by identifying adjacent squares in the Karnaugh map
that contain a 1.
A square is considered adjacent to another square if it is next to, above, or below it. In
addition, squares at the extreme ends of the same horizontal row are also considered
adjacent. The same applies to the top and bottom squares of a column. The objective to
identify adjacent squares containing 1's and group them together.
Groups must contain a number of squares that is an integral power of 2.
Groups of combined adjacent squares may share one or more squares with one or more
groups.
Each group of squares represents an algebraic term, and the OR of those terms gives the
simplified algebraic expression for the function.
To find the most simplified algebraic expression, the goal of map simplification is to identify
the least number of groups with the largest number of members.

We will simplify the Boolean function.
F (A,B,C) = (3,4,6,7)

Atmiya Infotech
Figure 2.4 Map for F(A,B,C) = (3,4,6,7)

The three variable maps for this function is shown in the figure 2.4
There are four squares marked with 1s, one for each minterm that produces 1 for the
function. These squares belong to minterm 3,4,6,7 and are recognized from the figure b.
Two adjacent squares are combined in the third column. This column belongs to both B and C
produces the term BC.
The remaining two squares with 1s in the two corner of the second row are adjacent and
belong to row columns of C, so they produce the term AC.

The simplified expression for the function is the or of the two terms:
F = BC + AC

The second example simplifies the following Boolean function:
F(A,B,C) = (0,2,4,5,6)
The five minterms are marked with 1s in the corresponding squares of the three variable
maps.
The four squares in the first and the fourth columns are adjacent and represent the term C.
The remaining square marked with a 1 belongs to minterm 5 and can be combined with the
square of minterm 4 to produce the term AB.

The simplified function is
F = C+AB

Figure 2.5 Map for F(A,B,C) = (0,2,4,5,6)

Figure 2.6 Map for F(A,B,C,D) = (0,1,2,6,8,9,10)

Atmiya Infotech
The area in the map covered by this four variable consists of the squares marked with 1s in
fig 1.10. The function contains 1s in the four corners that when taken as groups give the term
BD. This is possible because these four squares are adjacent when the map is considered
with the top and bottom or left and right edges touching.
The two 1s on the bottom row are combined with the two 1s on the left of the bottom row to
give the term BC.
The remaining 1 in the square of minterm 6 is combined with the minterm 2 to give the term
ACD.

The simplified function is:
F = BD + BC + ACD

Product-of-Sums Simplification

Another method for simplifying Boolean expressions can be to represent the function as a
product of sums.
This approach is similar to the Sum-of-Products simplification, but identifying adjacent squares
containing 0s instead of 1s forms the groups of adjacent squares.
Then, instead of representing the function as a sum of products, the function is represented as
a product of sums.

Examples
F(A,B,C,D) = (0,1,2,5,8,9,10)

The 1s marked in the map of figure 2.7 represents the minterms that produces a 1 for the
function.
The squares marked with 0s represent the minterm not included in F and therefore denote the
complement of F.
Combining the squares with 1s gives the simplified function in sum-of-products form:
F = BD +BC+ACD

If the squares marked with 0s are combined as shown in the diagram, we obtain the
simplified complement function:

F=(A+B)(CD)(B+D)

Figure 2.7 Map for F(A,B,C,D) = (0,1,2,5,8,9,10)

The logic diagram of the two simplified expression are shown in fig 2.8

Atmiya Infotech
Figure 2.8 Logic Diagram with AND and OR gates

The sum of product expression us implemented in fig 2.8(a) with a group of of AND gates,
one for each AND term.
The output of the AND gates are connected to the inputs of a single OR gate. The same
function is implemented in fig 2.8(b) in product of sum form with a group of OR gates, one for
each OR term, the outputs of the OR gates are connected to the inputs of a single And gate.
In each case it is assumed that the input variable are directly available in their complement,
so inverter are not included.
Atmiya Infotech
NAND and NOR Implementation

A sum-of-products expression can be implemented with NAND and NOR gates as shown in the
figure 2.9

Figure 2.9 Logic Diagram with NAND and NOR gates

Don't Care Conditions

On occasion, it doesn't matter whether a function produces a 0 or 1 for a given minterm.
When this condition occurs, an X is used in the map to represent the don't care condition.
Then, when performing map simplification, a square containing an X can be used in both the
Sum-of-Products approach and the Product-of-Sums approach.
When choosing adjacent squares for the function in the map, the Xs may be assumed to be
either 0 or 1, whichever gives the simplest expression.
In addition an X need not to be used at all if it does not contribute to the simplification of the
function.
In each case the choice depends only on the simplification that can be achieved.
As an example consider the following Boolean function together with the dont care minterms:
F(A,B,C) = (0,2,6)
d(A,B,C) = (1,3,5)
The minterm listed with F produce a 1 for the function. The dont care minterms listed with d
may produce either a 0 or 1 for the function. The remaining minterms 4,7 produce a 0 for the
function.

Figure 2.10 Example of map with don't-care condition

The map is shown fig 1.14. The minterms of F are marked with 1s those of d are marked with
Xs and the remaining squares are marked with 0s.
The 1s and Xs are combined in any convenient manner so as to enclose the maximum
number of adjacent squares.
It is not necessary to include all or any of the Xs, but all the 1s must be included.
By including the dont care minterms 1 and 3 with the 1s in the first row we obtain the term,
BC.
The simplified expression is F = A + BC
Atmiya Infotech

#3 Combinational Logical Circuits

Combinational Circuits

A combinational circuit is a connected arrangement of logic gates with a set of inputs and
outputs.
At any given time, the binary values of the outputs are a function of the binary values of the
inputs.
The design of a combinational circuit starts from a verbal outline of the problem and ends in a
logic circuit diagram. The procedure involves the following steps:
1. The problem is stated.
2. The input and output variables are assigned letter symbols.
3. The truth table that defines the relationship between inputs and outputs is derived.
4. The simplified Boolean functions for each output are obtained.
5. The logic diagram is drawn.
Half-Adder

The most basic digital arithmetic circuit.
Performs the addition of two binary digits.
The input variables of a half-adder are called the augend and the addend.
The output variables of a half-adder are called the sum and the carry.

Figure 3.1 Half-adder

Full-Adder

A full-adder performs the addition of three binary digits.
Two half-adders can be combined to for a full-adder..
Although a full adder has three inputs, it still only has two outputs since the largest number is
1+1+1 = 3, and 3 can be represented by two bits.

Atmiya Infotech
Table 3.1 Truth Table for Full-adder

Figure 3.2 Maps for Full-adder

Figure 3.3 Full-adder circuit

Parallel Adder

A binary parallel adder is a digital function that produces the arithmetic sum of two binary
numbers in parallel. It consists of full-adders connected in cascade, with the output carry from
one full-adder connected to the input carry of the next full-adder.

The parallel adder uses n full-adder circuits, and all bits of A and B are applied simultaneously.
The output carry from one full-adder is connected to the input carry of the full-adder one
position to its left. As soon as the carries are generated, the correct sum bits emerge from the
sum outputs of all full-adders.
Atmiya Infotech

Figure 3.4 4-bit full-adders (Parallel Adder)

Operation

Figure above shows the interconnection of four full-adder (FA) circuits to provide a 4-bit binary
parallel adder. The augend bits of A and the addend bits of B are designated by subscript
numbers from right to left, with subscript 1 denoting the low-order bit. The carries are
connected in a chain through the full-adders. The input carry to the adder is C
1
and the output
carry is C
5
. the S outputs generates the required sum bits.

Serial Adder

Operations in digital computers are mostly done in parallel because this is a faster mode of
operation. Serial operations are slower but require less equipment.

Construction

The two binary numbers to be added serially are stored in two shift registers. Bits are added
one pair at a time, sequentially, through a single full-adder (FA) circuit as shown in the figure
below. The carry out of the full-adder is transferred to a D flip-flop. The output of this flip-flop
is then used as an input carry for the next pair of significant bits. The two shift registers are
shifted to the right for one word-time period. The sum bits from the S output of the full-adder
could be transferred into a third shift register. By shifting the sum into A while the bits of A
are shifted out, it is possible to use one register for storing both the augend and the sum bits.
The serial input (SI) of register B is able to receive a new binary number while the addend bits
are shifted out during the addition.

Atmiya Infotech
Figure 3.5 Serial Adder

Operation

Initially, the register A holds the augend, the B register holds the addend, and the carry flip-
flop is cleared to 0, the serial outputs (SO) of A and B provide a pair of significant bits for the
full-adder at x and y. Output Q of the flip-flop gives the input carry at z. The shift-right control
enables both registers and the carry flip-flop; so at the next clock pulse, both registers are
shifted once to the right, the sum bit from S enters the leftmost flip-flop of A, and the output
carry is transferred into flip-flop Q. The shift-right control enables the registers for a number
of clock pulses equal to the number of bits in the registers. For each succeeding clock pulse, a
new sum bit is transferred to A, a new carry is transferred to Q, and both registers are shifted
once to the right. This process continues until the shift-right control is disables. Thus, the
addition is accomplished by passing each pair of bits together with the previous carry through
a single full-adder circuit and transferring the sum, one bit at a time, into register A.

If a new number has to be added to the content of register A, this number must be first
transferred serially into register B. Repeating the process once more will add the second
number to the previous number in A.

Comparing the serial adder with the parallel adder:

The parallel adder must use registers with parallel-load capability, whereas the serial adder
uses shift registers.
The number of full-adder circuits in the parallel adder is equal to the number of bits in the
binary numbers, whereas the serial adder requires only one full-adder circuit and a carry flip-
flop.
Excluding the registers, the parallel adder is a purely combinational circuit, whereas the serial
adder is a sequential circuit. The sequential circuit in the serial adder consists of a full-adder
circuit and a flip-flop that stores the output carry.
Atmiya Infotech
Subtractors

In subtractors, each subtrahend bit of the number is subtracted from its corresponding
significant minuend bit to form a difference bit. If the minuend bit is smaller than the
subtrahend bit, a 1 is borrowed from the next significant position. The fact that a 1 has been
borrowed must be conveyed to the next higher pair of bits by means of a binary signal coming
out (output) of a given stage and going into (input) the next higher stage. Just as there are
half and full-adders, there are half and full-subtractors.

Half-subtractor

A half-subtractor is a combinational circuit that subtracts two bits and produces their
difference. It also has an output to specify if a 1 has been borrowed. Designate the minuend
bit by x and the subtrahend bit by y. To perform x-y, the relative magnitudes of x and y are to
be checked. If x>=y, there are three possibilities: 0-0 = 0, 1-0 = 1, and 1-1 = 0. The result is
called the difference bit. If x<y, we have 0-1, and it is necessary to borrow a 1 from the next
higher stage. The 1 borrowed from the next higher stage adds 2 to the minuend bit, just as in
the decimal system a borrow adds 10 to a minuend digit. With the minuend equal to 2, the
difference becomes 2-1 = 1. the half-subtractor needs two outputs. One output generates the
difference and will be designated by the symbol D. The second output, designated B for
borrow, generates the binary signal that informs the next stage that a 1 has been borrowed.
The truth table for the input-output relationships of a half-subtractor can now be derived as
follows:

Table 3.2 Truth Table for Half-subtractor

x y B D
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0

The Boolean function for the two outputs of the half-subtractor are derived directly from the
truth table:
D = xy + xy
B = xy

Figure 3.6 Half-Subtractor

Full-subtractor

A full-subtractor is a combinational circuit that performs a subtraction between two bits, taking
into account that a 1 may have been borrowed by a lower significant stage. This circuit has
three inputs and two outputs. The three inputs, x, y, and z, denote the minuend, subtrahend,
and previous borrow, respectively. The two outputs, D and B, represent the difference and
output borrow, respectively. The truth table for the circuit as follows:

Atmiya Infotech
The eight rows under the input variables designate all possible combinations of 1s and 0s
that the binary variables may take. The 1s and 0s for the output variables are determined
from the subtraction of x-y-z. The combinations having input borrow z=0 reduce to the same
four conditions of the half-adder. For x=0, y=0, and z=1, we have to borrow a 1 from the next
stage, which makes B=1 and adds 2 to x. Since 2-0-1=1, D=1. For x=0 and yz=11, we need
to borrow again, making B=1 and x=2. Since 2-1-1=0, D=0. for x=1 and yz=01, we have x-
y-z=0, which makes B=0 and D=0. Finally, for x=1, y=1, z=1, we have to borrow 1, making
B=1 and x=3, and 3-1-1=1, making D=1.

Table 3.3 Full-subtractor

x y z B D
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

The simplified Boolean functions for the two outputs of the full-subtractor are derived in the
maps of fig. Above. The simplified sum of products output functions are:
D = xyz + xyz + xyz + xyz
B = xy + xz + yz

Figure 3.7 Maps for Full-subtractor

Code Converters

The availability of a large variety of codes for the same discrete elements of information
results in the use of different codes by different digital systems. It is sometimes necessary to
use the output of one system as the input to another. A conversion circuit must be inserted
between the two systems if each uses different codes for the same information. Thus, a code
converter is a circuit that makes the two systems compatible even though each uses a
different binary code.

To convert from binary code A to binary code B, the input lines must supply the bit
combination of elements as specified by code A and the output lines must generate the
corresponding bit combination of code B. a combinational circuit performs this transformation
by means of logic gates.

Atmiya Infotech
The design procedure of code converter is illustrated below by means of a specific example of
conversion from the BCD to the excess-3 code.

The bit combinations for the BCD and excess-3 codes are listed in the table. Since each code
uses four bits to represent a decimal digit, there must be four input variables and four output
variables. The four input variables are designated by the symbols A,B,C, and D, and the four
output variables by w,x,y, and z. the truth table relating the input and output variables is
shown below. The four binary variables may have 16 bit combinations, only 10 of which are
listed in the truth table. The six bit combinations not listed for the input variables are dont-
care combination. Since they will never occur, we are at liberty to assign to the output
variables either a 1 or a 0, whichever gives a simpler circuit.

Table 3.4 Truth Table for code-conversion example

Input
BCD
Output
Excess-3 code
A B C D w x y z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 1

Figure 3.8 Maps for BCD-to-excess-3 code converter

Atmiya Infotech
From the K-map,

z = D
y = CD + CD = CD + (C+D)
x = BC + BD + BCD = B (C+D) + B (C+D)
w = A + BC + BD = A + B(C+D)

The logic diagram that implements the above expressions is shown in figure below.

Figure 3.9 Logic Diagram for BCD-to-excess-3 code converter

Decoders

Discrete quantities of information are represented in digital computers with binary codes. A
binary code of n bits is capable of representing up to 2
n
distinct elements of the coded
information. A decoder is a combinational circuit that converts binary information from the n
coded inputs to a maximum of 2
n
unique outputs. If the n-bit coded information has unused
bit combinations, the decoder may have less than 2
n
outputs.

The decoders presented in this section are called n-to-m-line decoders, where m <= 2
n
. Their
purpose is to generate the 2
n
(or fewer) binary combinations of the n input variables. A
decoder has n inputs and m outputs and is also referred to as an n x m decoder.

The logic diagram of a 3-to-8-line decoder is shown in the Figure 3.10
Atmiya Infotech
Figure 3.10 3-to-8 line decoder

The three data inputs. A
0
, A
1
, and A
2
, are decoded into eight outputs, each output
representing one of the combinations of the three binary input variables. The three inverters
provide the complement of the inputs, and each of the eight AND gates generates one of the
binary combination. A particular application of this decoder is a binary-to-octal conversion. The
input variables represent a binary number and the outputs represent the eight digits of the
octal number system. However, a 3-to-8-line decoder can be used for decoding any 3-bit code
to provide eight outputs, one for each combination of the binary code.

Commercial decoders include one or more enable inputs to control the operation of the circuit.
The decoder of the Figure has one enable input, E. The decoder is enabled when E is equal to
1 and disabled when E is equal to 0. The operation of the decoder can be clarified using the
truth table listed in Table. When the enable input E is equal to 0, all the outputs are equal to
0 regardless of the values of the other three data inputs. The three x's in the table designate
don't-care conditions. When the enable input is equal to 1, the decoder operates in a normal
fashion. For each possible input combination, there are seven outputs that are equal to 0 and
only one that is equal to 1. The output variable whose value is equal to 1 represents the octal
number equivalent of the binary number that is available in the input data lines.

Table 3.5 Truth Table for 3-to-8-line Decoder

Atmiya Infotech
NAND Gate Decoder

Some decoders are constructed with NAND instead of AND gates. Since a NAND gate produces
the AND operation with an inverted output, it becomes more economical to generate the
decoder outputs in their complement form.
A 2-to-4-line decoder with an enable input constructed with NAND gates is shown in Figure.
The circuit operates with complemented outputs and a complemented enable input E. The
decoder is enabled when E is equal to 0. As indicated by the truth table, only one output is
equal to 0 at any given time; the other three outputs are equal to 1. The output whose value
is equal to 0 represents the equivalent binary number in inputs Ai and Ao. The circuit is
disabled when is equal to I, regardless of the values of the other two inputs.

Figure 3.11 2-to-4-line decoder with NAND gates

Decoder Expansion

A technique called decoder expansion can be utilized to construct larger decoders out of
smaller ones. For example, two 2-to-4-line decoders can be combined to construct a 3-to-8-
line decoder. Figure below shows 3-8-line decoder constructed with two 2x4 decoders.

Figure 3.12 A 3X8 decoder constructed with two 2X4 decoders

Atmiya Infotech
The above given Figure shows how the decoders with enable inputs can be connected to form
a larger decoder. As you can see that there are two 2-to-4-line decoders are combined to
achieve a 3-to-8-line decoder. The two least significant bits of the input are connected to
both decoders. The most significant bit is connected to the enable input of one decoder and
through an inverter to the enable input of the other decoder. It is assumed that each decoder
is enabled when its E input is equal to 1. When E is equal to 0, the decoder is disabled and all
its outputs are in the 0 level. When A2 = 0, the upper decoder is enabled and the lower is
disabled. The lower decoder outputs become inactive with all outputs at 0. The outputs of the
upper decoder generate outputs Do through D3, depending on the values of A1 and A0(while
A2 = 0). When A2= 1, the lower decoder is enabled and the upper is disabled. The lower
decoder output generates the binary equivalent D4, through D7 since these binary numbers
have a 1 in the A2 position.

Encoders

An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder
has 2
n
(or less) input lines and n output lines. The output lines generate the binary code
corresponding to the input value. An example of an encoder is the octal-to-binary encoder,
whose truth table is given below.

Table 3.6 Truth Table for Octal-to-binary Encoder

inputs outputs
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1

The encoder can be implemented with OR gates whose inputs are determined directly from the
truth table. Output A0 =1 if the input octal digit is 1 or 3 or 5 or 7. Similar conditions apply for
other two outputs.

These conditions can be expressed by the following Boolean functions :
A0 = D1 + D3 + D5 + D7
A1 = D2 + D4 + D6 + D7
A2 = D4 + D5 + D6 + D7

The encoder can be implemented with three OR gates.

Figure 3.13 Octal-to-binary Encoder

Atmiya Infotech
Multiplexer

A multiplexer is a combinational circuit that receives binary information from one of 2
n
input
data lines and directs it to a single output line.
The selection of a particular input data line for the output is determined by a set of selection
inputs. A 2
n
-to-1 multiplexer has 2
n
input data lines and n input selection lines whose bit
combinations determine which input data are selected for the output.
The 4-to-1 line multiplexer has six inputs and one output. A truth table describing the circuit
needs 64 rows since six input variables can have 2
6
binary combinations. This is an extremely
long table and will not be shown here. A more convenient way to describe the operation of
multiplexers is by means of a function table. The function table for the multiplexer is shown in
table. The table demonstrates the relationship between the four data inputs and the single
output as a function of the selection inputs S1 and S0.

Table 3.7 Function table for 4-to-1 line multiplexer

Select Output
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3

Figure 3.14 4-to-1 line Multiplexer

DeMultiplexer

A decoder with an enable input can function as a demultiplexer. A demultiplexer is a circuit
that receives information on a single line and transmits this information on one of 2
n
possible
output lines. The selection of a specific output line is controlled by the bit values of n selection
lines. The decoder of figure a can function as a demultiplexer if the E line is taken as a data
input line and lines A and B are taken as the selection lines. This is shown in figure 3.15(b).
The single input variable E has a path to all four outputs, but the input information is directed
to only one of the output lines, as specified by the binary value of the two selection lines A and
B. For example, if the selection lines AB = 10; output D
2
will be the same as the input value E,
while all other outputs are maintained at 1. Because decoder and demultiplexer operations are
Atmiya Infotech
obtained from the same circuit, a decoder with an enable input is referred to as a decoder /
demultiplexer. It is the enable input that makes the circuit a demultiplexer.

Figure 3.15 Block Diagram for DeMultiplexer

Atmiya Infotech
Practice Questions

Explain following logic gates with Truth Table: (2 Marks)

1. AND
2. OR
3. NOR
4. EX-OR
5. EX-NOR

Short Questions: (1-2 Marks)

1. Is (x + y) = xy possible? Verify.
2. NAND gate is a universal gate. Give reason.
3. Construct AND with NOR gate.

Long Questions: (5-10 Marks)

1. State and verify D Morgans Theorem through Truth Table.
2. Write a brief note on basic logic gates.
3. Briefly explain 3 to 8 line encoder.
4. Is X.(X+Y) = X.Y correct? If yes, prove it. If no, say why?
5. Can you construct AND, OR & NOT gates using NAND gate? If yes, Show how. If no, say why?
6. Discuss in short. Encoder and Decoder.
7. Explain Full Adder.
8. Write short note on 4-1 line Multiplexer.

Draw Logic Diagram: (5 Marks)

1. 1. XY + XZ
2. 2. Y + XY + XYZ
3. 3. XYZ + XYZ + XYZ + XYZ
4. 4. (X+Y+Z).(X+Z),(X+Y).(X+Y+Z)

Atmiya Infotech

#4 Sequential logic circuits

Flip-flops

A Flip-flop is a binary cell capable of storing one bit of information.
It has two outputs, one for the normal value and one for the complement value of the bit
stored in it.
Flip-flops are storage elements utilized in synchronous sequential circuits.
Synchronous sequential circuits employ signals that effect storage elements only at discrete
instances of time.
A timing device called a clock pulse generator that produces a periodic train of clock pulses
achieves synchronization.
Values maintained in the storage elements can only change when the clock pulses.
Hence, a flip-flop maintains a binary state until directed by a clock pulse to switch states.
The difference in the types of flip flops is in the number of inputs and the manner in which the
inputs affect the binary state.
Flip-flops can be described by a characteristic table which permutates all possible inputs (just
like a truth table).
The characteristic table of a flip-flop describes all possible outputs (called the next state) at
time Q(t+1) over all possible inputs and the present state at time Q(t).
The most common types of flip flops are:
SR Flip-Flop
D Flip-Flop
JK Flip-Flop
T Flip-Flop

SR Flip-Flop
Figure 4.1 SR Flip-Flop

Inputs:
S (for set)
R (for reset)
C (for clock)

Outputs:
Q
Q'

The operation of the SR flip-flop is as follow.

Atmiya Infotech
If there is no signal at the clock input C, the output of the circuit cannot change irrespective of
the values at inputs S and R.
Only when the clock signals changes from 0 to 1 can the output be affected according to the
values in inputs S and R
If S =1 and R = 0 when C changes when C changes from 0 to 1 output Q is set to 1. If S = 0
and R =1 when C changes from 0 to 1.
If both S and R are 0 during the clock transition, output does not change.
When both S and R are equal to 1, the output is unpredictable and may go to either 0 or 1,
depending on internal timing that occur within the circuit.

SR Flip-Flop circuit with NAND gate

Figure 4.2 Basic SR Flip-Flop circuit with NOR gates

Figure 4.3 Basic SR Flip-Flop circuit with NAND gates

D Flip-Flop
Figure 4.4 D D Flip-flop

Inputs:
D (for data)
C (for clock)

Outputs:
Atmiya Infotech
Q
Q'
The operation of the D flip-flop is as follow.

The D Flip-Flop can be converted from SR Flip-Flop by inserting an inverter between S and R
and assigning the symbol D to the single input.
The D input is sampled during the occurrence of a clock transition from 0 to 1.
If D=1, the output of the flip-flop goes to the 1 state, but if D=0, the output of the flip-flop
goes to the 0 state.
The next state Q(t+1) is determined from the D input. The relationship can be expressed by a
characteristic equation:
Q(t+1) = D
D Flip-Flop has the advantage of having only one input (excluding ), but the disadvantage that
its characteristic table does not have a "no change condition Q(t+1) = Q(t).

D Flip-Flop with NAND gate

Figure 4.5 D Flip-flop with NAND gates

JK Flip-Flop

Figure 4.6 Jk Flip-Flop

Inputs:
J
K
C (for clock)

Outputs:
Q
Q'

The operation of the JK flip-flop is as follow.

Atmiya Infotech
A JK Flip-Flop is a refinement of the SR flip-flop in that the indeterminate condition of the SR
type is defined in the JK type.
Inputs J and K behave like inputs S and R to set and clear the flip-flop, respectively.
When inputs J and K are both equal to 1, a clock transition switches the outputs of the flip-flop
to their complement state.
Instead of the indeterminate condition of the SR flip-flop, the JK flip-flop has a complement
condition Q(t+1) = Q(t) when both J and K are equal to 1.

Figure 4.7 Logic Diagram of JK Flip-Flop

T Flip-Flop

Figure 4.8 T Flip-Flop

Inputs:
T (for toggle)
C (for clock)

Outputs:
Q
Q'

The operation of the T flip-flop is as follow.

Most flip-flops are edge-triggered flip-flops, which means that the transition occurs at a
specific level of the clock pulse.
A positive-edge transition occurs on the rising edge of the clock signal.
A negative-edge transition occurs on the falling edge of the clock signal.
Another type of flip-flop is called a master-slave flip-flop that is basically two flip-flops in
series.
Atmiya Infotech
Flip-flops can also include special input terminals for setting or clearing the flip-flop
asynchronously. These inputs are usually called preset and clear and are useful for initialing
the flip-flops before clocked operations are initiated.

Figure 4.9 Logic Diagram for T Flip-Flop

Master-Slave JK Flip-Flop

A master-slave flip-flop is constructed from two separate flip-flops. One circuit serves as a
master and the other as a slave, and the overall circuit is referred to as a master-slave flip-
flop.

A master-slave JK flip-flop constructed with NAND gates is shown in figure below. It consists
of two flip-flops; gates 1 through 4 form the master flip-flop, and gates 5 through 8 form the
slave flip-flop. The information present at the J and K inputs is transmitted to the master flip-
flop on the positive edge of a clock pulse and is held there until the negative edge of the clock
pulse occurs, after which it is allowed to pass through to the slave flip-flop. The clock input is
normally 0, which the outputs of gates 1 and 2 at the 1 level. This prevents the J and K inputs
from affecting the master flip-flop. The slave flip-flop is a clocked RS type, with the master
flip-flop supplying the inputs and the clock input being inverted by gate 9. When the clock is 0,
the output of gate 9 is 1, so that output Q is equal to Y, and Q is equal to Y. When the
positive edge of a clock pulse occurs, the master flip-flop is affected and may switch states.
The slave flip-flop is isolated as long as the clock is at the 1 level, because the output of gate
9 provides a 1 to both inputs of the NAND basic flip-flop of gates 7 and 8. when the clock input
returns to 0, the master flip-flop is isolated from the J and K inputs and the slave flip-flop goes
to the same state as the master flip-flop.

Figure 4.10 Master-slave JK Flip-Flop

Atmiya Infotech
Flip-Flop Excitation Tables

During the design of sequential circuits, the required transition from present state to next
state is known.
What the designer needs to know is what input conditions must exist to implement the
required transition.
This requires the use of flip-flop excitation tables.

Figure 4.11 Excitation Tables

Atmiya Infotech
Sequential Circuits

When a circuit contains just gates, it is called a combinational circuit. However, if a circuit uses
both gates and flip-flops, it is called a sequential circuit. Hence, a sequential circuit is an
interconnection of flip-flops and gates.

If we think of a sequential circuit as some black box that, when provided with some external
input, produces some external output, a typical sequential circuit would function as follows:

The external inputs constitute some of the inputs to the combinational circuit. The internal
outputs of the combinational circuit are the internal inputs to the flip-flops.
The internal outputs of the flip-flops constitute the remaining inputs to the combinational
circuit. The external outputs are some combination of the outputs from the combinational
circuit and flip-flops. The behavior of a sequential circuit is determined from the inputs, the
outputs, and the state of the flip-flops. Both the outputs and the next state are determined by
the inputs and the present state.

A state diagram can represent the information in a state table graphically, where states are
represented by circles (vertices) and transitions on specific input is represented by the labels
on the directed lines (edges) connecting the circles.

Design Procedure

Formulate behavior of circuit using a state diagram.
Determine # of flip-flops needed (equal to # bits in circles).
Determine # inputs (specified on edges of diagram).
Create state table, assigning letters to flip-flips, input, and output variables.*
For each row, list the next state as specified by the state diagram.
Select flip-flop type to be used in circuit.
Extend state table into an excitation table by including columns for each input of each flip-flop.
Using excitation table and present state-to-next state transitions, formulate input conditions
for flip-flops.
Construct truth table for combinational circuit using present-state and input columns of
excitation table (for inputs) and flip-flop inputs (for outputs).
Use map simplification of truth table to obtain flip-flop input equations.**
Determine external outputs of sequential circuit (flip-flop outputs and potentially
combinational circuit outputs).
Draw logic diagram as follows:

Draw flip-flops and label all their inputs and outputs.
Draw combinational circuit from the Boolean expressions given by the flip-flop
input equations.
Connect outputs of flip-flops to inputs in the combinational circuit.
Connect outputs of combinational circuit to flip-flop inputs.

For m flip-flops and n inputs, the state table will consist of m columns for the present state, n
columns for the inputs, and m columns for the next state. The number of rows in the table will
be up to 2m+n, one row for each binary combination of present state and inputs.

** Each flip-flop input equation specifies a logic diagram whose output must be connected to
one of the flip-flop inputs.

Atmiya Infotech
#5 Registers

Registers

A register is a group of flip-flops capable of storing one bit of information.
An n-bit register has a group of n flip-flops and is capable of storing any binary information of
n bits.
In addition to flip-flops, registers can have combinational gates that perform certain data-
processing tasks. The gates control how and when new information is transferred into the
registers.
The transfer of new information into a register is referred to as a register load. If the loading
occurs simultaneously at a common clock pulse transition, we say that the load is done in
parallel.
The load input in a register determines the action to be taken with each clock pulse.
When the load input is 1, the data from the input lines is transferred into the register's flip-
flops. When the load input is 0, the data inputs are inhibited and the flip-flop maintains its
present state.

A 4-bit register is shown in the figure below. A clock transition applied to the C inputs of the
register will load all four inputs I
0
through I
3
in parallel.

Figure 5.1 4-bit register

Atmiya Infotech
Shift Registers

A register capable of shifting its binary information in one or both directions is called a shift
register.
Shift registers are constructed by connecting flip-flops in cascade, where the output of one
flip-flop is connected to the input of the next flip-flop.
All flip-flops receive common clock pulses that initiate the shift from one stage to the next.
A serial input shift register has a single external input (called the serial input) entering an
outermost flip-flop. Each remaining flip-flop uses the output of the previous flip-flop as its
input, with the last flip-flop producing the external output (called the serial output).
A register capable of shifting in one direction is called a unidirectional shift register.
A register that can shift in both directions is called a bi-directional shift register.
The most general shift register has the following capabilities:
An input for clock pulses to synchronize all operations.
A shift-right operation and a serial input line associated with the shift-right.
A shift-left operation and a serial input line associated with the shift-left.
A parallel load operation and n input lines associated with the parallel transfer.
N parallel output lines.
A control state that leaves the information in the register unchanged even though
clock pulses are applied continuously.
A mode control to determine which type of register operation to perform.

The simplest possible shift register is one that uses only flip-flops, as shown in the figure
below.

Figure 5.2 4-bit shift register

Bidirectional Shift Register with parallel load

A register that can shift in both directions is called a bi-directional shift register. A 4-bit
bidirectional shift register with parallel load is shown in figure below. Each stage consists of a
D flip-flop and a 4X1 MUX. The two selection inputs S1 and S0 select one of the MUX data
inputs for the D flip-flop. The selection lines control the mode of operation of the register
according to the function table shown in table below. When the mode control S1S0 = 00, data
input 0 of each MUX is selected. This condition forms a path from the output of each flip-flop
into the input of the same flip-flop. The next clock transition refers into each flip-flop the
binary value it held previously, and no change of state occurs. When S1S0 = 01, the terminal
marked 1 in each MUX has a path to the D input of the corresponding flip-flop. This causes a
shift-right operation, with the serial input data transferred into flip-flop A0 and the content of
each flip-flop Ai-1 transferred into flip-flop Ai for i=1,2,3. When S1S0 = 10 a shift-left
operations results, with the other serial input data going into flip-flop A3 and the content of
flip-flop Ai+1 transferred into flip-flop Ai for I=0,1,2. When S1S0 = 11, the binary information
from each input I0 through I3 is transferred into the corresponding flip-flop, resulting in a
parallel load operation. In the diagram, the shift-right operation shifts the contents of the
register in the down direction while the shift left operation causes the contents of the register
to shift in the upward direction.
Atmiya Infotech

Figure 5.3 Bidirectional Shift register with parallel load

Application of Shift Registers

Shift registers are often used to interface digital systems situated remotely from each other.
For example, suppose that it is necessary to transmit an n-bit quantity between two points. If
the distance between the source and the destination is too far, it will be expensive to use n
lines to transmit the n bits in parallel. It may be more economical to use a single line and
transmit the information serially one bit at a time. The transmitter loads the n-bit data in
parallel into a shift register and then transmits the data from the serial output line. The
receiver accepts the data serially into a shift register through its serial input line. When the
entire n bits are accumulated they can be taken from the outputs of the register in parallel.
Thus the transmitter performs a parallel-to-serial conversion of data and the receiver converts
the incoming serial data back to parallel data transfer.

Atmiya Infotech
#6 Counters

Introduction
A sequential circuit that goes through a prescribed sequence of states upon the application of
input pulses is called a counter. The input pulses, called count pulses, may be clock pulses, or
they may originate from an external source and may occur at prescribed intervals of time or at
random. In a counter, the sequence of states may follow a binary count or any other sequence
of states. Counters are found in almost all equipment containing digital logic. They are used
for counting the number of occurrences of an event and are useful for generating timing
sequences to control operations in a digital system.

Binary Counters
A counter that follows the binary sequence is called a binary counter. An n-bit binary counter
consists of n flip-flops and can count in binary from 0 to 2n-1.

Synchronous Counters
Up counters
A 4-bit synchronous binary counter is as shown in the figure below. The C inputs of all flip-
flops receive the common clock. If the count enable is 0, all J and K inputs are maintained at 0
and the output of the counter does not change. The first stage A
0
is complemented when the
counter is enabled and the clock goes through a positive transition. Each of the other three
flip-flops are complemented when all previous least significant flip-flops are equal to 1 and the
count is enabled. The chain of AND gates generate the required logic for the J and K inputs.
The output carry can be used to extend the counter to more stages, with each stage having an
additional flip-flop and an AND gate.

Figure 6.1 4-bit synchronous binary counter

Atmiya Infotech

Binary Up-Down counters

In a synchronous count-down binary counter, the flip-flop in the lowest-order position is
complemented with every pulse. A flip-flop in any other position is complemented with a pulse
provided all the lower-order bits are equal to 0.

The two operations can be combined in one circuit. A binary counter capable of counting either
up or down is shown in figure below. The T flip-flops employed in this circuit may be
considered as JK flip-flops with the J and K terminals tied together. When the up input control
is 1, the circuit counts up, since the T inputs are determined from the previous values of the
normal outputs in Q. When the down input control is 1, the circuit counts down, since the
complement outputs Q determine the states of the T inputs. When both the up and down
signals are 0s, the register does not change state but remains in the same count.

Figure 6.2 4 bit up-down binary counter

Asynchronous counters

Up Counters

In asynchronous counter, the flip-flop output transition serves as a source for triggering other
flip-flops. The clock inputs of all flip-flops (except the first) are triggered not by the incoming
pulses but rather by the transition that occurs in other flip-flops.

A 4-bit binary asynchronous counter consists of a series connection of complementing flip-
flops (T or JK type), with the output of each flip-flop connected to the clock input of the next
higher-order flip-flop as shown in the figure below. The flip-flop holding the least significant bit
receives the incoming count pulses. All J and K inputs are equal to 1. The small circle in the CP
input indicates that the flip-flop complements during a negative-going transition or when the
output to which it is connected goes from 1 to 0. To understand the operation of the binary
counter, refer to its count sequence given in the table below.
Atmiya Infotech

Figure 6.3 4-bit binary asynchronous counter

Table 6.1 Count sequence for a binary asynchronous counter

Down counters

A binary counter with a reverse count is called a binary down-counter. In a down-counter, the
binary counter is decremented by 1 with every input count pulse. The count of a 4-bit down-
counter starts from binary 15 and continues to binary counts 14, 13, 12, ..,0 and then back
to 15. The circuit of the 4-bit binary asynchronous counter will function as a binary down-
counter if the outputs are taken from the complement terminals Q of all flip-flops.

Error detection and correction codes

Binary information transmitted through some form of communication medium is subject to
external noise that could change bits from 1 to 0, and vice versa. And error detection code is a
binary code that detects digital errors during transmission. The detected errors cannot be
corrected but their presence is indicated. The usual procedure is to observe the frequency of
errors. If errors occur infrequently at random, the particular erroneous information is
transmitted again. If the error occurs too often, the system is checked for malfunction.

The most common error detection code used is the parity bit. A parity bit is an extra bit
included with a binary message to make the total number of 1s either odd or even. A
message of three bits and two possible parity bits is shown in the table below. The P (odd) bit
is chosen to make the sum of all 1s odd. The P(even) bit is chosen to make the sum of all 1s
even. In either case, the sum is taken over the message and the P bit. In any particular
application, one or the other type of parity will be adopted.

Atmiya Infotech
During transfer of information from one location to another, the parity bit is handled as
follows. At the sending end, the message is applied to a parity generator, where the required
parity bit is generated. The message, including the parity bit, is transmitted to its destination.
At the receiving end, all the incoming bits are applied to a parity checker that checks the
proper parity adopted. An error is detected if the checked parity does not conform to the
adopted parity. The parity method detects the presence of one, three, or any odd number of
errors. An even number of errors is not detected.

Figure 6.4 Error Detection with odd parity bit

The parity generator can use the same circuit as the parity checker if the fourth input is
permanently held at a logic 0 value. The advantage of this is that the same circuit can be used
for both parity generation and parity checking.

Digital Circuits &amp Logic Design

Transféré par

Informations du document

Description originale:

Titre original

Copyright

Formats disponibles

Partager ce document

Partager ou intégrer le document

Options de partage

Avez-vous trouvé ce document utile ?

Ce contenu est-il inapproprié ?

Droits d'auteur :

Formats disponibles

Digital Circuits &amp Logic Design

Transféré par

Droits d'auteur :

Formats disponibles

Atmiya Infotech

"Yogidham", Kalawad Road, Rajkot Ph : 572365, 576681

Vous aimerez peut-être aussi