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Modeling and Fabrication of ZnO Nanowire Transistors

Steve J. Pearton, Fellow, IEEE, David P. Norton, Li-Chia Tien, and Jing Guo
(Invited Paper)

AbstractZnO is attracting attention for application in transparent nanowire (NW) transistors because of the ease of synthesis of ZnO nanostructures, their good transport properties, the availability of heterostructures, and the possibility for optoelectronic integration. A variety of both top and bottom gate n-type ZnO NW transistors have been reported, showing generally high on/off ratios (104 107 ), subthreshold voltage swings of 130300 mV/dec, and excellent draincurrent saturation. Much higher electron mobilities and improved device stability are found when surface passivation is employed, pointing to the importance of controlling surface charge density. Simulations show that defects such as grain boundaries lead to a decrease of drain current. While the dc characteristics of such devices are generally reasonable, there have been no reports of the RF or high-speed switching performance. Additional work is needed on optimized gate dielectrics, reliability, and functionality of ZnO NW transistors. Index TermsHeterostructures, nanowires (NWs), ZnO.

I. INTRODUCTION HERE has been signicant interest recently in the development of ZnO-based UV/visible light-emitting diodes (LEDs) and transparent thin-lm transistors for display applications [1][4]. In particular, low-cost ZnO LEDs could be used in trafc signals, outdoor displays, backlighting in electronic displays, automobile brake lights, indicators on electronic devices, biodetectors, and general lighting applications. ZnO has a number of material advantages over GaN, including a large exciton binding energy (60 meV compared with 26 meV for GaN), exceptional resistant to radiation damage by high energy radiation, the commercial availability of large highquality single-crystal wafers, and simplied device processing because wet chemical etching is possible, unlike GaN. A tunable bandgap can be realized by alloying ZnO with CdO,

Manuscript received January 17, 2008; revised July 28, 2008. Current version published October 30, 2008. This work was supported by the NASA Hydrogen Research Grant NAG3-2930, by the Air Force Ofce of Scientic Research under Grant F49620-03-1-0370, by the Army Research Ofce under Grant DAAD19-01-1-0603, and by the National Science Foundation (DMR 0700416, Dr. L. Hess). The review of this paper was arranged by Editor M. J. Kumar. S. J. Pearton, D. P. Norton, and L.-C. Tien are with the Department of Materials Science and Engineering, University of Florida, Gainesville, FL 32611 USA (e-mail: spear@mse.u.edu; dnort@mse.u.edu; lctien@u.edu). J. Guo is with the Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611 USA (e-mail: guoj@u.edu). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TED.2008.2005157

MgO, or BeO. The bandgap can be changed from 3 to 4.0 eV in Zn1x Cdx O and Mgx Zn1x O alloy lms with small lattice mismatch. This makes it possible to realize strain-free and highquality multiple quantum well device structures. ZnO also has a high breakdown electric eld of 2 106 V/cm and a large saturation velocity of 3.2 107 cm/s at room temperature. ZnO is generally crystallized in the hexagonal wurtzite structure although metastable zincblende can be observed in some cases. The lattice parameters of wurtzite ZnO are a = b = 3.250 and c = 5.206 The specic gravity is 5.72 g/cm3 , corresponding to 4.21 1022 molecules per cubic centimeters. The ionic radii on Zn2+ and O2 are 0.60 and 1.38 , respectively, corresponding to a ZnO distance of 1.972 [2]. Asgrown undoped ZnO lms typically show nonstoichiometry and are usually n-type [2]. Typical values of the Hall mobility at room temperature for single crystals and polycrystalline samples are about 100200 and 110 cm2 /V s, respectively [2]. These properties make ZnO attractive for nanowires (NWs), which have been synthesized by a wide variety of methods that generally yield single-crystal material. The ease of synthesizing ZnO-based nanostructures [4], the good transport properties, and the transparency of the ZnMgCdO system have made this a natural for exploring the performance of ZnO NW eld-effect transistors (FETs). In general, these have employed metaloxidesemiconductor (MOS) gates because of the low Schottky barrier heights (typically < 1 eV) of metals on ZnO. Both bottom and top gate geometries have been reported, and initial reports of simple logic circuits have appeared [5]. In this paper, we review recent progress in the synthesis, modeling, and device performance of ZnO NW FETs [6][31]. The strong sensitivity of the NW device performance to surface quality means that it is imperative to develop optimized passivation approaches and low interface density dielectrics. We also discuss the development of one such dielectric in this paper. II. SYNTHESIS OF ZnO NWs The group at UF has focused on the growth of ZnO NWs and NWs using catalyst-driven molecular beam epitaxy [32]. The former process is site specic, as single-crystal ZnO nanorod growth is realized via nucleation on Ag or Au lms or islands that are deposited on a given substrate surface. Growth occurs at relatively low substrate temperatures, on the order of 300 C500 C, making it amenable to integration on numerous

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III. DEVICE DESIGN AND SIMULATION Most device modeling and simulation work on NW FETs have been focusing on Si and Ge NWs, as a potential device option to sustain the Moores law [42]. Quantum effects and 3-D electrostatic effects, which become inevitably important for NW FETs, need to be modeled. The quantum transport equation has been solved using the nonequilibrium Greens function (NEGF) formalism at the ballistic limit and in the presence of scattering self-consistently with a 3-D Poisson equation under the effective mass approximation [43]. For NWs with a diameter larger than 5 nm, the effective mass approximation works well. For NWs with even smaller diameters, atomistic details, however, can become important, and the effective mass approximation can break down [44]. Tight-binding atomistic simulations have been reported to model atomistic scale features for silicon NW transistors [45]. Simulation of Si and Ge NW FETs is beyond the scope of this paper, but it provides the context for discussing the simulation of ZnO NW FETs. For ZnO NW FETs, simulations of the gate insulator capacitance [11], diffusion transport [46], and the effect of grain boundaries [23] have been reported. In this section, we rst extend the NEGF simulation approach to model quantum transport and ballistic performance limits of ZnO NW FETs. Diffusive transport and the grain boundary (GB) effect are modeled next. As the channel length increases, the device performance is limited by scattering and nonideal effects, such as grain boundaries. The modeled device has an intrinsic ZnO NW channel with a diameter of 5 nm, and the source and drain extensions are n+ doped. The gate insulator thickness is 5 nm, and the dielectric constant is = 10 [19]. An effective mass description (with an electron effective mass of m = 0.318) is used. The carrier transport equation is numerically solved self-consistently with a 3-D Poisson equation. A mode space method is used to reduce the computational cost [47]. The mode space approach decouples the 3-D carrier transport equation to a 2-D quantum connement problem in the cross section of the NW, which is solved by a 2-D Schrdinger equation and a 1-D transport problem along the NW axis [43]. For ballistic transport, the 1-D transport equation is solved using the NEGF formalism for each mode (subband). In the diffusive transport regime, the drift-diffusion equation is solved for each subband. Quantum connement and quantum interference effects are observed in the ballistic simulation results. Fig. 2(a) shows the local density of states (LDOS) in the cross section of the NW for the lowest subband and the second lowest subband. For the lowest subband, the LDOS has the maximum value at the center of the NW and decreases isotropically as the radius increases. The second mode is twofold degenerate, and its LDOS has two symmetric maximum values. Fig. 2(b), which shows the LDOS along the transport direction, shows quantum interference patterns between the injected electron wave (from the source or drain contact) and the wave reected by the potential barrier in the channel. The LDOS plot also shows carrier injection from multiple subbands, which indicates an energy spacing of 100 meV between the lowest subband and the second lowest subband for a simulated diameter value of

Fig. 1. Transmission electron micrograph of a ZnMgO NW grown by catalyst-driven molecular beam epitaxy.

device platforms. With this approach, nanorod placement can be predened via location of metal catalyst islands or particles. The NWs are semiconducting [33], exhibit strong photoluminescence under ultraviolet illumination [34], and have been implemented in a number of sensor applications [35]. By using this technique, the synthesis of 1-D heteroepitaxial cored (Zn, Mg)O semiconductor NWs can also be realized [36]. The structures form spontaneously in a Zn, Mg, and O2 /O3 ux, consisting of a single-crystal Zn-rich Zn1x Mgx O (x < 0.02) 0.02) sheath. core encased by an epitaxial Zn1y Mgy O (y High-resolution Z-contrast scanning transmission electron microscopy shows core diameters as small as 4 nm, as shown in Fig. 1. The cored structure forms spontaneously under constant ux due to a bimodal growth mechanism in which the core forms via bulklike vaporliquidsolid growth, while the outer sheath grows as a heteroepitaxial layer. The cored ZnO/ZnMgO NW structures have the potential to serve as self-assembled FET heterostructures. More generally, the synthesis of ZnO NWs and nanorods has been demonstrated using a number of techniques, including chemical vapor deposition, vapor-phase transport, gas reactions, oxidation of metal in the pores of anodic alumina membranes, and solution-based methods [37][39]. Chemical vapor deposition has been used both with and without catalyst metal. In the former case, growth proceeds via a vaporliquidsolid mechanism. The most typical metal catalyst has been gold. Alternatively, chemical vapor deposition growth can be achieved without metal catalysts, with growth proceeding via a vaporsolid process. The latter has the advantage of avoiding any contamination issues with the metal catalyst. Metal-organic chemical vapor deposition has been used for the growth of ZnO on a number of substrates and includes interesting results for ZnO nanorod quantum wells [40]. In addition, one can also achieve the growth of ZnO NWs using a catalyst-free pulsed laser deposition technique by employing high temperatures and high background pressures [41]. A number of groups have also reported the growth of ZnO NWs from aqueous solution [39]. For many of these techniques, the optical and semiconducting properties of the resulting ZnO NWs are impressive.

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Fig. 2. (a) Quantummechanically conned electron modes in the cross section of the NW. (b) LDOS along the ZnO NW channel. The solid line shows the rst conduction subband edge as a function of the position. The channel length is 25 nm in the range of 20 nm < x < 45 nm.

5.0 nm. Because the energy spacing is larger than the thermal energy at room temperature, carrier transport is quasi-1-D. The energy spacing between the subbands decreases inversely proportional to the NW diameter square. For a ZnO NW with a diameter larger than 10 nm, the energy spacing between the subbands becomes comparable or smaller than the roomtemperature thermal energy. We next compare the different gate geometries of the ZnO NW FET. Fig. 3(a) shows a coaxial gate geometry and a planar gate geometry. The coaxial gate geometry is ideal for efcient gate electrostatic control and could be achieved by a vertical NW FET structure. On the other hand, a planar gate geometry is easier to be fabricated for a horizontal FET structure and has been experimentally demonstrated for ZnO NW FETs [19]. Fig. 3(b) shows the ballistic transfer characteristics of the coaxial structure and the planar structure. A common off-current of 1.0 nA is specied for a fair comparison, which is achieved by engineering the work function of the metal gate for each gate geometry. The subthreshold swing of the coaxially gated FET is slightly smaller than that of the NW FET with a planar gate, due to better gate electrostatic control and suppressed short channel effects. The advantage of the coaxial gate geometry is larger above the threshold. The transconductance of the coaxial gate device is about a factor of two larger than that of the planar gate device FET due to a larger gate capacitance. The coaxial gate geometry is preferred in terms of a larger transconductance and a smaller subthreshold swing. We next explore the effect of GBs in the diffusive transport regime. The GB is assumed to be in the cross section perpendicular to the NW with spatially uniformly distributed trap states, and a Gaussian distribution near the middle of the ZnO band gap over the energy scale [23]. The states below the middle gap energy are assumed to be donorlike, and those above the middle gap energy are acceptorlike. The trap states are lled

Fig. 3. Comparison of the gate geometries. (a) Schematic cross sections of the coaxially gated geometry and the planar top gate geometry. (b) Simulated ballistic ID versus VG characteristics for the ZnO NW FETs with (solid) the coaxial gate and (dashed) the planar gate on (left) the log scale and (right) the linear scale. The gate insulator thickness is 5 nm, and the dielectric constant is = 10. The channel length is 25 nm.

according to the quasi-Fermi level at each channel position. Fig. 4(a) compares the simulated ID versus VG characteristics at VD = 0.5 V for a channel length of Lch = 1.0 m without any GBs (the dashed line) and a channel with a single GB at the middle of the channel (the solid line). The GB results in a decrease of the sourcedrain current and an increase of the threshold voltage. Fig. 4(b), which compares the rst subband proles, shows voltage drops across the GB. The voltage drop lowers the electric eld in the rest part of the channel and the sourcedrain current. To explore the effect of multiple GBs, the currentvoltage (IV ) characteristics were simulated by varying the number of equally spaced GBs in the channel. Both the on-current and the off-current decrease as the number of the GBs nGB increases. As discussed earlier, the GBs increase the threshold voltage of the transistor. In order to separate this effect from other effects due to the GBs, we compared the ID versus VG characteristics for nGB = 0, 10, and 50 at a specied common off-current, as shown in Fig. 5(a), by shifting the ID VG characteristics along the x-axis. Fig. 5(b), which shows the same characteristics at a linear scale, indicates that the on-current of the FET with nGB = 10 is approximately the same as that in the absence of GBs if a common off-current is specied. The on-current of the FET with nGB = 50, however, is only about 60% of the value. The effective channel mobility, which can be extracted from the IV characteristics above the threshold, remains approximately unchanged for nGB = 10 and decreases by about 40% for nGB = 50. For a small number of GBs, the effect of the GBs on the IV characteristics is essentially increasing the threshold voltage. As the number of the GBs increases, the GBs result in

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Fig. 4. Effect of a single GB [23]. (a) ID versus VG at VD = 0.5 V. (b) First subband prole at VD = VG = 0.5 V for (the dashed lines) a single-crystal ZnO NW channel and (the solid lines) a channel with one GB. A single GB with a trap density constant of NT 0 = 8 1013 /cm2 exists at the middle of the channel. The channel length is 1 m.

Fig. 5. Effect of multiple grain boundaries [23]. The ID versus VG characteristics with the same VT specication (a) on the linear scale and (b) on the log scale at VD = 0.5 V for a channel (the dashed line) without GBs, (the dashdot line) with ten equally spaced GBs, and (the solid line) with 50 equally spaced GBs. The channel length is 1 m. A common off-current is specied by adjusting the threshold voltage of each ZnO NW FET.

both the increase of the threshold voltage and the decrease of the effective channel mobility [23]. The modeling of ZnO NW FETs has evolved to a stage that 3-D electrostatics, quantum effects, diffusive transport, and GB effects can be treated, and the dc device characteristics can be modeled. Future work needs to address the following issues. The surface and the interface, for example, between the NW and the gate insulator, need to be better modeled and understood. The understanding, particularly at the atomistic scale resolution, is useful for understanding the sensing mechanisms of the ZnO NW chemical and biological sensors. Bipolar transport characteristics and excitonic generation and recombination need to be simulated and explored for ZnO NW optoelectronic devices. The simulation of switching and RF characteristics is needed for understanding and optimizing the speed of ZnO NW FETs. Measuring wavefunction modes in the cross section of an NW is experimentally very challenging, and as a result, no such experiments have been reported so far. Nevertheless, we note that our simulation conclusion of the low-dimensional effects, which become important as the diameter decreases to about 5 nm, can be readily tested in future experiments. IV. DEVICE ISSUES AND PERFORMANCE As described earlier, most publications on ZnO NW FETs have focused on the use of MOS gates, based on SiO2 . We have found that a gate oxide of amorphous (Ce0.33 Tb0.67 )MgAl11 O19 actually produced the lowest interface state density on undoped ZnO thin lms, suggesting that they are also applicable to NWs for improved channel modulation. Since surface states are so important in NW transistors,

it is desirable to have low interface state density systems for the gate dielectric. To establish the properties of this interface, the oxide with 200 nm thickness was deposited on undoped ZnO lms by pulsed laser deposition at 100 C and a capacitor formed using Al contact (Fig. 6, top). Fig. 6 (center) shows the hysteresis curve of the capacitancevoltage (CV ) plots, indicating that there is little hysteresis effects in the MOS structure. The dielectric constant for the amorphous CTMA was determined to be 10, which is similar to that of Al2 O3 . The bottom of Fig. 6 shows the leakage current density of CTMA as a function of applied voltage. A low leakage current of 106 A/cm2 was obtained at the applied voltage of 5 V. Fig. 7 shows the interface trap density of MIS diode between (Ce, Tb)MgAl11 Ox and undoped ZnO thin lms using the Terman method [48]. From the fact that interface traps do not respond to the ac voltage in high-frequency CV measurements, high-frequency capacitance can be expressed as CHF = (Cox Cs )/(Cox + Cs ) because interface traps respond to the varying dc gate bias. The interface trap density of MIS diode was determined to be 1 1010 eV1 cm2 near the conduction band edge. This Terman method is generally considered to be useful for underestimating interface trap density due to its limitation of insufcient high frequencies. By using this gate oxide, top-gate NW transistors were fabricated [19]. Fig. 8 shows scanning electron microscopy (SEM) micrographs of the completed devices, using NWs that were grown by molecular beam epitaxy and then dispersed onto Si substrates. The wire diameter was 3050 nm, the channel length was 2 m, and both gatesource and gatedrain spacing was 2 m. The dielectric thickness was 50 nm. Typical dc characteristics are shown in Fig. 9 which displays the drain-currentdrain-voltage (ID VDS ) characteristics and the

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Fig. 8. SEM micrographs of ZnO NW FETs showing (top) contact pads and (bottom) close-up of active region.

Fig. 6. (Top) Schematic of MOS diode with top electrode diameter of 200 m, (center) 1-MHz CV characteristics of MOS diode using undoped ZnO as a semiconducting layer with electrode area of 3.14 104 cm2 , and (bottom) IV characteristics of same MOS diode.

Fig. 7. Interface trap density of MOS diode between Tb0.67 )MgAl11 O19 and undoped ZnO using Terman method.

(Ce0.33 ,

transfer characteristics measured at room temperature under 366-nm illumination. The use of illumination provides enhanced carrier concentration in the channel and larger device current by a factor of roughly two in our case. The modulation of the channel conductance indicates that the operation of the device is an n-channel depletion mode. The gate leakage current

Fig. 9. (Top) Transfer and (bottom) IDS VDS characteristics of ZnO NW FET at room temperature measured with illumination from UV (366 nm) light.

is low, and the NW MOSFETs exhibit excellent saturation and pinch-off characteristics, indicating that the entire channel region under the gate metal can be depleted of electrons. The

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TABLE I SUMMARY OF DEVICE PERFORMANCE OF VARIOUS GEOMETRIES OF ZnO NW TRANSISTORS

threshold voltage is 3 V with a maximum transconductance of 5 mS/mm. The on/off-current ratio at VD of 10 V was on the order of 125 [19]. The eld-effect mobility FE can be determined from the transconductance using the relation IDS = (W/L)FE COX (VGS VT )VDS , where W is the channel width, L is the channel, COX is the gate oxide capacitance, and VT is the threshold voltage. The extracted mobility was 3 cm2 /V s. The carrier concentration in the channel is estimated to be 1016 cm3 . Table I summarizes recent reports of the dc performance of ZnO NW FETs. While MOSFETs are the most common approach, there are a few reports of metal gate devices (MESFETs). The most common geometry is a bottom gate using the SiO2 on an underlying Si wafer, although the top gate approach allows for individual addressing of devices. The on/off ratios are generally above 106 , and the subthreshold voltage swing is in the range of a few hundred millivolts per decade. A noticeable feature is the wide variation in reported eldeffect mobilities. A common theme is that higher mobilities are obtained on devices with surface passivation [13], usually SiO2 or in some cases polymers such as poly(methylmetahacrylate) [26]. Passivated devices show higher mobility and less variation in threshold voltage than unpassivated devices, and this has been ascribed to a reduction in surface traps [26]. The sensitivity of the dc characteristics of the NW FETs to the partial pressure of oxygen in the measurement ambient has been used to advantage in fabricating oxygen sensors [18]. High offcurrents and threshold slopes are often observed and ascribed to interface states at the ZnO/dielectric interface and incomplete

gating effects due to the cylindrical geometry of the NW and the quasi-planar nature of the gate contact [31]. Both enhancement and depletion mode operations have been demonstrated [9]. ZnO NW FETs exhibit Hooges constants around 5103 obtained from the gate dependence of noise amplitude, and this is comparable to that obtained with CMOS Si [22]. The noise spectra have a classic 1/f dependence at room temperature [7], [22]. The devices show excellent radiation hardness to high energy protons of the type encountered in low earth orbit and are promising for space-based applications [14]. It is common for reports of signicant changes in threshold voltage and off-current as a result of repeated measurement sweeps [12], indicating the role of trap states at the ZnO/gate oxide interface. Control of threshold voltage variation and minimal leakage currents are, of course, the key requirements for integrated circuit application of NW transistors. At this stage, generalization and comparisons of the existing literature about NW FETs are still difcult because of the different geometries, dielectrics, and absence of many standard device parameters in the various reports. This will improve as the science matures. To date, there have been no reports of the RF or highspeed switching performance. This is important because it will establish the effect of parasitic capacitances on the high-speed performance of NW transistors. In other words, having a very short gate length is not the only parameter that determines switching speed, and it is also important to establish the effect of contact pads on the maximum frequency of oscillation and also determine the high eld mobility in the device channel.

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V. FUTURE WORK The ability to grow NWs with techniques that are considerably less costly than conventional molecular beam epitaxy and metal-organic vapor deposition (the tools of choice for thin lms) and at lower temperatures is one advantage, and of course, the freedom to transfer the NWs to any other substrate, including cheap ones such as glass, is another advantage. A clear advantage seems to reside in the low power requirements of ZnO NW transistors, particularly when coupled to a simple fabrication scheme that involves contacting multiple NWs. There needs to be more emphasis on measuring the type of routine transport properties (carrier density, mobility, resistivity, and temperature dependence of resistivity) for NWs that are common for thin lms. The measurement of surface recombination velocity and effects of various surface treatments is lacking. There is certainly room for investigating coaxial heterostructure NW FETs because of the natural carrier connement and surface passivation. The reproducibility of measurements and the stability of NW properties as a function of measurement current density are also largely absent to date. There is a paucity of data on higher levels of device integration, e.g., small-scale circuits involving a few dozen NW transistors and on-chip resistors, capacitors, and inductors. ACKNOWLEDGMENT The authors would like to thank Prof. F. Ren, Y.-W. Kwon, and H. S. Kim for technical discussions. R EFERENCES
[1] A. Tsukazaki, A. Ohtomo, T. Onuma, M. Ohtani, T. Makino, M. Sumiya, K. Ohtani, S. Chichibu, S. Fuke, Y. Segawa, H. Ohno, H. Koinuma, and M. Kawasaki, Repeated temperature modulation epitaxy for p-type doping and light-emitting diode based on ZnO, Nat. Mater., vol. 4, no. 1, pp. 4246, Jan. 2005. [2] C. Jagadish and S. J. Pearton, Eds., Zinc Oxide Bulk, Thin Films and Nanostructures. Oxford, U.K.: Elsevier, 2006. [3] S. J. Pearton, D. P. Norton, K. Ip, Y. W. Heo, and T. Steiner, Recent progress in processing and properties of ZnO, Prog. Mater. Sci., vol. 50, no. 3, pp. 293340, Mar. 2005. [4] Z. L. Wang, ZnO nanostructures, in Zinc Oxide Bulk, Thin Films and Nanostructures, C. Jagadish and S. J. Pearton, Eds. Oxford, U.K.: Elsevier, 2006. [5] W. I. Park, J. S. Kim, G. C. Yi, and H. J. Lee, ZnO nanorod logic circuits, Adv. Mater., vol. 17, no. 11, pp. 13931397, May 2005. [6] M. S. Arnold, P. Avouris, Z. W. Pan, and Z. L. Wang, Field-effect transistors based on single semiconducting oxide nanobelts, J. Phys. Chem., vol. 107, no. 3, pp. 659663, Mar. 2003. [7] H. D. Xiong, W. Wang, Q. Li, C. A. Richter, J. S. Suehle, W.-K. Hong, T. Lee, and D. M. Fleetwood, Random telegraph signals in n-type ZnO nanowire eld effect transistors at low temperature, Appl. Phys. Lett., vol. 91, no. 5, p. 053 107, Jul. 2007. [8] Y.-Y. Noh, X. Cheng, H. Sirringhaus, J. I. Sohn, M. E. Welland, and D. Joon Kang, Ink-jet printed ZnO nanowire eld effect transistors, Appl. Phys. Lett., vol. 91, no. 4, p. 043 109, Jul. 2007. [9] W.-K. Hong, D.-K. Hwang, I.-K. Park, G. Jo, S. Song, S.-J. Park, T. Lee, B.-J. Kim, and E. A. Stach, Realization of highly reproducible ZnO nanowire eld effect transistors with n-channel depletion and enhancement modes, Appl. Phys. Lett., vol. 90, no. 24, p. 243 103, Jun. 2007. [10] L. Luo, B. D. Sosnowchik, and L. Lin, Room temperature fast synthesis of zinc oxide nanowires by inductive heating, Appl. Phys. Lett., vol. 90, no. 9, p. 093 101, Feb. 2007. [11] S. N. Cha, J. E. Jang, Y. Choi, G. A. J. Amaratunga, G. W. Ho, M. E. Welland, D. G. Hasko, D.-J. Kang, and J. M. Kim, High performance ZnO nanowire eld effect transistor using self-aligned nanogap gate electrodes, Appl. Phys. Lett., vol. 89, no. 26, p. 263 102, Dec. 2006.

[12] S. Ju, D. B. Janes, G. Lu, A. Facchetti, and T. J. Marks, Effects of bias stress on ZnO nanowire eld-effect transistors fabricated with organic gate nanodielectrics, Appl. Phys. Lett., vol. 89, no. 19, p. 193 506, Nov. 2006. [13] P.-C. Chang, Z. Fan, C.-J. Chien, D. Stichtenoth, C. Ronning, and J. G. Lu, High-performance ZnO nanowire eld effect transistors, Appl. Phys. Lett., vol. 89, no. 13, p. 133 113, Sep. 2006. [14] S. Ju, K. Lee, D. B. Janes, R. C. Dwivedi, H. Baffour-Awuah, R. Wilkins, M.-H. Yoon, A. Facchetti, and T. J. Mark, Proton radiation hardness of single-nanowire transistors using robust organic gate nanodielectrics, Appl. Phys. Lett., vol. 89, no. 7, p. 073 510, Aug. 2006. [15] Z. Fan and J. G. Lu, Gate-refreshable nanowire chemical sensors, Appl. Phys. Lett., vol. 86, no. 12, p. 123 510, Mar. 2005. [16] Z. Fan and J. G. Lu, Electrical properties of ZnO nanowire eld effect transistors characterized with scanning probes, Appl. Phys. Lett., vol. 86, no. 3, p. 032 111, Jan. 2005. [17] Z. Fan, P. Chang, J. G. Lu, E. C. Walter, R. M. Penner, C. Lin, and H. P. Lee, Photoluminescence and polarized photodetection of single ZnO nanowires, Appl. Phys. Lett., vol. 85, no. 25, p. 6128, Dec. 2004. [18] Z. Fan, D. Wang, P.-C. Chang, W.-Y. Tseng, and J. G. Lu, ZnO nanowire eld-effect transistor and oxygen sensing property, Appl. Phys. Lett., vol. 85, no. 24, p. 5923, Dec. 2004. [19] Y. W. Heo, L. C. Tien, Y. Kwon, D. P. Norton, S. J. Pearton, B. S. Kang, and F. Ren, Depletion-mode ZnO nanowire eld-effect transistor, Appl. Phys. Lett., vol. 85, no. 12, pp. 22742276, Sep. 2004. [20] J. Y. Park, Y. S. Yun, Y. S. Hong, H. Oh, J.-J. Kim, and S. S. Kim, Synthesis, electrical and photoresponse properties of vertically well-aligned and epitaxial ZnO nanorods on GaN-buffered sapphire substrates, Appl. Phys. Lett., vol. 87, no. 12, p. 123 108, Apr. 2005. [21] W. I. Park, J. S. Kim, G.-C. Yi, M. H. Bae, and H.-J. Lee, Fabrication and electrical characteristics of high-performance ZnO nanorod eldeffect transistors, Appl. Phys. Lett., vol. 85, no. 21, pp. 50525054, Nov. 2004. [22] W. Wang, H. D. Xiong, M. D. Edelstein, D. Gundlach, J. S. Suehle, C. A. Richter, W.-K. Hong, and T. Lee, Low frequency noise characterizations of ZnO nanowire eld effect transistors, J. Appl. Phys., vol. 101, no. 4, p. 044 313, Feb. 2007. [23] Y. Yoon, J. Lin, S. J. Pearton, and J. Guo, Role of grain boundaries in ZnO nanowire eld-effect transistors, J. Appl. Phys., vol. 101, no. 2, p. 024 301, Jan. 2007. [24] Y. W. Heo, D. P. Norton, L. C. Tien, Y. Kwon, B. S. Kang, F. Ren, S. J. Pearton, and J. R. LaRoche, ZnO nanowire growth and devices, Mater. Sci. Eng., R Rep., vol. 47, no. 1/2, pp. 147, Dec. 2004. [25] K. Keem, J. Kang, C. Yoon, D. Yeom, D.-Y. Jeong, B. Moon, and S. Kim, A fabrication technique for top-gate ZnO nanowire eld-effect transistors by a photolithography process, Microelectron. Eng., vol. 84, no. 58, pp. 16221626, MayAug. 2007. [26] W.-K. Hong, B.-J. Kim, T.-W. Kim, G. S. Song, S.-S. Kwon, A. Yoon, E. A. Stach, and T. Lee, Electrical properties of ZnO nanowire eld effect transistors by surface passivation, Colloids Surf., A Physicochem. Eng. Asp, vol. 313314, no. 2, pp. 378382, Feb. 2008. [27] S. J. Pearton, D. P. Norton, and F. Ren, The promise and perils of widebandgap semiconductor nanowires for sensing, electronic, and photonic applications, Small, vol. 3, no. 7, pp. 11441150, Jul. 2, 2007. [28] H. T. Ng, J. Han, T. Yamada, P. Nguyen, Y. P. Chen, and M. Meyyappan, Single crystal nanowire vertical surround-gate eld-effect transistor, Nano Lett., vol. 4, no. 7, pp. 12471252, Feb. 2004. [29] Y. M. Oh, K. M. Lee, K. H. Park, Y. Kim, Y. H. Ahn, J. Y. Park, and S. Lee, Correlating luminescence from individual ZnO nanostructures with electronic transport characteristics, Nano Lett., vol. 7, no. 12, pp. 36813685, Jun. 2007. [30] Y. Li, F. Qian, J. Xiang, and C. M. Lieber, Nanowire electronic and optoelectronic devices, Mater. Today, vol. 9, no. 10, pp. 1827, Oct. 2006. [31] S. Ju, K. Lee, D. B. Janes, M. H. Yoon, A. Facchetti, and T. J. Marks, Low operating voltage single ZnO nanowire eld-effect transistors enabled by self-assembled organic gate nanodielectrics, Nano Lett., vol. 5, no. 11, pp. 22812286, Nov. 2005. [32] Y. W. Heo, V. Varadarajan, M. Kaufman, K. Kim, D. P. Norton, F. Ren, and P. H. Fleming, Site-specic growth of ZnO nanorods using catalysis-driven molecular-beam epitaxy, Appl. Phys. Lett., vol. 81, no. 16, pp. 30463048, Oct. 2002. [33] Y. W. Heo, L. C. Tien, D. P. Norton, B. S. Kang, F. Ren, B. P. Gila, and S. J. Pearton, Electrical transport properties of single ZnO nanorods, Appl. Phys. Lett., vol. 85, no. 11, pp. 20022004, Sep. 2004. [34] Y. W. Heo, M. Kaufman, K. Pruessner, D. P. Norton, F. Ren, M. F. Chisholm, and P. H. Fleming, Optical properties of Zn1x Mgx O

PEARTON et al.: MODELING AND FABRICATION OF ZnO NANOWIRE TRANSISTORS

3019

[35]

[36]

[37] [38] [39] [40]

[41] [42] [43] [44]

[45]

[46]

[47] [48]

nanorods using catalysis-driven molecular beam epitaxy, Solid State Electron., vol. 47, no. 12, pp. 22692273, Dec. 2003. H. T. Wang, B. S. Kang, F. Ren, L. C. Tien, P. W. Sadik, D. P. Norton, S. J. Pearton, and J. Lin, Hydrogen-selective sensing at room temperature with ZnO nanorods, Appl. Phys. Lett., vol. 86, no. 24, p. 243 503, Jun. 2005. Y. W. Heo, C. Abernathy, K. Pruessner, W. Sigmund, D. P. Norton, M. Overberg, F. Ren, and M. F. Chisholm, Structure and optical properties of cored wurtzite (Zn,Mg)O heteroepitaxial nanowires, J. Appl. Phys., vol. 96, no. 6, pp. 34243428, Sep. 2004. L. Schmidt-Mende and J. L. MacManus-Driscoll, ZnO-nanostructures, defects, and devices, Mater. Today, vol. 10, no. 5, pp. 4048, May 2007. G. C. Yi, C. R. Wang, and W. I. Park, ZnO nanorods: Synthesis, characterization and applications, Semicond. Sci. Technol., vol. 20, no. 4, pp. S22S34, Mar. 2005. L. E. Greene, B. D. Yuhas, M. Law, D. Zitoun, and P. Yang, Solutiongrown zinc oxide nanowires, Inorg. Chem., vol. 45, no. 19, pp. 7535 7543, Sep. 2006. T. Yatsui, J. Lim, M. Ohtsu, S. J. An, and G. C. Yi, Evaluation of the discrete energy levels of individual ZnO nanorod single-quantum-well structures using near-eld ultraviolet photoluminescence spectroscopy, Appl. Phys. Lett., vol. 85, no. 5, pp. 727729, Aug. 2004. S. Yang and Y. H. Ni, Low-dimensional ZnO nanomaterials, Prog. Chem., vol. 19, no. 10, pp. 15101516, Oct. 2007. ITRS Roadmap, [Online]. Available: http://www.itrs.net J. Wang, E. Polizzi, and M. Lundstrom, A three-dimensional quantum simulation of silicon nanowire transistors with the effective-mass approximation, J. Appl. Phys., vol. 96, no. 4, pp. 21922203, Aug. 2004. J. Wang, A. Rahman, A. Ghosh et al., On the validity of the parabolic effective-mass approximation for the IV calculation of silicon nanowire transistors, IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 15891595, Jul. 2005. M. Luisier, A. Schenk, W. Fichtner, and G. Klimeck, Atomistic simulation of nanowires in the sp3 d5 s tight-binding formalism: From boundary conditions to strain calculations, Phys. Rev. B, Condens. Matter, vol. 74, no. 20, pp. 205 323205 327, Nov. 2006. S. Ju, K. Lee, M. Yoon, A. Facchetti, T. Marks, and D. Janes, High performance ZnO nanowire eld effect transistors with organic gate nanodielectrics: Effects of metal contacts and ozone treatment, Nanotechnology, vol. 18, no. 15, pp. 155 201155 205, Mar. 2007. S. Datta, Quantum Transport: Atom to Transistor. Cambridge, U.K.: Cambridge Univ. Press, 2005. L. M. Terman, An investigation of surface states at a silicon/silicon oxide interface employing metaloxidesilicon diodes, Solid State Electron., vol. 5, no. 5, pp. 285299, Sep./Oct. 1962.

David P. Norton received the Ph.D. degree in electrical engineering from Louisiana State University, Baton Rouge, in 1989. Since 2000, he has been with the University of Florida (UF), Gainesville, where he is currently a Professor with the Department of Materials Science and Engineering and the Director of the Nanofabrication Facility. Prior to joining UF, he was with Oak Ridge National Laboratory for eight years, where he won numerous awards. His research interests include electronic oxides and nanostructured materials and devices. Prof. Norton is a Fellow of AVS and APS.

Li-Chia Tien was born in Taipei, Taiwan, R.O.C., in 1976. He received the B.S. degree in chemistry and the M.S. degree in materials science and engineering from the National Tsing Hua University, Hsinchu, Taiwan, in 1999 and 2001, respectively. He is currently working toward the Ph.D. degree in the Department of Materials Science and Engineering, University of Florida, Gainesville. His research interests center on the synthesis of 1-D semiconductor and fabrication of nanometerscale devices.

Steve J. Pearton (A91SM93F01) received the Ph.D. degree in physics from the University of Tasmania, Hobart, Australia. He was a Postdoctoral Fellow with the University of California, Berkeley, prior to working at AT&T Bell Laboratories, Murray Hill, NJ, from 1994 to 2004. He is currently a Distinguished Professor and an Alumni Chair of the Department of Materials Science and Engineering, University of Florida, Gainesville. His research interests include the electronic and optical properties of semiconductors. Prof. Pearton is a Fellow of the AVS, ECS, TMS, and APS. He was the recipient of the 2007 J.J. Ebers Award from IEEE.

Jing Guo received the Ph.D. degree in electrical engineering from Purdue University, West Lafayette, IN, 2004. He is currently an Assistant Professor in electrical engineering with the Department of Electrical and Computer Engineering, University of Florida, Gainesville. His current research interests include modeling and simulation of nanodevices, carbon nanotube and graphene electronics and optoelectronics, nanowire electronics, and device physics of nanotransistors. He is the coauthor of the book Nanoscale Transistors: Device Physics, Modeling, and Simulation (SpringerVerlag, 2006). Dr. Guo has served in the technical program committees of the International Electron Devices Meeting and the Device Research Conference.