UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EE 130 Spring 2003 Homework Assignment

#15 Solutions Problem 1: Dynamic Threshold MOSFET a) Three ways to adjust VT: - adjust Tox - adjust channel doping - adjust the gate material work function b) It is desirable to have a low VT in order to maximize the transistor current when it is ON, to maximize Idsat It is desirable to have a high VT in order to minimize the transistor leakage current when it is OFF, to reduce the static power consumption. c) i) VB should be connected to VDD to reduce VT and hence increase Idsat ii) VB should be connected to GND in order to maximize VT and hence minimize subthreshold leakage current ii) The main advantage of connecting VB to VG is to dynamically optimize VT for high speed (in the ON state) and low static power consumption (in the OFF state). iii) The disadvantage of connecting VB to VG is an increase power consumption when the transistor is turned ON, due to the forward-bias pn-junction diode current associated with the source and drain regions. If the area of the source and drain junctions is small (e.g. if SOI technology is used), this power consumption penalty will be small. Prof. King

Problem 2: SOI Technology a) Advantages of SOI technology: Simpler device isolation: NMOSFET and PMOSFET devices can be easily electrically isolated from each other on the surface of the wafer; this saves circuit layout area and can simplify the fabrication process, to lower the cost (but not completely compensating for the higher cost of the starting SOI wafer substrates!) No body effect issues for circuit operation: Since the body region is floating, the circuit will never apply a reverse bias to the source/body junction to affect VT Near-zero S/D junction capacitance: the thick buried oxide under the source/drain regions essentially eliminates vertical pn junction capacitances; only the sidewall junction areal capacitances are significant but the area of the pn-junction sidewalls is very small. b) In a partially depleted SOI device, TSOI>Wdm. For a channel doping concentration of 51017cm-3:

B =

kT N body 5 1017 ln = 0.026 ln = 0.46V q ni 1010

Wdm

2 s (2 B ) 2 * 10 12 * (2 * 0.46) = = = 4.79 10 6 cm = 0.047 m = 47.9nm 19 17 qN body 1.6 10 * 5 10

Therefore, the range of SOI thicknesses that will result in partially depleted body MOSFETs is TSOI > 47.9nm c) The floating-body effect can be described as follow: When a PD-SOI NMOSFET is in the ON state at moderate Vds, holes that are generated via impact ionization near the drain are swept into the neutral body, where they flow to the back interface (with the buried oxide) at the source end of the body, accumulating there (because of the potential barrier which exists at the source junction). As a result: - the body-source pn junction is forward biased (VBS > 0) - VT is lowered, thus Idsat increases (and the holes leak out into the source because of the reduced potential barrier height, at a rate equal to that of holes being generated by impact ionization, in steady state) - a kink is present in the output ID vs. VDS curve, i.e. Idsat increases noticeably (corresponding to the lowering of VT) when VDS is increased beyond a certain point The floating-body effect is negligible in fully depleted SOI devices because in the ON state, the energy bands are bent down (for an NMOSFET), even at the backside of the body, lowering the potential barrier to holes flowing into the source. Thus, holes do not tend to accumulate in the body at the source junction, to forward bias it significantly. Problem 3: MOS Memory Devices a) Some of advantages of 6-transistor SRAM technology as compared with 1-transistor + 1 capacitor DRAM technology are: - no refreshing needed - faster access time - better soft error immunity - conventional CMOS fabrication process can be used to implement SRAM on the same chip as logic circuitry The primary disadvantage of 6-transistor SRAM technology is its larger cell area, which translates to lower density and higher cost per bit b) Let D be the depth of the trench, and A the total capacitor area: A = r2 + 2rD 2rD D can then be calculated as follows:

Cox = D=

ox A
Tox

A=

Cox Tox

ox

( 25 10 15 )(10 7 ) = 7.246 10 9 cm 2 3.45 10 13

A 7.246 10 9 = = 2.3 10 4 cm = 2.3m 4 2r (0.1 10 )

The trench will be 23 times deeper than it is wide. This is practically difficult to achieve. Thus, an alternative capacitor dielectric with higher permittivity than SiO2, or a stacked capacitor structure with much higher electrode surface area may be needed.

c) The gate stack can be considered as two capacitors in series. The VT shift due to charge QFG (in C/cm2) on the floating gate is simply:

15 QFG VT = 15 + 8 CCG
where CCG is the areal capacitance of the control gate:

CCG =

SiO

Tox ,total

3.45 10 13 F / cm = 1.5 10 7 F / cm 2 23 10 7 cm

The areal charge density required to achieve VT = 2V is

23 23 QFG = CCG VT = (1.5 10 7 )( 2) = 4.6 10 7 C / cm 2 15 15

Thus, the total number of electrons on the floating gate required to achieve VT = 2V is

QFG 4.6 10 7 C / cm 2 = 2.9 1012 electrons / cm 2 = 19 1.6 10 C q