Prof.

Jinsang Kim 1 VLSI Design

CMOS logic design and layout
Prof. Jinsang Kim 2 VLSI Design
Invention of the Transistor
Vacuum tubes ruled in first half of 20
th

century: Large, expensive, power-hungry,
unreliable
1947: first point contact transistor
John Bardeen and Walter Brattain at Bell Labs
Read Crystal Fire
by Riordan, Hoddeson
Prof. Jinsang Kim 3 VLSI Design
Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls
large currents between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect
Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current
between source and drain
Low power allows very high integration
Prof. Jinsang Kim 4 VLSI Design
1970s processes usually had only nMOS transistors
Inexpensive, but consume power while idle










1980s-present: CMOS processes for low idle power
MOS Integrated Circuits
Intel 1101 256-bit SRAM Intel 4004 4-bit Proc
Prof. Jinsang Kim 5 VLSI Design
Moores Law
1965: Gordon Moore plotted transistor on each chip
Fit straight line on semilog scale: most economical!!
Transistor counts of Intel uPs have doubled every 26
months (following fiugure)









Moores Law: Transistor counts doubles every 18 months.
Year
T
r
a
n
s
i
s
t
o
r
s
4004
8008
8080
8086
80286
Intel386
Intel486
Pentium
Pentium Pro
Pentium II
Pentium III
Pentium 4
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
1,000,000,000
1970 1975 1980 1985 1990 1995 2000
Integration Levels
SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
VLSI: > 10k gates
Prof. Jinsang Kim 6 VLSI Design
Corollaries
Many other factors grow exponentially
Ex: clock frequency, processor performance
Year
1
10
100
1,000
10,000
1970 1975 1980 1985 1990 1995 2000 2005
4004
8008
8080
8086
80286
Intel386
Intel486
Pentium
Pentium Pro/II/III
Pentium 4
C
l
o
c
k

S
p
e
e
d

(
M
H
z
)
Prof. Jinsang Kim 7 VLSI Design
CMOS Gate Design
Activity:
Sketch a 4-input CMOS NOR gate
A
B
C
D
Y
Prof. Jinsang Kim 8 VLSI Design
Complementary CMOS
Complementary CMOS logic gates
nMOS pull-down network
pMOS pull-up network
a.k.a. static CMOS
pMOS
pull-up
network
output
inputs
nMOS
pull-down
network
Pull-up
OFF
Pull-up
ON
Pull-down
OFF
Z (float) 1
Pull-down
ON
0 X
(crowbar)
Prof. Jinsang Kim 9 VLSI Design
Series and Parallel
nMOS: 1 = ON
pMOS: 0 = ON
Series: both must be ON
Parallel: either can be ON
(a)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
OFF OFF OFF ON
(b)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
ON OFF OFF OFF
(c)
a
b
a
b
g1 g2
0 0
OFF ON ON ON
(d) ON ON ON OFF
a
b
0
a
b
1
a
b
1 1 0 1
a
b
0 0
a
b
0
a
b
1
a
b
1 1 0 1
a
b
g1 g2
Prof. Jinsang Kim 10 VLSI Design
Conduction Complement
Complementary CMOS gates always produce
0 or 1
Ex: NAND gate
Series nMOS: Y=0 when both inputs are 1
Thus Y=1 when either input is 0
Requires parallel pMOS

Rule of Conduction Complements
Pull-up network is complement of pull-down
Parallel -> series, series -> parallel


A
B
Y
Prof. Jinsang Kim 11 VLSI Design
Compound Gates
Compound gates can do any inverting
function
Ex:
(AND-AND-OR-INVERT, AOI22) Y A B C D = +
A
B
C
D
A
B
C
D
A B C D
A B
C D
B
D
Y
A
C
A
C
A
B
C
D
B
D
Y
(a)
(c)
(e)
(b)
(d)
(f)
Prof. Jinsang Kim 12 VLSI Design
Example: O3AI

( )
Y A B C D = + +
A B
Y
C
D
D C
B
A
Prof. Jinsang Kim 13 VLSI Design
Signal Strength
Strength of signal
How close it approximates ideal voltage source
V
DD
and GND rails are strongest 1 and 0
nMOS pass strong 0
But degraded or weak 1
pMOS pass strong 1
But degraded or weak 0
Thus nMOS are best for pull-down network
Prof. Jinsang Kim 14 VLSI Design
Pass Transistors
Transistors can be used as switches
g
s d
g = 0
s d
g = 1
s d
0 strong 0
Input Output
1 degraded 1
g
s d
g = 0
s d
g = 1
s d
0 degraded 0
Input Output
strong 1
g = 1
g = 1
g = 0
g = 0
Prof. Jinsang Kim 15 VLSI Design
Transmission Gates
Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well
g = 0, gb = 1
a b
g = 1, gb = 0
a b
0 strong 0
Input Output
1
strong 1
g
gb
a
b
a b
g
gb
a b
g
gb
a b
g
gb
g = 1, gb = 0
g = 1, gb = 0
Prof. Jinsang Kim 16 VLSI Design
Tristates
Tristate buffer produces Z when not enabled
EN A Y
0 0 Z
0 1 Z
1 0 0
1 1 1
A
Y
EN
A
Y
EN
EN
Prof. Jinsang Kim 17 VLSI Design
Nonrestoring Tristate
Transmission gate acts as tristate buffer
Only two transistors
But nonrestoring
Noise on A is passed on to Y
A Y
EN
EN
Prof. Jinsang Kim 18 VLSI Design
Tristate Inverter
Tristate inverter produces restored output
Violates conduction complement rule
Because we want a Z output
A
Y
EN
EN
Prof. Jinsang Kim 19 VLSI Design
Tristate Inverter
Tristate inverter produces restored output
Violates conduction complement rule
Because we want a Z output
A
Y
EN
A
Y
EN = 0
Y = 'Z'
Y
EN = 1
Y = A
A
EN
Prof. Jinsang Kim 20 VLSI Design
Multiplexers
2:1 multiplexer chooses between two inputs
S D1 D0 Y
0 X 0
0 X 1
1 0 X
1 1 X
0
1
S
D0
D1
Y
Prof. Jinsang Kim 21 VLSI Design
Multiplexers
2:1 multiplexer chooses between two inputs
S D1 D0 Y
0 X 0 0
0 X 1 1
1 0 X 0
1 1 X 1
0
1
S
D0
D1
Y
Prof. Jinsang Kim 22 VLSI Design
Gate-Level Mux Design

How many transistors are needed? 20
1 0
(too many transistors) Y SD SD = +
4
4
D1
D0
S
Y
4
2
2
2
Y
2
D1
D0
S
Prof. Jinsang Kim 23 VLSI Design
Transmission Gate Mux
Nonrestoring mux uses two transmission
gates
Only 4 transistors
S
S
D0
D1
Y S
Prof. Jinsang Kim 24 VLSI Design
Inverting Mux
Inverting multiplexer
Use compound AOI22
Or pair of tristate inverters
Essentially the same thing
Noninverting multiplexer adds an inverter
S
D0
D1
Y
S
D0
D1
Y
0
1
S
Y
D0
D1
S
S
S
S
S
S
Prof. Jinsang Kim 25 VLSI Design
4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two
selects
Two levels of 2:1 muxes
Or four tristates
S0
D0
D1
0
1
0
1
0
1
Y
S1
D2
D3
D0
D1
D2
D3
Y
S1S0 S1S0 S1S0 S1S0
Prof. Jinsang Kim 26 VLSI Design
D Latch
When CLK = 1, latch is transparent
D flows through to Q like a buffer
When CLK = 0, the latch is opaque
Q holds its old value independent of D
a.k.a. transparent latch or level-sensitive latch
CLK
D Q
L
a
t
c
h
D
CLK
Q
Prof. Jinsang Kim 27 VLSI Design
D Latch Design
Multiplexer chooses D or old Q
1
0
D
CLK
Q
CLK
CLK
CLK
CLK
D Q
Q
Q
Prof. Jinsang Kim 28 VLSI Design
D Latch Operation
CLK = 1
D
Q
Q
CLK = 0
D
Q
Q
D
CLK
Q
Prof. Jinsang Kim 29 VLSI Design
D Flip-flop
When CLK rises, D is copied to Q
At all other times, Q holds its value
a.k.a. positive edge-triggered flip-flop,
master-slave flip-flop
F
l
o
p
CLK
D Q
D
CLK
Q
Prof. Jinsang Kim 30 VLSI Design
D Flip-flop Design
Built from master and slave D latches
QM
CLK
CLK
CLK
CLK
Q
CLK
CLK
CLK
CLK
D
L
a
t
c
h
L
a
t
c
h
D Q
QM
CLK
CLK
Prof. Jinsang Kim 31 VLSI Design
D Flip-flop Operation
CLK = 1
D
CLK = 0
Q
D
QM
QM
Q
D
CLK
Q
Prof. Jinsang Kim 32 VLSI Design
Race Condition
Back-to-back flops can malfunction from
clock skew
Second flip-flop fires late
Sees first flip-flop change and captures its result
Called hold-time failure or race condition
CLK1
D
Q1
F
l
o
p
F
l
o
p
CLK2
Q2
CLK1
CLK2
Q1
Q2
Prof. Jinsang Kim 33 VLSI Design
Nonoverlapping Clocks
Nonoverlapping clocks can prevent races
As long as nonoverlap exceeds clock skew
We will use them in this class for safe design
Industry manages skew more carefully instead
|
1
|
1 |
1
|
1
|
2
|
2 |
2
|
2
|
2
|
1
QM
Q D
Prof. Jinsang Kim 34 VLSI Design
Gate Layout
Layout can be very time consuming
Design gates to fit together nicely
Build a library of standard cells
Standard cell design methodology
V
DD
and GND should abut (standard height)
Adjacent gates should satisfy design rules
nMOS at bottom and pMOS at top
All gates include well and substrate contacts
Prof. Jinsang Kim 35 VLSI Design
Example: Inverter
Prof. Jinsang Kim 36 VLSI Design
Example: NAND3
Horizontal N-diffusion and p-diffusion strips
Vertical polysilicon gates
Metal1 V
DD
rail at top
Metal1 GND rail at bottom
32 by 40
Prof. Jinsang Kim 37 VLSI Design
Stick Diagrams
Stick diagrams help plan layout quickly
Need not be to scale
Draw with color pencils or dry-erase markers
Prof. Jinsang Kim 38 VLSI Design
Wiring Tracks
A wiring track is the space required for a wire
4 width, 4 spacing from neighbor = 8 pitch
Transistors also consume one wiring track

Prof. Jinsang Kim 39 VLSI Design
Well spacing
Wells must surround transistors by 6
Implies 12 between opposite transistor flavors
Leaves room for one wire track
Prof. Jinsang Kim 40 VLSI Design
Area Estimation
Estimate area by counting wiring tracks
Multiply by 8 to express in
Prof. Jinsang Kim 41 VLSI Design
Example: O3AI
Sketch a stick diagram for O3AI and
estimate area

( )
Y A B C D = + +
Prof. Jinsang Kim 42 VLSI Design
Transistor Sizing
Decide the W and L of a CMOS circuit to provide equal current
driving capability in both directions (PUN and PDN) as the
basic inverter.
- If

PDN's capacitor discharge current should be at least equal that of
NMOS TR of inverter.
PUD's capacitor charging current should be at least equal that of
PMOS TR of inverter.

the above two conditions will guarantee a worst-cast gate delay
equal to that of the basic inverter.

we need to find the equivalent W/L ratio of a network of MOS
transistor as that of an inverter.
( / ) , ( / ) , ( / ) .
n p
W L n W L p p n p n for a matched design = = =
Prof. Jinsang Kim 43 VLSI Design
- Equivalent series resistance when a number of MOSFETs are
connected in series










- In the same manner, for parallel connection of TRs
1 2 series DS DS
R r r = + +
( ) ( )
1 2
/ /
constant constant
W L W L
= + +
( ) ( )
1 2
1 1
/ /
constant
W L W L
(
= + +
(
(

( )
/
eq
constant
W L
=
( )
( ) ( )
1 2
1
/
1 1
/ /
eq
W L
W L W L
=
+ +
( ) ( ) ( )
1 2
/ / /
eq
W L W L W L = + +
Transistor Sizing
Prof. Jinsang Kim 44 VLSI Design
Proper transistor sizing for a four-input NOR gate. Note that n and p denote the (W/L) ratios of Q
N
and Q
P
, respectively, of the basic inverter.
Transistor Sizing
Prof. Jinsang Kim 45 VLSI Design
Proper transistor sizing for a four-input NAND gate. Note that n and p denote the (W/L) ratios of Q
N
and Q
P
, respectively, of the basic inverter.
Transistor Sizing
Prof. Jinsang Kim 46 VLSI Design
: / 2 3 0.75/ 0.25
NB
Q W L n = = =
: / 2 3 0.75/ 0.25
NC
Q W L n = = =
: / 2 3 0.75/ 0.25
ND
Q W L n = = =
: / 1.5 0.375/ 0.25
NA
Q W L n = = =
: / 3 15 3.75/ 0.25
PA
Q W L p = = =
: / 3 15 3.75/ 0.25
PC
Q W L p = = =
: / 3 15 3.75/ 0.25
PD
Q W L p = = =
: / 1.5 7.5 1.875/ 0.25
PB
Q W L p = = =
Transistor Sizing
Prof. Jinsang Kim 47 VLSI Design
Transistor Sizing