EE 421: Digital System Design Instructor: Dr.

Shahid Masud Email: smasud Office Hours: Friday 0930 to 1030 hrs Office: 9-323A, SSE Building Tel: LUMS Ext 8199 Credits: 4 Semester: Fall 2011-12

Course Description: This course explains how to go about designing complex, high-speed digital circuits and systems. The use of modern EDA tools in the design, simulation, synthesis and implementation is explored. Application of a hardware description language such as Verilog or VHDL to model digital systems at Behavior and RTL level is studied. Field programmable gate arrays (FPGA) are used in the laboratory exercises as a vehicle to understand complete design-flow of an integrated circuit. Advanced methods of logic minimization and state-machine design are discussed. Design and implementation of digital system building blocks such as arithmetic circuits, datapaths, microprocessors, I/O modules, UARTs, frequency generators, memories etc. is included. BIST and Scan techniques for testing of digital systems are also covered. Laboratories and projects are an integral part of this course that culminates in a comprehensive design exercise. Course Status: Core for MS CmpE Elective for BS Electrical Engineering Pre-requisites: Computer Organization and Assembly Language at BS/BE level Text Book: 1. Principles of Digital Systems Design using VHDL, Charles H. Roth, Lizy K. John, CEngage Learning, 1998 Supplementary Reading: 1. Digital Electronics and Design with VHDL, Volnei A. Pedroni, Elsevier Publishers, 2008 2. Digital System Design with VHDL, Second edition, Mark Zwolinski, Pearson Education, 2004 Learning Outcomes: Upon completion of the course, students should be able to: i. Understand issues in designing high-speed complex digital systems ii. Understand hardware architectures of basic building blocks of digital systems iii. Undertake design and optimization complex combinational and sequential logic iv. Describe a complex digital system using VHDL v. Simulate and Debug digital systems using EDA tools

vi. vii.

Implement digital systems on FPGA platforms Analyze and specify timing in high-speed design

Grading Scheme: Quizzes (6): 15% Ten Labs for 15%, marks breakup is as follows: Attendance: 4% Completion: 6% Midterm Lab Exam: 5% One Design Exercise for 15%, marks breakup is as follows: Specifications: 2% (due before midterm exam) Coding and simulation testing: 5% (due before last lecture) FPGA implementation and demonstration: 4% (due before last lecture) Report on architecture and operation: 4% (due before final exam) Midterm: 25% Final: 30% Lectures and Examinations: Two weekly lecture sessions of 75 minutes duration each One weekly lab session in EE Embedded Systems Lab Attendance is not compulsory, punctuality is desired One in-class midterm One design exercise Comprehensive final examination Lecture Topics: Lecture / Course Topics Week 1 / Wk 1 Introduction to digital systems and their design flow 2 / Wk 1 Review of combinational logic, logic minimization Lab 1 Introductory VHDL 1 3 / Wk 2 Timing in Combinational Circuits, Hazards and Glitches, Review of sequential logic 4 / Wk 2 Lecture - Introductory VHDL - 2 Lab 2 VHDL Coding and Simulation on Modelsim 5 / Wk 3 Design using flip-flop and latches, State machines 6 / Wk 3 State reduction, timing issues Lab 3 VHDL Behavioural Coding and Simulation 7 / Wk 4 Design of Adders and Subtractors, Carry Lookahead Adders 8 / Wk 4 Serial Adders, Array Multipliers, Critical Paths Lab 4 VHDL Sequential Coding and Simulation 9 / Wk 5 Booth and Radix-4 Encoded Signed Multipliers

Readings Roth Roth

Lab / Quiz

Lab 1 Roth

Lab 2 Roth Roth Lab 3 Roth Roth Lab 4 Pedroni

Further VHDL modeling, parameterization VHDL Design of State Machines Design of dividers and other arithmetic circuits Circuits for Floating Point Implementation Serial Multipliers, Keyboard Scanner, Signed Multiplication of Fractions Wk 7 Due Specifications (up to 2 pages) of Design Exercise 14 / Wk 7 Midterm Exam 14 / Wk 7 Midterm Exam 15 / Wk 8 Programmable logic, PAL, PLA, CPLD 16 / Wk 8 Construction and operation of FPGA Lab 7 Midterm Lab Exam 17 / Wk 9 Controller design using ASM charts 18 / Wk 9 Controller Design for Sequential Multipliers and Dividers Lab 8 FPGA Implementation 1 19 / Wk 10 LFSR, BRM, Function Generators 20 / Wk 10 Faults and Testability BIST and SCAN techniques Lab 9 FPGA Implementation 2 21 / Wk 11 Design for test JTAG 22 / Wk 11 Advanced VHDL Memories and Register Files Lab 10 Design Example 1 22 / Wk 11 VHDL Synthesis Issues 23 / Wk 12 Advanced VHDL Lab 11 Design Example 2 24 / Wk 13 Asynchronous Sequential Design 25 / Wk 13 Processor Design 1 Labs 12 to Design Exercise (Simulation, FPGA 14 Implementation, Demonstration) 26 / Wk 14 Processor Design - 2 27 / Wk 14 Digital Design Case Study Due Final Report and Submission of Design Exercise Final Exam Week 15

10 / Wk 5 Lab 5 11 / Wk 6 12 / Wk 6 13 / Wk 7

Lab 6 Roth Roth Roth

Roth Roth L - Exam Roth Roth Lab 8 Pedroni Roth Lab 9 Roth Lab 10 Zwolinski Lab 11 Zwolinski Roth Design Exercise Roth Pedroni

Lab Exercises: Lab / Week Lab Topics 1. / Wk 1 Structural and Modular VHDL coding 2. / Wk 2 Simulation and testing of VHDL code 3. / Wk 3 Behavior Design Examples, coding and simulation

Readings

4. / Wk 4 5. / Wk 5 6. / Wk 6 Wk 7 7. / Wk 8 8. / Wk 9 9. / Wk 10 10. / Wk 11 11. / Wk 12 Wk 13 - 14

RTL Design, coding and simulation FSM in VHDL, coding and simulation VHDL Design Examples Lab Exam VHDL Simulation Xilinx Synthesis - FPGA implementation of design 1 Xilinx Synthesis - FPGA implementation of design 2 Optimize logic design (speed, area), placement and routing Design Exercise and further FPGA experiments Advanced VHDL Concepts, simulation and synthesis Design Exercise including FPGA Implementation